15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 1899722c8aSChristophe JAILLET #include <linux/kstrtox.h> 19dc90f084SChristoph Hellwig #include <linux/memremap.h> 2057dacad5SJay Sternberg #include <linux/mm.h> 2157dacad5SJay Sternberg #include <linux/module.h> 2277bf25eaSKeith Busch #include <linux/mutex.h> 23d0877473SKeith Busch #include <linux/once.h> 2457dacad5SJay Sternberg #include <linux/pci.h> 25d916b1beSKeith Busch #include <linux/suspend.h> 2657dacad5SJay Sternberg #include <linux/t10-pi.h> 2757dacad5SJay Sternberg #include <linux/types.h> 289cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2920d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 30a98e58e5SScott Bauer #include <linux/sed-opal.h> 310f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3257dacad5SJay Sternberg 33604c01d5Syupeng #include "trace.h" 3457dacad5SJay Sternberg #include "nvme.h" 3557dacad5SJay Sternberg 36c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 378a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3857dacad5SJay Sternberg 39a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40adf68f21SChristoph Hellwig 41943e942eSJens Axboe /* 42943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 43943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 44943e942eSJens Axboe */ 45943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 46943e942eSJens Axboe #define NVME_MAX_SEGS 127 47943e942eSJens Axboe 4857dacad5SJay Sternberg static int use_threaded_interrupts; 492e21e445SXin Hao module_param(use_threaded_interrupts, int, 0444); 5057dacad5SJay Sternberg 5157dacad5SJay Sternberg static bool use_cmb_sqes = true; 5269f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5357dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5457dacad5SJay Sternberg 5587ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5687ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5787ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5887ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5957dacad5SJay Sternberg 60a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 61a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 62a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 63a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 64a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 65a7a7cbe3SChaitanya Kulkarni 6627453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6727453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 68b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 69b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 70b27c1e68Sweiping zhang .set = io_queue_depth_set, 7161f3b896SChaitanya Kulkarni .get = param_get_uint, 72b27c1e68Sweiping zhang }; 73b27c1e68Sweiping zhang 7461f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 75b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7627453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 77b27c1e68Sweiping zhang 789c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 799c9e76d5SWeiping Zhang { 809c9e76d5SWeiping Zhang unsigned int n; 819c9e76d5SWeiping Zhang int ret; 829c9e76d5SWeiping Zhang 839c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 849c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 859c9e76d5SWeiping Zhang return -EINVAL; 869c9e76d5SWeiping Zhang return param_set_uint(val, kp); 879c9e76d5SWeiping Zhang } 889c9e76d5SWeiping Zhang 899c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 909c9e76d5SWeiping Zhang .set = io_queue_count_set, 919c9e76d5SWeiping Zhang .get = param_get_uint, 929c9e76d5SWeiping Zhang }; 939c9e76d5SWeiping Zhang 943f68baf7SKeith Busch static unsigned int write_queues; 959c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 963b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 973b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 983b6592f7SJens Axboe "will share a queue set."); 993b6592f7SJens Axboe 1003f68baf7SKeith Busch static unsigned int poll_queues; 1019c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1024b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1034b04cc6aSJens Axboe 104df4f9bc4SDavid E. Box static bool noacpi; 105df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 106df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 107df4f9bc4SDavid E. Box 1081c63dc66SChristoph Hellwig struct nvme_dev; 1091c63dc66SChristoph Hellwig struct nvme_queue; 11057dacad5SJay Sternberg 111a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1128fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11357dacad5SJay Sternberg 11457dacad5SJay Sternberg /* 1151c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1161c63dc66SChristoph Hellwig */ 1171c63dc66SChristoph Hellwig struct nvme_dev { 118147b27e4SSagi Grimberg struct nvme_queue *queues; 1191c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1201c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1211c63dc66SChristoph Hellwig u32 __iomem *dbs; 1221c63dc66SChristoph Hellwig struct device *dev; 1231c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1241c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1251c63dc66SChristoph Hellwig unsigned online_queues; 1261c63dc66SChristoph Hellwig unsigned max_qid; 127e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12822b55601SKeith Busch unsigned int num_vecs; 1297442ddceSJohn Garry u32 q_depth; 130c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1311c63dc66SChristoph Hellwig u32 db_stride; 1321c63dc66SChristoph Hellwig void __iomem *bar; 13397f6ef64SXu Yu unsigned long bar_mapped_size; 13477bf25eaSKeith Busch struct mutex shutdown_lock; 1351c63dc66SChristoph Hellwig bool subsystem; 1361c63dc66SChristoph Hellwig u64 cmb_size; 1370f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1381c63dc66SChristoph Hellwig u32 cmbsz; 139202021c1SStephen Bates u32 cmbloc; 1401c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 141d916b1beSKeith Busch u32 last_ps; 142a5df5e79SKeith Busch bool hmb; 14387ad72a5SChristoph Hellwig 144943e942eSJens Axboe mempool_t *iod_mempool; 145943e942eSJens Axboe 14687ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 147f9f38e33SHelen Koike u32 *dbbuf_dbs; 148f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 149f9f38e33SHelen Koike u32 *dbbuf_eis; 150f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15187ad72a5SChristoph Hellwig 15287ad72a5SChristoph Hellwig /* host memory buffer support: */ 15387ad72a5SChristoph Hellwig u64 host_mem_size; 15487ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1554033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15787ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1582a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1592a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1602a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 16157dacad5SJay Sternberg }; 16257dacad5SJay Sternberg 163b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 164b27c1e68Sweiping zhang { 16527453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16627453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 167b27c1e68Sweiping zhang } 168b27c1e68Sweiping zhang 169f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 170f9f38e33SHelen Koike { 171f9f38e33SHelen Koike return qid * 2 * stride; 172f9f38e33SHelen Koike } 173f9f38e33SHelen Koike 174f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 175f9f38e33SHelen Koike { 176f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 177f9f38e33SHelen Koike } 178f9f38e33SHelen Koike 1791c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1801c63dc66SChristoph Hellwig { 1811c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1821c63dc66SChristoph Hellwig } 1831c63dc66SChristoph Hellwig 18457dacad5SJay Sternberg /* 18557dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18657dacad5SJay Sternberg * commands and one for I/O commands). 18757dacad5SJay Sternberg */ 18857dacad5SJay Sternberg struct nvme_queue { 18957dacad5SJay Sternberg struct nvme_dev *dev; 1901ab0cd69SJens Axboe spinlock_t sq_lock; 191c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1923a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1933a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19474943d45SKeith Busch struct nvme_completion *cqes; 19557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19757dacad5SJay Sternberg u32 __iomem *q_db; 1987442ddceSJohn Garry u32 q_depth; 1997c349ddeSKeith Busch u16 cq_vector; 20057dacad5SJay Sternberg u16 sq_tail; 20138210800SKeith Busch u16 last_sq_tail; 20257dacad5SJay Sternberg u16 cq_head; 20357dacad5SJay Sternberg u16 qid; 20457dacad5SJay Sternberg u8 cq_phase; 205c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2064e224106SChristoph Hellwig unsigned long flags; 2074e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20863223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 209d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2107c349ddeSKeith Busch #define NVMEQ_POLLED 3 211f9f38e33SHelen Koike u32 *dbbuf_sq_db; 212f9f38e33SHelen Koike u32 *dbbuf_cq_db; 213f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 214f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 215d1ed6aa1SChristoph Hellwig struct completion delete_done; 21657dacad5SJay Sternberg }; 21757dacad5SJay Sternberg 21857dacad5SJay Sternberg /* 2199b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2209b048119SChristoph Hellwig * 2219b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2229b048119SChristoph Hellwig * to the actual struct scatterlist. 22371bd150cSChristoph Hellwig */ 22471bd150cSChristoph Hellwig struct nvme_iod { 225d49187e9SChristoph Hellwig struct nvme_request req; 226af7fae85SKeith Busch struct nvme_command cmd; 227a7a7cbe3SChaitanya Kulkarni bool use_sgl; 22852da4f3fSKeith Busch bool aborted; 229c372cdd1SKeith Busch s8 nr_allocations; /* PRP list pool allocations. 0 means small 230c372cdd1SKeith Busch pool in use */ 231dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 232c4c22c52SKeith Busch dma_addr_t first_dma; 233783b94bdSChristoph Hellwig dma_addr_t meta_dma; 23491fb2b60SLogan Gunthorpe struct sg_table sgt; 23557dacad5SJay Sternberg }; 23657dacad5SJay Sternberg 2372a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2383b6592f7SJens Axboe { 2392a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 240f9f38e33SHelen Koike } 241f9f38e33SHelen Koike 24265a54646SChristoph Hellwig static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 243f9f38e33SHelen Koike { 2442a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 245f9f38e33SHelen Koike 24665a54646SChristoph Hellwig if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) 24765a54646SChristoph Hellwig return; 24865a54646SChristoph Hellwig 24958847f12SKeith Busch if (dev->dbbuf_dbs) { 25058847f12SKeith Busch /* 25158847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25258847f12SKeith Busch * values from the previous instantiation. 25358847f12SKeith Busch */ 25458847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 25558847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 25665a54646SChristoph Hellwig return; 25758847f12SKeith Busch } 258f9f38e33SHelen Koike 259f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 260f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 261f9f38e33SHelen Koike GFP_KERNEL); 262f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 26365a54646SChristoph Hellwig goto fail; 264f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 265f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 266f9f38e33SHelen Koike GFP_KERNEL); 26765a54646SChristoph Hellwig if (!dev->dbbuf_eis) 26865a54646SChristoph Hellwig goto fail_free_dbbuf_dbs; 26965a54646SChristoph Hellwig return; 270f9f38e33SHelen Koike 27165a54646SChristoph Hellwig fail_free_dbbuf_dbs: 27265a54646SChristoph Hellwig dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, 27365a54646SChristoph Hellwig dev->dbbuf_dbs_dma_addr); 27465a54646SChristoph Hellwig dev->dbbuf_dbs = NULL; 27565a54646SChristoph Hellwig fail: 27665a54646SChristoph Hellwig dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); 277f9f38e33SHelen Koike } 278f9f38e33SHelen Koike 279f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 280f9f38e33SHelen Koike { 2812a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 282f9f38e33SHelen Koike 283f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 284f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 285f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 286f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 287f9f38e33SHelen Koike } 288f9f38e33SHelen Koike if (dev->dbbuf_eis) { 289f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 290f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 291f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 292f9f38e33SHelen Koike } 293f9f38e33SHelen Koike } 294f9f38e33SHelen Koike 295f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 296f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 297f9f38e33SHelen Koike { 298f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 299f9f38e33SHelen Koike return; 300f9f38e33SHelen Koike 301f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 302f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 303f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 304f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 305f9f38e33SHelen Koike } 306f9f38e33SHelen Koike 3070f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3080f0d2c87SMinwoo Im { 3090f0d2c87SMinwoo Im if (!nvmeq->qid) 3100f0d2c87SMinwoo Im return; 3110f0d2c87SMinwoo Im 3120f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3130f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3140f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3150f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3160f0d2c87SMinwoo Im } 3170f0d2c87SMinwoo Im 318f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 319f9f38e33SHelen Koike { 320f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3210f0d2c87SMinwoo Im unsigned int i; 322f9f38e33SHelen Koike 323f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 324f9f38e33SHelen Koike return; 325f9f38e33SHelen Koike 326f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 327f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 328f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3319bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 332f9f38e33SHelen Koike /* Free memory and continue on */ 333f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3340f0d2c87SMinwoo Im 3350f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3360f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 337f9f38e33SHelen Koike } 338f9f38e33SHelen Koike } 339f9f38e33SHelen Koike 340f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 341f9f38e33SHelen Koike { 342f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 343f9f38e33SHelen Koike } 344f9f38e33SHelen Koike 345f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 346f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 347f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 348f9f38e33SHelen Koike { 349f9f38e33SHelen Koike if (dbbuf_db) { 350f9f38e33SHelen Koike u16 old_value; 351f9f38e33SHelen Koike 352f9f38e33SHelen Koike /* 353f9f38e33SHelen Koike * Ensure that the queue is written before updating 354f9f38e33SHelen Koike * the doorbell in memory 355f9f38e33SHelen Koike */ 356f9f38e33SHelen Koike wmb(); 357f9f38e33SHelen Koike 358f9f38e33SHelen Koike old_value = *dbbuf_db; 359f9f38e33SHelen Koike *dbbuf_db = value; 360f9f38e33SHelen Koike 361f1ed3df2SMichal Wnukowski /* 362f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 363f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 364f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 365f1ed3df2SMichal Wnukowski * the doorbell. 366f1ed3df2SMichal Wnukowski */ 367f1ed3df2SMichal Wnukowski mb(); 368f1ed3df2SMichal Wnukowski 369f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 370f9f38e33SHelen Koike return false; 371f9f38e33SHelen Koike } 372f9f38e33SHelen Koike 373f9f38e33SHelen Koike return true; 37457dacad5SJay Sternberg } 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg /* 37757dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37857dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37957dacad5SJay Sternberg * the I/O. 38057dacad5SJay Sternberg */ 381b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 38257dacad5SJay Sternberg { 383b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3846c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 38557dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38657dacad5SJay Sternberg } 38757dacad5SJay Sternberg 388a7a7cbe3SChaitanya Kulkarni /* 389a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 390a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 391a7a7cbe3SChaitanya Kulkarni */ 392b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 393f4800d6dSChristoph Hellwig { 394b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 395b13c6393SChaitanya Kulkarni PAGE_SIZE); 396f4800d6dSChristoph Hellwig } 397f4800d6dSChristoph Hellwig 39857dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39957dacad5SJay Sternberg unsigned int hctx_idx) 40057dacad5SJay Sternberg { 40157dacad5SJay Sternberg struct nvme_dev *dev = data; 402147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40357dacad5SJay Sternberg 40457dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40557dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40657dacad5SJay Sternberg 40757dacad5SJay Sternberg hctx->driver_data = nvmeq; 40857dacad5SJay Sternberg return 0; 40957dacad5SJay Sternberg } 41057dacad5SJay Sternberg 41157dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41257dacad5SJay Sternberg unsigned int hctx_idx) 41357dacad5SJay Sternberg { 41457dacad5SJay Sternberg struct nvme_dev *dev = data; 415147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41657dacad5SJay Sternberg 41757dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41857dacad5SJay Sternberg hctx->driver_data = nvmeq; 41957dacad5SJay Sternberg return 0; 42057dacad5SJay Sternberg } 42157dacad5SJay Sternberg 422e559398fSChristoph Hellwig static int nvme_pci_init_request(struct blk_mq_tag_set *set, 423e559398fSChristoph Hellwig struct request *req, unsigned int hctx_idx, 424e559398fSChristoph Hellwig unsigned int numa_node) 42557dacad5SJay Sternberg { 426d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 427f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 42859e29ce6SSagi Grimberg 42959e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 430f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 43157dacad5SJay Sternberg return 0; 43257dacad5SJay Sternberg } 43357dacad5SJay Sternberg 4343b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4353b6592f7SJens Axboe { 4363b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4373b6592f7SJens Axboe if (dev->num_vecs > 1) 4383b6592f7SJens Axboe return 1; 4393b6592f7SJens Axboe 4403b6592f7SJens Axboe return 0; 4413b6592f7SJens Axboe } 4423b6592f7SJens Axboe 443a4e1d0b7SBart Van Assche static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 444dca51e78SChristoph Hellwig { 445dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4463b6592f7SJens Axboe int i, qoff, offset; 447dca51e78SChristoph Hellwig 4483b6592f7SJens Axboe offset = queue_irq_offset(dev); 4493b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4503b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4513b6592f7SJens Axboe 4523b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4533b6592f7SJens Axboe if (!map->nr_queues) { 454e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4557e849dd9SChristoph Hellwig continue; 4563b6592f7SJens Axboe } 4573b6592f7SJens Axboe 4584b04cc6aSJens Axboe /* 4594b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4604b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4614b04cc6aSJens Axboe */ 4623b6592f7SJens Axboe map->queue_offset = qoff; 463cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4643b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4654b04cc6aSJens Axboe else 4664b04cc6aSJens Axboe blk_mq_map_queues(map); 4673b6592f7SJens Axboe qoff += map->nr_queues; 4683b6592f7SJens Axboe offset += map->nr_queues; 4693b6592f7SJens Axboe } 470dca51e78SChristoph Hellwig } 471dca51e78SChristoph Hellwig 47238210800SKeith Busch /* 47338210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47438210800SKeith Busch */ 47538210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47604f3eafdSJens Axboe { 47738210800SKeith Busch if (!write_sq) { 47838210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 47938210800SKeith Busch 48038210800SKeith Busch if (next_tail == nvmeq->q_depth) 48138210800SKeith Busch next_tail = 0; 48238210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 48338210800SKeith Busch return; 48438210800SKeith Busch } 48538210800SKeith Busch 48604f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 48704f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 48804f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 48938210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 49004f3eafdSJens Axboe } 49104f3eafdSJens Axboe 4923233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 4933233b94cSJens Axboe struct nvme_command *cmd) 49457dacad5SJay Sternberg { 495c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 4963233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 49790ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 49890ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 49904f3eafdSJens Axboe } 50004f3eafdSJens Axboe 50104f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 50204f3eafdSJens Axboe { 50304f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 50404f3eafdSJens Axboe 50504f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 50638210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 50738210800SKeith Busch nvme_write_sq_db(nvmeq, true); 50890ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 50957dacad5SJay Sternberg } 51057dacad5SJay Sternberg 511a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 51257dacad5SJay Sternberg { 513f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 51491fb2b60SLogan Gunthorpe return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req)); 51557dacad5SJay Sternberg } 51657dacad5SJay Sternberg 517955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 518955b1b5aSMinwoo Im { 519a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 52020469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 521955b1b5aSMinwoo Im unsigned int avg_seg_size; 522955b1b5aSMinwoo Im 52320469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 524955b1b5aSMinwoo Im 525253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 526955b1b5aSMinwoo Im return false; 527a53232cbSKeith Busch if (!nvmeq->qid) 528955b1b5aSMinwoo Im return false; 529955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 530955b1b5aSMinwoo Im return false; 531955b1b5aSMinwoo Im return true; 532955b1b5aSMinwoo Im } 533955b1b5aSMinwoo Im 5349275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 53557dacad5SJay Sternberg { 5366c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5379275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5389275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 53957dacad5SJay Sternberg int i; 54057dacad5SJay Sternberg 541c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 5429275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5439275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5449275c206SChristoph Hellwig 5459275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5469275c206SChristoph Hellwig dma_addr = next_dma_addr; 547dff824b2SChristoph Hellwig } 5489275c206SChristoph Hellwig } 5499275c206SChristoph Hellwig 5509275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5519275c206SChristoph Hellwig { 5529275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5539275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5549275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5559275c206SChristoph Hellwig int i; 5569275c206SChristoph Hellwig 557c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 5589275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5599275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5609275c206SChristoph Hellwig 5619275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5629275c206SChristoph Hellwig dma_addr = next_dma_addr; 5639275c206SChristoph Hellwig } 5649275c206SChristoph Hellwig } 5659275c206SChristoph Hellwig 5669275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5679275c206SChristoph Hellwig { 5689275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5697fe07d14SChristoph Hellwig 5709275c206SChristoph Hellwig if (iod->dma_len) { 5719275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5729275c206SChristoph Hellwig rq_dma_dir(req)); 5739275c206SChristoph Hellwig return; 5749275c206SChristoph Hellwig } 5759275c206SChristoph Hellwig 57691fb2b60SLogan Gunthorpe WARN_ON_ONCE(!iod->sgt.nents); 5779275c206SChristoph Hellwig 57891fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 57991fb2b60SLogan Gunthorpe 580c372cdd1SKeith Busch if (iod->nr_allocations == 0) 581a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 5829275c206SChristoph Hellwig iod->first_dma); 5839275c206SChristoph Hellwig else if (iod->use_sgl) 5849275c206SChristoph Hellwig nvme_free_sgls(dev, req); 5859275c206SChristoph Hellwig else 5869275c206SChristoph Hellwig nvme_free_prps(dev, req); 58791fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 58857dacad5SJay Sternberg } 58957dacad5SJay Sternberg 590d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 591d0877473SKeith Busch { 592d0877473SKeith Busch int i; 593d0877473SKeith Busch struct scatterlist *sg; 594d0877473SKeith Busch 595d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 596d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 597d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 598d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 599d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 600d0877473SKeith Busch sg_dma_len(sg)); 601d0877473SKeith Busch } 602d0877473SKeith Busch } 603d0877473SKeith Busch 604a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 605a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 60657dacad5SJay Sternberg { 607f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 60857dacad5SJay Sternberg struct dma_pool *pool; 609b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 61091fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 61157dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 61257dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6136c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 61457dacad5SJay Sternberg __le64 *prp_list; 615a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 61657dacad5SJay Sternberg dma_addr_t prp_dma; 61757dacad5SJay Sternberg int nprps, i; 61857dacad5SJay Sternberg 6196c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6205228b328SJan H. Schönherr if (length <= 0) { 6215228b328SJan H. Schönherr iod->first_dma = 0; 622a7a7cbe3SChaitanya Kulkarni goto done; 6235228b328SJan H. Schönherr } 62457dacad5SJay Sternberg 6256c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 62657dacad5SJay Sternberg if (dma_len) { 6276c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 62857dacad5SJay Sternberg } else { 62957dacad5SJay Sternberg sg = sg_next(sg); 63057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 63157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 63257dacad5SJay Sternberg } 63357dacad5SJay Sternberg 6346c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 63557dacad5SJay Sternberg iod->first_dma = dma_addr; 636a7a7cbe3SChaitanya Kulkarni goto done; 63757dacad5SJay Sternberg } 63857dacad5SJay Sternberg 6396c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 64057dacad5SJay Sternberg if (nprps <= (256 / 8)) { 64157dacad5SJay Sternberg pool = dev->prp_small_pool; 642c372cdd1SKeith Busch iod->nr_allocations = 0; 64357dacad5SJay Sternberg } else { 64457dacad5SJay Sternberg pool = dev->prp_page_pool; 645c372cdd1SKeith Busch iod->nr_allocations = 1; 64657dacad5SJay Sternberg } 64757dacad5SJay Sternberg 64869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 64957dacad5SJay Sternberg if (!prp_list) { 650c372cdd1SKeith Busch iod->nr_allocations = -1; 65186eea289SKeith Busch return BLK_STS_RESOURCE; 65257dacad5SJay Sternberg } 65357dacad5SJay Sternberg list[0] = prp_list; 65457dacad5SJay Sternberg iod->first_dma = prp_dma; 65557dacad5SJay Sternberg i = 0; 65657dacad5SJay Sternberg for (;;) { 6576c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 65857dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 65969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 66057dacad5SJay Sternberg if (!prp_list) 661fa073216SChristoph Hellwig goto free_prps; 662c372cdd1SKeith Busch list[iod->nr_allocations++] = prp_list; 66357dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 66457dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 66557dacad5SJay Sternberg i = 1; 66657dacad5SJay Sternberg } 66757dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6686c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6696c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6706c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 67157dacad5SJay Sternberg if (length <= 0) 67257dacad5SJay Sternberg break; 67357dacad5SJay Sternberg if (dma_len > 0) 67457dacad5SJay Sternberg continue; 67586eea289SKeith Busch if (unlikely(dma_len < 0)) 67686eea289SKeith Busch goto bad_sgl; 67757dacad5SJay Sternberg sg = sg_next(sg); 67857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 67957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 68057dacad5SJay Sternberg } 681a7a7cbe3SChaitanya Kulkarni done: 68291fb2b60SLogan Gunthorpe cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 683a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 68486eea289SKeith Busch return BLK_STS_OK; 685fa073216SChristoph Hellwig free_prps: 686fa073216SChristoph Hellwig nvme_free_prps(dev, req); 687fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 68886eea289SKeith Busch bad_sgl: 68991fb2b60SLogan Gunthorpe WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 690d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 69191fb2b60SLogan Gunthorpe blk_rq_payload_bytes(req), iod->sgt.nents); 69286eea289SKeith Busch return BLK_STS_IOERR; 69357dacad5SJay Sternberg } 69457dacad5SJay Sternberg 695a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 696a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 697a7a7cbe3SChaitanya Kulkarni { 698a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 699a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 700a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 701a7a7cbe3SChaitanya Kulkarni } 702a7a7cbe3SChaitanya Kulkarni 703a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 704a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 705a7a7cbe3SChaitanya Kulkarni { 706a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 707a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 708a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 709a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 710a7a7cbe3SChaitanya Kulkarni } else { 711a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 712a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 713a7a7cbe3SChaitanya Kulkarni } 714a7a7cbe3SChaitanya Kulkarni } 715a7a7cbe3SChaitanya Kulkarni 716a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 71791fb2b60SLogan Gunthorpe struct request *req, struct nvme_rw_command *cmd) 718a7a7cbe3SChaitanya Kulkarni { 719a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 720a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 721a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 72291fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 72391fb2b60SLogan Gunthorpe unsigned int entries = iod->sgt.nents; 724a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 725b0f2853bSChristoph Hellwig int i = 0; 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 728a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 729a7a7cbe3SChaitanya Kulkarni 730b0f2853bSChristoph Hellwig if (entries == 1) { 731a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 732a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 733a7a7cbe3SChaitanya Kulkarni } 734a7a7cbe3SChaitanya Kulkarni 735a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 736a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 737c372cdd1SKeith Busch iod->nr_allocations = 0; 738a7a7cbe3SChaitanya Kulkarni } else { 739a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 740c372cdd1SKeith Busch iod->nr_allocations = 1; 741a7a7cbe3SChaitanya Kulkarni } 742a7a7cbe3SChaitanya Kulkarni 743a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 744a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 745c372cdd1SKeith Busch iod->nr_allocations = -1; 746a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 747a7a7cbe3SChaitanya Kulkarni } 748a7a7cbe3SChaitanya Kulkarni 749a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 750a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 751a7a7cbe3SChaitanya Kulkarni 752a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 753a7a7cbe3SChaitanya Kulkarni 754a7a7cbe3SChaitanya Kulkarni do { 755a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 756a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 757a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 758a7a7cbe3SChaitanya Kulkarni 759a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 760a7a7cbe3SChaitanya Kulkarni if (!sg_list) 761fa073216SChristoph Hellwig goto free_sgls; 762a7a7cbe3SChaitanya Kulkarni 763a7a7cbe3SChaitanya Kulkarni i = 0; 764c372cdd1SKeith Busch nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list; 765a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 766a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 767a7a7cbe3SChaitanya Kulkarni } 768a7a7cbe3SChaitanya Kulkarni 769a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 770a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 771b0f2853bSChristoph Hellwig } while (--entries > 0); 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 774fa073216SChristoph Hellwig free_sgls: 775fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 776fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 777a7a7cbe3SChaitanya Kulkarni } 778a7a7cbe3SChaitanya Kulkarni 779dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 780dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 781dff824b2SChristoph Hellwig struct bio_vec *bv) 782dff824b2SChristoph Hellwig { 783dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7846c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7856c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 786dff824b2SChristoph Hellwig 787dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 788dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 789dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 790dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 791dff824b2SChristoph Hellwig 792dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 793dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 794dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 795359c1f88SBaolin Wang return BLK_STS_OK; 796dff824b2SChristoph Hellwig } 797dff824b2SChristoph Hellwig 79829791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 79929791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 80029791057SChristoph Hellwig struct bio_vec *bv) 80129791057SChristoph Hellwig { 80229791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 80329791057SChristoph Hellwig 80429791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 80529791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 80629791057SChristoph Hellwig return BLK_STS_RESOURCE; 80729791057SChristoph Hellwig iod->dma_len = bv->bv_len; 80829791057SChristoph Hellwig 809049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 81029791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 81129791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 81229791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 813359c1f88SBaolin Wang return BLK_STS_OK; 81429791057SChristoph Hellwig } 81529791057SChristoph Hellwig 816fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 817b131c61dSChristoph Hellwig struct nvme_command *cmnd) 81857dacad5SJay Sternberg { 819f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82070479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 82191fb2b60SLogan Gunthorpe int rc; 82257dacad5SJay Sternberg 823dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 824a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 825dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 826dff824b2SChristoph Hellwig 827dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8286c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 829dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 830dff824b2SChristoph Hellwig &cmnd->rw, &bv); 83129791057SChristoph Hellwig 832a53232cbSKeith Busch if (nvmeq->qid && sgl_threshold && 833253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 83429791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 83529791057SChristoph Hellwig &cmnd->rw, &bv); 836dff824b2SChristoph Hellwig } 837dff824b2SChristoph Hellwig } 838dff824b2SChristoph Hellwig 839dff824b2SChristoph Hellwig iod->dma_len = 0; 84091fb2b60SLogan Gunthorpe iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 84191fb2b60SLogan Gunthorpe if (!iod->sgt.sgl) 8429b048119SChristoph Hellwig return BLK_STS_RESOURCE; 84391fb2b60SLogan Gunthorpe sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 84491fb2b60SLogan Gunthorpe iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 84591fb2b60SLogan Gunthorpe if (!iod->sgt.orig_nents) 846fa073216SChristoph Hellwig goto out_free_sg; 847ba1ca37eSChristoph Hellwig 84891fb2b60SLogan Gunthorpe rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 84991fb2b60SLogan Gunthorpe DMA_ATTR_NO_WARN); 85091fb2b60SLogan Gunthorpe if (rc) { 85191fb2b60SLogan Gunthorpe if (rc == -EREMOTEIO) 85291fb2b60SLogan Gunthorpe ret = BLK_STS_TARGET; 853fa073216SChristoph Hellwig goto out_free_sg; 85491fb2b60SLogan Gunthorpe } 855ba1ca37eSChristoph Hellwig 85670479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 857955b1b5aSMinwoo Im if (iod->use_sgl) 85891fb2b60SLogan Gunthorpe ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 859a7a7cbe3SChaitanya Kulkarni else 860a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8614aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 862fa073216SChristoph Hellwig goto out_unmap_sg; 863fa073216SChristoph Hellwig return BLK_STS_OK; 864fa073216SChristoph Hellwig 865fa073216SChristoph Hellwig out_unmap_sg: 86691fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 867fa073216SChristoph Hellwig out_free_sg: 86891fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 869ba1ca37eSChristoph Hellwig return ret; 87057dacad5SJay Sternberg } 87157dacad5SJay Sternberg 8724aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8734aedb705SChristoph Hellwig struct nvme_command *cmnd) 8744aedb705SChristoph Hellwig { 8754aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8764aedb705SChristoph Hellwig 8774aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8784aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8794aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8804aedb705SChristoph Hellwig return BLK_STS_IOERR; 8814aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 882359c1f88SBaolin Wang return BLK_STS_OK; 8834aedb705SChristoph Hellwig } 8844aedb705SChristoph Hellwig 88562451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 88662451a2bSJens Axboe { 88762451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 88862451a2bSJens Axboe blk_status_t ret; 88962451a2bSJens Axboe 89052da4f3fSKeith Busch iod->aborted = false; 891c372cdd1SKeith Busch iod->nr_allocations = -1; 89291fb2b60SLogan Gunthorpe iod->sgt.nents = 0; 89362451a2bSJens Axboe 89462451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 89562451a2bSJens Axboe if (ret) 89662451a2bSJens Axboe return ret; 89762451a2bSJens Axboe 89862451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 89962451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 90062451a2bSJens Axboe if (ret) 90162451a2bSJens Axboe goto out_free_cmd; 90262451a2bSJens Axboe } 90362451a2bSJens Axboe 90462451a2bSJens Axboe if (blk_integrity_rq(req)) { 90562451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 90662451a2bSJens Axboe if (ret) 90762451a2bSJens Axboe goto out_unmap_data; 90862451a2bSJens Axboe } 90962451a2bSJens Axboe 910*6887fc64SSagi Grimberg nvme_start_request(req); 91162451a2bSJens Axboe return BLK_STS_OK; 91262451a2bSJens Axboe out_unmap_data: 91362451a2bSJens Axboe nvme_unmap_data(dev, req); 91462451a2bSJens Axboe out_free_cmd: 91562451a2bSJens Axboe nvme_cleanup_cmd(req); 91662451a2bSJens Axboe return ret; 91762451a2bSJens Axboe } 91862451a2bSJens Axboe 91957dacad5SJay Sternberg /* 92057dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 92157dacad5SJay Sternberg */ 922fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 92357dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 92457dacad5SJay Sternberg { 92557dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 92657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 92757dacad5SJay Sternberg struct request *req = bd->rq; 9289b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 929ebe6d874SChristoph Hellwig blk_status_t ret; 93057dacad5SJay Sternberg 931d1f06f4aSJens Axboe /* 932d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 933d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 934d1f06f4aSJens Axboe */ 9354e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 936d1f06f4aSJens Axboe return BLK_STS_IOERR; 937d1f06f4aSJens Axboe 93862451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 939d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 940d4060d2bSTao Chiu 94162451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 94262451a2bSJens Axboe if (unlikely(ret)) 943f4800d6dSChristoph Hellwig return ret; 9443233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 9453233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 9463233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 9473233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 948fc17b653SChristoph Hellwig return BLK_STS_OK; 94957dacad5SJay Sternberg } 95057dacad5SJay Sternberg 951d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 952d62cbcf6SJens Axboe { 953d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 954d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 955d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 956d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 957d62cbcf6SJens Axboe 958d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 959d62cbcf6SJens Axboe } 960d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 961d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 962d62cbcf6SJens Axboe } 963d62cbcf6SJens Axboe 964d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 965d62cbcf6SJens Axboe { 966d62cbcf6SJens Axboe /* 967d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 968d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 969d62cbcf6SJens Axboe */ 970d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 971d62cbcf6SJens Axboe return false; 972d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 973d62cbcf6SJens Axboe return false; 974d62cbcf6SJens Axboe 975d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 976d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 977d62cbcf6SJens Axboe } 978d62cbcf6SJens Axboe 979d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 980d62cbcf6SJens Axboe { 9816bfec799SKeith Busch struct request *req, *next, *prev = NULL; 982d62cbcf6SJens Axboe struct request *requeue_list = NULL; 983d62cbcf6SJens Axboe 9846bfec799SKeith Busch rq_list_for_each_safe(rqlist, req, next) { 985d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 986d62cbcf6SJens Axboe 987d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 988d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 9896bfec799SKeith Busch rq_list_move(rqlist, &requeue_list, req, prev); 9906bfec799SKeith Busch 9916bfec799SKeith Busch req = prev; 9926bfec799SKeith Busch if (!req) 9936bfec799SKeith Busch continue; 994d62cbcf6SJens Axboe } 995d62cbcf6SJens Axboe 9966bfec799SKeith Busch if (!next || req->mq_hctx != next->mq_hctx) { 997d62cbcf6SJens Axboe /* detach rest of list, and submit */ 9986bfec799SKeith Busch req->rq_next = NULL; 999d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 10006bfec799SKeith Busch *rqlist = next; 10016bfec799SKeith Busch prev = NULL; 10026bfec799SKeith Busch } else 10036bfec799SKeith Busch prev = req; 1004d62cbcf6SJens Axboe } 1005d62cbcf6SJens Axboe 1006d62cbcf6SJens Axboe *rqlist = requeue_list; 1007d62cbcf6SJens Axboe } 1008d62cbcf6SJens Axboe 1009c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 1010eee417b0SChristoph Hellwig { 1011a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1012a53232cbSKeith Busch struct nvme_dev *dev = nvmeq->dev; 1013eee417b0SChristoph Hellwig 1014a53232cbSKeith Busch if (blk_integrity_rq(req)) { 1015a53232cbSKeith Busch struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1016a53232cbSKeith Busch 10174aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 10184aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1019a53232cbSKeith Busch } 1020a53232cbSKeith Busch 1021b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 10224aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 1023c234a653SJens Axboe } 1024c234a653SJens Axboe 1025c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 1026c234a653SJens Axboe { 1027c234a653SJens Axboe nvme_pci_unmap_rq(req); 102877f02a7aSChristoph Hellwig nvme_complete_rq(req); 102957dacad5SJay Sternberg } 103057dacad5SJay Sternberg 1031c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1032c234a653SJens Axboe { 1033c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 1034c234a653SJens Axboe } 1035c234a653SJens Axboe 1036d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 1037750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1038d783e0bdSMarta Rybczynska { 103974943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 104074943d45SKeith Busch 104174943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1042d783e0bdSMarta Rybczynska } 1043d783e0bdSMarta Rybczynska 1044eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 104557dacad5SJay Sternberg { 1046eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 104757dacad5SJay Sternberg 1048eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1049eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1050eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1051eb281c82SSagi Grimberg } 1052adf68f21SChristoph Hellwig 1053cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1054cfa27356SChristoph Hellwig { 1055cfa27356SChristoph Hellwig if (!nvmeq->qid) 1056cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1057cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1058cfa27356SChristoph Hellwig } 1059cfa27356SChristoph Hellwig 1060c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1061c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 106257dacad5SJay Sternberg { 106374943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 106462df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 106557dacad5SJay Sternberg struct request *req; 1066adf68f21SChristoph Hellwig 1067adf68f21SChristoph Hellwig /* 1068adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1069adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1070adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1071adf68f21SChristoph Hellwig * for them but rather special case them here. 1072adf68f21SChristoph Hellwig */ 107362df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10747bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 107583a12fb7SSagi Grimberg cqe->status, &cqe->result); 1076a0fa9647SJens Axboe return; 107757dacad5SJay Sternberg } 107857dacad5SJay Sternberg 1079e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 108050b7c243SXianting Tian if (unlikely(!req)) { 108150b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 108250b7c243SXianting Tian "invalid id %d completed on queue %d\n", 108362df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 108450b7c243SXianting Tian return; 108550b7c243SXianting Tian } 108650b7c243SXianting Tian 1087604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1088c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1089c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1090c234a653SJens Axboe nvme_pci_complete_batch)) 1091ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 109283a12fb7SSagi Grimberg } 109357dacad5SJay Sternberg 10945cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10955cb525c8SJens Axboe { 1096a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1097a8de6639SAlexey Dobriyan 1098a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1099920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1100e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1101a8de6639SAlexey Dobriyan } else { 1102a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1103920d13a8SSagi Grimberg } 1104a0fa9647SJens Axboe } 1105a0fa9647SJens Axboe 1106c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1107c234a653SJens Axboe struct io_comp_batch *iob) 1108a0fa9647SJens Axboe { 11091052b8acSJens Axboe int found = 0; 111083a12fb7SSagi Grimberg 11111052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 11121052b8acSJens Axboe found++; 1113b69e2ef2SKeith Busch /* 1114b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1115b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1116b69e2ef2SKeith Busch */ 1117b69e2ef2SKeith Busch dma_rmb(); 1118c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 11195cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 112057dacad5SJay Sternberg } 112157dacad5SJay Sternberg 1122324b494cSKeith Busch if (found) 1123eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 11245cb525c8SJens Axboe return found; 112557dacad5SJay Sternberg } 112657dacad5SJay Sternberg 112757dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 112857dacad5SJay Sternberg { 112957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11304f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 11315cb525c8SJens Axboe 11324f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 11334f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 11344f502245SJens Axboe nvme_pci_complete_batch(&iob); 113505fae499SChaitanya Kulkarni return IRQ_HANDLED; 11364f502245SJens Axboe } 113705fae499SChaitanya Kulkarni return IRQ_NONE; 113857dacad5SJay Sternberg } 113957dacad5SJay Sternberg 114057dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 114157dacad5SJay Sternberg { 114257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11434e523547SBaolin Wang 1144750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 114557dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1146d783e0bdSMarta Rybczynska return IRQ_NONE; 114757dacad5SJay Sternberg } 114857dacad5SJay Sternberg 11490b2a8a9fSChristoph Hellwig /* 1150fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11510b2a8a9fSChristoph Hellwig * Can be called from any context. 11520b2a8a9fSChristoph Hellwig */ 1153fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1154a0fa9647SJens Axboe { 11553a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1156a0fa9647SJens Axboe 1157fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1158fa059b85SKeith Busch 11593a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1160c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11613a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 116291a509f8SChristoph Hellwig } 1163442e19b7SSagi Grimberg 11645a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11657776db1cSKeith Busch { 11667776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1167dabcefabSJens Axboe bool found; 1168dabcefabSJens Axboe 1169dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1170dabcefabSJens Axboe return 0; 1171dabcefabSJens Axboe 11723a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1173c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11743a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1175dabcefabSJens Axboe 1176dabcefabSJens Axboe return found; 1177dabcefabSJens Axboe } 1178dabcefabSJens Axboe 1179ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 118057dacad5SJay Sternberg { 1181f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1182147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1183f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 118457dacad5SJay Sternberg 118557dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1186ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 11873233b94cSJens Axboe 11883233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 11893233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 11903233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 11913233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 119257dacad5SJay Sternberg } 119357dacad5SJay Sternberg 119457dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 119557dacad5SJay Sternberg { 1196f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 119757dacad5SJay Sternberg 119857dacad5SJay Sternberg c.delete_queue.opcode = opcode; 119957dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 120057dacad5SJay Sternberg 12011c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120257dacad5SJay Sternberg } 120357dacad5SJay Sternberg 120457dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1205a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 120657dacad5SJay Sternberg { 1207f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 12084b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 12094b04cc6aSJens Axboe 12107c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 12114b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 121257dacad5SJay Sternberg 121357dacad5SJay Sternberg /* 121416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 121557dacad5SJay Sternberg * is attached to the request. 121657dacad5SJay Sternberg */ 121757dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 121857dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 121957dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 122057dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 122157dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1222a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 122357dacad5SJay Sternberg 12241c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 122557dacad5SJay Sternberg } 122657dacad5SJay Sternberg 122757dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 122857dacad5SJay Sternberg struct nvme_queue *nvmeq) 122957dacad5SJay Sternberg { 12309abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1231f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 123281c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 123357dacad5SJay Sternberg 123457dacad5SJay Sternberg /* 12359abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 12369abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 12379abd68efSJens Axboe * URGENT. 12389abd68efSJens Axboe */ 12399abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 12409abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 12419abd68efSJens Axboe 12429abd68efSJens Axboe /* 124316772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 124457dacad5SJay Sternberg * is attached to the request. 124557dacad5SJay Sternberg */ 124657dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 124757dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 124857dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 124957dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 125057dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 125157dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 125257dacad5SJay Sternberg 12531c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 125457dacad5SJay Sternberg } 125557dacad5SJay Sternberg 125657dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 125757dacad5SJay Sternberg { 125857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 125957dacad5SJay Sternberg } 126057dacad5SJay Sternberg 126157dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 126257dacad5SJay Sternberg { 126357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 126457dacad5SJay Sternberg } 126557dacad5SJay Sternberg 1266de671d61SJens Axboe static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 126757dacad5SJay Sternberg { 1268a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 126957dacad5SJay Sternberg 127027fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 127127fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1272e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1273e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 1274de671d61SJens Axboe return RQ_END_IO_NONE; 127557dacad5SJay Sternberg } 127657dacad5SJay Sternberg 1277b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1278b2a0eb1aSKeith Busch { 1279b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1280b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1281b2a0eb1aSKeith Busch */ 1282b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1283b2a0eb1aSKeith Busch 1284ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1285ad70062cSJianchao Wang switch (dev->ctrl.state) { 1286ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1287ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1288b2a0eb1aSKeith Busch return false; 1289ad70062cSJianchao Wang default: 1290ad70062cSJianchao Wang break; 1291ad70062cSJianchao Wang } 1292b2a0eb1aSKeith Busch 1293b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1294b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1295b2a0eb1aSKeith Busch */ 1296b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1297b2a0eb1aSKeith Busch return false; 1298b2a0eb1aSKeith Busch 1299b2a0eb1aSKeith Busch return true; 1300b2a0eb1aSKeith Busch } 1301b2a0eb1aSKeith Busch 1302b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1303b2a0eb1aSKeith Busch { 1304b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1305b2a0eb1aSKeith Busch u16 pci_status; 1306b2a0eb1aSKeith Busch int result; 1307b2a0eb1aSKeith Busch 1308b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1309b2a0eb1aSKeith Busch &pci_status); 1310b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1311b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1312b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1313b2a0eb1aSKeith Busch csts, pci_status); 1314b2a0eb1aSKeith Busch else 1315b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1316b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1317b2a0eb1aSKeith Busch csts, result); 13184641a8e6SKeith Busch 13194641a8e6SKeith Busch if (csts != ~0) 13204641a8e6SKeith Busch return; 13214641a8e6SKeith Busch 13224641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13234641a8e6SKeith Busch "Does your device have a faulty power saving mode enabled?\n"); 13244641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13254641a8e6SKeith Busch "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1326b2a0eb1aSKeith Busch } 1327b2a0eb1aSKeith Busch 13289bdb4833SJohn Garry static enum blk_eh_timer_return nvme_timeout(struct request *req) 132957dacad5SJay Sternberg { 1330f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1331a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 133257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 133357dacad5SJay Sternberg struct request *abort_req; 1334f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1335b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1336b2a0eb1aSKeith Busch 1337651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1338651438bbSWen Xiong * the recovery mechanism will surely fail. 1339651438bbSWen Xiong */ 1340651438bbSWen Xiong mb(); 1341651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1342651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1343651438bbSWen Xiong 1344b2a0eb1aSKeith Busch /* 1345b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1346b2a0eb1aSKeith Busch */ 1347b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1348b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1349b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1350d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1351db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1352b2a0eb1aSKeith Busch } 135357dacad5SJay Sternberg 135431c7c7d2SChristoph Hellwig /* 13557776db1cSKeith Busch * Did we miss an interrupt? 13567776db1cSKeith Busch */ 1357fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13585a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1359fa059b85SKeith Busch else 1360bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1361fa059b85SKeith Busch 1362bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 13637776db1cSKeith Busch dev_warn(dev->ctrl.device, 13647776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13657776db1cSKeith Busch req->tag, nvmeq->qid); 1366db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13677776db1cSKeith Busch } 13687776db1cSKeith Busch 13697776db1cSKeith Busch /* 1370fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1371fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1372fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1373db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1374fd634f41SChristoph Hellwig */ 13754244140dSKeith Busch switch (dev->ctrl.state) { 13764244140dSKeith Busch case NVME_CTRL_CONNECTING: 13772036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1378df561f66SGustavo A. R. Silva fallthrough; 13792036f726SKeith Busch case NVME_CTRL_DELETING: 1380b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1381fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1382fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 138327fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13847ad92f65STong Zhang nvme_dev_disable(dev, true); 1385db8c48e4SChristoph Hellwig return BLK_EH_DONE; 138639a9dd81SKeith Busch case NVME_CTRL_RESETTING: 138739a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13884244140dSKeith Busch default: 13894244140dSKeith Busch break; 1390fd634f41SChristoph Hellwig } 1391fd634f41SChristoph Hellwig 1392fd634f41SChristoph Hellwig /* 1393e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1394e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1395e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 139631c7c7d2SChristoph Hellwig */ 1397f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13981b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 139957dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 140057dacad5SJay Sternberg req->tag, nvmeq->qid); 14017ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1402a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1403d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1404e1569a16SKeith Busch 1405db8c48e4SChristoph Hellwig return BLK_EH_DONE; 140657dacad5SJay Sternberg } 140757dacad5SJay Sternberg 1408e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1409e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1410e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1411e7a2a87dSChristoph Hellwig } 141252da4f3fSKeith Busch iod->aborted = true; 141357dacad5SJay Sternberg 141457dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 141585f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 141657dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 141757dacad5SJay Sternberg 14181b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 141986141440SChristoph Hellwig "I/O %d (%s) QID %d timeout, aborting\n", 142086141440SChristoph Hellwig req->tag, 142186141440SChristoph Hellwig nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 142286141440SChristoph Hellwig nvmeq->qid); 1423e7a2a87dSChristoph Hellwig 1424e559398fSChristoph Hellwig abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 142539dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 14266bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 14276bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 142831c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 142957dacad5SJay Sternberg } 1430e559398fSChristoph Hellwig nvme_init_request(abort_req, &cmd); 143157dacad5SJay Sternberg 1432e2e53086SChristoph Hellwig abort_req->end_io = abort_endio; 1433e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1434128126a7SChaitanya Kulkarni abort_req->rq_flags |= RQF_QUIET; 1435e2e53086SChristoph Hellwig blk_execute_rq_nowait(abort_req, false); 143657dacad5SJay Sternberg 143757dacad5SJay Sternberg /* 143857dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 143957dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 144057dacad5SJay Sternberg * as the device then is in a faulty state. 144157dacad5SJay Sternberg */ 144257dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 144357dacad5SJay Sternberg } 144457dacad5SJay Sternberg 144557dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 144657dacad5SJay Sternberg { 14478a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 144857dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 144963223078SChristoph Hellwig if (!nvmeq->sq_cmds) 145063223078SChristoph Hellwig return; 14510f238ff5SLogan Gunthorpe 145263223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 145388a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14548a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 145563223078SChristoph Hellwig } else { 14568a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 145763223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14580f238ff5SLogan Gunthorpe } 145957dacad5SJay Sternberg } 146057dacad5SJay Sternberg 146157dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 146257dacad5SJay Sternberg { 146357dacad5SJay Sternberg int i; 146457dacad5SJay Sternberg 1465d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1466d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1467147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 146857dacad5SJay Sternberg } 146957dacad5SJay Sternberg } 147057dacad5SJay Sternberg 147157dacad5SJay Sternberg /** 147257dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 147340581d1aSBart Van Assche * @nvmeq: queue to suspend 147457dacad5SJay Sternberg */ 147557dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 147657dacad5SJay Sternberg { 14774e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 147857dacad5SJay Sternberg return 1; 147957dacad5SJay Sternberg 14804e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1481d1f06f4aSJens Axboe mb(); 148257dacad5SJay Sternberg 14834e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14841c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 14859f27bd70SChristoph Hellwig nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); 14867c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14874e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 148857dacad5SJay Sternberg return 0; 148957dacad5SJay Sternberg } 149057dacad5SJay Sternberg 14918fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14928fae268bSKeith Busch { 14938fae268bSKeith Busch int i; 14948fae268bSKeith Busch 14958fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14968fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14978fae268bSKeith Busch } 14988fae268bSKeith Busch 1499a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 150057dacad5SJay Sternberg { 1501147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 150257dacad5SJay Sternberg 1503a5cdb68cSKeith Busch if (shutdown) 1504a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1505a5cdb68cSKeith Busch else 1506b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 150757dacad5SJay Sternberg 1508bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 150957dacad5SJay Sternberg } 151057dacad5SJay Sternberg 1511fa46c6fbSKeith Busch /* 1512fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 15139210c075SDongli Zhang * that can check this device's completion queues have synced, except 15149210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 15159210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1516fa46c6fbSKeith Busch */ 1517fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1518fa46c6fbSKeith Busch { 1519fa46c6fbSKeith Busch int i; 1520fa46c6fbSKeith Busch 15219210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 15229210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1523c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 15249210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 15259210c075SDongli Zhang } 1526fa46c6fbSKeith Busch } 1527fa46c6fbSKeith Busch 152857dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 152957dacad5SJay Sternberg int entry_size) 153057dacad5SJay Sternberg { 153157dacad5SJay Sternberg int q_depth = dev->q_depth; 15325fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 15336c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 153457dacad5SJay Sternberg 153557dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 153657dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 15374e523547SBaolin Wang 15386c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 153957dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 154057dacad5SJay Sternberg 154157dacad5SJay Sternberg /* 154257dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 154357dacad5SJay Sternberg * would be better to map queues in system memory with the 154457dacad5SJay Sternberg * original depth 154557dacad5SJay Sternberg */ 154657dacad5SJay Sternberg if (q_depth < 64) 154757dacad5SJay Sternberg return -ENOMEM; 154857dacad5SJay Sternberg } 154957dacad5SJay Sternberg 155057dacad5SJay Sternberg return q_depth; 155157dacad5SJay Sternberg } 155257dacad5SJay Sternberg 155357dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 15548a1d09a6SBenjamin Herrenschmidt int qid) 155557dacad5SJay Sternberg { 15560f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1557815c6704SKeith Busch 15580f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 15598a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1560bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15610f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15620f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 156363223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 156463223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 156563223078SChristoph Hellwig return 0; 156663223078SChristoph Hellwig } 1567bfac8e9fSAlan Mikhak 15688a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1569bfac8e9fSAlan Mikhak } 15700f238ff5SLogan Gunthorpe } 15710f238ff5SLogan Gunthorpe 15728a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 157357dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 157457dacad5SJay Sternberg if (!nvmeq->sq_cmds) 157557dacad5SJay Sternberg return -ENOMEM; 157657dacad5SJay Sternberg return 0; 157757dacad5SJay Sternberg } 157857dacad5SJay Sternberg 1579a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 158057dacad5SJay Sternberg { 1581147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 158257dacad5SJay Sternberg 158362314e40SKeith Busch if (dev->ctrl.queue_count > qid) 158462314e40SKeith Busch return 0; 158557dacad5SJay Sternberg 1586c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15878a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15888a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 158957dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 159057dacad5SJay Sternberg if (!nvmeq->cqes) 159157dacad5SJay Sternberg goto free_nvmeq; 159257dacad5SJay Sternberg 15938a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 159457dacad5SJay Sternberg goto free_cqdma; 159557dacad5SJay Sternberg 159657dacad5SJay Sternberg nvmeq->dev = dev; 15971ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15983a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 159957dacad5SJay Sternberg nvmeq->cq_head = 0; 160057dacad5SJay Sternberg nvmeq->cq_phase = 1; 160157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 160257dacad5SJay Sternberg nvmeq->qid = qid; 1603d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 160457dacad5SJay Sternberg 1605147b27e4SSagi Grimberg return 0; 160657dacad5SJay Sternberg 160757dacad5SJay Sternberg free_cqdma: 16088a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 160957dacad5SJay Sternberg nvmeq->cq_dma_addr); 161057dacad5SJay Sternberg free_nvmeq: 1611147b27e4SSagi Grimberg return -ENOMEM; 161257dacad5SJay Sternberg } 161357dacad5SJay Sternberg 1614dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 161557dacad5SJay Sternberg { 16160ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 16170ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 16180ff199cbSChristoph Hellwig 16190ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 16200ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 16210ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16220ff199cbSChristoph Hellwig } else { 16230ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 16240ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16250ff199cbSChristoph Hellwig } 162657dacad5SJay Sternberg } 162757dacad5SJay Sternberg 162857dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 162957dacad5SJay Sternberg { 163057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 163157dacad5SJay Sternberg 163257dacad5SJay Sternberg nvmeq->sq_tail = 0; 163338210800SKeith Busch nvmeq->last_sq_tail = 0; 163457dacad5SJay Sternberg nvmeq->cq_head = 0; 163557dacad5SJay Sternberg nvmeq->cq_phase = 1; 163657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 16378a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1638f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 163957dacad5SJay Sternberg dev->online_queues++; 16403a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 164157dacad5SJay Sternberg } 164257dacad5SJay Sternberg 1643e4b9852aSCasey Chen /* 1644e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1645e4b9852aSCasey Chen */ 1646e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1647e4b9852aSCasey Chen { 1648e4b9852aSCasey Chen /* 1649e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1650e4b9852aSCasey Chen */ 1651e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1652e4b9852aSCasey Chen return -ENODEV; 1653e4b9852aSCasey Chen 1654e4b9852aSCasey Chen /* 1655e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1656e4b9852aSCasey Chen */ 1657e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1658e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1659e4b9852aSCasey Chen return -ENODEV; 1660e4b9852aSCasey Chen } 1661e4b9852aSCasey Chen 1662e4b9852aSCasey Chen return 0; 1663e4b9852aSCasey Chen } 1664e4b9852aSCasey Chen 16654b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 166657dacad5SJay Sternberg { 166757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 166857dacad5SJay Sternberg int result; 16697c349ddeSKeith Busch u16 vector = 0; 167057dacad5SJay Sternberg 1671d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1672d1ed6aa1SChristoph Hellwig 167322b55601SKeith Busch /* 167422b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 167522b55601SKeith Busch * has only one vector available. 167622b55601SKeith Busch */ 16774b04cc6aSJens Axboe if (!polled) 1678a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16794b04cc6aSJens Axboe else 16807c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16814b04cc6aSJens Axboe 1682a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1683ded45505SKeith Busch if (result) 1684ded45505SKeith Busch return result; 168557dacad5SJay Sternberg 168657dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 168757dacad5SJay Sternberg if (result < 0) 1688ded45505SKeith Busch return result; 1689c80b36cdSEdmund Nadolski if (result) 169057dacad5SJay Sternberg goto release_cq; 169157dacad5SJay Sternberg 1692a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16934b04cc6aSJens Axboe 1694e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1695e4b9852aSCasey Chen if (result) 1696e4b9852aSCasey Chen return result; 1697e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 16987c349ddeSKeith Busch if (!polled) { 1699dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 170057dacad5SJay Sternberg if (result < 0) 170157dacad5SJay Sternberg goto release_sq; 17024b04cc6aSJens Axboe } 170357dacad5SJay Sternberg 17044e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1705e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 170657dacad5SJay Sternberg return result; 170757dacad5SJay Sternberg 170857dacad5SJay Sternberg release_sq: 1709f25a2dfcSJianchao Wang dev->online_queues--; 1710e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 171157dacad5SJay Sternberg adapter_delete_sq(dev, qid); 171257dacad5SJay Sternberg release_cq: 171357dacad5SJay Sternberg adapter_delete_cq(dev, qid); 171457dacad5SJay Sternberg return result; 171557dacad5SJay Sternberg } 171657dacad5SJay Sternberg 1717f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 171857dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 171977f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 172057dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 1721e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 172257dacad5SJay Sternberg .timeout = nvme_timeout, 172357dacad5SJay Sternberg }; 172457dacad5SJay Sternberg 1725f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1726376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1727d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1728376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1729376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1730376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1731e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 1732376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1733376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1734c6d962aeSChristoph Hellwig .poll = nvme_poll, 1735dabcefabSJens Axboe }; 1736dabcefabSJens Axboe 173757dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 173857dacad5SJay Sternberg { 17391c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 174069d9a99cSKeith Busch /* 174169d9a99cSKeith Busch * If the controller was reset during removal, it's possible 174269d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 174369d9a99cSKeith Busch * queue to flush these to completion. 174469d9a99cSKeith Busch */ 17459f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 17466f8191fdSChristoph Hellwig blk_mq_destroy_queue(dev->ctrl.admin_q); 174796ef1be5SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 174857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 174957dacad5SJay Sternberg } 175057dacad5SJay Sternberg } 175157dacad5SJay Sternberg 1752f91b727cSChristoph Hellwig static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) 175357dacad5SJay Sternberg { 1754f91b727cSChristoph Hellwig struct blk_mq_tag_set *set = &dev->admin_tagset; 1755e3e9d50cSKeith Busch 1756f91b727cSChristoph Hellwig set->ops = &nvme_mq_admin_ops; 1757f91b727cSChristoph Hellwig set->nr_hw_queues = 1; 175857dacad5SJay Sternberg 1759f91b727cSChristoph Hellwig set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1760f91b727cSChristoph Hellwig set->timeout = NVME_ADMIN_TIMEOUT; 1761f91b727cSChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 1762f91b727cSChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 1763f91b727cSChristoph Hellwig set->flags = BLK_MQ_F_NO_SCHED; 1764f91b727cSChristoph Hellwig set->driver_data = dev; 1765f91b727cSChristoph Hellwig 1766f91b727cSChristoph Hellwig if (blk_mq_alloc_tag_set(set)) 176757dacad5SJay Sternberg return -ENOMEM; 1768f91b727cSChristoph Hellwig dev->ctrl.admin_tagset = set; 176957dacad5SJay Sternberg 1770f91b727cSChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(set); 17711c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 1772f91b727cSChristoph Hellwig blk_mq_free_tag_set(set); 1773da427611SSmith, Kyle Miller (Nimble Kernel) dev->ctrl.admin_q = NULL; 177457dacad5SJay Sternberg return -ENOMEM; 177557dacad5SJay Sternberg } 177657dacad5SJay Sternberg return 0; 177757dacad5SJay Sternberg } 177857dacad5SJay Sternberg 177997f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 178097f6ef64SXu Yu { 178197f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 178297f6ef64SXu Yu } 178397f6ef64SXu Yu 178497f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 178597f6ef64SXu Yu { 178697f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 178797f6ef64SXu Yu 178897f6ef64SXu Yu if (size <= dev->bar_mapped_size) 178997f6ef64SXu Yu return 0; 179097f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 179197f6ef64SXu Yu return -ENOMEM; 179297f6ef64SXu Yu if (dev->bar) 179397f6ef64SXu Yu iounmap(dev->bar); 179497f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 179597f6ef64SXu Yu if (!dev->bar) { 179697f6ef64SXu Yu dev->bar_mapped_size = 0; 179797f6ef64SXu Yu return -ENOMEM; 179897f6ef64SXu Yu } 179997f6ef64SXu Yu dev->bar_mapped_size = size; 180097f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 180197f6ef64SXu Yu 180297f6ef64SXu Yu return 0; 180397f6ef64SXu Yu } 180497f6ef64SXu Yu 180501ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 180657dacad5SJay Sternberg { 180757dacad5SJay Sternberg int result; 180857dacad5SJay Sternberg u32 aqa; 180957dacad5SJay Sternberg struct nvme_queue *nvmeq; 181057dacad5SJay Sternberg 181197f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 181297f6ef64SXu Yu if (result < 0) 181397f6ef64SXu Yu return result; 181497f6ef64SXu Yu 18158ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 181620d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 181757dacad5SJay Sternberg 18187a67cbeaSChristoph Hellwig if (dev->subsystem && 18197a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 18207a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 182157dacad5SJay Sternberg 1822b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 182357dacad5SJay Sternberg if (result < 0) 182457dacad5SJay Sternberg return result; 182557dacad5SJay Sternberg 1826a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1827147b27e4SSagi Grimberg if (result) 1828147b27e4SSagi Grimberg return result; 182957dacad5SJay Sternberg 1830635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1831635333e4SMax Gurtovoy 1832147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 183357dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 183457dacad5SJay Sternberg aqa |= aqa << 16; 183557dacad5SJay Sternberg 18367a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 18377a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 18387a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 183957dacad5SJay Sternberg 1840c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 184157dacad5SJay Sternberg if (result) 1842d4875622SKeith Busch return result; 184357dacad5SJay Sternberg 184457dacad5SJay Sternberg nvmeq->cq_vector = 0; 1845161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1846dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 184757dacad5SJay Sternberg if (result) { 18487c349ddeSKeith Busch dev->online_queues--; 1849d4875622SKeith Busch return result; 185057dacad5SJay Sternberg } 185157dacad5SJay Sternberg 18524e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 185357dacad5SJay Sternberg return result; 185457dacad5SJay Sternberg } 185557dacad5SJay Sternberg 1856749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 185757dacad5SJay Sternberg { 18584b04cc6aSJens Axboe unsigned i, max, rw_queues; 1859749941f2SChristoph Hellwig int ret = 0; 186057dacad5SJay Sternberg 1861d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1862a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1863749941f2SChristoph Hellwig ret = -ENOMEM; 186457dacad5SJay Sternberg break; 1865749941f2SChristoph Hellwig } 1866749941f2SChristoph Hellwig } 186757dacad5SJay Sternberg 1868d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1869e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1870e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1871e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 18724b04cc6aSJens Axboe } else { 18734b04cc6aSJens Axboe rw_queues = max; 18744b04cc6aSJens Axboe } 18754b04cc6aSJens Axboe 1876949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 18774b04cc6aSJens Axboe bool polled = i > rw_queues; 18784b04cc6aSJens Axboe 18794b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1880d4875622SKeith Busch if (ret) 188157dacad5SJay Sternberg break; 188257dacad5SJay Sternberg } 188357dacad5SJay Sternberg 1884749941f2SChristoph Hellwig /* 1885749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18868adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18878adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1888749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1889749941f2SChristoph Hellwig */ 1890749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 189157dacad5SJay Sternberg } 189257dacad5SJay Sternberg 189388de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 189457dacad5SJay Sternberg { 189588de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 189688de4598SChristoph Hellwig 189788de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 189888de4598SChristoph Hellwig } 189988de4598SChristoph Hellwig 190088de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 190188de4598SChristoph Hellwig { 190288de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 190388de4598SChristoph Hellwig } 190488de4598SChristoph Hellwig 1905f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 190657dacad5SJay Sternberg { 190788de4598SChristoph Hellwig u64 size, offset; 190857dacad5SJay Sternberg resource_size_t bar_size; 190957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 19108969f1f8SChristoph Hellwig int bar; 191157dacad5SJay Sternberg 19129fe5c59fSKeith Busch if (dev->cmb_size) 19139fe5c59fSKeith Busch return; 19149fe5c59fSKeith Busch 191520d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 191620d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 191720d3bb92SKlaus Jensen 19187a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1919f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1920f65efd6dSChristoph Hellwig return; 1921202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 192257dacad5SJay Sternberg 192388de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 192488de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 19258969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 19268969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 192757dacad5SJay Sternberg 192857dacad5SJay Sternberg if (offset > bar_size) 1929f65efd6dSChristoph Hellwig return; 193057dacad5SJay Sternberg 193157dacad5SJay Sternberg /* 193220d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 193320d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 193420d3bb92SKlaus Jensen */ 193520d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 193620d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 193720d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 193820d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 193920d3bb92SKlaus Jensen } 194020d3bb92SKlaus Jensen 194120d3bb92SKlaus Jensen /* 194257dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 194357dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 194457dacad5SJay Sternberg * the reported size of the BAR 194557dacad5SJay Sternberg */ 194657dacad5SJay Sternberg if (size > bar_size - offset) 194757dacad5SJay Sternberg size = bar_size - offset; 194857dacad5SJay Sternberg 19490f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 19500f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 19510f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1952f65efd6dSChristoph Hellwig return; 19530f238ff5SLogan Gunthorpe } 19540f238ff5SLogan Gunthorpe 195557dacad5SJay Sternberg dev->cmb_size = size; 19560f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 19570f238ff5SLogan Gunthorpe 19580f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 19590f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 19600f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 196157dacad5SJay Sternberg } 196257dacad5SJay Sternberg 196387ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 196457dacad5SJay Sternberg { 19656c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19664033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1967f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 196887ad72a5SChristoph Hellwig int ret; 196987ad72a5SChristoph Hellwig 197087ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 197187ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 197287ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19736c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 197487ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 197587ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 197687ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 197787ad72a5SChristoph Hellwig 197887ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 197987ad72a5SChristoph Hellwig if (ret) { 198087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 198187ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 198287ad72a5SChristoph Hellwig ret, bits); 1983a5df5e79SKeith Busch } else 1984a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1985a5df5e79SKeith Busch 198687ad72a5SChristoph Hellwig return ret; 198787ad72a5SChristoph Hellwig } 198887ad72a5SChristoph Hellwig 198987ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 199087ad72a5SChristoph Hellwig { 199187ad72a5SChristoph Hellwig int i; 199287ad72a5SChristoph Hellwig 199387ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 199487ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19956c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 199687ad72a5SChristoph Hellwig 1997cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1998cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1999cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 200087ad72a5SChristoph Hellwig } 200187ad72a5SChristoph Hellwig 200287ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 200387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 20044033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 20054033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 20064033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 200787ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 20087e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 200987ad72a5SChristoph Hellwig } 201087ad72a5SChristoph Hellwig 201192dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 201292dc6895SChristoph Hellwig u32 chunk_size) 201387ad72a5SChristoph Hellwig { 201487ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 201592dc6895SChristoph Hellwig u32 max_entries, len; 20164033f35dSChristoph Hellwig dma_addr_t descs_dma; 20172ee0e4edSDan Carpenter int i = 0; 201887ad72a5SChristoph Hellwig void **bufs; 20196fbcde66SMinwoo Im u64 size, tmp; 202087ad72a5SChristoph Hellwig 202187ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 202287ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 202387ad72a5SChristoph Hellwig max_entries = tmp; 2024044a9df1SChristoph Hellwig 2025044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2026044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 2027044a9df1SChristoph Hellwig 2028750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 20294033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 203087ad72a5SChristoph Hellwig if (!descs) 203187ad72a5SChristoph Hellwig goto out; 203287ad72a5SChristoph Hellwig 203387ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 203487ad72a5SChristoph Hellwig if (!bufs) 203587ad72a5SChristoph Hellwig goto out_free_descs; 203687ad72a5SChristoph Hellwig 2037244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 203887ad72a5SChristoph Hellwig dma_addr_t dma_addr; 203987ad72a5SChristoph Hellwig 204050cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 204187ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 204287ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 204387ad72a5SChristoph Hellwig if (!bufs[i]) 204487ad72a5SChristoph Hellwig break; 204587ad72a5SChristoph Hellwig 204687ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 20476c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 204887ad72a5SChristoph Hellwig i++; 204987ad72a5SChristoph Hellwig } 205087ad72a5SChristoph Hellwig 205192dc6895SChristoph Hellwig if (!size) 205287ad72a5SChristoph Hellwig goto out_free_bufs; 205387ad72a5SChristoph Hellwig 205487ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 205587ad72a5SChristoph Hellwig dev->host_mem_size = size; 205687ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 20574033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 205887ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 205987ad72a5SChristoph Hellwig return 0; 206087ad72a5SChristoph Hellwig 206187ad72a5SChristoph Hellwig out_free_bufs: 206287ad72a5SChristoph Hellwig while (--i >= 0) { 20636c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 206487ad72a5SChristoph Hellwig 2065cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2066cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2067cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 206887ad72a5SChristoph Hellwig } 206987ad72a5SChristoph Hellwig 207087ad72a5SChristoph Hellwig kfree(bufs); 207187ad72a5SChristoph Hellwig out_free_descs: 20724033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20734033f35dSChristoph Hellwig descs_dma); 207487ad72a5SChristoph Hellwig out: 207587ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 207687ad72a5SChristoph Hellwig return -ENOMEM; 207787ad72a5SChristoph Hellwig } 207887ad72a5SChristoph Hellwig 207992dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 208092dc6895SChristoph Hellwig { 20819dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20829dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20839dc54a0dSChaitanya Kulkarni u64 chunk_size; 208492dc6895SChristoph Hellwig 208592dc6895SChristoph Hellwig /* start big and work our way down */ 20869dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 208792dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 208892dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 208992dc6895SChristoph Hellwig return 0; 209092dc6895SChristoph Hellwig nvme_free_host_mem(dev); 209192dc6895SChristoph Hellwig } 209292dc6895SChristoph Hellwig } 209392dc6895SChristoph Hellwig 209492dc6895SChristoph Hellwig return -ENOMEM; 209592dc6895SChristoph Hellwig } 209692dc6895SChristoph Hellwig 20979620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 209887ad72a5SChristoph Hellwig { 209987ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 210087ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 210187ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 210287ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 21036fbcde66SMinwoo Im int ret; 210487ad72a5SChristoph Hellwig 2105acb71e53SChristoph Hellwig if (!dev->ctrl.hmpre) 2106acb71e53SChristoph Hellwig return 0; 2107acb71e53SChristoph Hellwig 210887ad72a5SChristoph Hellwig preferred = min(preferred, max); 210987ad72a5SChristoph Hellwig if (min > max) { 211087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 211187ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 211287ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 211387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21149620cfbaSChristoph Hellwig return 0; 211587ad72a5SChristoph Hellwig } 211687ad72a5SChristoph Hellwig 211787ad72a5SChristoph Hellwig /* 211887ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 211987ad72a5SChristoph Hellwig */ 212087ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 212187ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 212287ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 212387ad72a5SChristoph Hellwig else 212487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 212587ad72a5SChristoph Hellwig } 212687ad72a5SChristoph Hellwig 212787ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 212892dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 212992dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 213092dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 21319620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 213287ad72a5SChristoph Hellwig } 213387ad72a5SChristoph Hellwig 213492dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 213592dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 213692dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 213792dc6895SChristoph Hellwig } 213892dc6895SChristoph Hellwig 21399620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 21409620cfbaSChristoph Hellwig if (ret) 214187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21429620cfbaSChristoph Hellwig return ret; 214357dacad5SJay Sternberg } 214457dacad5SJay Sternberg 21450521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 21460521905eSKeith Busch char *buf) 21470521905eSKeith Busch { 21480521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21490521905eSKeith Busch 21500521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 21510521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 21520521905eSKeith Busch } 21530521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 21540521905eSKeith Busch 21551751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 21561751e97aSKeith Busch char *buf) 21571751e97aSKeith Busch { 21581751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21591751e97aSKeith Busch 21601751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 21611751e97aSKeith Busch } 21621751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 21631751e97aSKeith Busch 21641751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 21651751e97aSKeith Busch char *buf) 21661751e97aSKeith Busch { 21671751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21681751e97aSKeith Busch 21691751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 21701751e97aSKeith Busch } 21711751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 21721751e97aSKeith Busch 2173a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2174a5df5e79SKeith Busch char *buf) 2175a5df5e79SKeith Busch { 2176a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2177a5df5e79SKeith Busch 2178a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2179a5df5e79SKeith Busch } 2180a5df5e79SKeith Busch 2181a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2182a5df5e79SKeith Busch const char *buf, size_t count) 2183a5df5e79SKeith Busch { 2184a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2185a5df5e79SKeith Busch bool new; 2186a5df5e79SKeith Busch int ret; 2187a5df5e79SKeith Busch 218899722c8aSChristophe JAILLET if (kstrtobool(buf, &new) < 0) 2189a5df5e79SKeith Busch return -EINVAL; 2190a5df5e79SKeith Busch 2191a5df5e79SKeith Busch if (new == ndev->hmb) 2192a5df5e79SKeith Busch return count; 2193a5df5e79SKeith Busch 2194a5df5e79SKeith Busch if (new) { 2195a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2196a5df5e79SKeith Busch } else { 2197a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2198a5df5e79SKeith Busch if (!ret) 2199a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2200a5df5e79SKeith Busch } 2201a5df5e79SKeith Busch 2202a5df5e79SKeith Busch if (ret < 0) 2203a5df5e79SKeith Busch return ret; 2204a5df5e79SKeith Busch 2205a5df5e79SKeith Busch return count; 2206a5df5e79SKeith Busch } 2207a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2208a5df5e79SKeith Busch 22090521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 22100521905eSKeith Busch struct attribute *a, int n) 22110521905eSKeith Busch { 22120521905eSKeith Busch struct nvme_ctrl *ctrl = 22130521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 22140521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 22150521905eSKeith Busch 22161751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 22171751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 22181751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 22191751e97aSKeith Busch if (!dev->cmbsz) 22200521905eSKeith Busch return 0; 22211751e97aSKeith Busch } 2222a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2223a5df5e79SKeith Busch return 0; 2224a5df5e79SKeith Busch 22250521905eSKeith Busch return a->mode; 22260521905eSKeith Busch } 22270521905eSKeith Busch 22280521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 22290521905eSKeith Busch &dev_attr_cmb.attr, 22301751e97aSKeith Busch &dev_attr_cmbloc.attr, 22311751e97aSKeith Busch &dev_attr_cmbsz.attr, 2232a5df5e79SKeith Busch &dev_attr_hmb.attr, 22330521905eSKeith Busch NULL, 22340521905eSKeith Busch }; 22350521905eSKeith Busch 223686adbf0cSChristoph Hellwig static const struct attribute_group nvme_pci_dev_attrs_group = { 22370521905eSKeith Busch .attrs = nvme_pci_attrs, 22380521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 22390521905eSKeith Busch }; 22400521905eSKeith Busch 224186adbf0cSChristoph Hellwig static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 224286adbf0cSChristoph Hellwig &nvme_dev_attrs_group, 224386adbf0cSChristoph Hellwig &nvme_pci_dev_attrs_group, 224486adbf0cSChristoph Hellwig NULL, 224586adbf0cSChristoph Hellwig }; 224686adbf0cSChristoph Hellwig 2247612b7286SMing Lei /* 2248612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2249612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2250612b7286SMing Lei */ 2251612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 22523b6592f7SJens Axboe { 2253612b7286SMing Lei struct nvme_dev *dev = affd->priv; 22542a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2255c45b1fa2SMing Lei 22563b6592f7SJens Axboe /* 2257ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2258612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2259612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2260612b7286SMing Lei * 2261612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2262612b7286SMing Lei * write and read queues. 2263612b7286SMing Lei * 2264612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2265612b7286SMing Lei * queue. 22663b6592f7SJens Axboe */ 2267612b7286SMing Lei if (!nrirqs) { 2268612b7286SMing Lei nrirqs = 1; 2269612b7286SMing Lei nr_read_queues = 0; 22702a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2271612b7286SMing Lei nr_read_queues = 0; 22722a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2273612b7286SMing Lei nr_read_queues = 1; 22743b6592f7SJens Axboe } else { 22752a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22763b6592f7SJens Axboe } 2277612b7286SMing Lei 2278612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2279612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2280612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2281612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2282612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22833b6592f7SJens Axboe } 22843b6592f7SJens Axboe 22856451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22863b6592f7SJens Axboe { 22873b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22883b6592f7SJens Axboe struct irq_affinity affd = { 22893b6592f7SJens Axboe .pre_vectors = 1, 2290612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2291612b7286SMing Lei .priv = dev, 22923b6592f7SJens Axboe }; 229321cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22946451fe73SJens Axboe 22956451fe73SJens Axboe /* 229621cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 229721cc2f3fSJeffle Xu * left over for non-polled I/O. 22986451fe73SJens Axboe */ 229921cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 230021cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 23013b6592f7SJens Axboe 230221cc2f3fSJeffle Xu /* 230321cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 230421cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 230521cc2f3fSJeffle Xu */ 2306612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2307612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 23083b6592f7SJens Axboe 230966341331SBenjamin Herrenschmidt /* 231021cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 231121cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 231221cc2f3fSJeffle Xu * vector. 231366341331SBenjamin Herrenschmidt */ 231466341331SBenjamin Herrenschmidt irq_queues = 1; 231521cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 231621cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2317612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 23183b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 23193b6592f7SJens Axboe } 23203b6592f7SJens Axboe 23218fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 23228fae268bSKeith Busch { 23238fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 23248fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 23258fae268bSKeith Busch } 23268fae268bSKeith Busch 23272a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 23282a5bcfddSWeiping Zhang { 2329e3aef095SNiklas Schnelle /* 2330e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2331e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2332e3aef095SNiklas Schnelle */ 2333e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2334e3aef095SNiklas Schnelle return 1; 23352a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 23362a5bcfddSWeiping Zhang } 23372a5bcfddSWeiping Zhang 233857dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 233957dacad5SJay Sternberg { 2340147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 234157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 23422a5bcfddSWeiping Zhang unsigned int nr_io_queues; 234397f6ef64SXu Yu unsigned long size; 23442a5bcfddSWeiping Zhang int result; 234557dacad5SJay Sternberg 23462a5bcfddSWeiping Zhang /* 23472a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 23482a5bcfddSWeiping Zhang * stable values to work with. 23492a5bcfddSWeiping Zhang */ 23502a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 23512a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2352d38e9f04SBenjamin Herrenschmidt 2353ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 23549a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 23559a0be7abSChristoph Hellwig if (result < 0) 235657dacad5SJay Sternberg return result; 23579a0be7abSChristoph Hellwig 2358f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2359a5229050SKeith Busch return 0; 236057dacad5SJay Sternberg 2361e4b9852aSCasey Chen /* 2362e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2363e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2364e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2365e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2366e4b9852aSCasey Chen * nvme_dev_disable() path. 2367e4b9852aSCasey Chen */ 2368e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2369e4b9852aSCasey Chen if (result) 2370e4b9852aSCasey Chen return result; 2371e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2372e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 23734e224106SChristoph Hellwig 23740f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 237557dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 237657dacad5SJay Sternberg sizeof(struct nvme_command)); 237757dacad5SJay Sternberg if (result > 0) 237857dacad5SJay Sternberg dev->q_depth = result; 237957dacad5SJay Sternberg else 23800f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 238157dacad5SJay Sternberg } 238257dacad5SJay Sternberg 238357dacad5SJay Sternberg do { 238497f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 238597f6ef64SXu Yu result = nvme_remap_bar(dev, size); 238697f6ef64SXu Yu if (!result) 238757dacad5SJay Sternberg break; 2388e4b9852aSCasey Chen if (!--nr_io_queues) { 2389e4b9852aSCasey Chen result = -ENOMEM; 2390e4b9852aSCasey Chen goto out_unlock; 2391e4b9852aSCasey Chen } 239257dacad5SJay Sternberg } while (1); 239357dacad5SJay Sternberg adminq->q_db = dev->dbs; 239457dacad5SJay Sternberg 23958fae268bSKeith Busch retry: 239657dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2397e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23980ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 239957dacad5SJay Sternberg 240057dacad5SJay Sternberg /* 240157dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 240257dacad5SJay Sternberg * setting up the full range we need. 240357dacad5SJay Sternberg */ 2404dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 24053b6592f7SJens Axboe 24063b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2407e4b9852aSCasey Chen if (result <= 0) { 2408e4b9852aSCasey Chen result = -EIO; 2409e4b9852aSCasey Chen goto out_unlock; 2410e4b9852aSCasey Chen } 24113b6592f7SJens Axboe 241222b55601SKeith Busch dev->num_vecs = result; 24134b04cc6aSJens Axboe result = max(result - 1, 1); 2414e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 241557dacad5SJay Sternberg 241657dacad5SJay Sternberg /* 241757dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 241857dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 241957dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 242057dacad5SJay Sternberg * number of interrupts. 242157dacad5SJay Sternberg */ 2422dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 24237c349ddeSKeith Busch if (result) 2424e4b9852aSCasey Chen goto out_unlock; 24254e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2426e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 24278fae268bSKeith Busch 24288fae268bSKeith Busch result = nvme_create_io_queues(dev); 24298fae268bSKeith Busch if (result || dev->online_queues < 2) 24308fae268bSKeith Busch return result; 24318fae268bSKeith Busch 24328fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 24338fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 24348fae268bSKeith Busch nvme_disable_io_queues(dev); 2435e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2436e4b9852aSCasey Chen if (result) 2437e4b9852aSCasey Chen return result; 24388fae268bSKeith Busch nvme_suspend_io_queues(dev); 24398fae268bSKeith Busch goto retry; 24408fae268bSKeith Busch } 24418fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 24428fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 24438fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 24448fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 24458fae268bSKeith Busch return 0; 2446e4b9852aSCasey Chen out_unlock: 2447e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2448e4b9852aSCasey Chen return result; 244957dacad5SJay Sternberg } 245057dacad5SJay Sternberg 2451de671d61SJens Axboe static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2452de671d61SJens Axboe blk_status_t error) 2453db3cbfffSKeith Busch { 2454db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2455db3cbfffSKeith Busch 2456db3cbfffSKeith Busch blk_mq_free_request(req); 2457d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2458de671d61SJens Axboe return RQ_END_IO_NONE; 2459db3cbfffSKeith Busch } 2460db3cbfffSKeith Busch 2461de671d61SJens Axboe static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2462de671d61SJens Axboe blk_status_t error) 2463db3cbfffSKeith Busch { 2464db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2465db3cbfffSKeith Busch 2466d1ed6aa1SChristoph Hellwig if (error) 2467d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2468db3cbfffSKeith Busch 2469de671d61SJens Axboe return nvme_del_queue_end(req, error); 2470db3cbfffSKeith Busch } 2471db3cbfffSKeith Busch 2472db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2473db3cbfffSKeith Busch { 2474db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2475db3cbfffSKeith Busch struct request *req; 2476f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2477db3cbfffSKeith Busch 2478db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2479db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2480db3cbfffSKeith Busch 2481e559398fSChristoph Hellwig req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2482db3cbfffSKeith Busch if (IS_ERR(req)) 2483db3cbfffSKeith Busch return PTR_ERR(req); 2484e559398fSChristoph Hellwig nvme_init_request(req, &cmd); 2485db3cbfffSKeith Busch 2486e2e53086SChristoph Hellwig if (opcode == nvme_admin_delete_cq) 2487e2e53086SChristoph Hellwig req->end_io = nvme_del_cq_end; 2488e2e53086SChristoph Hellwig else 2489e2e53086SChristoph Hellwig req->end_io = nvme_del_queue_end; 2490db3cbfffSKeith Busch req->end_io_data = nvmeq; 2491db3cbfffSKeith Busch 2492d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2493128126a7SChaitanya Kulkarni req->rq_flags |= RQF_QUIET; 2494e2e53086SChristoph Hellwig blk_execute_rq_nowait(req, false); 2495db3cbfffSKeith Busch return 0; 2496db3cbfffSKeith Busch } 2497db3cbfffSKeith Busch 24988fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2499db3cbfffSKeith Busch { 25005271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2501db3cbfffSKeith Busch unsigned long timeout; 2502db3cbfffSKeith Busch 2503db3cbfffSKeith Busch retry: 2504dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 25055271edd4SChristoph Hellwig while (nr_queues > 0) { 25065271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2507db3cbfffSKeith Busch break; 25085271edd4SChristoph Hellwig nr_queues--; 25095271edd4SChristoph Hellwig sent++; 25105271edd4SChristoph Hellwig } 2511d1ed6aa1SChristoph Hellwig while (sent) { 2512d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2513d1ed6aa1SChristoph Hellwig 2514d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 25155271edd4SChristoph Hellwig timeout); 2516db3cbfffSKeith Busch if (timeout == 0) 25175271edd4SChristoph Hellwig return false; 2518d1ed6aa1SChristoph Hellwig 2519d1ed6aa1SChristoph Hellwig sent--; 25205271edd4SChristoph Hellwig if (nr_queues) 2521db3cbfffSKeith Busch goto retry; 2522db3cbfffSKeith Busch } 25235271edd4SChristoph Hellwig return true; 2524db3cbfffSKeith Busch } 2525db3cbfffSKeith Busch 25262455a4b7SChristoph Hellwig static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) 252757dacad5SJay Sternberg { 25282455a4b7SChristoph Hellwig struct blk_mq_tag_set * set = &dev->tagset; 25292b1b7e78SJianchao Wang int ret; 25302b1b7e78SJianchao Wang 25312455a4b7SChristoph Hellwig set->ops = &nvme_mq_ops; 25322455a4b7SChristoph Hellwig set->nr_hw_queues = dev->online_queues - 1; 25336ee742faSKeith Busch set->nr_maps = 1; 25346ee742faSKeith Busch if (dev->io_queues[HCTX_TYPE_READ]) 25356ee742faSKeith Busch set->nr_maps = 2; 2536ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 25376ee742faSKeith Busch set->nr_maps = 3; 25382455a4b7SChristoph Hellwig set->timeout = NVME_IO_TIMEOUT; 25392455a4b7SChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 25402455a4b7SChristoph Hellwig set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 25412455a4b7SChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 25422455a4b7SChristoph Hellwig set->flags = BLK_MQ_F_SHOULD_MERGE; 25432455a4b7SChristoph Hellwig set->driver_data = dev; 254457dacad5SJay Sternberg 2545d38e9f04SBenjamin Herrenschmidt /* 2546d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2547d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2548d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2549d38e9f04SBenjamin Herrenschmidt */ 2550d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 25512455a4b7SChristoph Hellwig set->reserved_tags = NVME_AQ_DEPTH; 2552d38e9f04SBenjamin Herrenschmidt 25532455a4b7SChristoph Hellwig ret = blk_mq_alloc_tag_set(set); 25542b1b7e78SJianchao Wang if (ret) { 25552b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25562b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 25575d02a5c1SKeith Busch return; 25582b1b7e78SJianchao Wang } 25592455a4b7SChristoph Hellwig dev->ctrl.tagset = set; 256057dacad5SJay Sternberg } 2561949928c1SKeith Busch 25622455a4b7SChristoph Hellwig static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 25632455a4b7SChristoph Hellwig { 25642455a4b7SChristoph Hellwig blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 25652455a4b7SChristoph Hellwig /* free previously allocated queues that are no longer usable */ 25662455a4b7SChristoph Hellwig nvme_free_queues(dev, dev->online_queues); 256757dacad5SJay Sternberg } 256857dacad5SJay Sternberg 2569b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 257057dacad5SJay Sternberg { 2571b00a726aSKeith Busch int result = -ENOMEM; 257257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 25734bdf2603SFilippo Sironi int dma_address_bits = 64; 257457dacad5SJay Sternberg 257557dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 257657dacad5SJay Sternberg return result; 257757dacad5SJay Sternberg 257857dacad5SJay Sternberg pci_set_master(pdev); 257957dacad5SJay Sternberg 25804bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 25814bdf2603SFilippo Sironi dma_address_bits = 48; 25824bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 258357dacad5SJay Sternberg goto disable; 258457dacad5SJay Sternberg 25857a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 258657dacad5SJay Sternberg result = -ENODEV; 2587b00a726aSKeith Busch goto disable; 258857dacad5SJay Sternberg } 258957dacad5SJay Sternberg 259057dacad5SJay Sternberg /* 2591a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2592a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2593a5229050SKeith Busch * adjust this later. 259457dacad5SJay Sternberg */ 2595dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2596dca51e78SChristoph Hellwig if (result < 0) 2597dca51e78SChristoph Hellwig return result; 259857dacad5SJay Sternberg 259920d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 26007a67cbeaSChristoph Hellwig 26017442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2602b27c1e68Sweiping zhang io_queue_depth); 2603aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 260420d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 26057a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 26061f390c1fSStephan Günther 26071f390c1fSStephan Günther /* 260866341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 260966341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 261066341331SBenjamin Herrenschmidt * so we don't bother updating it here. 261166341331SBenjamin Herrenschmidt */ 261266341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 261366341331SBenjamin Herrenschmidt dev->io_sqes = 7; 261466341331SBenjamin Herrenschmidt else 2615c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 26161f390c1fSStephan Günther 26171f390c1fSStephan Günther /* 26181f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 26191f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 26201f390c1fSStephan Günther */ 26211f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 26221f390c1fSStephan Günther dev->q_depth = 2; 26239bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 26249bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 26251f390c1fSStephan Günther dev->q_depth); 2626d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2627d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 262820d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2629d554b5e1SMartin K. Petersen dev->q_depth = 64; 2630d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2631d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 26321f390c1fSStephan Günther } 26331f390c1fSStephan Günther 2634d38e9f04SBenjamin Herrenschmidt /* 2635d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2636d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2637d38e9f04SBenjamin Herrenschmidt */ 2638d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2639d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2640d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2641d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2642d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2643d38e9f04SBenjamin Herrenschmidt } 2644d38e9f04SBenjamin Herrenschmidt 2645d38e9f04SBenjamin Herrenschmidt 2646f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2647202021c1SStephen Bates 2648a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2649a0a3408eSKeith Busch pci_save_state(pdev); 2650a6ee7f19SChristoph Hellwig 2651a6ee7f19SChristoph Hellwig return nvme_pci_configure_admin_queue(dev); 265257dacad5SJay Sternberg 265357dacad5SJay Sternberg disable: 265457dacad5SJay Sternberg pci_disable_device(pdev); 265557dacad5SJay Sternberg return result; 265657dacad5SJay Sternberg } 265757dacad5SJay Sternberg 265857dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 265957dacad5SJay Sternberg { 2660b00a726aSKeith Busch if (dev->bar) 2661b00a726aSKeith Busch iounmap(dev->bar); 2662a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2663b00a726aSKeith Busch } 2664b00a726aSKeith Busch 2665b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2666b00a726aSKeith Busch { 266757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 266857dacad5SJay Sternberg 2669dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 267057dacad5SJay Sternberg 2671a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2672a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 267357dacad5SJay Sternberg pci_disable_device(pdev); 267457dacad5SJay Sternberg } 2675a0a3408eSKeith Busch } 267657dacad5SJay Sternberg 2677a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 267857dacad5SJay Sternberg { 2679e43269e6SKeith Busch bool dead = true, freeze = false; 2680302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 268157dacad5SJay Sternberg 268277bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2683081f5e75SKeith Busch if (pci_is_enabled(pdev)) { 2684081f5e75SKeith Busch u32 csts; 2685081f5e75SKeith Busch 2686081f5e75SKeith Busch if (pci_device_is_present(pdev)) 2687081f5e75SKeith Busch csts = readl(dev->bar + NVME_REG_CSTS); 2688081f5e75SKeith Busch else 2689081f5e75SKeith Busch csts = ~0; 2690302ad8ccSKeith Busch 2691ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2692e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2693e43269e6SKeith Busch freeze = true; 2694302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2695e43269e6SKeith Busch } 2696302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2697302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 269857dacad5SJay Sternberg } 2699c21377f8SGabriel Krisman Bertazi 2700302ad8ccSKeith Busch /* 2701302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2702302ad8ccSKeith Busch * doing a safe shutdown. 2703302ad8ccSKeith Busch */ 2704e43269e6SKeith Busch if (!dead && shutdown && freeze) 2705302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 270687ad72a5SChristoph Hellwig 27079f27bd70SChristoph Hellwig nvme_quiesce_io_queues(&dev->ctrl); 27089a915a5bSJianchao Wang 270964ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 27108fae268bSKeith Busch nvme_disable_io_queues(dev); 2711a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 271257dacad5SJay Sternberg } 27138fae268bSKeith Busch nvme_suspend_io_queues(dev); 27148fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2715b00a726aSKeith Busch nvme_pci_disable(dev); 2716fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 271757dacad5SJay Sternberg 27181fcfca78SGuixin Liu nvme_cancel_tagset(&dev->ctrl); 27191fcfca78SGuixin Liu nvme_cancel_admin_tagset(&dev->ctrl); 2720302ad8ccSKeith Busch 2721302ad8ccSKeith Busch /* 2722302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2723302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2724302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2725302ad8ccSKeith Busch */ 2726c8e9e9b7SKeith Busch if (shutdown) { 27279f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2728c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 27299f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 2730c8e9e9b7SKeith Busch } 273177bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 273257dacad5SJay Sternberg } 273357dacad5SJay Sternberg 2734c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2735c1ac9a4bSKeith Busch { 2736c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2737c1ac9a4bSKeith Busch return -EBUSY; 2738c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2739c1ac9a4bSKeith Busch return 0; 2740c1ac9a4bSKeith Busch } 2741c1ac9a4bSKeith Busch 274257dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 274357dacad5SJay Sternberg { 274457dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2745c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2746c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 274757dacad5SJay Sternberg if (!dev->prp_page_pool) 274857dacad5SJay Sternberg return -ENOMEM; 274957dacad5SJay Sternberg 275057dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 275157dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 275257dacad5SJay Sternberg 256, 256, 0); 275357dacad5SJay Sternberg if (!dev->prp_small_pool) { 275457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 275557dacad5SJay Sternberg return -ENOMEM; 275657dacad5SJay Sternberg } 275757dacad5SJay Sternberg return 0; 275857dacad5SJay Sternberg } 275957dacad5SJay Sternberg 276057dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 276157dacad5SJay Sternberg { 276257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 276357dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 276457dacad5SJay Sternberg } 276557dacad5SJay Sternberg 2766081a7d95SChristoph Hellwig static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2767081a7d95SChristoph Hellwig { 2768081a7d95SChristoph Hellwig size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 2769081a7d95SChristoph Hellwig size_t alloc_size = sizeof(__le64 *) * npages + 2770081a7d95SChristoph Hellwig sizeof(struct scatterlist) * NVME_MAX_SEGS; 2771081a7d95SChristoph Hellwig 2772081a7d95SChristoph Hellwig WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2773081a7d95SChristoph Hellwig dev->iod_mempool = mempool_create_node(1, 2774081a7d95SChristoph Hellwig mempool_kmalloc, mempool_kfree, 2775081a7d95SChristoph Hellwig (void *)alloc_size, GFP_KERNEL, 2776081a7d95SChristoph Hellwig dev_to_node(dev->dev)); 2777081a7d95SChristoph Hellwig if (!dev->iod_mempool) 2778081a7d95SChristoph Hellwig return -ENOMEM; 2779081a7d95SChristoph Hellwig return 0; 2780081a7d95SChristoph Hellwig } 2781081a7d95SChristoph Hellwig 2782770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2783770597ecSKeith Busch { 2784770597ecSKeith Busch if (dev->tagset.tags) 2785770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2786770597ecSKeith Busch dev->ctrl.tagset = NULL; 2787770597ecSKeith Busch } 2788770597ecSKeith Busch 27892e87570bSChristoph Hellwig /* pairs with nvme_pci_alloc_dev */ 27901673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 279157dacad5SJay Sternberg { 27921673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 279357dacad5SJay Sternberg 2794770597ecSKeith Busch nvme_free_tagset(dev); 2795253fd4acSIsrael Rukshin put_device(dev->dev); 2796253fd4acSIsrael Rukshin kfree(dev->queues); 279757dacad5SJay Sternberg kfree(dev); 279857dacad5SJay Sternberg } 279957dacad5SJay Sternberg 2800fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 280157dacad5SJay Sternberg { 2802d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2803d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2804a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2805e71afda4SChaitanya Kulkarni int result; 280657dacad5SJay Sternberg 28077764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 28087764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 28097764656bSZhihao Cheng dev->ctrl.state); 2810e71afda4SChaitanya Kulkarni result = -ENODEV; 2811fd634f41SChristoph Hellwig goto out; 2812e71afda4SChaitanya Kulkarni } 2813fd634f41SChristoph Hellwig 2814fd634f41SChristoph Hellwig /* 2815fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2816fd634f41SChristoph Hellwig * moving on. 2817fd634f41SChristoph Hellwig */ 2818b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2819a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2820d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2821fd634f41SChristoph Hellwig 28225c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2823b00a726aSKeith Busch result = nvme_pci_enable(dev); 282457dacad5SJay Sternberg if (result) 28254726bcf3SKeith Busch goto out_unlock; 28269f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 28275c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 28285c959d73SKeith Busch 28295c959d73SKeith Busch /* 28305c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 28315c959d73SKeith Busch * initializing procedure here. 28325c959d73SKeith Busch */ 28335c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 28345c959d73SKeith Busch dev_warn(dev->ctrl.device, 28355c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2836cee6c269SMinwoo Im result = -EBUSY; 28375c959d73SKeith Busch goto out; 28385c959d73SKeith Busch } 2839943e942eSJens Axboe 284094cc781fSChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2841ce4541f4SChristoph Hellwig if (result) 2842f58944e2SKeith Busch goto out; 2843ce4541f4SChristoph Hellwig 284465a54646SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 2845f9f38e33SHelen Koike 28469620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 28479620cfbaSChristoph Hellwig if (result < 0) 28489620cfbaSChristoph Hellwig goto out; 284987ad72a5SChristoph Hellwig 285057dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 285157dacad5SJay Sternberg if (result) 2852f58944e2SKeith Busch goto out; 285357dacad5SJay Sternberg 285421f033f7SKeith Busch /* 28550ffc7e98SChristoph Hellwig * Freeze and update the number of I/O queues as thos might have 2856eac3ef26SChristoph Hellwig * changed. If there are no I/O queues left after this reset, keep the 2857eac3ef26SChristoph Hellwig * controller around but remove all namespaces. 285857dacad5SJay Sternberg */ 28590ffc7e98SChristoph Hellwig if (dev->online_queues > 1) { 28609f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2861302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 28622455a4b7SChristoph Hellwig nvme_pci_update_nr_queues(dev); 28632455a4b7SChristoph Hellwig nvme_dbbuf_set(dev); 2864302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 28650ffc7e98SChristoph Hellwig } else { 28660ffc7e98SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues lost\n"); 2867cd50f9b2SChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 28689f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 28690ffc7e98SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 28700ffc7e98SChristoph Hellwig nvme_free_tagset(dev); 28710ffc7e98SChristoph Hellwig } 287257dacad5SJay Sternberg 28732b1b7e78SJianchao Wang /* 28742b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 28752b1b7e78SJianchao Wang * recovery. 28762b1b7e78SJianchao Wang */ 28775d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 28782b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 28795d02a5c1SKeith Busch "failed to mark controller live state\n"); 2880e71afda4SChaitanya Kulkarni result = -ENODEV; 2881bb8d261eSChristoph Hellwig goto out; 2882bb8d261eSChristoph Hellwig } 288392911a55SChristoph Hellwig 2884d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 288557dacad5SJay Sternberg return; 288657dacad5SJay Sternberg 28874726bcf3SKeith Busch out_unlock: 28884726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 288957dacad5SJay Sternberg out: 2890c7c16c5bSChristoph Hellwig /* 2891c7c16c5bSChristoph Hellwig * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2892c7c16c5bSChristoph Hellwig * may be holding this pci_dev's device lock. 2893c7c16c5bSChristoph Hellwig */ 2894c7c16c5bSChristoph Hellwig dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", 2895c7c16c5bSChristoph Hellwig result); 2896c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2897c7c16c5bSChristoph Hellwig nvme_dev_disable(dev, true); 2898c7c16c5bSChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 2899c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 290057dacad5SJay Sternberg } 290157dacad5SJay Sternberg 29021c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 290357dacad5SJay Sternberg { 29041c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 29051c63dc66SChristoph Hellwig return 0; 290657dacad5SJay Sternberg } 29071c63dc66SChristoph Hellwig 29085fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 29095fd4ce1bSChristoph Hellwig { 29105fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 29115fd4ce1bSChristoph Hellwig return 0; 29125fd4ce1bSChristoph Hellwig } 29135fd4ce1bSChristoph Hellwig 29147fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 29157fd8930fSChristoph Hellwig { 29163a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 29177fd8930fSChristoph Hellwig return 0; 29187fd8930fSChristoph Hellwig } 29197fd8930fSChristoph Hellwig 292097c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 292197c12223SKeith Busch { 292297c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 292397c12223SKeith Busch 29242db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 292597c12223SKeith Busch } 292697c12223SKeith Busch 29272f0dad17SKeith Busch static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 29282f0dad17SKeith Busch { 29292f0dad17SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 29302f0dad17SKeith Busch struct nvme_subsystem *subsys = ctrl->subsys; 29312f0dad17SKeith Busch 29322f0dad17SKeith Busch dev_err(ctrl->device, 29332f0dad17SKeith Busch "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 29342f0dad17SKeith Busch pdev->vendor, pdev->device, 29352f0dad17SKeith Busch nvme_strlen(subsys->model, sizeof(subsys->model)), 29362f0dad17SKeith Busch subsys->model, nvme_strlen(subsys->firmware_rev, 29372f0dad17SKeith Busch sizeof(subsys->firmware_rev)), 29382f0dad17SKeith Busch subsys->firmware_rev); 29392f0dad17SKeith Busch } 29402f0dad17SKeith Busch 29412f859441SLogan Gunthorpe static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 29422f859441SLogan Gunthorpe { 29432f859441SLogan Gunthorpe struct nvme_dev *dev = to_nvme_dev(ctrl); 29442f859441SLogan Gunthorpe 29452f859441SLogan Gunthorpe return dma_pci_p2pdma_supported(dev->dev); 29462f859441SLogan Gunthorpe } 29472f859441SLogan Gunthorpe 29481c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 29491a353d85SMing Lin .name = "pcie", 2950e439bb12SSagi Grimberg .module = THIS_MODULE, 29512f859441SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED, 295286adbf0cSChristoph Hellwig .dev_attr_groups = nvme_pci_dev_attr_groups, 29531c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 29545fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 29557fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 29561673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2957f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 295897c12223SKeith Busch .get_address = nvme_pci_get_address, 29592f0dad17SKeith Busch .print_device_info = nvme_pci_print_device_info, 29602f859441SLogan Gunthorpe .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 29611c63dc66SChristoph Hellwig }; 296257dacad5SJay Sternberg 2963b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2964b00a726aSKeith Busch { 2965b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2966b00a726aSKeith Busch 2967a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2968b00a726aSKeith Busch return -ENODEV; 2969b00a726aSKeith Busch 297097f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2971b00a726aSKeith Busch goto release; 2972b00a726aSKeith Busch 2973b00a726aSKeith Busch return 0; 2974b00a726aSKeith Busch release: 2975a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2976b00a726aSKeith Busch return -ENODEV; 2977b00a726aSKeith Busch } 2978b00a726aSKeith Busch 29798427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2980ff5350a8SAndy Lutomirski { 2981ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2982ff5350a8SAndy Lutomirski /* 2983ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2984ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2985ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2986ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2987ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2988ff5350a8SAndy Lutomirski * laptops. 2989ff5350a8SAndy Lutomirski */ 2990ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2991ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2992ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2993ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 29948427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 29958427bbc2SKai-Heng Feng /* 29968427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2997467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2998467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2999467c77d4SJarosław Janik * ASUS PRIME Z370-A 30008427bbc2SKai-Heng Feng */ 30018427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3002467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3003467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 30048427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 30051fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 30061fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 30071fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 30081fae37acSShyjumon N /* 30091fae37acSShyjumon N * Forcing to use host managed nvme power settings for 30101fae37acSShyjumon N * lowest idle power with quick resume latency on 30111fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 30121fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 30131fae37acSShyjumon N */ 30141fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 30151fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 30161fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 3017ff5350a8SAndy Lutomirski } 3018ff5350a8SAndy Lutomirski 3019ff5350a8SAndy Lutomirski return 0; 3020ff5350a8SAndy Lutomirski } 3021ff5350a8SAndy Lutomirski 30222e87570bSChristoph Hellwig static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 30232e87570bSChristoph Hellwig const struct pci_device_id *id) 302457dacad5SJay Sternberg { 3025ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 30262e87570bSChristoph Hellwig int node = dev_to_node(&pdev->dev); 30272e87570bSChristoph Hellwig struct nvme_dev *dev; 30282e87570bSChristoph Hellwig int ret = -ENOMEM; 302957dacad5SJay Sternberg 303057dacad5SJay Sternberg if (node == NUMA_NO_NODE) 30312fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 303257dacad5SJay Sternberg 303357dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 303457dacad5SJay Sternberg if (!dev) 30352e87570bSChristoph Hellwig return NULL; 30362e87570bSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 30372e87570bSChristoph Hellwig mutex_init(&dev->shutdown_lock); 3038147b27e4SSagi Grimberg 30392a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 30402a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 30412a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 30422a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 30432a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 304457dacad5SJay Sternberg if (!dev->queues) 30452e87570bSChristoph Hellwig goto out_free_dev; 304657dacad5SJay Sternberg 304757dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 3048f3ca80fcSChristoph Hellwig 30498427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 30502744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3051df4f9bc4SDavid E. Box /* 3052df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3053df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3054df4f9bc4SDavid E. Box */ 3055df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3056df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3057df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3058df4f9bc4SDavid E. Box } 30592e87570bSChristoph Hellwig ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 30602e87570bSChristoph Hellwig quirks); 30612e87570bSChristoph Hellwig if (ret) 30622e87570bSChristoph Hellwig goto out_put_device; 30633f30a79cSChristoph Hellwig 30643f30a79cSChristoph Hellwig dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 30653f30a79cSChristoph Hellwig dma_set_max_seg_size(&pdev->dev, 0xffffffff); 30663f30a79cSChristoph Hellwig 30673f30a79cSChristoph Hellwig /* 30683f30a79cSChristoph Hellwig * Limit the max command size to prevent iod->sg allocations going 30693f30a79cSChristoph Hellwig * over a single page. 30703f30a79cSChristoph Hellwig */ 30713f30a79cSChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 30723f30a79cSChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9); 30733f30a79cSChristoph Hellwig dev->ctrl.max_segments = NVME_MAX_SEGS; 30743f30a79cSChristoph Hellwig 30753f30a79cSChristoph Hellwig /* 30763f30a79cSChristoph Hellwig * There is no support for SGLs for metadata (yet), so we are limited to 30773f30a79cSChristoph Hellwig * a single integrity segment for the separate metadata pointer. 30783f30a79cSChristoph Hellwig */ 30793f30a79cSChristoph Hellwig dev->ctrl.max_integrity_segments = 1; 30802e87570bSChristoph Hellwig return dev; 30812e87570bSChristoph Hellwig 30822e87570bSChristoph Hellwig out_put_device: 30832e87570bSChristoph Hellwig put_device(dev->dev); 30842e87570bSChristoph Hellwig kfree(dev->queues); 30852e87570bSChristoph Hellwig out_free_dev: 30862e87570bSChristoph Hellwig kfree(dev); 30872e87570bSChristoph Hellwig return ERR_PTR(ret); 30882e87570bSChristoph Hellwig } 30892e87570bSChristoph Hellwig 30902e87570bSChristoph Hellwig static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 30912e87570bSChristoph Hellwig { 30922e87570bSChristoph Hellwig struct nvme_dev *dev; 30932e87570bSChristoph Hellwig int result = -ENOMEM; 30942e87570bSChristoph Hellwig 30952e87570bSChristoph Hellwig dev = nvme_pci_alloc_dev(pdev, id); 30962e87570bSChristoph Hellwig if (!dev) 30972e87570bSChristoph Hellwig return -ENOMEM; 30982e87570bSChristoph Hellwig 30992e87570bSChristoph Hellwig result = nvme_dev_map(dev); 31002e87570bSChristoph Hellwig if (result) 31012e87570bSChristoph Hellwig goto out_uninit_ctrl; 31022e87570bSChristoph Hellwig 31032e87570bSChristoph Hellwig result = nvme_setup_prp_pools(dev); 31042e87570bSChristoph Hellwig if (result) 31052e87570bSChristoph Hellwig goto out_dev_unmap; 3106df4f9bc4SDavid E. Box 3107081a7d95SChristoph Hellwig result = nvme_pci_alloc_iod_mempool(dev); 3108081a7d95SChristoph Hellwig if (result) 31092e87570bSChristoph Hellwig goto out_release_prp_pools; 3110b6e44b4cSKeith Busch 31111b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 3112eac3ef26SChristoph Hellwig 3113eac3ef26SChristoph Hellwig result = nvme_pci_enable(dev); 3114eac3ef26SChristoph Hellwig if (result) 3115eac3ef26SChristoph Hellwig goto out_release_iod_mempool; 3116eac3ef26SChristoph Hellwig 3117eac3ef26SChristoph Hellwig result = nvme_pci_alloc_admin_tag_set(dev); 3118eac3ef26SChristoph Hellwig if (result) 3119eac3ef26SChristoph Hellwig goto out_disable; 3120eac3ef26SChristoph Hellwig 3121eac3ef26SChristoph Hellwig /* 3122eac3ef26SChristoph Hellwig * Mark the controller as connecting before sending admin commands to 3123eac3ef26SChristoph Hellwig * allow the timeout handler to do the right thing. 3124eac3ef26SChristoph Hellwig */ 3125eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 3126eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3127eac3ef26SChristoph Hellwig "failed to mark controller CONNECTING\n"); 3128eac3ef26SChristoph Hellwig result = -EBUSY; 3129eac3ef26SChristoph Hellwig goto out_disable; 3130eac3ef26SChristoph Hellwig } 3131eac3ef26SChristoph Hellwig 3132eac3ef26SChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, false); 3133eac3ef26SChristoph Hellwig if (result) 3134eac3ef26SChristoph Hellwig goto out_disable; 3135eac3ef26SChristoph Hellwig 3136eac3ef26SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 3137eac3ef26SChristoph Hellwig 3138eac3ef26SChristoph Hellwig result = nvme_setup_host_mem(dev); 3139eac3ef26SChristoph Hellwig if (result < 0) 3140eac3ef26SChristoph Hellwig goto out_disable; 3141eac3ef26SChristoph Hellwig 3142eac3ef26SChristoph Hellwig result = nvme_setup_io_queues(dev); 3143eac3ef26SChristoph Hellwig if (result) 3144eac3ef26SChristoph Hellwig goto out_disable; 3145eac3ef26SChristoph Hellwig 3146eac3ef26SChristoph Hellwig if (dev->online_queues > 1) { 3147eac3ef26SChristoph Hellwig nvme_pci_alloc_tag_set(dev); 3148eac3ef26SChristoph Hellwig nvme_dbbuf_set(dev); 3149eac3ef26SChristoph Hellwig } else { 3150eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues not created\n"); 3151eac3ef26SChristoph Hellwig } 3152eac3ef26SChristoph Hellwig 3153eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 3154eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3155eac3ef26SChristoph Hellwig "failed to mark controller live state\n"); 3156eac3ef26SChristoph Hellwig result = -ENODEV; 3157eac3ef26SChristoph Hellwig goto out_disable; 3158eac3ef26SChristoph Hellwig } 3159eac3ef26SChristoph Hellwig 31602e87570bSChristoph Hellwig pci_set_drvdata(pdev, dev); 31611b3c47c1SSagi Grimberg 3162eac3ef26SChristoph Hellwig nvme_start_ctrl(&dev->ctrl); 3163eac3ef26SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 316457dacad5SJay Sternberg return 0; 316557dacad5SJay Sternberg 3166eac3ef26SChristoph Hellwig out_disable: 3167eac3ef26SChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3168eac3ef26SChristoph Hellwig nvme_dev_disable(dev, true); 3169eac3ef26SChristoph Hellwig nvme_free_host_mem(dev); 3170eac3ef26SChristoph Hellwig nvme_dev_remove_admin(dev); 3171eac3ef26SChristoph Hellwig nvme_dbbuf_dma_free(dev); 3172eac3ef26SChristoph Hellwig nvme_free_queues(dev, 0); 3173eac3ef26SChristoph Hellwig out_release_iod_mempool: 3174eac3ef26SChristoph Hellwig mempool_destroy(dev->iod_mempool); 31752e87570bSChristoph Hellwig out_release_prp_pools: 317657dacad5SJay Sternberg nvme_release_prp_pools(dev); 31772e87570bSChristoph Hellwig out_dev_unmap: 3178b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 31792e87570bSChristoph Hellwig out_uninit_ctrl: 31802e87570bSChristoph Hellwig nvme_uninit_ctrl(&dev->ctrl); 318157dacad5SJay Sternberg return result; 318257dacad5SJay Sternberg } 318357dacad5SJay Sternberg 3184775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 318557dacad5SJay Sternberg { 318657dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3187c1ac9a4bSKeith Busch 3188c1ac9a4bSKeith Busch /* 3189c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3190c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3191c1ac9a4bSKeith Busch * with ->remove(). 3192c1ac9a4bSKeith Busch */ 3193c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3194c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3195775755edSChristoph Hellwig } 319657dacad5SJay Sternberg 3197775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3198775755edSChristoph Hellwig { 3199f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3200c1ac9a4bSKeith Busch 3201c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3202c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 320357dacad5SJay Sternberg } 320457dacad5SJay Sternberg 320557dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 320657dacad5SJay Sternberg { 320757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 32084e523547SBaolin Wang 3209c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 321057dacad5SJay Sternberg } 321157dacad5SJay Sternberg 3212f58944e2SKeith Busch /* 3213f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3214f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3215f58944e2SKeith Busch * order to proceed. 3216f58944e2SKeith Busch */ 321757dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 321857dacad5SJay Sternberg { 321957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 322057dacad5SJay Sternberg 3221bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 322257dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 32230ff9d4e1SKeith Busch 32246db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 32250ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 32261d39e692SKeith Busch nvme_dev_disable(dev, true); 32276db28edaSKeith Busch } 32280ff9d4e1SKeith Busch 3229d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3230d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3231d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3232a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 323387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 323457dacad5SJay Sternberg nvme_dev_remove_admin(dev); 3235c11b7716SChristoph Hellwig nvme_dbbuf_dma_free(dev); 323657dacad5SJay Sternberg nvme_free_queues(dev, 0); 3237c11b7716SChristoph Hellwig mempool_destroy(dev->iod_mempool); 323857dacad5SJay Sternberg nvme_release_prp_pools(dev); 3239b00a726aSKeith Busch nvme_dev_unmap(dev); 3240726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 324157dacad5SJay Sternberg } 324257dacad5SJay Sternberg 324357dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3244d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3245d916b1beSKeith Busch { 3246d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3247d916b1beSKeith Busch } 3248d916b1beSKeith Busch 3249d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3250d916b1beSKeith Busch { 3251d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3252d916b1beSKeith Busch } 3253d916b1beSKeith Busch 3254d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3255d916b1beSKeith Busch { 3256d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3257d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3258d916b1beSKeith Busch 32594eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3260d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3261e5ad96f3SKeith Busch goto reset; 3262e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3263e5ad96f3SKeith Busch goto reset; 3264e5ad96f3SKeith Busch 3265d916b1beSKeith Busch return 0; 3266e5ad96f3SKeith Busch reset: 3267e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3268d916b1beSKeith Busch } 3269d916b1beSKeith Busch 327057dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 327157dacad5SJay Sternberg { 327257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 327357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3274d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3275d916b1beSKeith Busch int ret = -EBUSY; 3276d916b1beSKeith Busch 32774eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 32784eaefe8cSRafael J. Wysocki 3279d916b1beSKeith Busch /* 3280d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3281d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3282d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3283d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3284d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3285d916b1beSKeith Busch * device fully. 32864eaefe8cSRafael J. Wysocki * 32874eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 32884eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 32894eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 32904eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3291d916b1beSKeith Busch */ 32924eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3293cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3294c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3295c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3296d916b1beSKeith Busch 3297d916b1beSKeith Busch nvme_start_freeze(ctrl); 3298d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3299d916b1beSKeith Busch nvme_sync_queues(ctrl); 3300d916b1beSKeith Busch 33015d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3302d916b1beSKeith Busch goto unfreeze; 3303d916b1beSKeith Busch 3304e5ad96f3SKeith Busch /* 3305e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3306e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3307e5ad96f3SKeith Busch * non-operational power state. 3308e5ad96f3SKeith Busch */ 3309e5ad96f3SKeith Busch if (ndev->hmb) { 3310e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3311e5ad96f3SKeith Busch if (ret < 0) 3312e5ad96f3SKeith Busch goto unfreeze; 3313e5ad96f3SKeith Busch } 3314e5ad96f3SKeith Busch 3315d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3316d916b1beSKeith Busch if (ret < 0) 3317d916b1beSKeith Busch goto unfreeze; 3318d916b1beSKeith Busch 33197cbb5c6fSMario Limonciello /* 33207cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 33217cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 33227cbb5c6fSMario Limonciello * want pci interfering. 33237cbb5c6fSMario Limonciello */ 33247cbb5c6fSMario Limonciello pci_save_state(pdev); 33257cbb5c6fSMario Limonciello 3326d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3327d916b1beSKeith Busch if (ret < 0) 3328d916b1beSKeith Busch goto unfreeze; 3329d916b1beSKeith Busch 3330d916b1beSKeith Busch if (ret) { 33317cbb5c6fSMario Limonciello /* discard the saved state */ 33327cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 33337cbb5c6fSMario Limonciello 3334d916b1beSKeith Busch /* 3335d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 333605d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3337d916b1beSKeith Busch */ 3338c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3339d916b1beSKeith Busch ctrl->npss = 0; 3340d916b1beSKeith Busch } 3341d916b1beSKeith Busch unfreeze: 3342d916b1beSKeith Busch nvme_unfreeze(ctrl); 3343d916b1beSKeith Busch return ret; 3344d916b1beSKeith Busch } 3345d916b1beSKeith Busch 3346d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3347d916b1beSKeith Busch { 3348d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 33494e523547SBaolin Wang 3350c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 335157dacad5SJay Sternberg } 335257dacad5SJay Sternberg 3353d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 335457dacad5SJay Sternberg { 335557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 335657dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 335757dacad5SJay Sternberg 3358c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 335957dacad5SJay Sternberg } 336057dacad5SJay Sternberg 336121774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3362d916b1beSKeith Busch .suspend = nvme_suspend, 3363d916b1beSKeith Busch .resume = nvme_resume, 3364d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3365d916b1beSKeith Busch .thaw = nvme_simple_resume, 3366d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3367d916b1beSKeith Busch .restore = nvme_simple_resume, 3368d916b1beSKeith Busch }; 3369d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 337057dacad5SJay Sternberg 3371a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3372a0a3408eSKeith Busch pci_channel_state_t state) 3373a0a3408eSKeith Busch { 3374a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3375a0a3408eSKeith Busch 3376a0a3408eSKeith Busch /* 3377a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3378a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3379a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3380a0a3408eSKeith Busch */ 3381a0a3408eSKeith Busch switch (state) { 3382a0a3408eSKeith Busch case pci_channel_io_normal: 3383a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3384a0a3408eSKeith Busch case pci_channel_io_frozen: 3385d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3386d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3387a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3388a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3389a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3390d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3391d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3392a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3393a0a3408eSKeith Busch } 3394a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3395a0a3408eSKeith Busch } 3396a0a3408eSKeith Busch 3397a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3398a0a3408eSKeith Busch { 3399a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3400a0a3408eSKeith Busch 34011b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3402a0a3408eSKeith Busch pci_restore_state(pdev); 3403d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3404a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3405a0a3408eSKeith Busch } 3406a0a3408eSKeith Busch 3407a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3408a0a3408eSKeith Busch { 340972cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 341072cd4cc2SKeith Busch 341172cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3412a0a3408eSKeith Busch } 3413a0a3408eSKeith Busch 341457dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 341557dacad5SJay Sternberg .error_detected = nvme_error_detected, 341657dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 341757dacad5SJay Sternberg .resume = nvme_error_resume, 3418775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3419775755edSChristoph Hellwig .reset_done = nvme_reset_done, 342057dacad5SJay Sternberg }; 342157dacad5SJay Sternberg 342257dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3423972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 342408095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3425e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3426972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 342799466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3428e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3429972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 343099466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 343125e58af4SWu Zheng NVME_QUIRK_DEALLOCATE_ZEROES | 343225e58af4SWu Zheng NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3433972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3434f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3435f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 343650af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 34379abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 34386c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3439ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3440ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34416299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 34426299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3443540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 34447b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 344566dd346bSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES | 344666dd346bSChristoph Hellwig NVME_QUIRK_BOGUS_NID, }, 344766dd346bSChristoph Hellwig { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 344866dd346bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 34495bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3450c98a8793SKeith Busch .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3451c98a8793SKeith Busch NVME_QUIRK_BOGUS_NID, }, 34520302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 34535e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 34545e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 345554adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 345654adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 34578c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 34588c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3459015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3460015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3461d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3462d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3463d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 34647ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3465abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 34667ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34672cf7a77eSKeith Busch { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 34682cf7a77eSKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 3469c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 347073029c9bSKeith Busch .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 347173029c9bSKeith Busch NVME_QUIRK_BOGUS_NID, }, 3472d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3473d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3474d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3475d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34766e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 34776e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 34786e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3479e1c70d79SLamarque Vieira Souza { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3480e1c70d79SLamarque Vieira Souza .driver_data = NVME_QUIRK_BOGUS_NID, }, 348108b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 34821629de0eSPablo Greco .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 34831629de0eSPablo Greco NVME_QUIRK_BOGUS_NID, }, 3484f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3485f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3486f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 348741f38043SLeo Savernik { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 348841f38043SLeo Savernik .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 34895611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 34905611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3491c4f01a77SKeith Busch { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3492c4f01a77SKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 349302ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 349402ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349589919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 349689919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349743047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 349843047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349943047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 350043047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 350143047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 350243047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 350343047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 350443047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3505dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3506dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3507538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3508538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3509ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3510ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3511ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3512ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3513ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3514ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3515ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3516ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3517ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3518ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 351970ce3455SChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 352070ce3455SChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3521a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3522a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3523a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3524a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 35253765fad5SStefan Reiter { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 35263765fad5SStefan Reiter .driver_data = NVME_QUIRK_BOGUS_NID, }, 3527f37527a0SDennis P. Kliem { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3528f37527a0SDennis P. Kliem .driver_data = NVME_QUIRK_BOGUS_NID, }, 3529d5d3c100SXi Ruoyao { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3530d5d3c100SXi Ruoyao .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 35316b961bceSNing Wang { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 35326b961bceSNing Wang .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3533d6c52fa3STobias Gruetzmacher { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3534d6c52fa3STobias Gruetzmacher .driver_data = NVME_QUIRK_BOGUS_NID, }, 3535200dccd0SShyamin Ayesh { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3536200dccd0SShyamin Ayesh .driver_data = NVME_QUIRK_BOGUS_NID, }, 353780b26240SAbhijit { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 353880b26240SAbhijit .driver_data = NVME_QUIRK_BOGUS_NID, }, 35394bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 35404bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35414bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 35424bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35434bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 35444bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35454bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 35464bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35474bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 35484bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35494bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 35504bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 355198f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 355298f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3553124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 355466341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 355566341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3556d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3557a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3558a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 35590b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 356057dacad5SJay Sternberg { 0, } 356157dacad5SJay Sternberg }; 356257dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 356357dacad5SJay Sternberg 356457dacad5SJay Sternberg static struct pci_driver nvme_driver = { 356557dacad5SJay Sternberg .name = "nvme", 356657dacad5SJay Sternberg .id_table = nvme_id_table, 356757dacad5SJay Sternberg .probe = nvme_probe, 356857dacad5SJay Sternberg .remove = nvme_remove, 356957dacad5SJay Sternberg .shutdown = nvme_shutdown, 357057dacad5SJay Sternberg .driver = { 3571eac3ef26SChristoph Hellwig .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3572eac3ef26SChristoph Hellwig #ifdef CONFIG_PM_SLEEP 357357dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 3574d916b1beSKeith Busch #endif 3575eac3ef26SChristoph Hellwig }, 357674d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 357757dacad5SJay Sternberg .err_handler = &nvme_err_handler, 357857dacad5SJay Sternberg }; 357957dacad5SJay Sternberg 358057dacad5SJay Sternberg static int __init nvme_init(void) 358157dacad5SJay Sternberg { 358281101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 358381101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 358481101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3585612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3586c372cdd1SKeith Busch BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) > 3587c372cdd1SKeith Busch S8_MAX); 358817c33167SKeith Busch 35899a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 359057dacad5SJay Sternberg } 359157dacad5SJay Sternberg 359257dacad5SJay Sternberg static void __exit nvme_exit(void) 359357dacad5SJay Sternberg { 359457dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 359503e0f3a6SMing Lei flush_workqueue(nvme_wq); 359657dacad5SJay Sternberg } 359757dacad5SJay Sternberg 359857dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 359957dacad5SJay Sternberg MODULE_LICENSE("GPL"); 360057dacad5SJay Sternberg MODULE_VERSION("1.0"); 360157dacad5SJay Sternberg module_init(nvme_init); 360257dacad5SJay Sternberg module_exit(nvme_exit); 3603