15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1457dacad5SJay Sternberg #include <linux/init.h> 1557dacad5SJay Sternberg #include <linux/interrupt.h> 1657dacad5SJay Sternberg #include <linux/io.h> 1757dacad5SJay Sternberg #include <linux/mm.h> 1857dacad5SJay Sternberg #include <linux/module.h> 1977bf25eaSKeith Busch #include <linux/mutex.h> 20d0877473SKeith Busch #include <linux/once.h> 2157dacad5SJay Sternberg #include <linux/pci.h> 22d916b1beSKeith Busch #include <linux/suspend.h> 2357dacad5SJay Sternberg #include <linux/t10-pi.h> 2457dacad5SJay Sternberg #include <linux/types.h> 259cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 26a98e58e5SScott Bauer #include <linux/sed-opal.h> 270f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2857dacad5SJay Sternberg 29604c01d5Syupeng #include "trace.h" 3057dacad5SJay Sternberg #include "nvme.h" 3157dacad5SJay Sternberg 32c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 338a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3457dacad5SJay Sternberg 35a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 36adf68f21SChristoph Hellwig 37943e942eSJens Axboe /* 38943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 39943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 40943e942eSJens Axboe */ 41943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 42943e942eSJens Axboe #define NVME_MAX_SEGS 127 43943e942eSJens Axboe 4457dacad5SJay Sternberg static int use_threaded_interrupts; 4557dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4657dacad5SJay Sternberg 4757dacad5SJay Sternberg static bool use_cmb_sqes = true; 4869f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4957dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5057dacad5SJay Sternberg 5187ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5287ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5387ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5487ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5557dacad5SJay Sternberg 56a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 57a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 58a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 59a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 60a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 61a7a7cbe3SChaitanya Kulkarni 62b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 63b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 64b27c1e68Sweiping zhang .set = io_queue_depth_set, 6561f3b896SChaitanya Kulkarni .get = param_get_uint, 66b27c1e68Sweiping zhang }; 67b27c1e68Sweiping zhang 6861f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 69b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 70b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 71b27c1e68Sweiping zhang 729c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 739c9e76d5SWeiping Zhang { 749c9e76d5SWeiping Zhang unsigned int n; 759c9e76d5SWeiping Zhang int ret; 769c9e76d5SWeiping Zhang 779c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 789c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 799c9e76d5SWeiping Zhang return -EINVAL; 809c9e76d5SWeiping Zhang return param_set_uint(val, kp); 819c9e76d5SWeiping Zhang } 829c9e76d5SWeiping Zhang 839c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 849c9e76d5SWeiping Zhang .set = io_queue_count_set, 859c9e76d5SWeiping Zhang .get = param_get_uint, 869c9e76d5SWeiping Zhang }; 879c9e76d5SWeiping Zhang 883f68baf7SKeith Busch static unsigned int write_queues; 899c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 903b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 913b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 923b6592f7SJens Axboe "will share a queue set."); 933b6592f7SJens Axboe 943f68baf7SKeith Busch static unsigned int poll_queues; 959c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 964b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 974b04cc6aSJens Axboe 98df4f9bc4SDavid E. Box static bool noacpi; 99df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 100df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 101df4f9bc4SDavid E. Box 1021c63dc66SChristoph Hellwig struct nvme_dev; 1031c63dc66SChristoph Hellwig struct nvme_queue; 10457dacad5SJay Sternberg 105a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1068fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 10757dacad5SJay Sternberg 10857dacad5SJay Sternberg /* 1091c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1101c63dc66SChristoph Hellwig */ 1111c63dc66SChristoph Hellwig struct nvme_dev { 112147b27e4SSagi Grimberg struct nvme_queue *queues; 1131c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1141c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1151c63dc66SChristoph Hellwig u32 __iomem *dbs; 1161c63dc66SChristoph Hellwig struct device *dev; 1171c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1181c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1191c63dc66SChristoph Hellwig unsigned online_queues; 1201c63dc66SChristoph Hellwig unsigned max_qid; 121e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12222b55601SKeith Busch unsigned int num_vecs; 1237442ddceSJohn Garry u32 q_depth; 124c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1251c63dc66SChristoph Hellwig u32 db_stride; 1261c63dc66SChristoph Hellwig void __iomem *bar; 12797f6ef64SXu Yu unsigned long bar_mapped_size; 1285c8809e6SChristoph Hellwig struct work_struct remove_work; 12977bf25eaSKeith Busch struct mutex shutdown_lock; 1301c63dc66SChristoph Hellwig bool subsystem; 1311c63dc66SChristoph Hellwig u64 cmb_size; 1320f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1331c63dc66SChristoph Hellwig u32 cmbsz; 134202021c1SStephen Bates u32 cmbloc; 1351c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 136d916b1beSKeith Busch u32 last_ps; 13787ad72a5SChristoph Hellwig 138943e942eSJens Axboe mempool_t *iod_mempool; 139943e942eSJens Axboe 14087ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 141f9f38e33SHelen Koike u32 *dbbuf_dbs; 142f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 143f9f38e33SHelen Koike u32 *dbbuf_eis; 144f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 14587ad72a5SChristoph Hellwig 14687ad72a5SChristoph Hellwig /* host memory buffer support: */ 14787ad72a5SChristoph Hellwig u64 host_mem_size; 14887ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1494033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15087ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15187ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1522a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1532a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1542a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 15557dacad5SJay Sternberg }; 15657dacad5SJay Sternberg 157b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 158b27c1e68Sweiping zhang { 15961f3b896SChaitanya Kulkarni int ret; 1607442ddceSJohn Garry u32 n; 161b27c1e68Sweiping zhang 1627442ddceSJohn Garry ret = kstrtou32(val, 10, &n); 163b27c1e68Sweiping zhang if (ret != 0 || n < 2) 164b27c1e68Sweiping zhang return -EINVAL; 165b27c1e68Sweiping zhang 1667442ddceSJohn Garry return param_set_uint(val, kp); 167b27c1e68Sweiping zhang } 168b27c1e68Sweiping zhang 169f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 170f9f38e33SHelen Koike { 171f9f38e33SHelen Koike return qid * 2 * stride; 172f9f38e33SHelen Koike } 173f9f38e33SHelen Koike 174f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 175f9f38e33SHelen Koike { 176f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 177f9f38e33SHelen Koike } 178f9f38e33SHelen Koike 1791c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1801c63dc66SChristoph Hellwig { 1811c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1821c63dc66SChristoph Hellwig } 1831c63dc66SChristoph Hellwig 18457dacad5SJay Sternberg /* 18557dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18657dacad5SJay Sternberg * commands and one for I/O commands). 18757dacad5SJay Sternberg */ 18857dacad5SJay Sternberg struct nvme_queue { 18957dacad5SJay Sternberg struct nvme_dev *dev; 1901ab0cd69SJens Axboe spinlock_t sq_lock; 191c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1923a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1933a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19474943d45SKeith Busch struct nvme_completion *cqes; 19557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19757dacad5SJay Sternberg u32 __iomem *q_db; 1987442ddceSJohn Garry u32 q_depth; 1997c349ddeSKeith Busch u16 cq_vector; 20057dacad5SJay Sternberg u16 sq_tail; 20138210800SKeith Busch u16 last_sq_tail; 20257dacad5SJay Sternberg u16 cq_head; 20357dacad5SJay Sternberg u16 qid; 20457dacad5SJay Sternberg u8 cq_phase; 205c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2064e224106SChristoph Hellwig unsigned long flags; 2074e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20863223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 209d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2107c349ddeSKeith Busch #define NVMEQ_POLLED 3 211f9f38e33SHelen Koike u32 *dbbuf_sq_db; 212f9f38e33SHelen Koike u32 *dbbuf_cq_db; 213f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 214f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 215d1ed6aa1SChristoph Hellwig struct completion delete_done; 21657dacad5SJay Sternberg }; 21757dacad5SJay Sternberg 21857dacad5SJay Sternberg /* 2199b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2209b048119SChristoph Hellwig * 2219b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2229b048119SChristoph Hellwig * to the actual struct scatterlist. 22371bd150cSChristoph Hellwig */ 22471bd150cSChristoph Hellwig struct nvme_iod { 225d49187e9SChristoph Hellwig struct nvme_request req; 226f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 227a7a7cbe3SChaitanya Kulkarni bool use_sgl; 228f4800d6dSChristoph Hellwig int aborted; 22971bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 23071bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 23171bd150cSChristoph Hellwig dma_addr_t first_dma; 232dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 233783b94bdSChristoph Hellwig dma_addr_t meta_dma; 234f4800d6dSChristoph Hellwig struct scatterlist *sg; 23557dacad5SJay Sternberg }; 23657dacad5SJay Sternberg 2372a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2383b6592f7SJens Axboe { 2392a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 240f9f38e33SHelen Koike } 241f9f38e33SHelen Koike 242f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 243f9f38e33SHelen Koike { 2442a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 245f9f38e33SHelen Koike 246f9f38e33SHelen Koike if (dev->dbbuf_dbs) 247f9f38e33SHelen Koike return 0; 248f9f38e33SHelen Koike 249f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 250f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 251f9f38e33SHelen Koike GFP_KERNEL); 252f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 253f9f38e33SHelen Koike return -ENOMEM; 254f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 255f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 256f9f38e33SHelen Koike GFP_KERNEL); 257f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 258f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 259f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 260f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 261f9f38e33SHelen Koike return -ENOMEM; 262f9f38e33SHelen Koike } 263f9f38e33SHelen Koike 264f9f38e33SHelen Koike return 0; 265f9f38e33SHelen Koike } 266f9f38e33SHelen Koike 267f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 268f9f38e33SHelen Koike { 2692a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 270f9f38e33SHelen Koike 271f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 272f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 273f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 274f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 275f9f38e33SHelen Koike } 276f9f38e33SHelen Koike if (dev->dbbuf_eis) { 277f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 278f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 279f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 280f9f38e33SHelen Koike } 281f9f38e33SHelen Koike } 282f9f38e33SHelen Koike 283f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 284f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 285f9f38e33SHelen Koike { 286f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 287f9f38e33SHelen Koike return; 288f9f38e33SHelen Koike 289f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 290f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 291f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 292f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 293f9f38e33SHelen Koike } 294f9f38e33SHelen Koike 2950f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 2960f0d2c87SMinwoo Im { 2970f0d2c87SMinwoo Im if (!nvmeq->qid) 2980f0d2c87SMinwoo Im return; 2990f0d2c87SMinwoo Im 3000f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3010f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3020f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3030f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3040f0d2c87SMinwoo Im } 3050f0d2c87SMinwoo Im 306f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 307f9f38e33SHelen Koike { 308f9f38e33SHelen Koike struct nvme_command c; 3090f0d2c87SMinwoo Im unsigned int i; 310f9f38e33SHelen Koike 311f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 312f9f38e33SHelen Koike return; 313f9f38e33SHelen Koike 314f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 315f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 316f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 317f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 318f9f38e33SHelen Koike 319f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3209bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 321f9f38e33SHelen Koike /* Free memory and continue on */ 322f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3230f0d2c87SMinwoo Im 3240f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3250f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 326f9f38e33SHelen Koike } 327f9f38e33SHelen Koike } 328f9f38e33SHelen Koike 329f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 330f9f38e33SHelen Koike { 331f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 332f9f38e33SHelen Koike } 333f9f38e33SHelen Koike 334f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 335f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 336f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 337f9f38e33SHelen Koike { 338f9f38e33SHelen Koike if (dbbuf_db) { 339f9f38e33SHelen Koike u16 old_value; 340f9f38e33SHelen Koike 341f9f38e33SHelen Koike /* 342f9f38e33SHelen Koike * Ensure that the queue is written before updating 343f9f38e33SHelen Koike * the doorbell in memory 344f9f38e33SHelen Koike */ 345f9f38e33SHelen Koike wmb(); 346f9f38e33SHelen Koike 347f9f38e33SHelen Koike old_value = *dbbuf_db; 348f9f38e33SHelen Koike *dbbuf_db = value; 349f9f38e33SHelen Koike 350f1ed3df2SMichal Wnukowski /* 351f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 352f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 353f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 354f1ed3df2SMichal Wnukowski * the doorbell. 355f1ed3df2SMichal Wnukowski */ 356f1ed3df2SMichal Wnukowski mb(); 357f1ed3df2SMichal Wnukowski 358f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 359f9f38e33SHelen Koike return false; 360f9f38e33SHelen Koike } 361f9f38e33SHelen Koike 362f9f38e33SHelen Koike return true; 36357dacad5SJay Sternberg } 36457dacad5SJay Sternberg 36557dacad5SJay Sternberg /* 36657dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 36757dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 36857dacad5SJay Sternberg * the I/O. 36957dacad5SJay Sternberg */ 370b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 37157dacad5SJay Sternberg { 372b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3736c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 37457dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 37557dacad5SJay Sternberg } 37657dacad5SJay Sternberg 377a7a7cbe3SChaitanya Kulkarni /* 378a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 379a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 380a7a7cbe3SChaitanya Kulkarni */ 381b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 382f4800d6dSChristoph Hellwig { 383b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 384b13c6393SChaitanya Kulkarni PAGE_SIZE); 385f4800d6dSChristoph Hellwig } 386f4800d6dSChristoph Hellwig 387b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 38857dacad5SJay Sternberg { 389b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 390a7a7cbe3SChaitanya Kulkarni 391b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 392b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 393a7a7cbe3SChaitanya Kulkarni } 394a7a7cbe3SChaitanya Kulkarni 39557dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39657dacad5SJay Sternberg unsigned int hctx_idx) 39757dacad5SJay Sternberg { 39857dacad5SJay Sternberg struct nvme_dev *dev = data; 399147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40057dacad5SJay Sternberg 40157dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40257dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40357dacad5SJay Sternberg 40457dacad5SJay Sternberg hctx->driver_data = nvmeq; 40557dacad5SJay Sternberg return 0; 40657dacad5SJay Sternberg } 40757dacad5SJay Sternberg 40857dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40957dacad5SJay Sternberg unsigned int hctx_idx) 41057dacad5SJay Sternberg { 41157dacad5SJay Sternberg struct nvme_dev *dev = data; 412147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41357dacad5SJay Sternberg 41457dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41557dacad5SJay Sternberg hctx->driver_data = nvmeq; 41657dacad5SJay Sternberg return 0; 41757dacad5SJay Sternberg } 41857dacad5SJay Sternberg 419d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 420d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 42157dacad5SJay Sternberg { 422d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 423f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4240350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 425147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 42657dacad5SJay Sternberg 42757dacad5SJay Sternberg BUG_ON(!nvmeq); 428f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 42959e29ce6SSagi Grimberg 43059e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 43157dacad5SJay Sternberg return 0; 43257dacad5SJay Sternberg } 43357dacad5SJay Sternberg 4343b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4353b6592f7SJens Axboe { 4363b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4373b6592f7SJens Axboe if (dev->num_vecs > 1) 4383b6592f7SJens Axboe return 1; 4393b6592f7SJens Axboe 4403b6592f7SJens Axboe return 0; 4413b6592f7SJens Axboe } 4423b6592f7SJens Axboe 443dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 444dca51e78SChristoph Hellwig { 445dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4463b6592f7SJens Axboe int i, qoff, offset; 447dca51e78SChristoph Hellwig 4483b6592f7SJens Axboe offset = queue_irq_offset(dev); 4493b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4503b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4513b6592f7SJens Axboe 4523b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4533b6592f7SJens Axboe if (!map->nr_queues) { 454e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4557e849dd9SChristoph Hellwig continue; 4563b6592f7SJens Axboe } 4573b6592f7SJens Axboe 4584b04cc6aSJens Axboe /* 4594b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4604b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4614b04cc6aSJens Axboe */ 4623b6592f7SJens Axboe map->queue_offset = qoff; 463cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4643b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4654b04cc6aSJens Axboe else 4664b04cc6aSJens Axboe blk_mq_map_queues(map); 4673b6592f7SJens Axboe qoff += map->nr_queues; 4683b6592f7SJens Axboe offset += map->nr_queues; 4693b6592f7SJens Axboe } 4703b6592f7SJens Axboe 4713b6592f7SJens Axboe return 0; 472dca51e78SChristoph Hellwig } 473dca51e78SChristoph Hellwig 47438210800SKeith Busch /* 47538210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47638210800SKeith Busch */ 47738210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47804f3eafdSJens Axboe { 47938210800SKeith Busch if (!write_sq) { 48038210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 48138210800SKeith Busch 48238210800SKeith Busch if (next_tail == nvmeq->q_depth) 48338210800SKeith Busch next_tail = 0; 48438210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 48538210800SKeith Busch return; 48638210800SKeith Busch } 48738210800SKeith Busch 48804f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 48904f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 49004f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 49138210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 49204f3eafdSJens Axboe } 49304f3eafdSJens Axboe 49457dacad5SJay Sternberg /** 49590ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 49657dacad5SJay Sternberg * @nvmeq: The queue to use 49757dacad5SJay Sternberg * @cmd: The command to send 49804f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 49957dacad5SJay Sternberg */ 50004f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 50104f3eafdSJens Axboe bool write_sq) 50257dacad5SJay Sternberg { 50390ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 504c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 505c1e0cc7eSBenjamin Herrenschmidt cmd, sizeof(*cmd)); 50690ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 50790ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 50838210800SKeith Busch nvme_write_sq_db(nvmeq, write_sq); 50904f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 51004f3eafdSJens Axboe } 51104f3eafdSJens Axboe 51204f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 51304f3eafdSJens Axboe { 51404f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 51504f3eafdSJens Axboe 51604f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 51738210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 51838210800SKeith Busch nvme_write_sq_db(nvmeq, true); 51990ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 52057dacad5SJay Sternberg } 52157dacad5SJay Sternberg 522a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 52357dacad5SJay Sternberg { 524f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 525a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 52657dacad5SJay Sternberg } 52757dacad5SJay Sternberg 528955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 529955b1b5aSMinwoo Im { 530955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 53120469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 532955b1b5aSMinwoo Im unsigned int avg_seg_size; 533955b1b5aSMinwoo Im 53420469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 535955b1b5aSMinwoo Im 536955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 537955b1b5aSMinwoo Im return false; 538955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 539955b1b5aSMinwoo Im return false; 540955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 541955b1b5aSMinwoo Im return false; 542955b1b5aSMinwoo Im return true; 543955b1b5aSMinwoo Im } 544955b1b5aSMinwoo Im 5457fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 54657dacad5SJay Sternberg { 547f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5486c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 549a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 55057dacad5SJay Sternberg int i; 55157dacad5SJay Sternberg 552dff824b2SChristoph Hellwig if (iod->dma_len) { 553f2fa006fSIsrael Rukshin dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 554f2fa006fSIsrael Rukshin rq_dma_dir(req)); 555dff824b2SChristoph Hellwig return; 556dff824b2SChristoph Hellwig } 557dff824b2SChristoph Hellwig 558dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 559dff824b2SChristoph Hellwig 5607f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5617f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5627f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5637f73eac3SLogan Gunthorpe else 564dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5657fe07d14SChristoph Hellwig 5667fe07d14SChristoph Hellwig 56757dacad5SJay Sternberg if (iod->npages == 0) 568a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 569a7a7cbe3SChaitanya Kulkarni dma_addr); 570a7a7cbe3SChaitanya Kulkarni 57157dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 572a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 573a7a7cbe3SChaitanya Kulkarni 574a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 575a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 576a7a7cbe3SChaitanya Kulkarni 577a7a7cbe3SChaitanya Kulkarni next_dma_addr = 578a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 579a7a7cbe3SChaitanya Kulkarni } else { 580a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 581a7a7cbe3SChaitanya Kulkarni 582a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 583a7a7cbe3SChaitanya Kulkarni } 584a7a7cbe3SChaitanya Kulkarni 585a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 586a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 58757dacad5SJay Sternberg } 58857dacad5SJay Sternberg 589943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 59057dacad5SJay Sternberg } 59157dacad5SJay Sternberg 592d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 593d0877473SKeith Busch { 594d0877473SKeith Busch int i; 595d0877473SKeith Busch struct scatterlist *sg; 596d0877473SKeith Busch 597d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 598d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 599d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 600d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 601d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 602d0877473SKeith Busch sg_dma_len(sg)); 603d0877473SKeith Busch } 604d0877473SKeith Busch } 605d0877473SKeith Busch 606a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 607a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 60857dacad5SJay Sternberg { 609f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 61057dacad5SJay Sternberg struct dma_pool *pool; 611b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 61257dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 61357dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 61457dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6156c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 61657dacad5SJay Sternberg __le64 *prp_list; 617a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 61857dacad5SJay Sternberg dma_addr_t prp_dma; 61957dacad5SJay Sternberg int nprps, i; 62057dacad5SJay Sternberg 6216c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6225228b328SJan H. Schönherr if (length <= 0) { 6235228b328SJan H. Schönherr iod->first_dma = 0; 624a7a7cbe3SChaitanya Kulkarni goto done; 6255228b328SJan H. Schönherr } 62657dacad5SJay Sternberg 6276c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 62857dacad5SJay Sternberg if (dma_len) { 6296c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 63057dacad5SJay Sternberg } else { 63157dacad5SJay Sternberg sg = sg_next(sg); 63257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 63357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 63457dacad5SJay Sternberg } 63557dacad5SJay Sternberg 6366c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 63757dacad5SJay Sternberg iod->first_dma = dma_addr; 638a7a7cbe3SChaitanya Kulkarni goto done; 63957dacad5SJay Sternberg } 64057dacad5SJay Sternberg 6416c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 64257dacad5SJay Sternberg if (nprps <= (256 / 8)) { 64357dacad5SJay Sternberg pool = dev->prp_small_pool; 64457dacad5SJay Sternberg iod->npages = 0; 64557dacad5SJay Sternberg } else { 64657dacad5SJay Sternberg pool = dev->prp_page_pool; 64757dacad5SJay Sternberg iod->npages = 1; 64857dacad5SJay Sternberg } 64957dacad5SJay Sternberg 65069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65157dacad5SJay Sternberg if (!prp_list) { 65257dacad5SJay Sternberg iod->first_dma = dma_addr; 65357dacad5SJay Sternberg iod->npages = -1; 65486eea289SKeith Busch return BLK_STS_RESOURCE; 65557dacad5SJay Sternberg } 65657dacad5SJay Sternberg list[0] = prp_list; 65757dacad5SJay Sternberg iod->first_dma = prp_dma; 65857dacad5SJay Sternberg i = 0; 65957dacad5SJay Sternberg for (;;) { 6606c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 66157dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 66269d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 66357dacad5SJay Sternberg if (!prp_list) 66486eea289SKeith Busch return BLK_STS_RESOURCE; 66557dacad5SJay Sternberg list[iod->npages++] = prp_list; 66657dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 66757dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 66857dacad5SJay Sternberg i = 1; 66957dacad5SJay Sternberg } 67057dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6716c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6726c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6736c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 67457dacad5SJay Sternberg if (length <= 0) 67557dacad5SJay Sternberg break; 67657dacad5SJay Sternberg if (dma_len > 0) 67757dacad5SJay Sternberg continue; 67886eea289SKeith Busch if (unlikely(dma_len < 0)) 67986eea289SKeith Busch goto bad_sgl; 68057dacad5SJay Sternberg sg = sg_next(sg); 68157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 68257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 68357dacad5SJay Sternberg } 68457dacad5SJay Sternberg 685a7a7cbe3SChaitanya Kulkarni done: 686a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 687a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 688a7a7cbe3SChaitanya Kulkarni 68986eea289SKeith Busch return BLK_STS_OK; 69086eea289SKeith Busch 69186eea289SKeith Busch bad_sgl: 692d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 693d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 694d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 69586eea289SKeith Busch return BLK_STS_IOERR; 69657dacad5SJay Sternberg } 69757dacad5SJay Sternberg 698a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 699a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 700a7a7cbe3SChaitanya Kulkarni { 701a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 702a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 703a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 704a7a7cbe3SChaitanya Kulkarni } 705a7a7cbe3SChaitanya Kulkarni 706a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 707a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 708a7a7cbe3SChaitanya Kulkarni { 709a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 710a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 711a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 712a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 713a7a7cbe3SChaitanya Kulkarni } else { 714a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 715a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 716a7a7cbe3SChaitanya Kulkarni } 717a7a7cbe3SChaitanya Kulkarni } 718a7a7cbe3SChaitanya Kulkarni 719a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 720b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 721a7a7cbe3SChaitanya Kulkarni { 722a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 723a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 724a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 725a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 726a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 727b0f2853bSChristoph Hellwig int i = 0; 728a7a7cbe3SChaitanya Kulkarni 729a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 730a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 731a7a7cbe3SChaitanya Kulkarni 732b0f2853bSChristoph Hellwig if (entries == 1) { 733a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 734a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 735a7a7cbe3SChaitanya Kulkarni } 736a7a7cbe3SChaitanya Kulkarni 737a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 738a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 739a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 740a7a7cbe3SChaitanya Kulkarni } else { 741a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 742a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 743a7a7cbe3SChaitanya Kulkarni } 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 746a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 747a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 748a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 749a7a7cbe3SChaitanya Kulkarni } 750a7a7cbe3SChaitanya Kulkarni 751a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 752a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 753a7a7cbe3SChaitanya Kulkarni 754a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 755a7a7cbe3SChaitanya Kulkarni 756a7a7cbe3SChaitanya Kulkarni do { 757a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 758a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 759a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 760a7a7cbe3SChaitanya Kulkarni 761a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 762a7a7cbe3SChaitanya Kulkarni if (!sg_list) 763a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 764a7a7cbe3SChaitanya Kulkarni 765a7a7cbe3SChaitanya Kulkarni i = 0; 766a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 767a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 768a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 769a7a7cbe3SChaitanya Kulkarni } 770a7a7cbe3SChaitanya Kulkarni 771a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 772a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 773b0f2853bSChristoph Hellwig } while (--entries > 0); 774a7a7cbe3SChaitanya Kulkarni 775a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 776a7a7cbe3SChaitanya Kulkarni } 777a7a7cbe3SChaitanya Kulkarni 778dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 779dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 780dff824b2SChristoph Hellwig struct bio_vec *bv) 781dff824b2SChristoph Hellwig { 782dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7836c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7846c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 785dff824b2SChristoph Hellwig 786dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 787dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 788dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 789dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 790dff824b2SChristoph Hellwig 791dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 792dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 793dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 794359c1f88SBaolin Wang return BLK_STS_OK; 795dff824b2SChristoph Hellwig } 796dff824b2SChristoph Hellwig 79729791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 79829791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 79929791057SChristoph Hellwig struct bio_vec *bv) 80029791057SChristoph Hellwig { 80129791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 80229791057SChristoph Hellwig 80329791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 80429791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 80529791057SChristoph Hellwig return BLK_STS_RESOURCE; 80629791057SChristoph Hellwig iod->dma_len = bv->bv_len; 80729791057SChristoph Hellwig 808049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 80929791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 81029791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 81129791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 812359c1f88SBaolin Wang return BLK_STS_OK; 81329791057SChristoph Hellwig } 81429791057SChristoph Hellwig 815fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 816b131c61dSChristoph Hellwig struct nvme_command *cmnd) 81757dacad5SJay Sternberg { 818f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 81970479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 820b0f2853bSChristoph Hellwig int nr_mapped; 82157dacad5SJay Sternberg 822dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 823dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 824dff824b2SChristoph Hellwig 825dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8266c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 827dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 828dff824b2SChristoph Hellwig &cmnd->rw, &bv); 82929791057SChristoph Hellwig 83029791057SChristoph Hellwig if (iod->nvmeq->qid && 83129791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 83229791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 83329791057SChristoph Hellwig &cmnd->rw, &bv); 834dff824b2SChristoph Hellwig } 835dff824b2SChristoph Hellwig } 836dff824b2SChristoph Hellwig 837dff824b2SChristoph Hellwig iod->dma_len = 0; 8389b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8399b048119SChristoph Hellwig if (!iod->sg) 8409b048119SChristoph Hellwig return BLK_STS_RESOURCE; 841f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 84270479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 843ba1ca37eSChristoph Hellwig if (!iod->nents) 844ba1ca37eSChristoph Hellwig goto out; 845ba1ca37eSChristoph Hellwig 846e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8472b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8482b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 849e0596ab2SLogan Gunthorpe else 850e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 85170479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 852b0f2853bSChristoph Hellwig if (!nr_mapped) 853ba1ca37eSChristoph Hellwig goto out; 854ba1ca37eSChristoph Hellwig 85570479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 856955b1b5aSMinwoo Im if (iod->use_sgl) 857b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 858a7a7cbe3SChaitanya Kulkarni else 859a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 860ba1ca37eSChristoph Hellwig out: 8614aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8627fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 863ba1ca37eSChristoph Hellwig return ret; 86457dacad5SJay Sternberg } 86557dacad5SJay Sternberg 8664aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8674aedb705SChristoph Hellwig struct nvme_command *cmnd) 8684aedb705SChristoph Hellwig { 8694aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8704aedb705SChristoph Hellwig 8714aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8724aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8734aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8744aedb705SChristoph Hellwig return BLK_STS_IOERR; 8754aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 876359c1f88SBaolin Wang return BLK_STS_OK; 8774aedb705SChristoph Hellwig } 8784aedb705SChristoph Hellwig 87957dacad5SJay Sternberg /* 88057dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 88157dacad5SJay Sternberg */ 882fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 88357dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 88457dacad5SJay Sternberg { 88557dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 88657dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 88757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 88857dacad5SJay Sternberg struct request *req = bd->rq; 8899b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 890ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 891ebe6d874SChristoph Hellwig blk_status_t ret; 89257dacad5SJay Sternberg 8939b048119SChristoph Hellwig iod->aborted = 0; 8949b048119SChristoph Hellwig iod->npages = -1; 8959b048119SChristoph Hellwig iod->nents = 0; 8969b048119SChristoph Hellwig 897d1f06f4aSJens Axboe /* 898d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 899d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 900d1f06f4aSJens Axboe */ 9014e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 902d1f06f4aSJens Axboe return BLK_STS_IOERR; 903d1f06f4aSJens Axboe 904f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 905fc17b653SChristoph Hellwig if (ret) 906f4800d6dSChristoph Hellwig return ret; 90757dacad5SJay Sternberg 908fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 909b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 910fc17b653SChristoph Hellwig if (ret) 9119b048119SChristoph Hellwig goto out_free_cmd; 912fc17b653SChristoph Hellwig } 913ba1ca37eSChristoph Hellwig 9144aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 9154aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 9164aedb705SChristoph Hellwig if (ret) 9174aedb705SChristoph Hellwig goto out_unmap_data; 9184aedb705SChristoph Hellwig } 9194aedb705SChristoph Hellwig 920aae239e1SChristoph Hellwig blk_mq_start_request(req); 92104f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 922fc17b653SChristoph Hellwig return BLK_STS_OK; 9234aedb705SChristoph Hellwig out_unmap_data: 9244aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 925f9d03f96SChristoph Hellwig out_free_cmd: 926f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 927ba1ca37eSChristoph Hellwig return ret; 92857dacad5SJay Sternberg } 92957dacad5SJay Sternberg 93077f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 931eee417b0SChristoph Hellwig { 932f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9334aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 934eee417b0SChristoph Hellwig 9354aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9364aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9374aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 938b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9394aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 94077f02a7aSChristoph Hellwig nvme_complete_rq(req); 94157dacad5SJay Sternberg } 94257dacad5SJay Sternberg 943d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 944750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 945d783e0bdSMarta Rybczynska { 94674943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 94774943d45SKeith Busch 94874943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 949d783e0bdSMarta Rybczynska } 950d783e0bdSMarta Rybczynska 951eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 95257dacad5SJay Sternberg { 953eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 95457dacad5SJay Sternberg 955eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 956eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 957eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 958eb281c82SSagi Grimberg } 959adf68f21SChristoph Hellwig 960cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 961cfa27356SChristoph Hellwig { 962cfa27356SChristoph Hellwig if (!nvmeq->qid) 963cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 964cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 965cfa27356SChristoph Hellwig } 966cfa27356SChristoph Hellwig 9675cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 96857dacad5SJay Sternberg { 96974943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 970*62df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 97157dacad5SJay Sternberg struct request *req; 972adf68f21SChristoph Hellwig 973adf68f21SChristoph Hellwig /* 974adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 975adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 976adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 977adf68f21SChristoph Hellwig * for them but rather special case them here. 978adf68f21SChristoph Hellwig */ 979*62df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 9807bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 98183a12fb7SSagi Grimberg cqe->status, &cqe->result); 982a0fa9647SJens Axboe return; 98357dacad5SJay Sternberg } 98457dacad5SJay Sternberg 985*62df8016SLalithambika Krishnakumar req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id); 98650b7c243SXianting Tian if (unlikely(!req)) { 98750b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 98850b7c243SXianting Tian "invalid id %d completed on queue %d\n", 989*62df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 99050b7c243SXianting Tian return; 99150b7c243SXianting Tian } 99250b7c243SXianting Tian 993604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 9942eb81a33SChristoph Hellwig if (!nvme_try_complete_req(req, cqe->status, cqe->result)) 995ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 99683a12fb7SSagi Grimberg } 99757dacad5SJay Sternberg 9985cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9995cb525c8SJens Axboe { 1000a8de6639SAlexey Dobriyan u16 tmp = nvmeq->cq_head + 1; 1001a8de6639SAlexey Dobriyan 1002a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1003920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1004e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1005a8de6639SAlexey Dobriyan } else { 1006a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1007920d13a8SSagi Grimberg } 1008a0fa9647SJens Axboe } 1009a0fa9647SJens Axboe 1010324b494cSKeith Busch static inline int nvme_process_cq(struct nvme_queue *nvmeq) 1011a0fa9647SJens Axboe { 10121052b8acSJens Axboe int found = 0; 101383a12fb7SSagi Grimberg 10141052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10151052b8acSJens Axboe found++; 1016b69e2ef2SKeith Busch /* 1017b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1018b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1019b69e2ef2SKeith Busch */ 1020b69e2ef2SKeith Busch dma_rmb(); 1021324b494cSKeith Busch nvme_handle_cqe(nvmeq, nvmeq->cq_head); 10225cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 102357dacad5SJay Sternberg } 102457dacad5SJay Sternberg 1025324b494cSKeith Busch if (found) 1026eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10275cb525c8SJens Axboe return found; 102857dacad5SJay Sternberg } 102957dacad5SJay Sternberg 103057dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 103157dacad5SJay Sternberg { 103257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 103368fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10345cb525c8SJens Axboe 10353a7afd8eSChristoph Hellwig /* 10363a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10373a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10383a7afd8eSChristoph Hellwig */ 10393a7afd8eSChristoph Hellwig rmb(); 1040324b494cSKeith Busch if (nvme_process_cq(nvmeq)) 1041324b494cSKeith Busch ret = IRQ_HANDLED; 10423a7afd8eSChristoph Hellwig wmb(); 10435cb525c8SJens Axboe 104468fa9dbeSJens Axboe return ret; 104557dacad5SJay Sternberg } 104657dacad5SJay Sternberg 104757dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 104857dacad5SJay Sternberg { 104957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10504e523547SBaolin Wang 1051750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 105257dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1053d783e0bdSMarta Rybczynska return IRQ_NONE; 105457dacad5SJay Sternberg } 105557dacad5SJay Sternberg 10560b2a8a9fSChristoph Hellwig /* 1057fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 10580b2a8a9fSChristoph Hellwig * Can be called from any context. 10590b2a8a9fSChristoph Hellwig */ 1060fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1061a0fa9647SJens Axboe { 10623a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1063a0fa9647SJens Axboe 1064fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1065fa059b85SKeith Busch 10663a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1067fa059b85SKeith Busch nvme_process_cq(nvmeq); 10683a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 106991a509f8SChristoph Hellwig } 1070442e19b7SSagi Grimberg 10719743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10727776db1cSKeith Busch { 10737776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1074dabcefabSJens Axboe bool found; 1075dabcefabSJens Axboe 1076dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1077dabcefabSJens Axboe return 0; 1078dabcefabSJens Axboe 10793a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1080324b494cSKeith Busch found = nvme_process_cq(nvmeq); 10813a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1082dabcefabSJens Axboe 1083dabcefabSJens Axboe return found; 1084dabcefabSJens Axboe } 1085dabcefabSJens Axboe 1086ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 108757dacad5SJay Sternberg { 1088f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1089147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 109057dacad5SJay Sternberg struct nvme_command c; 109157dacad5SJay Sternberg 109257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 109357dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1094ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 109504f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 109657dacad5SJay Sternberg } 109757dacad5SJay Sternberg 109857dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 109957dacad5SJay Sternberg { 110057dacad5SJay Sternberg struct nvme_command c; 110157dacad5SJay Sternberg 110257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 110357dacad5SJay Sternberg c.delete_queue.opcode = opcode; 110457dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 110557dacad5SJay Sternberg 11061c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 110757dacad5SJay Sternberg } 110857dacad5SJay Sternberg 110957dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1110a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 111157dacad5SJay Sternberg { 111257dacad5SJay Sternberg struct nvme_command c; 11134b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11144b04cc6aSJens Axboe 11157c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11164b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 111757dacad5SJay Sternberg 111857dacad5SJay Sternberg /* 111916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 112057dacad5SJay Sternberg * is attached to the request. 112157dacad5SJay Sternberg */ 112257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112357dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 112457dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 112557dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 112657dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 112757dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1128a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 112957dacad5SJay Sternberg 11301c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 113157dacad5SJay Sternberg } 113257dacad5SJay Sternberg 113357dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 113457dacad5SJay Sternberg struct nvme_queue *nvmeq) 113557dacad5SJay Sternberg { 11369abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 113757dacad5SJay Sternberg struct nvme_command c; 113881c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 113957dacad5SJay Sternberg 114057dacad5SJay Sternberg /* 11419abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11429abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11439abd68efSJens Axboe * URGENT. 11449abd68efSJens Axboe */ 11459abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11469abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11479abd68efSJens Axboe 11489abd68efSJens Axboe /* 114916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 115057dacad5SJay Sternberg * is attached to the request. 115157dacad5SJay Sternberg */ 115257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 115357dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 115457dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 115557dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 115657dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 115757dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 115857dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 115957dacad5SJay Sternberg 11601c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 116157dacad5SJay Sternberg } 116257dacad5SJay Sternberg 116357dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 116457dacad5SJay Sternberg { 116557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 116657dacad5SJay Sternberg } 116757dacad5SJay Sternberg 116857dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 116957dacad5SJay Sternberg { 117057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 117157dacad5SJay Sternberg } 117257dacad5SJay Sternberg 11732a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 117457dacad5SJay Sternberg { 1175f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1176f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 117757dacad5SJay Sternberg 117827fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 117927fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1180e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1181e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 118257dacad5SJay Sternberg } 118357dacad5SJay Sternberg 1184b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1185b2a0eb1aSKeith Busch { 1186b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1187b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1188b2a0eb1aSKeith Busch */ 1189b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1190b2a0eb1aSKeith Busch 1191ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1192ad70062cSJianchao Wang switch (dev->ctrl.state) { 1193ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1194ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1195b2a0eb1aSKeith Busch return false; 1196ad70062cSJianchao Wang default: 1197ad70062cSJianchao Wang break; 1198ad70062cSJianchao Wang } 1199b2a0eb1aSKeith Busch 1200b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1201b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1202b2a0eb1aSKeith Busch */ 1203b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1204b2a0eb1aSKeith Busch return false; 1205b2a0eb1aSKeith Busch 1206b2a0eb1aSKeith Busch return true; 1207b2a0eb1aSKeith Busch } 1208b2a0eb1aSKeith Busch 1209b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1210b2a0eb1aSKeith Busch { 1211b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1212b2a0eb1aSKeith Busch u16 pci_status; 1213b2a0eb1aSKeith Busch int result; 1214b2a0eb1aSKeith Busch 1215b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1216b2a0eb1aSKeith Busch &pci_status); 1217b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1218b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1219b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1220b2a0eb1aSKeith Busch csts, pci_status); 1221b2a0eb1aSKeith Busch else 1222b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1223b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1224b2a0eb1aSKeith Busch csts, result); 1225b2a0eb1aSKeith Busch } 1226b2a0eb1aSKeith Busch 122731c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 122857dacad5SJay Sternberg { 1229f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1230f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 123157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 123257dacad5SJay Sternberg struct request *abort_req; 123357dacad5SJay Sternberg struct nvme_command cmd; 1234b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1235b2a0eb1aSKeith Busch 1236651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1237651438bbSWen Xiong * the recovery mechanism will surely fail. 1238651438bbSWen Xiong */ 1239651438bbSWen Xiong mb(); 1240651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1241651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1242651438bbSWen Xiong 1243b2a0eb1aSKeith Busch /* 1244b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1245b2a0eb1aSKeith Busch */ 1246b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1247b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1248b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1249d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1250db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1251b2a0eb1aSKeith Busch } 125257dacad5SJay Sternberg 125331c7c7d2SChristoph Hellwig /* 12547776db1cSKeith Busch * Did we miss an interrupt? 12557776db1cSKeith Busch */ 1256fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1257fa059b85SKeith Busch nvme_poll(req->mq_hctx); 1258fa059b85SKeith Busch else 1259bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1260fa059b85SKeith Busch 1261bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 12627776db1cSKeith Busch dev_warn(dev->ctrl.device, 12637776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12647776db1cSKeith Busch req->tag, nvmeq->qid); 1265db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12667776db1cSKeith Busch } 12677776db1cSKeith Busch 12687776db1cSKeith Busch /* 1269fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1270fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1271fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1272db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1273fd634f41SChristoph Hellwig */ 12744244140dSKeith Busch switch (dev->ctrl.state) { 12754244140dSKeith Busch case NVME_CTRL_CONNECTING: 12762036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1277df561f66SGustavo A. R. Silva fallthrough; 12782036f726SKeith Busch case NVME_CTRL_DELETING: 1279b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1280fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1281fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 128227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 12837ad92f65STong Zhang nvme_dev_disable(dev, true); 1284db8c48e4SChristoph Hellwig return BLK_EH_DONE; 128539a9dd81SKeith Busch case NVME_CTRL_RESETTING: 128639a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 12874244140dSKeith Busch default: 12884244140dSKeith Busch break; 1289fd634f41SChristoph Hellwig } 1290fd634f41SChristoph Hellwig 1291fd634f41SChristoph Hellwig /* 1292e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1293e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1294e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 129531c7c7d2SChristoph Hellwig */ 1296f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12971b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 129857dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 129957dacad5SJay Sternberg req->tag, nvmeq->qid); 13007ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1301a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1302d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1303e1569a16SKeith Busch 1304db8c48e4SChristoph Hellwig return BLK_EH_DONE; 130557dacad5SJay Sternberg } 130657dacad5SJay Sternberg 1307e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1308e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1309e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1310e7a2a87dSChristoph Hellwig } 13117bf7d778SKeith Busch iod->aborted = 1; 131257dacad5SJay Sternberg 131357dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 131457dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 131557dacad5SJay Sternberg cmd.abort.cid = req->tag; 131657dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 131757dacad5SJay Sternberg 13181b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13191b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 132057dacad5SJay Sternberg req->tag, nvmeq->qid); 1321e7a2a87dSChristoph Hellwig 1322e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 132339dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 13246bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13256bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 132631c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 132757dacad5SJay Sternberg } 132857dacad5SJay Sternberg 1329e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1330e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 133157dacad5SJay Sternberg 133257dacad5SJay Sternberg /* 133357dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 133457dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 133557dacad5SJay Sternberg * as the device then is in a faulty state. 133657dacad5SJay Sternberg */ 133757dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 133857dacad5SJay Sternberg } 133957dacad5SJay Sternberg 134057dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 134157dacad5SJay Sternberg { 13428a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 134357dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 134463223078SChristoph Hellwig if (!nvmeq->sq_cmds) 134563223078SChristoph Hellwig return; 13460f238ff5SLogan Gunthorpe 134763223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 134888a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13498a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 135063223078SChristoph Hellwig } else { 13518a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 135263223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13530f238ff5SLogan Gunthorpe } 135457dacad5SJay Sternberg } 135557dacad5SJay Sternberg 135657dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 135757dacad5SJay Sternberg { 135857dacad5SJay Sternberg int i; 135957dacad5SJay Sternberg 1360d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1361d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1362147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 136357dacad5SJay Sternberg } 136457dacad5SJay Sternberg } 136557dacad5SJay Sternberg 136657dacad5SJay Sternberg /** 136757dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 136840581d1aSBart Van Assche * @nvmeq: queue to suspend 136957dacad5SJay Sternberg */ 137057dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 137157dacad5SJay Sternberg { 13724e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 137357dacad5SJay Sternberg return 1; 137457dacad5SJay Sternberg 13754e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1376d1f06f4aSJens Axboe mb(); 137757dacad5SJay Sternberg 13784e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13791c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1380c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13817c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 13824e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 138357dacad5SJay Sternberg return 0; 138457dacad5SJay Sternberg } 138557dacad5SJay Sternberg 13868fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 13878fae268bSKeith Busch { 13888fae268bSKeith Busch int i; 13898fae268bSKeith Busch 13908fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 13918fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 13928fae268bSKeith Busch } 13938fae268bSKeith Busch 1394a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 139557dacad5SJay Sternberg { 1396147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 139757dacad5SJay Sternberg 1398a5cdb68cSKeith Busch if (shutdown) 1399a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1400a5cdb68cSKeith Busch else 1401b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 140257dacad5SJay Sternberg 1403bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 140457dacad5SJay Sternberg } 140557dacad5SJay Sternberg 1406fa46c6fbSKeith Busch /* 1407fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 14089210c075SDongli Zhang * that can check this device's completion queues have synced, except 14099210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 14109210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1411fa46c6fbSKeith Busch */ 1412fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1413fa46c6fbSKeith Busch { 1414fa46c6fbSKeith Busch int i; 1415fa46c6fbSKeith Busch 14169210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 14179210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1418324b494cSKeith Busch nvme_process_cq(&dev->queues[i]); 14199210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 14209210c075SDongli Zhang } 1421fa46c6fbSKeith Busch } 1422fa46c6fbSKeith Busch 142357dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 142457dacad5SJay Sternberg int entry_size) 142557dacad5SJay Sternberg { 142657dacad5SJay Sternberg int q_depth = dev->q_depth; 14275fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14286c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 142957dacad5SJay Sternberg 143057dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 143157dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14324e523547SBaolin Wang 14336c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 143457dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 143557dacad5SJay Sternberg 143657dacad5SJay Sternberg /* 143757dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 143857dacad5SJay Sternberg * would be better to map queues in system memory with the 143957dacad5SJay Sternberg * original depth 144057dacad5SJay Sternberg */ 144157dacad5SJay Sternberg if (q_depth < 64) 144257dacad5SJay Sternberg return -ENOMEM; 144357dacad5SJay Sternberg } 144457dacad5SJay Sternberg 144557dacad5SJay Sternberg return q_depth; 144657dacad5SJay Sternberg } 144757dacad5SJay Sternberg 144857dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14498a1d09a6SBenjamin Herrenschmidt int qid) 145057dacad5SJay Sternberg { 14510f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1452815c6704SKeith Busch 14530f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14548a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1455bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14560f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14570f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 145863223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 145963223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 146063223078SChristoph Hellwig return 0; 146163223078SChristoph Hellwig } 1462bfac8e9fSAlan Mikhak 14638a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1464bfac8e9fSAlan Mikhak } 14650f238ff5SLogan Gunthorpe } 14660f238ff5SLogan Gunthorpe 14678a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 146857dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 146957dacad5SJay Sternberg if (!nvmeq->sq_cmds) 147057dacad5SJay Sternberg return -ENOMEM; 147157dacad5SJay Sternberg return 0; 147257dacad5SJay Sternberg } 147357dacad5SJay Sternberg 1474a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 147557dacad5SJay Sternberg { 1476147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 147757dacad5SJay Sternberg 147862314e40SKeith Busch if (dev->ctrl.queue_count > qid) 147962314e40SKeith Busch return 0; 148057dacad5SJay Sternberg 1481c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 14828a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 14838a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 148457dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 148557dacad5SJay Sternberg if (!nvmeq->cqes) 148657dacad5SJay Sternberg goto free_nvmeq; 148757dacad5SJay Sternberg 14888a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 148957dacad5SJay Sternberg goto free_cqdma; 149057dacad5SJay Sternberg 149157dacad5SJay Sternberg nvmeq->dev = dev; 14921ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14933a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 149457dacad5SJay Sternberg nvmeq->cq_head = 0; 149557dacad5SJay Sternberg nvmeq->cq_phase = 1; 149657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 149757dacad5SJay Sternberg nvmeq->qid = qid; 1498d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 149957dacad5SJay Sternberg 1500147b27e4SSagi Grimberg return 0; 150157dacad5SJay Sternberg 150257dacad5SJay Sternberg free_cqdma: 15038a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 150457dacad5SJay Sternberg nvmeq->cq_dma_addr); 150557dacad5SJay Sternberg free_nvmeq: 1506147b27e4SSagi Grimberg return -ENOMEM; 150757dacad5SJay Sternberg } 150857dacad5SJay Sternberg 1509dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 151057dacad5SJay Sternberg { 15110ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15120ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15130ff199cbSChristoph Hellwig 15140ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15150ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15160ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15170ff199cbSChristoph Hellwig } else { 15180ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15190ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15200ff199cbSChristoph Hellwig } 152157dacad5SJay Sternberg } 152257dacad5SJay Sternberg 152357dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 152457dacad5SJay Sternberg { 152557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 152657dacad5SJay Sternberg 152757dacad5SJay Sternberg nvmeq->sq_tail = 0; 152838210800SKeith Busch nvmeq->last_sq_tail = 0; 152957dacad5SJay Sternberg nvmeq->cq_head = 0; 153057dacad5SJay Sternberg nvmeq->cq_phase = 1; 153157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15328a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1533f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 153457dacad5SJay Sternberg dev->online_queues++; 15353a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 153657dacad5SJay Sternberg } 153757dacad5SJay Sternberg 15384b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 153957dacad5SJay Sternberg { 154057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 154157dacad5SJay Sternberg int result; 15427c349ddeSKeith Busch u16 vector = 0; 154357dacad5SJay Sternberg 1544d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1545d1ed6aa1SChristoph Hellwig 154622b55601SKeith Busch /* 154722b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 154822b55601SKeith Busch * has only one vector available. 154922b55601SKeith Busch */ 15504b04cc6aSJens Axboe if (!polled) 1551a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15524b04cc6aSJens Axboe else 15537c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15544b04cc6aSJens Axboe 1555a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1556ded45505SKeith Busch if (result) 1557ded45505SKeith Busch return result; 155857dacad5SJay Sternberg 155957dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 156057dacad5SJay Sternberg if (result < 0) 1561ded45505SKeith Busch return result; 1562c80b36cdSEdmund Nadolski if (result) 156357dacad5SJay Sternberg goto release_cq; 156457dacad5SJay Sternberg 1565a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1566161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15674b04cc6aSJens Axboe 15687c349ddeSKeith Busch if (!polled) { 1569dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 157057dacad5SJay Sternberg if (result < 0) 157157dacad5SJay Sternberg goto release_sq; 15724b04cc6aSJens Axboe } 157357dacad5SJay Sternberg 15744e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 157557dacad5SJay Sternberg return result; 157657dacad5SJay Sternberg 157757dacad5SJay Sternberg release_sq: 1578f25a2dfcSJianchao Wang dev->online_queues--; 157957dacad5SJay Sternberg adapter_delete_sq(dev, qid); 158057dacad5SJay Sternberg release_cq: 158157dacad5SJay Sternberg adapter_delete_cq(dev, qid); 158257dacad5SJay Sternberg return result; 158357dacad5SJay Sternberg } 158457dacad5SJay Sternberg 1585f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 158657dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 158777f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 158857dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 15890350815aSChristoph Hellwig .init_request = nvme_init_request, 159057dacad5SJay Sternberg .timeout = nvme_timeout, 159157dacad5SJay Sternberg }; 159257dacad5SJay Sternberg 1593f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1594376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1595376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1596376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1597376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1598376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1599376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1600376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1601c6d962aeSChristoph Hellwig .poll = nvme_poll, 1602dabcefabSJens Axboe }; 1603dabcefabSJens Axboe 160457dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 160557dacad5SJay Sternberg { 16061c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 160769d9a99cSKeith Busch /* 160869d9a99cSKeith Busch * If the controller was reset during removal, it's possible 160969d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 161069d9a99cSKeith Busch * queue to flush these to completion. 161169d9a99cSKeith Busch */ 1612c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16131c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 161457dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 161557dacad5SJay Sternberg } 161657dacad5SJay Sternberg } 161757dacad5SJay Sternberg 161857dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 161957dacad5SJay Sternberg { 16201c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 162157dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 162257dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1623e3e9d50cSKeith Busch 162438dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1625dc96f938SChaitanya Kulkarni dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; 1626d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1627d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1628d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 162957dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 163057dacad5SJay Sternberg 163157dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 163257dacad5SJay Sternberg return -ENOMEM; 163334b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 163457dacad5SJay Sternberg 16351c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16361c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 163757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 163857dacad5SJay Sternberg return -ENOMEM; 163957dacad5SJay Sternberg } 16401c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 164157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16421c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 164357dacad5SJay Sternberg return -ENODEV; 164457dacad5SJay Sternberg } 164557dacad5SJay Sternberg } else 1646c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 164757dacad5SJay Sternberg 164857dacad5SJay Sternberg return 0; 164957dacad5SJay Sternberg } 165057dacad5SJay Sternberg 165197f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 165297f6ef64SXu Yu { 165397f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 165497f6ef64SXu Yu } 165597f6ef64SXu Yu 165697f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 165797f6ef64SXu Yu { 165897f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 165997f6ef64SXu Yu 166097f6ef64SXu Yu if (size <= dev->bar_mapped_size) 166197f6ef64SXu Yu return 0; 166297f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 166397f6ef64SXu Yu return -ENOMEM; 166497f6ef64SXu Yu if (dev->bar) 166597f6ef64SXu Yu iounmap(dev->bar); 166697f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 166797f6ef64SXu Yu if (!dev->bar) { 166897f6ef64SXu Yu dev->bar_mapped_size = 0; 166997f6ef64SXu Yu return -ENOMEM; 167097f6ef64SXu Yu } 167197f6ef64SXu Yu dev->bar_mapped_size = size; 167297f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 167397f6ef64SXu Yu 167497f6ef64SXu Yu return 0; 167597f6ef64SXu Yu } 167697f6ef64SXu Yu 167701ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 167857dacad5SJay Sternberg { 167957dacad5SJay Sternberg int result; 168057dacad5SJay Sternberg u32 aqa; 168157dacad5SJay Sternberg struct nvme_queue *nvmeq; 168257dacad5SJay Sternberg 168397f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 168497f6ef64SXu Yu if (result < 0) 168597f6ef64SXu Yu return result; 168697f6ef64SXu Yu 16878ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 168820d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 168957dacad5SJay Sternberg 16907a67cbeaSChristoph Hellwig if (dev->subsystem && 16917a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16927a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 169357dacad5SJay Sternberg 1694b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 169557dacad5SJay Sternberg if (result < 0) 169657dacad5SJay Sternberg return result; 169757dacad5SJay Sternberg 1698a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1699147b27e4SSagi Grimberg if (result) 1700147b27e4SSagi Grimberg return result; 170157dacad5SJay Sternberg 1702635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1703635333e4SMax Gurtovoy 1704147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 170557dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 170657dacad5SJay Sternberg aqa |= aqa << 16; 170757dacad5SJay Sternberg 17087a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17097a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17107a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 171157dacad5SJay Sternberg 1712c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 171357dacad5SJay Sternberg if (result) 1714d4875622SKeith Busch return result; 171557dacad5SJay Sternberg 171657dacad5SJay Sternberg nvmeq->cq_vector = 0; 1717161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1718dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 171957dacad5SJay Sternberg if (result) { 17207c349ddeSKeith Busch dev->online_queues--; 1721d4875622SKeith Busch return result; 172257dacad5SJay Sternberg } 172357dacad5SJay Sternberg 17244e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 172557dacad5SJay Sternberg return result; 172657dacad5SJay Sternberg } 172757dacad5SJay Sternberg 1728749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 172957dacad5SJay Sternberg { 17304b04cc6aSJens Axboe unsigned i, max, rw_queues; 1731749941f2SChristoph Hellwig int ret = 0; 173257dacad5SJay Sternberg 1733d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1734a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1735749941f2SChristoph Hellwig ret = -ENOMEM; 173657dacad5SJay Sternberg break; 1737749941f2SChristoph Hellwig } 1738749941f2SChristoph Hellwig } 173957dacad5SJay Sternberg 1740d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1741e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1742e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1743e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17444b04cc6aSJens Axboe } else { 17454b04cc6aSJens Axboe rw_queues = max; 17464b04cc6aSJens Axboe } 17474b04cc6aSJens Axboe 1748949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17494b04cc6aSJens Axboe bool polled = i > rw_queues; 17504b04cc6aSJens Axboe 17514b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1752d4875622SKeith Busch if (ret) 175357dacad5SJay Sternberg break; 175457dacad5SJay Sternberg } 175557dacad5SJay Sternberg 1756749941f2SChristoph Hellwig /* 1757749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17588adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17598adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1760749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1761749941f2SChristoph Hellwig */ 1762749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 176357dacad5SJay Sternberg } 176457dacad5SJay Sternberg 1765202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1766202021c1SStephen Bates struct device_attribute *attr, 1767202021c1SStephen Bates char *buf) 1768202021c1SStephen Bates { 1769202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1770202021c1SStephen Bates 1771c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1772202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1773202021c1SStephen Bates } 1774202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1775202021c1SStephen Bates 177688de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 177757dacad5SJay Sternberg { 177888de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 177988de4598SChristoph Hellwig 178088de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 178188de4598SChristoph Hellwig } 178288de4598SChristoph Hellwig 178388de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 178488de4598SChristoph Hellwig { 178588de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 178688de4598SChristoph Hellwig } 178788de4598SChristoph Hellwig 1788f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 178957dacad5SJay Sternberg { 179088de4598SChristoph Hellwig u64 size, offset; 179157dacad5SJay Sternberg resource_size_t bar_size; 179257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17938969f1f8SChristoph Hellwig int bar; 179457dacad5SJay Sternberg 17959fe5c59fSKeith Busch if (dev->cmb_size) 17969fe5c59fSKeith Busch return; 17979fe5c59fSKeith Busch 17987a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1799f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1800f65efd6dSChristoph Hellwig return; 1801202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 180257dacad5SJay Sternberg 180388de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 180488de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18058969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18068969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 180757dacad5SJay Sternberg 180857dacad5SJay Sternberg if (offset > bar_size) 1809f65efd6dSChristoph Hellwig return; 181057dacad5SJay Sternberg 181157dacad5SJay Sternberg /* 181257dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 181357dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 181457dacad5SJay Sternberg * the reported size of the BAR 181557dacad5SJay Sternberg */ 181657dacad5SJay Sternberg if (size > bar_size - offset) 181757dacad5SJay Sternberg size = bar_size - offset; 181857dacad5SJay Sternberg 18190f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18200f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18210f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1822f65efd6dSChristoph Hellwig return; 18230f238ff5SLogan Gunthorpe } 18240f238ff5SLogan Gunthorpe 182557dacad5SJay Sternberg dev->cmb_size = size; 18260f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18270f238ff5SLogan Gunthorpe 18280f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18290f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18300f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1831f65efd6dSChristoph Hellwig 1832f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1833f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1834f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1835f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 183657dacad5SJay Sternberg } 183757dacad5SJay Sternberg 183857dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 183957dacad5SJay Sternberg { 18400f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1841f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1842f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18430f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1844f63572dfSJon Derrick } 184557dacad5SJay Sternberg } 184657dacad5SJay Sternberg 184787ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 184857dacad5SJay Sternberg { 18496c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 18504033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 185187ad72a5SChristoph Hellwig struct nvme_command c; 185287ad72a5SChristoph Hellwig int ret; 185387ad72a5SChristoph Hellwig 185487ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 185587ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 185687ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 185787ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 18586c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 185987ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 186087ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 186187ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 186287ad72a5SChristoph Hellwig 186387ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 186487ad72a5SChristoph Hellwig if (ret) { 186587ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 186687ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 186787ad72a5SChristoph Hellwig ret, bits); 186887ad72a5SChristoph Hellwig } 186987ad72a5SChristoph Hellwig return ret; 187087ad72a5SChristoph Hellwig } 187187ad72a5SChristoph Hellwig 187287ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 187387ad72a5SChristoph Hellwig { 187487ad72a5SChristoph Hellwig int i; 187587ad72a5SChristoph Hellwig 187687ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 187787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 18786c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 187987ad72a5SChristoph Hellwig 1880cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1881cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1882cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 188387ad72a5SChristoph Hellwig } 188487ad72a5SChristoph Hellwig 188587ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 188687ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18874033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18884033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18894033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 189087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18917e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 189287ad72a5SChristoph Hellwig } 189387ad72a5SChristoph Hellwig 189492dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 189592dc6895SChristoph Hellwig u32 chunk_size) 189687ad72a5SChristoph Hellwig { 189787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 189892dc6895SChristoph Hellwig u32 max_entries, len; 18994033f35dSChristoph Hellwig dma_addr_t descs_dma; 19002ee0e4edSDan Carpenter int i = 0; 190187ad72a5SChristoph Hellwig void **bufs; 19026fbcde66SMinwoo Im u64 size, tmp; 190387ad72a5SChristoph Hellwig 190487ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 190587ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 190687ad72a5SChristoph Hellwig max_entries = tmp; 1907044a9df1SChristoph Hellwig 1908044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1909044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1910044a9df1SChristoph Hellwig 1911750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19124033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 191387ad72a5SChristoph Hellwig if (!descs) 191487ad72a5SChristoph Hellwig goto out; 191587ad72a5SChristoph Hellwig 191687ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 191787ad72a5SChristoph Hellwig if (!bufs) 191887ad72a5SChristoph Hellwig goto out_free_descs; 191987ad72a5SChristoph Hellwig 1920244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 192187ad72a5SChristoph Hellwig dma_addr_t dma_addr; 192287ad72a5SChristoph Hellwig 192350cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 192487ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 192587ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 192687ad72a5SChristoph Hellwig if (!bufs[i]) 192787ad72a5SChristoph Hellwig break; 192887ad72a5SChristoph Hellwig 192987ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 19306c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 193187ad72a5SChristoph Hellwig i++; 193287ad72a5SChristoph Hellwig } 193387ad72a5SChristoph Hellwig 193492dc6895SChristoph Hellwig if (!size) 193587ad72a5SChristoph Hellwig goto out_free_bufs; 193687ad72a5SChristoph Hellwig 193787ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 193887ad72a5SChristoph Hellwig dev->host_mem_size = size; 193987ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19404033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 194187ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 194287ad72a5SChristoph Hellwig return 0; 194387ad72a5SChristoph Hellwig 194487ad72a5SChristoph Hellwig out_free_bufs: 194587ad72a5SChristoph Hellwig while (--i >= 0) { 19466c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 194787ad72a5SChristoph Hellwig 1948cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1949cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1950cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 195187ad72a5SChristoph Hellwig } 195287ad72a5SChristoph Hellwig 195387ad72a5SChristoph Hellwig kfree(bufs); 195487ad72a5SChristoph Hellwig out_free_descs: 19554033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19564033f35dSChristoph Hellwig descs_dma); 195787ad72a5SChristoph Hellwig out: 195887ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 195987ad72a5SChristoph Hellwig return -ENOMEM; 196087ad72a5SChristoph Hellwig } 196187ad72a5SChristoph Hellwig 196292dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 196392dc6895SChristoph Hellwig { 19649dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 19659dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 19669dc54a0dSChaitanya Kulkarni u64 chunk_size; 196792dc6895SChristoph Hellwig 196892dc6895SChristoph Hellwig /* start big and work our way down */ 19699dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 197092dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 197192dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 197292dc6895SChristoph Hellwig return 0; 197392dc6895SChristoph Hellwig nvme_free_host_mem(dev); 197492dc6895SChristoph Hellwig } 197592dc6895SChristoph Hellwig } 197692dc6895SChristoph Hellwig 197792dc6895SChristoph Hellwig return -ENOMEM; 197892dc6895SChristoph Hellwig } 197992dc6895SChristoph Hellwig 19809620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 198187ad72a5SChristoph Hellwig { 198287ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 198387ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 198487ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 198587ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19866fbcde66SMinwoo Im int ret; 198787ad72a5SChristoph Hellwig 198887ad72a5SChristoph Hellwig preferred = min(preferred, max); 198987ad72a5SChristoph Hellwig if (min > max) { 199087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 199187ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 199287ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 199387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19949620cfbaSChristoph Hellwig return 0; 199587ad72a5SChristoph Hellwig } 199687ad72a5SChristoph Hellwig 199787ad72a5SChristoph Hellwig /* 199887ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 199987ad72a5SChristoph Hellwig */ 200087ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 200187ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 200287ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 200387ad72a5SChristoph Hellwig else 200487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 200587ad72a5SChristoph Hellwig } 200687ad72a5SChristoph Hellwig 200787ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 200892dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 200992dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 201092dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20119620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 201287ad72a5SChristoph Hellwig } 201387ad72a5SChristoph Hellwig 201492dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 201592dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 201692dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 201792dc6895SChristoph Hellwig } 201892dc6895SChristoph Hellwig 20199620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20209620cfbaSChristoph Hellwig if (ret) 202187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20229620cfbaSChristoph Hellwig return ret; 202357dacad5SJay Sternberg } 202457dacad5SJay Sternberg 2025612b7286SMing Lei /* 2026612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2027612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2028612b7286SMing Lei */ 2029612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20303b6592f7SJens Axboe { 2031612b7286SMing Lei struct nvme_dev *dev = affd->priv; 20322a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2033c45b1fa2SMing Lei 20343b6592f7SJens Axboe /* 2035ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2036612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2037612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2038612b7286SMing Lei * 2039612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2040612b7286SMing Lei * write and read queues. 2041612b7286SMing Lei * 2042612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2043612b7286SMing Lei * queue. 20443b6592f7SJens Axboe */ 2045612b7286SMing Lei if (!nrirqs) { 2046612b7286SMing Lei nrirqs = 1; 2047612b7286SMing Lei nr_read_queues = 0; 20482a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2049612b7286SMing Lei nr_read_queues = 0; 20502a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2051612b7286SMing Lei nr_read_queues = 1; 20523b6592f7SJens Axboe } else { 20532a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 20543b6592f7SJens Axboe } 2055612b7286SMing Lei 2056612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2057612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2058612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2059612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2060612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20613b6592f7SJens Axboe } 20623b6592f7SJens Axboe 20636451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20643b6592f7SJens Axboe { 20653b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20663b6592f7SJens Axboe struct irq_affinity affd = { 20673b6592f7SJens Axboe .pre_vectors = 1, 2068612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2069612b7286SMing Lei .priv = dev, 20703b6592f7SJens Axboe }; 207121cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 20726451fe73SJens Axboe 20736451fe73SJens Axboe /* 207421cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 207521cc2f3fSJeffle Xu * left over for non-polled I/O. 20766451fe73SJens Axboe */ 207721cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 207821cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 20793b6592f7SJens Axboe 208021cc2f3fSJeffle Xu /* 208121cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 208221cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 208321cc2f3fSJeffle Xu */ 2084612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2085612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20863b6592f7SJens Axboe 208766341331SBenjamin Herrenschmidt /* 208821cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 208921cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 209021cc2f3fSJeffle Xu * vector. 209166341331SBenjamin Herrenschmidt */ 209266341331SBenjamin Herrenschmidt irq_queues = 1; 209321cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 209421cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2095612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20963b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20973b6592f7SJens Axboe } 20983b6592f7SJens Axboe 20998fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 21008fae268bSKeith Busch { 21018fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 21028fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 21038fae268bSKeith Busch } 21048fae268bSKeith Busch 21052a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 21062a5bcfddSWeiping Zhang { 2107e3aef095SNiklas Schnelle /* 2108e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2109e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2110e3aef095SNiklas Schnelle */ 2111e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2112e3aef095SNiklas Schnelle return 1; 21132a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 21142a5bcfddSWeiping Zhang } 21152a5bcfddSWeiping Zhang 211657dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 211757dacad5SJay Sternberg { 2118147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 211957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 21202a5bcfddSWeiping Zhang unsigned int nr_io_queues; 212197f6ef64SXu Yu unsigned long size; 21222a5bcfddSWeiping Zhang int result; 212357dacad5SJay Sternberg 21242a5bcfddSWeiping Zhang /* 21252a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 21262a5bcfddSWeiping Zhang * stable values to work with. 21272a5bcfddSWeiping Zhang */ 21282a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 21292a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2130d38e9f04SBenjamin Herrenschmidt 2131ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 21329a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21339a0be7abSChristoph Hellwig if (result < 0) 213457dacad5SJay Sternberg return result; 21359a0be7abSChristoph Hellwig 2136f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2137a5229050SKeith Busch return 0; 213857dacad5SJay Sternberg 21394e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21404e224106SChristoph Hellwig 21410f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 214257dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 214357dacad5SJay Sternberg sizeof(struct nvme_command)); 214457dacad5SJay Sternberg if (result > 0) 214557dacad5SJay Sternberg dev->q_depth = result; 214657dacad5SJay Sternberg else 21470f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 214857dacad5SJay Sternberg } 214957dacad5SJay Sternberg 215057dacad5SJay Sternberg do { 215197f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 215297f6ef64SXu Yu result = nvme_remap_bar(dev, size); 215397f6ef64SXu Yu if (!result) 215457dacad5SJay Sternberg break; 215557dacad5SJay Sternberg if (!--nr_io_queues) 215657dacad5SJay Sternberg return -ENOMEM; 215757dacad5SJay Sternberg } while (1); 215857dacad5SJay Sternberg adminq->q_db = dev->dbs; 215957dacad5SJay Sternberg 21608fae268bSKeith Busch retry: 216157dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21620ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 216357dacad5SJay Sternberg 216457dacad5SJay Sternberg /* 216557dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 216657dacad5SJay Sternberg * setting up the full range we need. 216757dacad5SJay Sternberg */ 2168dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21693b6592f7SJens Axboe 21703b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 217122b55601SKeith Busch if (result <= 0) 2172dca51e78SChristoph Hellwig return -EIO; 21733b6592f7SJens Axboe 217422b55601SKeith Busch dev->num_vecs = result; 21754b04cc6aSJens Axboe result = max(result - 1, 1); 2176e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 217757dacad5SJay Sternberg 217857dacad5SJay Sternberg /* 217957dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 218057dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 218157dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 218257dacad5SJay Sternberg * number of interrupts. 218357dacad5SJay Sternberg */ 2184dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21857c349ddeSKeith Busch if (result) 2186d4875622SKeith Busch return result; 21874e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21888fae268bSKeith Busch 21898fae268bSKeith Busch result = nvme_create_io_queues(dev); 21908fae268bSKeith Busch if (result || dev->online_queues < 2) 21918fae268bSKeith Busch return result; 21928fae268bSKeith Busch 21938fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21948fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21958fae268bSKeith Busch nvme_disable_io_queues(dev); 21968fae268bSKeith Busch nvme_suspend_io_queues(dev); 21978fae268bSKeith Busch goto retry; 21988fae268bSKeith Busch } 21998fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 22008fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 22018fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 22028fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 22038fae268bSKeith Busch return 0; 220457dacad5SJay Sternberg } 220557dacad5SJay Sternberg 22062a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2207db3cbfffSKeith Busch { 2208db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2209db3cbfffSKeith Busch 2210db3cbfffSKeith Busch blk_mq_free_request(req); 2211d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2212db3cbfffSKeith Busch } 2213db3cbfffSKeith Busch 22142a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2215db3cbfffSKeith Busch { 2216db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2217db3cbfffSKeith Busch 2218d1ed6aa1SChristoph Hellwig if (error) 2219d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2220db3cbfffSKeith Busch 2221db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2222db3cbfffSKeith Busch } 2223db3cbfffSKeith Busch 2224db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2225db3cbfffSKeith Busch { 2226db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2227db3cbfffSKeith Busch struct request *req; 2228db3cbfffSKeith Busch struct nvme_command cmd; 2229db3cbfffSKeith Busch 2230db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2231db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2232db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2233db3cbfffSKeith Busch 223439dfe844SChaitanya Kulkarni req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); 2235db3cbfffSKeith Busch if (IS_ERR(req)) 2236db3cbfffSKeith Busch return PTR_ERR(req); 2237db3cbfffSKeith Busch 2238db3cbfffSKeith Busch req->end_io_data = nvmeq; 2239db3cbfffSKeith Busch 2240d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2241db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2242db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2243db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2244db3cbfffSKeith Busch return 0; 2245db3cbfffSKeith Busch } 2246db3cbfffSKeith Busch 22478fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2248db3cbfffSKeith Busch { 22495271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2250db3cbfffSKeith Busch unsigned long timeout; 2251db3cbfffSKeith Busch 2252db3cbfffSKeith Busch retry: 2253dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 22545271edd4SChristoph Hellwig while (nr_queues > 0) { 22555271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2256db3cbfffSKeith Busch break; 22575271edd4SChristoph Hellwig nr_queues--; 22585271edd4SChristoph Hellwig sent++; 22595271edd4SChristoph Hellwig } 2260d1ed6aa1SChristoph Hellwig while (sent) { 2261d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2262d1ed6aa1SChristoph Hellwig 2263d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22645271edd4SChristoph Hellwig timeout); 2265db3cbfffSKeith Busch if (timeout == 0) 22665271edd4SChristoph Hellwig return false; 2267d1ed6aa1SChristoph Hellwig 2268d1ed6aa1SChristoph Hellwig sent--; 22695271edd4SChristoph Hellwig if (nr_queues) 2270db3cbfffSKeith Busch goto retry; 2271db3cbfffSKeith Busch } 22725271edd4SChristoph Hellwig return true; 2273db3cbfffSKeith Busch } 2274db3cbfffSKeith Busch 22755d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 227657dacad5SJay Sternberg { 22772b1b7e78SJianchao Wang int ret; 22782b1b7e78SJianchao Wang 22795bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2280c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 228157dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 22828fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2283ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2284ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 228557dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2286d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 228761f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 228861f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2289d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 229057dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 229157dacad5SJay Sternberg dev->tagset.driver_data = dev; 229257dacad5SJay Sternberg 2293d38e9f04SBenjamin Herrenschmidt /* 2294d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2295d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2296d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2297d38e9f04SBenjamin Herrenschmidt */ 2298d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2299d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2300d38e9f04SBenjamin Herrenschmidt 23012b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 23022b1b7e78SJianchao Wang if (ret) { 23032b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23042b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 23055d02a5c1SKeith Busch return; 23062b1b7e78SJianchao Wang } 23075bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2308949928c1SKeith Busch } else { 2309949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2310949928c1SKeith Busch 2311949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2312949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 231357dacad5SJay Sternberg } 2314949928c1SKeith Busch 2315e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 231657dacad5SJay Sternberg } 231757dacad5SJay Sternberg 2318b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 231957dacad5SJay Sternberg { 2320b00a726aSKeith Busch int result = -ENOMEM; 232157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 232257dacad5SJay Sternberg 232357dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 232457dacad5SJay Sternberg return result; 232557dacad5SJay Sternberg 232657dacad5SJay Sternberg pci_set_master(pdev); 232757dacad5SJay Sternberg 23284fe06923SChristoph Hellwig if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 232957dacad5SJay Sternberg goto disable; 233057dacad5SJay Sternberg 23317a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 233257dacad5SJay Sternberg result = -ENODEV; 2333b00a726aSKeith Busch goto disable; 233457dacad5SJay Sternberg } 233557dacad5SJay Sternberg 233657dacad5SJay Sternberg /* 2337a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2338a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2339a5229050SKeith Busch * adjust this later. 234057dacad5SJay Sternberg */ 2341dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2342dca51e78SChristoph Hellwig if (result < 0) 2343dca51e78SChristoph Hellwig return result; 234457dacad5SJay Sternberg 234520d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23467a67cbeaSChristoph Hellwig 23477442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2348b27c1e68Sweiping zhang io_queue_depth); 2349aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 235020d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23517a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23521f390c1fSStephan Günther 23531f390c1fSStephan Günther /* 235466341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 235566341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 235666341331SBenjamin Herrenschmidt * so we don't bother updating it here. 235766341331SBenjamin Herrenschmidt */ 235866341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 235966341331SBenjamin Herrenschmidt dev->io_sqes = 7; 236066341331SBenjamin Herrenschmidt else 2361c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 23621f390c1fSStephan Günther 23631f390c1fSStephan Günther /* 23641f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23651f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23661f390c1fSStephan Günther */ 23671f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23681f390c1fSStephan Günther dev->q_depth = 2; 23699bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23709bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23711f390c1fSStephan Günther dev->q_depth); 2372d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2373d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 237420d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2375d554b5e1SMartin K. Petersen dev->q_depth = 64; 2376d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2377d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23781f390c1fSStephan Günther } 23791f390c1fSStephan Günther 2380d38e9f04SBenjamin Herrenschmidt /* 2381d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2382d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2383d38e9f04SBenjamin Herrenschmidt */ 2384d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2385d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2386d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2387d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2388d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2389d38e9f04SBenjamin Herrenschmidt } 2390d38e9f04SBenjamin Herrenschmidt 2391d38e9f04SBenjamin Herrenschmidt 2392f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2393202021c1SStephen Bates 2394a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2395a0a3408eSKeith Busch pci_save_state(pdev); 239657dacad5SJay Sternberg return 0; 239757dacad5SJay Sternberg 239857dacad5SJay Sternberg disable: 239957dacad5SJay Sternberg pci_disable_device(pdev); 240057dacad5SJay Sternberg return result; 240157dacad5SJay Sternberg } 240257dacad5SJay Sternberg 240357dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 240457dacad5SJay Sternberg { 2405b00a726aSKeith Busch if (dev->bar) 2406b00a726aSKeith Busch iounmap(dev->bar); 2407a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2408b00a726aSKeith Busch } 2409b00a726aSKeith Busch 2410b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2411b00a726aSKeith Busch { 241257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 241357dacad5SJay Sternberg 2414dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 241557dacad5SJay Sternberg 2416a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2417a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 241857dacad5SJay Sternberg pci_disable_device(pdev); 241957dacad5SJay Sternberg } 2420a0a3408eSKeith Busch } 242157dacad5SJay Sternberg 2422a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 242357dacad5SJay Sternberg { 2424e43269e6SKeith Busch bool dead = true, freeze = false; 2425302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 242657dacad5SJay Sternberg 242777bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2428302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2429302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2430302ad8ccSKeith Busch 2431ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2432e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2433e43269e6SKeith Busch freeze = true; 2434302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2435e43269e6SKeith Busch } 2436302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2437302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 243857dacad5SJay Sternberg } 2439c21377f8SGabriel Krisman Bertazi 2440302ad8ccSKeith Busch /* 2441302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2442302ad8ccSKeith Busch * doing a safe shutdown. 2443302ad8ccSKeith Busch */ 2444e43269e6SKeith Busch if (!dead && shutdown && freeze) 2445302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 244687ad72a5SChristoph Hellwig 24479a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24489a915a5bSJianchao Wang 244964ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24508fae268bSKeith Busch nvme_disable_io_queues(dev); 2451a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 245257dacad5SJay Sternberg } 24538fae268bSKeith Busch nvme_suspend_io_queues(dev); 24548fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2455b00a726aSKeith Busch nvme_pci_disable(dev); 2456fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 245757dacad5SJay Sternberg 2458e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2459e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2460622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2461622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2462302ad8ccSKeith Busch 2463302ad8ccSKeith Busch /* 2464302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2465302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2466302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2467302ad8ccSKeith Busch */ 2468c8e9e9b7SKeith Busch if (shutdown) { 2469302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2470c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2471c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2472c8e9e9b7SKeith Busch } 247377bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 247457dacad5SJay Sternberg } 247557dacad5SJay Sternberg 2476c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2477c1ac9a4bSKeith Busch { 2478c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2479c1ac9a4bSKeith Busch return -EBUSY; 2480c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2481c1ac9a4bSKeith Busch return 0; 2482c1ac9a4bSKeith Busch } 2483c1ac9a4bSKeith Busch 248457dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 248557dacad5SJay Sternberg { 248657dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2487c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2488c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 248957dacad5SJay Sternberg if (!dev->prp_page_pool) 249057dacad5SJay Sternberg return -ENOMEM; 249157dacad5SJay Sternberg 249257dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 249357dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 249457dacad5SJay Sternberg 256, 256, 0); 249557dacad5SJay Sternberg if (!dev->prp_small_pool) { 249657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 249757dacad5SJay Sternberg return -ENOMEM; 249857dacad5SJay Sternberg } 249957dacad5SJay Sternberg return 0; 250057dacad5SJay Sternberg } 250157dacad5SJay Sternberg 250257dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 250357dacad5SJay Sternberg { 250457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 250557dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 250657dacad5SJay Sternberg } 250757dacad5SJay Sternberg 2508770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2509770597ecSKeith Busch { 2510770597ecSKeith Busch if (dev->tagset.tags) 2511770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2512770597ecSKeith Busch dev->ctrl.tagset = NULL; 2513770597ecSKeith Busch } 2514770597ecSKeith Busch 25151673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 251657dacad5SJay Sternberg { 25171673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 251857dacad5SJay Sternberg 2519f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2520770597ecSKeith Busch nvme_free_tagset(dev); 25211c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 25221c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2523e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2524943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2525253fd4acSIsrael Rukshin put_device(dev->dev); 2526253fd4acSIsrael Rukshin kfree(dev->queues); 252757dacad5SJay Sternberg kfree(dev); 252857dacad5SJay Sternberg } 252957dacad5SJay Sternberg 25307c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2531f58944e2SKeith Busch { 2532c1ac9a4bSKeith Busch /* 2533c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2534c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2535c1ac9a4bSKeith Busch */ 2536c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2537d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 253869d9a99cSKeith Busch nvme_dev_disable(dev, false); 25399f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 254003e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2541f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2542f58944e2SKeith Busch } 2543f58944e2SKeith Busch 2544fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 254557dacad5SJay Sternberg { 2546d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2547d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2548a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2549e71afda4SChaitanya Kulkarni int result; 255057dacad5SJay Sternberg 2551e71afda4SChaitanya Kulkarni if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2552e71afda4SChaitanya Kulkarni result = -ENODEV; 2553fd634f41SChristoph Hellwig goto out; 2554e71afda4SChaitanya Kulkarni } 2555fd634f41SChristoph Hellwig 2556fd634f41SChristoph Hellwig /* 2557fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2558fd634f41SChristoph Hellwig * moving on. 2559fd634f41SChristoph Hellwig */ 2560b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2561a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2562d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2563fd634f41SChristoph Hellwig 25645c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2565b00a726aSKeith Busch result = nvme_pci_enable(dev); 256657dacad5SJay Sternberg if (result) 25674726bcf3SKeith Busch goto out_unlock; 256857dacad5SJay Sternberg 256901ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 257057dacad5SJay Sternberg if (result) 25714726bcf3SKeith Busch goto out_unlock; 257257dacad5SJay Sternberg 257357dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 257457dacad5SJay Sternberg if (result) 25754726bcf3SKeith Busch goto out_unlock; 257657dacad5SJay Sternberg 2577943e942eSJens Axboe /* 2578943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2579943e942eSJens Axboe * over a single page. 2580943e942eSJens Axboe */ 25817637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 25827637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2583943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2584a48bc520SChristoph Hellwig 2585a48bc520SChristoph Hellwig /* 2586a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2587a48bc520SChristoph Hellwig */ 2588a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 2589a48bc520SChristoph Hellwig 25905c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25915c959d73SKeith Busch 25925c959d73SKeith Busch /* 25935c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25945c959d73SKeith Busch * initializing procedure here. 25955c959d73SKeith Busch */ 25965c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25975c959d73SKeith Busch dev_warn(dev->ctrl.device, 25985c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2599cee6c269SMinwoo Im result = -EBUSY; 26005c959d73SKeith Busch goto out; 26015c959d73SKeith Busch } 2602943e942eSJens Axboe 260395093350SMax Gurtovoy /* 260495093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 260595093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 260695093350SMax Gurtovoy */ 260795093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 260895093350SMax Gurtovoy 2609ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2610ce4541f4SChristoph Hellwig if (result) 2611f58944e2SKeith Busch goto out; 2612ce4541f4SChristoph Hellwig 2613e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2614e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 26154f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 26164f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2617e286bcfcSScott Bauer else if (was_suspend) 26184f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2619e286bcfcSScott Bauer } else { 2620e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2621e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2622e286bcfcSScott Bauer } 2623a98e58e5SScott Bauer 2624f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2625f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2626f9f38e33SHelen Koike if (result) 2627f9f38e33SHelen Koike dev_warn(dev->dev, 2628f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2629f9f38e33SHelen Koike } 2630f9f38e33SHelen Koike 26319620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 26329620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 26339620cfbaSChristoph Hellwig if (result < 0) 26349620cfbaSChristoph Hellwig goto out; 26359620cfbaSChristoph Hellwig } 263687ad72a5SChristoph Hellwig 263757dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 263857dacad5SJay Sternberg if (result) 2639f58944e2SKeith Busch goto out; 264057dacad5SJay Sternberg 264121f033f7SKeith Busch /* 264257dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 264357dacad5SJay Sternberg * any working I/O queue. 264457dacad5SJay Sternberg */ 264557dacad5SJay Sternberg if (dev->online_queues < 2) { 26461b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 26473b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 26485bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2649770597ecSKeith Busch nvme_free_tagset(dev); 265057dacad5SJay Sternberg } else { 265125646264SKeith Busch nvme_start_queues(&dev->ctrl); 2652302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26535d02a5c1SKeith Busch nvme_dev_add(dev); 2654302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 265557dacad5SJay Sternberg } 265657dacad5SJay Sternberg 26572b1b7e78SJianchao Wang /* 26582b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26592b1b7e78SJianchao Wang * recovery. 26602b1b7e78SJianchao Wang */ 26615d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 26622b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26635d02a5c1SKeith Busch "failed to mark controller live state\n"); 2664e71afda4SChaitanya Kulkarni result = -ENODEV; 2665bb8d261eSChristoph Hellwig goto out; 2666bb8d261eSChristoph Hellwig } 266792911a55SChristoph Hellwig 2668d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 266957dacad5SJay Sternberg return; 267057dacad5SJay Sternberg 26714726bcf3SKeith Busch out_unlock: 26724726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 267357dacad5SJay Sternberg out: 26747c1ce408SChaitanya Kulkarni if (result) 26757c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 26767c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 26777c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 267857dacad5SJay Sternberg } 267957dacad5SJay Sternberg 26805c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 268157dacad5SJay Sternberg { 26825c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 268357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 268457dacad5SJay Sternberg 268557dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2686921920abSKeith Busch device_release_driver(&pdev->dev); 26871673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 268857dacad5SJay Sternberg } 268957dacad5SJay Sternberg 26901c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 269157dacad5SJay Sternberg { 26921c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26931c63dc66SChristoph Hellwig return 0; 269457dacad5SJay Sternberg } 26951c63dc66SChristoph Hellwig 26965fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26975fd4ce1bSChristoph Hellwig { 26985fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26995fd4ce1bSChristoph Hellwig return 0; 27005fd4ce1bSChristoph Hellwig } 27015fd4ce1bSChristoph Hellwig 27027fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 27037fd8930fSChristoph Hellwig { 27043a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 27057fd8930fSChristoph Hellwig return 0; 27067fd8930fSChristoph Hellwig } 27077fd8930fSChristoph Hellwig 270897c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 270997c12223SKeith Busch { 271097c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 271197c12223SKeith Busch 27122db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 271397c12223SKeith Busch } 271497c12223SKeith Busch 27151c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 27161a353d85SMing Lin .name = "pcie", 2717e439bb12SSagi Grimberg .module = THIS_MODULE, 2718e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2719e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 27201c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 27215fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 27227fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 27231673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2724f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 272597c12223SKeith Busch .get_address = nvme_pci_get_address, 27261c63dc66SChristoph Hellwig }; 272757dacad5SJay Sternberg 2728b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2729b00a726aSKeith Busch { 2730b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2731b00a726aSKeith Busch 2732a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2733b00a726aSKeith Busch return -ENODEV; 2734b00a726aSKeith Busch 273597f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2736b00a726aSKeith Busch goto release; 2737b00a726aSKeith Busch 2738b00a726aSKeith Busch return 0; 2739b00a726aSKeith Busch release: 2740a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2741b00a726aSKeith Busch return -ENODEV; 2742b00a726aSKeith Busch } 2743b00a726aSKeith Busch 27448427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2745ff5350a8SAndy Lutomirski { 2746ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2747ff5350a8SAndy Lutomirski /* 2748ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2749ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2750ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2751ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2752ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2753ff5350a8SAndy Lutomirski * laptops. 2754ff5350a8SAndy Lutomirski */ 2755ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2756ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2757ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2758ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27598427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27608427bbc2SKai-Heng Feng /* 27618427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2762467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2763467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2764467c77d4SJarosław Janik * ASUS PRIME Z370-A 27658427bbc2SKai-Heng Feng */ 27668427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2767467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2768467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27698427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 27701fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 27711fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 27721fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 27731fae37acSShyjumon N /* 27741fae37acSShyjumon N * Forcing to use host managed nvme power settings for 27751fae37acSShyjumon N * lowest idle power with quick resume latency on 27761fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 27771fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 27781fae37acSShyjumon N */ 27791fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 27801fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 27811fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2782ff5350a8SAndy Lutomirski } 2783ff5350a8SAndy Lutomirski 2784ff5350a8SAndy Lutomirski return 0; 2785ff5350a8SAndy Lutomirski } 2786ff5350a8SAndy Lutomirski 2787df4f9bc4SDavid E. Box #ifdef CONFIG_ACPI 2788df4f9bc4SDavid E. Box static bool nvme_acpi_storage_d3(struct pci_dev *dev) 2789df4f9bc4SDavid E. Box { 2790df4f9bc4SDavid E. Box struct acpi_device *adev; 2791df4f9bc4SDavid E. Box struct pci_dev *root; 2792df4f9bc4SDavid E. Box acpi_handle handle; 2793df4f9bc4SDavid E. Box acpi_status status; 2794df4f9bc4SDavid E. Box u8 val; 2795df4f9bc4SDavid E. Box 2796df4f9bc4SDavid E. Box /* 2797df4f9bc4SDavid E. Box * Look for _DSD property specifying that the storage device on the port 2798df4f9bc4SDavid E. Box * must use D3 to support deep platform power savings during 2799df4f9bc4SDavid E. Box * suspend-to-idle. 2800df4f9bc4SDavid E. Box */ 2801df4f9bc4SDavid E. Box root = pcie_find_root_port(dev); 2802df4f9bc4SDavid E. Box if (!root) 2803df4f9bc4SDavid E. Box return false; 2804df4f9bc4SDavid E. Box 2805df4f9bc4SDavid E. Box adev = ACPI_COMPANION(&root->dev); 2806df4f9bc4SDavid E. Box if (!adev) 2807df4f9bc4SDavid E. Box return false; 2808df4f9bc4SDavid E. Box 2809df4f9bc4SDavid E. Box /* 2810df4f9bc4SDavid E. Box * The property is defined in the PXSX device for South complex ports 2811df4f9bc4SDavid E. Box * and in the PEGP device for North complex ports. 2812df4f9bc4SDavid E. Box */ 2813df4f9bc4SDavid E. Box status = acpi_get_handle(adev->handle, "PXSX", &handle); 2814df4f9bc4SDavid E. Box if (ACPI_FAILURE(status)) { 2815df4f9bc4SDavid E. Box status = acpi_get_handle(adev->handle, "PEGP", &handle); 2816df4f9bc4SDavid E. Box if (ACPI_FAILURE(status)) 2817df4f9bc4SDavid E. Box return false; 2818df4f9bc4SDavid E. Box } 2819df4f9bc4SDavid E. Box 2820df4f9bc4SDavid E. Box if (acpi_bus_get_device(handle, &adev)) 2821df4f9bc4SDavid E. Box return false; 2822df4f9bc4SDavid E. Box 2823df4f9bc4SDavid E. Box if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable", 2824df4f9bc4SDavid E. Box &val)) 2825df4f9bc4SDavid E. Box return false; 2826df4f9bc4SDavid E. Box return val == 1; 2827df4f9bc4SDavid E. Box } 2828df4f9bc4SDavid E. Box #else 2829df4f9bc4SDavid E. Box static inline bool nvme_acpi_storage_d3(struct pci_dev *dev) 2830df4f9bc4SDavid E. Box { 2831df4f9bc4SDavid E. Box return false; 2832df4f9bc4SDavid E. Box } 2833df4f9bc4SDavid E. Box #endif /* CONFIG_ACPI */ 2834df4f9bc4SDavid E. Box 283518119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 283618119775SKeith Busch { 283718119775SKeith Busch struct nvme_dev *dev = data; 283880f513b5SKeith Busch 2839bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 284018119775SKeith Busch flush_work(&dev->ctrl.scan_work); 284180f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 284218119775SKeith Busch } 284318119775SKeith Busch 284457dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 284557dacad5SJay Sternberg { 284657dacad5SJay Sternberg int node, result = -ENOMEM; 284757dacad5SJay Sternberg struct nvme_dev *dev; 2848ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2849943e942eSJens Axboe size_t alloc_size; 285057dacad5SJay Sternberg 285157dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 285257dacad5SJay Sternberg if (node == NUMA_NO_NODE) 28532fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 285457dacad5SJay Sternberg 285557dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 285657dacad5SJay Sternberg if (!dev) 285757dacad5SJay Sternberg return -ENOMEM; 2858147b27e4SSagi Grimberg 28592a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 28602a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 28612a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 28622a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 28632a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 286457dacad5SJay Sternberg if (!dev->queues) 286557dacad5SJay Sternberg goto free; 286657dacad5SJay Sternberg 286757dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 286857dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 286957dacad5SJay Sternberg 2870b00a726aSKeith Busch result = nvme_dev_map(dev); 2871b00a726aSKeith Busch if (result) 2872b00c9b7aSChristophe JAILLET goto put_pci; 2873b00a726aSKeith Busch 2874d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 28755c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 287677bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2877f3ca80fcSChristoph Hellwig 2878f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2879f3ca80fcSChristoph Hellwig if (result) 2880b00c9b7aSChristophe JAILLET goto unmap; 2881f3ca80fcSChristoph Hellwig 28828427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2883ff5350a8SAndy Lutomirski 2884df4f9bc4SDavid E. Box if (!noacpi && nvme_acpi_storage_d3(pdev)) { 2885df4f9bc4SDavid E. Box /* 2886df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 2887df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 2888df4f9bc4SDavid E. Box */ 2889df4f9bc4SDavid E. Box dev_info(&pdev->dev, 2890df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 2891df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 2892df4f9bc4SDavid E. Box } 2893df4f9bc4SDavid E. Box 2894943e942eSJens Axboe /* 2895943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2896943e942eSJens Axboe * command we support. 2897943e942eSJens Axboe */ 2898b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 2899943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2900943e942eSJens Axboe 2901943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2902943e942eSJens Axboe mempool_kfree, 2903943e942eSJens Axboe (void *) alloc_size, 2904943e942eSJens Axboe GFP_KERNEL, node); 2905943e942eSJens Axboe if (!dev->iod_mempool) { 2906943e942eSJens Axboe result = -ENOMEM; 2907943e942eSJens Axboe goto release_pools; 2908943e942eSJens Axboe } 2909943e942eSJens Axboe 2910b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2911b6e44b4cSKeith Busch quirks); 2912b6e44b4cSKeith Busch if (result) 2913b6e44b4cSKeith Busch goto release_mempool; 2914b6e44b4cSKeith Busch 29151b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 29161b3c47c1SSagi Grimberg 2917bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 291818119775SKeith Busch async_schedule(nvme_async_probe, dev); 29194caff8fcSSagi Grimberg 292057dacad5SJay Sternberg return 0; 292157dacad5SJay Sternberg 2922b6e44b4cSKeith Busch release_mempool: 2923b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 292457dacad5SJay Sternberg release_pools: 292557dacad5SJay Sternberg nvme_release_prp_pools(dev); 2926b00c9b7aSChristophe JAILLET unmap: 2927b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 292857dacad5SJay Sternberg put_pci: 292957dacad5SJay Sternberg put_device(dev->dev); 293057dacad5SJay Sternberg free: 293157dacad5SJay Sternberg kfree(dev->queues); 293257dacad5SJay Sternberg kfree(dev); 293357dacad5SJay Sternberg return result; 293457dacad5SJay Sternberg } 293557dacad5SJay Sternberg 2936775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 293757dacad5SJay Sternberg { 293857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2939c1ac9a4bSKeith Busch 2940c1ac9a4bSKeith Busch /* 2941c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 2942c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 2943c1ac9a4bSKeith Busch * with ->remove(). 2944c1ac9a4bSKeith Busch */ 2945c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 2946c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 2947775755edSChristoph Hellwig } 294857dacad5SJay Sternberg 2949775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2950775755edSChristoph Hellwig { 2951f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2952c1ac9a4bSKeith Busch 2953c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 2954c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 295557dacad5SJay Sternberg } 295657dacad5SJay Sternberg 295757dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 295857dacad5SJay Sternberg { 295957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 29604e523547SBaolin Wang 2961c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 296257dacad5SJay Sternberg } 296357dacad5SJay Sternberg 2964f58944e2SKeith Busch /* 2965f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2966f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2967f58944e2SKeith Busch * order to proceed. 2968f58944e2SKeith Busch */ 296957dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 297057dacad5SJay Sternberg { 297157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 297257dacad5SJay Sternberg 2973bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 297457dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 29750ff9d4e1SKeith Busch 29766db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 29770ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 29781d39e692SKeith Busch nvme_dev_disable(dev, true); 2979cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 29806db28edaSKeith Busch } 29810ff9d4e1SKeith Busch 2982d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2983d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2984d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2985a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 29869fe5c59fSKeith Busch nvme_release_cmb(dev); 298787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 298857dacad5SJay Sternberg nvme_dev_remove_admin(dev); 298957dacad5SJay Sternberg nvme_free_queues(dev, 0); 299057dacad5SJay Sternberg nvme_release_prp_pools(dev); 2991b00a726aSKeith Busch nvme_dev_unmap(dev); 2992726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 299357dacad5SJay Sternberg } 299457dacad5SJay Sternberg 299557dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 2996d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2997d916b1beSKeith Busch { 2998d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2999d916b1beSKeith Busch } 3000d916b1beSKeith Busch 3001d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3002d916b1beSKeith Busch { 3003d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3004d916b1beSKeith Busch } 3005d916b1beSKeith Busch 3006d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3007d916b1beSKeith Busch { 3008d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3009d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3010d916b1beSKeith Busch 30114eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3012d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3013c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 3014d916b1beSKeith Busch return 0; 3015d916b1beSKeith Busch } 3016d916b1beSKeith Busch 301757dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 301857dacad5SJay Sternberg { 301957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 302057dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3021d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3022d916b1beSKeith Busch int ret = -EBUSY; 3023d916b1beSKeith Busch 30244eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 30254eaefe8cSRafael J. Wysocki 3026d916b1beSKeith Busch /* 3027d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3028d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3029d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3030d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3031d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3032d916b1beSKeith Busch * device fully. 30334eaefe8cSRafael J. Wysocki * 30344eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 30354eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 30364eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 30374eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3038b97120b1SChristoph Hellwig * 3039b97120b1SChristoph Hellwig * If a host memory buffer is enabled, shut down the device as the NVMe 3040b97120b1SChristoph Hellwig * specification allows the device to access the host memory buffer in 3041b97120b1SChristoph Hellwig * host DRAM from all power states, but hosts will fail access to DRAM 3042b97120b1SChristoph Hellwig * during S3. 3043d916b1beSKeith Busch */ 30444eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3045cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3046b97120b1SChristoph Hellwig ndev->nr_host_mem_descs || 3047c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3048c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3049d916b1beSKeith Busch 3050d916b1beSKeith Busch nvme_start_freeze(ctrl); 3051d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3052d916b1beSKeith Busch nvme_sync_queues(ctrl); 3053d916b1beSKeith Busch 30545d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3055d916b1beSKeith Busch goto unfreeze; 3056d916b1beSKeith Busch 3057d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3058d916b1beSKeith Busch if (ret < 0) 3059d916b1beSKeith Busch goto unfreeze; 3060d916b1beSKeith Busch 30617cbb5c6fSMario Limonciello /* 30627cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 30637cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 30647cbb5c6fSMario Limonciello * want pci interfering. 30657cbb5c6fSMario Limonciello */ 30667cbb5c6fSMario Limonciello pci_save_state(pdev); 30677cbb5c6fSMario Limonciello 3068d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3069d916b1beSKeith Busch if (ret < 0) 3070d916b1beSKeith Busch goto unfreeze; 3071d916b1beSKeith Busch 3072d916b1beSKeith Busch if (ret) { 30737cbb5c6fSMario Limonciello /* discard the saved state */ 30747cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 30757cbb5c6fSMario Limonciello 3076d916b1beSKeith Busch /* 3077d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 307805d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3079d916b1beSKeith Busch */ 3080c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3081d916b1beSKeith Busch ctrl->npss = 0; 3082d916b1beSKeith Busch } 3083d916b1beSKeith Busch unfreeze: 3084d916b1beSKeith Busch nvme_unfreeze(ctrl); 3085d916b1beSKeith Busch return ret; 3086d916b1beSKeith Busch } 3087d916b1beSKeith Busch 3088d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3089d916b1beSKeith Busch { 3090d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 30914e523547SBaolin Wang 3092c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 309357dacad5SJay Sternberg } 309457dacad5SJay Sternberg 3095d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 309657dacad5SJay Sternberg { 309757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 309857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 309957dacad5SJay Sternberg 3100c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 310157dacad5SJay Sternberg } 310257dacad5SJay Sternberg 310321774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3104d916b1beSKeith Busch .suspend = nvme_suspend, 3105d916b1beSKeith Busch .resume = nvme_resume, 3106d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3107d916b1beSKeith Busch .thaw = nvme_simple_resume, 3108d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3109d916b1beSKeith Busch .restore = nvme_simple_resume, 3110d916b1beSKeith Busch }; 3111d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 311257dacad5SJay Sternberg 3113a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3114a0a3408eSKeith Busch pci_channel_state_t state) 3115a0a3408eSKeith Busch { 3116a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3117a0a3408eSKeith Busch 3118a0a3408eSKeith Busch /* 3119a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3120a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3121a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3122a0a3408eSKeith Busch */ 3123a0a3408eSKeith Busch switch (state) { 3124a0a3408eSKeith Busch case pci_channel_io_normal: 3125a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3126a0a3408eSKeith Busch case pci_channel_io_frozen: 3127d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3128d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3129a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3130a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3131a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3132d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3133d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3134a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3135a0a3408eSKeith Busch } 3136a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3137a0a3408eSKeith Busch } 3138a0a3408eSKeith Busch 3139a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3140a0a3408eSKeith Busch { 3141a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3142a0a3408eSKeith Busch 31431b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3144a0a3408eSKeith Busch pci_restore_state(pdev); 3145d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3146a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3147a0a3408eSKeith Busch } 3148a0a3408eSKeith Busch 3149a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3150a0a3408eSKeith Busch { 315172cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 315272cd4cc2SKeith Busch 315372cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3154a0a3408eSKeith Busch } 3155a0a3408eSKeith Busch 315657dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 315757dacad5SJay Sternberg .error_detected = nvme_error_detected, 315857dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 315957dacad5SJay Sternberg .resume = nvme_error_resume, 3160775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3161775755edSChristoph Hellwig .reset_done = nvme_reset_done, 316257dacad5SJay Sternberg }; 316357dacad5SJay Sternberg 316457dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3165972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 316608095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3167e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3168972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 316999466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3170e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3171972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 317299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3173e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3174972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3175f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3176f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 317750af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 31789abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 31796c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3180ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3181ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 31826299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 31836299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3184540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 31857b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 31867b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 31875bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 31885bedd3afSChristoph Hellwig .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 31890302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 31900302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 319154adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 319254adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 31938c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 31948c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3195015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3196015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3197d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3198d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3199d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 32007ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 32017ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3202608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3203608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3204608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3205608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3206ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3207ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 320808b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 320908b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3210f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3211f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3212f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 32135611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 32145611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 321502ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 321602ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 321798f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 321898f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3219124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 322066341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 322166341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3222d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3223d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_SHARED_TAGS }, 32240b85f59dSAndy Shevchenko 32250b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 322657dacad5SJay Sternberg { 0, } 322757dacad5SJay Sternberg }; 322857dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 322957dacad5SJay Sternberg 323057dacad5SJay Sternberg static struct pci_driver nvme_driver = { 323157dacad5SJay Sternberg .name = "nvme", 323257dacad5SJay Sternberg .id_table = nvme_id_table, 323357dacad5SJay Sternberg .probe = nvme_probe, 323457dacad5SJay Sternberg .remove = nvme_remove, 323557dacad5SJay Sternberg .shutdown = nvme_shutdown, 3236d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 323757dacad5SJay Sternberg .driver = { 323857dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 323957dacad5SJay Sternberg }, 3240d916b1beSKeith Busch #endif 324174d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 324257dacad5SJay Sternberg .err_handler = &nvme_err_handler, 324357dacad5SJay Sternberg }; 324457dacad5SJay Sternberg 324557dacad5SJay Sternberg static int __init nvme_init(void) 324657dacad5SJay Sternberg { 324781101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 324881101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 324981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3250612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 325117c33167SKeith Busch 32529a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 325357dacad5SJay Sternberg } 325457dacad5SJay Sternberg 325557dacad5SJay Sternberg static void __exit nvme_exit(void) 325657dacad5SJay Sternberg { 325757dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 325803e0f3a6SMing Lei flush_workqueue(nvme_wq); 325957dacad5SJay Sternberg } 326057dacad5SJay Sternberg 326157dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 326257dacad5SJay Sternberg MODULE_LICENSE("GPL"); 326357dacad5SJay Sternberg MODULE_VERSION("1.0"); 326457dacad5SJay Sternberg module_init(nvme_init); 326557dacad5SJay Sternberg module_exit(nvme_exit); 3266