157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 3357dacad5SJay Sternberg 3457dacad5SJay Sternberg #include "nvme.h" 3557dacad5SJay Sternberg 3657dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3757dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3857dacad5SJay Sternberg 39a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40adf68f21SChristoph Hellwig 41943e942eSJens Axboe /* 42943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 43943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 44943e942eSJens Axboe */ 45943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 46943e942eSJens Axboe #define NVME_MAX_SEGS 127 47943e942eSJens Axboe 4857dacad5SJay Sternberg static int use_threaded_interrupts; 4957dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 5057dacad5SJay Sternberg 5157dacad5SJay Sternberg static bool use_cmb_sqes = true; 5269f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5357dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5457dacad5SJay Sternberg 5587ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5687ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5787ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5887ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5957dacad5SJay Sternberg 60a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 61a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 62a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 63a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 64a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 65a7a7cbe3SChaitanya Kulkarni 66b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 67b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 68b27c1e68Sweiping zhang .set = io_queue_depth_set, 69b27c1e68Sweiping zhang .get = param_get_int, 70b27c1e68Sweiping zhang }; 71b27c1e68Sweiping zhang 72b27c1e68Sweiping zhang static int io_queue_depth = 1024; 73b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 74b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 75b27c1e68Sweiping zhang 761c63dc66SChristoph Hellwig struct nvme_dev; 771c63dc66SChristoph Hellwig struct nvme_queue; 7857dacad5SJay Sternberg 79a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 8057dacad5SJay Sternberg 8157dacad5SJay Sternberg /* 821c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 831c63dc66SChristoph Hellwig */ 841c63dc66SChristoph Hellwig struct nvme_dev { 85147b27e4SSagi Grimberg struct nvme_queue *queues; 861c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 871c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 881c63dc66SChristoph Hellwig u32 __iomem *dbs; 891c63dc66SChristoph Hellwig struct device *dev; 901c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 911c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 921c63dc66SChristoph Hellwig unsigned online_queues; 931c63dc66SChristoph Hellwig unsigned max_qid; 9422b55601SKeith Busch unsigned int num_vecs; 951c63dc66SChristoph Hellwig int q_depth; 961c63dc66SChristoph Hellwig u32 db_stride; 971c63dc66SChristoph Hellwig void __iomem *bar; 9897f6ef64SXu Yu unsigned long bar_mapped_size; 995c8809e6SChristoph Hellwig struct work_struct remove_work; 10077bf25eaSKeith Busch struct mutex shutdown_lock; 1011c63dc66SChristoph Hellwig bool subsystem; 1021c63dc66SChristoph Hellwig void __iomem *cmb; 1038969f1f8SChristoph Hellwig pci_bus_addr_t cmb_bus_addr; 1041c63dc66SChristoph Hellwig u64 cmb_size; 1051c63dc66SChristoph Hellwig u32 cmbsz; 106202021c1SStephen Bates u32 cmbloc; 1071c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 108db3cbfffSKeith Busch struct completion ioq_wait; 10987ad72a5SChristoph Hellwig 110943e942eSJens Axboe mempool_t *iod_mempool; 111943e942eSJens Axboe 11287ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 113f9f38e33SHelen Koike u32 *dbbuf_dbs; 114f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 115f9f38e33SHelen Koike u32 *dbbuf_eis; 116f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 11787ad72a5SChristoph Hellwig 11887ad72a5SChristoph Hellwig /* host memory buffer support: */ 11987ad72a5SChristoph Hellwig u64 host_mem_size; 12087ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1214033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 12287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 12387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 12457dacad5SJay Sternberg }; 12557dacad5SJay Sternberg 126b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 127b27c1e68Sweiping zhang { 128b27c1e68Sweiping zhang int n = 0, ret; 129b27c1e68Sweiping zhang 130b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 131b27c1e68Sweiping zhang if (ret != 0 || n < 2) 132b27c1e68Sweiping zhang return -EINVAL; 133b27c1e68Sweiping zhang 134b27c1e68Sweiping zhang return param_set_int(val, kp); 135b27c1e68Sweiping zhang } 136b27c1e68Sweiping zhang 137f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 138f9f38e33SHelen Koike { 139f9f38e33SHelen Koike return qid * 2 * stride; 140f9f38e33SHelen Koike } 141f9f38e33SHelen Koike 142f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 143f9f38e33SHelen Koike { 144f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 145f9f38e33SHelen Koike } 146f9f38e33SHelen Koike 1471c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1481c63dc66SChristoph Hellwig { 1491c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1501c63dc66SChristoph Hellwig } 1511c63dc66SChristoph Hellwig 15257dacad5SJay Sternberg /* 15357dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 15457dacad5SJay Sternberg * commands and one for I/O commands). 15557dacad5SJay Sternberg */ 15657dacad5SJay Sternberg struct nvme_queue { 15757dacad5SJay Sternberg struct device *q_dmadev; 15857dacad5SJay Sternberg struct nvme_dev *dev; 1591ab0cd69SJens Axboe spinlock_t sq_lock; 16057dacad5SJay Sternberg struct nvme_command *sq_cmds; 16157dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 1621ab0cd69SJens Axboe spinlock_t cq_lock ____cacheline_aligned_in_smp; 16357dacad5SJay Sternberg volatile struct nvme_completion *cqes; 16457dacad5SJay Sternberg struct blk_mq_tags **tags; 16557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 16657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 16757dacad5SJay Sternberg u32 __iomem *q_db; 16857dacad5SJay Sternberg u16 q_depth; 16957dacad5SJay Sternberg s16 cq_vector; 17057dacad5SJay Sternberg u16 sq_tail; 17157dacad5SJay Sternberg u16 cq_head; 17268fa9dbeSJens Axboe u16 last_cq_head; 17357dacad5SJay Sternberg u16 qid; 17457dacad5SJay Sternberg u8 cq_phase; 175f9f38e33SHelen Koike u32 *dbbuf_sq_db; 176f9f38e33SHelen Koike u32 *dbbuf_cq_db; 177f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 178f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 17957dacad5SJay Sternberg }; 18057dacad5SJay Sternberg 18157dacad5SJay Sternberg /* 18271bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 18371bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 184f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 18571bd150cSChristoph Hellwig * allocated to store the PRP list. 18671bd150cSChristoph Hellwig */ 18771bd150cSChristoph Hellwig struct nvme_iod { 188d49187e9SChristoph Hellwig struct nvme_request req; 189f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 190a7a7cbe3SChaitanya Kulkarni bool use_sgl; 191f4800d6dSChristoph Hellwig int aborted; 19271bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 19371bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 19471bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 19571bd150cSChristoph Hellwig dma_addr_t first_dma; 196bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 197f4800d6dSChristoph Hellwig struct scatterlist *sg; 198f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 19957dacad5SJay Sternberg }; 20057dacad5SJay Sternberg 20157dacad5SJay Sternberg /* 20257dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 20357dacad5SJay Sternberg */ 20457dacad5SJay Sternberg static inline void _nvme_check_size(void) 20557dacad5SJay Sternberg { 20657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 20757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 20857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 20957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 21057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 21157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 21257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 21357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2140add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2150add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 21657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 21757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 218f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 219f9f38e33SHelen Koike } 220f9f38e33SHelen Koike 221f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 222f9f38e33SHelen Koike { 223f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 224f9f38e33SHelen Koike } 225f9f38e33SHelen Koike 226f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 227f9f38e33SHelen Koike { 228f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 229f9f38e33SHelen Koike 230f9f38e33SHelen Koike if (dev->dbbuf_dbs) 231f9f38e33SHelen Koike return 0; 232f9f38e33SHelen Koike 233f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 234f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 235f9f38e33SHelen Koike GFP_KERNEL); 236f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 237f9f38e33SHelen Koike return -ENOMEM; 238f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 239f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 240f9f38e33SHelen Koike GFP_KERNEL); 241f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 242f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 243f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 244f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 245f9f38e33SHelen Koike return -ENOMEM; 246f9f38e33SHelen Koike } 247f9f38e33SHelen Koike 248f9f38e33SHelen Koike return 0; 249f9f38e33SHelen Koike } 250f9f38e33SHelen Koike 251f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 252f9f38e33SHelen Koike { 253f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 254f9f38e33SHelen Koike 255f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 256f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 257f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 258f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 259f9f38e33SHelen Koike } 260f9f38e33SHelen Koike if (dev->dbbuf_eis) { 261f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 262f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 263f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 264f9f38e33SHelen Koike } 265f9f38e33SHelen Koike } 266f9f38e33SHelen Koike 267f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 268f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 269f9f38e33SHelen Koike { 270f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 271f9f38e33SHelen Koike return; 272f9f38e33SHelen Koike 273f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 274f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 275f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 276f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 277f9f38e33SHelen Koike } 278f9f38e33SHelen Koike 279f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 280f9f38e33SHelen Koike { 281f9f38e33SHelen Koike struct nvme_command c; 282f9f38e33SHelen Koike 283f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 284f9f38e33SHelen Koike return; 285f9f38e33SHelen Koike 286f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 287f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 288f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 289f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 290f9f38e33SHelen Koike 291f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2929bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 293f9f38e33SHelen Koike /* Free memory and continue on */ 294f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 295f9f38e33SHelen Koike } 296f9f38e33SHelen Koike } 297f9f38e33SHelen Koike 298f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 299f9f38e33SHelen Koike { 300f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 301f9f38e33SHelen Koike } 302f9f38e33SHelen Koike 303f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 304f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 305f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 306f9f38e33SHelen Koike { 307f9f38e33SHelen Koike if (dbbuf_db) { 308f9f38e33SHelen Koike u16 old_value; 309f9f38e33SHelen Koike 310f9f38e33SHelen Koike /* 311f9f38e33SHelen Koike * Ensure that the queue is written before updating 312f9f38e33SHelen Koike * the doorbell in memory 313f9f38e33SHelen Koike */ 314f9f38e33SHelen Koike wmb(); 315f9f38e33SHelen Koike 316f9f38e33SHelen Koike old_value = *dbbuf_db; 317f9f38e33SHelen Koike *dbbuf_db = value; 318f9f38e33SHelen Koike 319f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 320f9f38e33SHelen Koike return false; 321f9f38e33SHelen Koike } 322f9f38e33SHelen Koike 323f9f38e33SHelen Koike return true; 32457dacad5SJay Sternberg } 32557dacad5SJay Sternberg 32657dacad5SJay Sternberg /* 32757dacad5SJay Sternberg * Max size of iod being embedded in the request payload 32857dacad5SJay Sternberg */ 32957dacad5SJay Sternberg #define NVME_INT_PAGES 2 3305fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 33157dacad5SJay Sternberg 33257dacad5SJay Sternberg /* 33357dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 33457dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 33557dacad5SJay Sternberg * the I/O. 33657dacad5SJay Sternberg */ 33757dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 33857dacad5SJay Sternberg { 3395fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3405fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 34157dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 34257dacad5SJay Sternberg } 34357dacad5SJay Sternberg 344a7a7cbe3SChaitanya Kulkarni /* 345a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 346a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 347a7a7cbe3SChaitanya Kulkarni */ 348a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 349f4800d6dSChristoph Hellwig { 350a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 351f4800d6dSChristoph Hellwig } 352f4800d6dSChristoph Hellwig 353a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 354a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 35557dacad5SJay Sternberg { 356a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 357a7a7cbe3SChaitanya Kulkarni 358a7a7cbe3SChaitanya Kulkarni if (use_sgl) 359a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 360a7a7cbe3SChaitanya Kulkarni else 361a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 362a7a7cbe3SChaitanya Kulkarni 363a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 364a7a7cbe3SChaitanya Kulkarni } 365a7a7cbe3SChaitanya Kulkarni 366a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 367a7a7cbe3SChaitanya Kulkarni { 368a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 369a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 370a7a7cbe3SChaitanya Kulkarni use_sgl); 371a7a7cbe3SChaitanya Kulkarni 372a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 37357dacad5SJay Sternberg } 37457dacad5SJay Sternberg 37557dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 37657dacad5SJay Sternberg unsigned int hctx_idx) 37757dacad5SJay Sternberg { 37857dacad5SJay Sternberg struct nvme_dev *dev = data; 379147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 38057dacad5SJay Sternberg 38157dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 38257dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 38357dacad5SJay Sternberg WARN_ON(nvmeq->tags); 38457dacad5SJay Sternberg 38557dacad5SJay Sternberg hctx->driver_data = nvmeq; 38657dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 38757dacad5SJay Sternberg return 0; 38857dacad5SJay Sternberg } 38957dacad5SJay Sternberg 39057dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 39157dacad5SJay Sternberg { 39257dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 39357dacad5SJay Sternberg 39457dacad5SJay Sternberg nvmeq->tags = NULL; 39557dacad5SJay Sternberg } 39657dacad5SJay Sternberg 39757dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39857dacad5SJay Sternberg unsigned int hctx_idx) 39957dacad5SJay Sternberg { 40057dacad5SJay Sternberg struct nvme_dev *dev = data; 401147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 40257dacad5SJay Sternberg 40357dacad5SJay Sternberg if (!nvmeq->tags) 40457dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 40557dacad5SJay Sternberg 40657dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 40757dacad5SJay Sternberg hctx->driver_data = nvmeq; 40857dacad5SJay Sternberg return 0; 40957dacad5SJay Sternberg } 41057dacad5SJay Sternberg 411d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 412d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 41357dacad5SJay Sternberg { 414d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 415f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4160350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 417147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 41857dacad5SJay Sternberg 41957dacad5SJay Sternberg BUG_ON(!nvmeq); 420f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 421*59e29ce6SSagi Grimberg 422*59e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 42357dacad5SJay Sternberg return 0; 42457dacad5SJay Sternberg } 42557dacad5SJay Sternberg 426dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 427dca51e78SChristoph Hellwig { 428dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 429dca51e78SChristoph Hellwig 43022b55601SKeith Busch return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), 43122b55601SKeith Busch dev->num_vecs > 1 ? 1 /* admin queue */ : 0); 432dca51e78SChristoph Hellwig } 433dca51e78SChristoph Hellwig 43457dacad5SJay Sternberg /** 43590ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 43657dacad5SJay Sternberg * @nvmeq: The queue to use 43757dacad5SJay Sternberg * @cmd: The command to send 43857dacad5SJay Sternberg */ 43990ea5ca4SChristoph Hellwig static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 44057dacad5SJay Sternberg { 44190ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 44257dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 44390ea5ca4SChristoph Hellwig memcpy_toio(&nvmeq->sq_cmds_io[nvmeq->sq_tail], cmd, 44490ea5ca4SChristoph Hellwig sizeof(*cmd)); 44557dacad5SJay Sternberg else 44690ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 44757dacad5SJay Sternberg 44890ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 44990ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 45090ea5ca4SChristoph Hellwig if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 45190ea5ca4SChristoph Hellwig nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 45290ea5ca4SChristoph Hellwig writel(nvmeq->sq_tail, nvmeq->q_db); 45390ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 45457dacad5SJay Sternberg } 45557dacad5SJay Sternberg 456a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 45757dacad5SJay Sternberg { 458f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 459a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 46057dacad5SJay Sternberg } 46157dacad5SJay Sternberg 462955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 463955b1b5aSMinwoo Im { 464955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 46520469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 466955b1b5aSMinwoo Im unsigned int avg_seg_size; 467955b1b5aSMinwoo Im 46820469a37SKeith Busch if (nseg == 0) 46920469a37SKeith Busch return false; 47020469a37SKeith Busch 47120469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 472955b1b5aSMinwoo Im 473955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 474955b1b5aSMinwoo Im return false; 475955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 476955b1b5aSMinwoo Im return false; 477955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 478955b1b5aSMinwoo Im return false; 479955b1b5aSMinwoo Im return true; 480955b1b5aSMinwoo Im } 481955b1b5aSMinwoo Im 482fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 48357dacad5SJay Sternberg { 484f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 485f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 486b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 487f4800d6dSChristoph Hellwig 488955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 489955b1b5aSMinwoo Im 490f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 491943e942eSJens Axboe iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 492f4800d6dSChristoph Hellwig if (!iod->sg) 493fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 494f4800d6dSChristoph Hellwig } else { 495f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 49657dacad5SJay Sternberg } 49757dacad5SJay Sternberg 498f4800d6dSChristoph Hellwig iod->aborted = 0; 49957dacad5SJay Sternberg iod->npages = -1; 50057dacad5SJay Sternberg iod->nents = 0; 501f4800d6dSChristoph Hellwig iod->length = size; 502f80ec966SKeith Busch 503fc17b653SChristoph Hellwig return BLK_STS_OK; 50457dacad5SJay Sternberg } 50557dacad5SJay Sternberg 506f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 50757dacad5SJay Sternberg { 508f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 509a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 510a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 511a7a7cbe3SChaitanya Kulkarni 51257dacad5SJay Sternberg int i; 51357dacad5SJay Sternberg 51457dacad5SJay Sternberg if (iod->npages == 0) 515a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 516a7a7cbe3SChaitanya Kulkarni dma_addr); 517a7a7cbe3SChaitanya Kulkarni 51857dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 519a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 520a7a7cbe3SChaitanya Kulkarni 521a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 522a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 523a7a7cbe3SChaitanya Kulkarni 524a7a7cbe3SChaitanya Kulkarni next_dma_addr = 525a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 526a7a7cbe3SChaitanya Kulkarni } else { 527a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 528a7a7cbe3SChaitanya Kulkarni 529a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 530a7a7cbe3SChaitanya Kulkarni } 531a7a7cbe3SChaitanya Kulkarni 532a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 533a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 53457dacad5SJay Sternberg } 53557dacad5SJay Sternberg 536f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 537943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 53857dacad5SJay Sternberg } 53957dacad5SJay Sternberg 54057dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 54157dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 54257dacad5SJay Sternberg { 54357dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 54457dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 54557dacad5SJay Sternberg } 54657dacad5SJay Sternberg 54757dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 54857dacad5SJay Sternberg { 54957dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 55057dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 55157dacad5SJay Sternberg } 55257dacad5SJay Sternberg 55357dacad5SJay Sternberg /** 55457dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 55557dacad5SJay Sternberg * 55657dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 55757dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 55857dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 55957dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 56057dacad5SJay Sternberg * 56157dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 56257dacad5SJay Sternberg */ 56357dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 56457dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 56557dacad5SJay Sternberg { 56657dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 56757dacad5SJay Sternberg struct bio_integrity_payload *bip; 56857dacad5SJay Sternberg struct t10_pi_tuple *pi; 56957dacad5SJay Sternberg void *p, *pmap; 57057dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 57157dacad5SJay Sternberg 57257dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 57357dacad5SJay Sternberg return; 57457dacad5SJay Sternberg 57557dacad5SJay Sternberg bip = bio_integrity(req->bio); 57657dacad5SJay Sternberg if (!bip) 57757dacad5SJay Sternberg return; 57857dacad5SJay Sternberg 57957dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 58057dacad5SJay Sternberg 58157dacad5SJay Sternberg p = pmap; 58257dacad5SJay Sternberg virt = bip_get_seed(bip); 58357dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 58457dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 585ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 58657dacad5SJay Sternberg 58757dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 58857dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 58957dacad5SJay Sternberg dif_swap(phys, virt, pi); 59057dacad5SJay Sternberg p += ts; 59157dacad5SJay Sternberg } 59257dacad5SJay Sternberg kunmap_atomic(pmap); 59357dacad5SJay Sternberg } 59457dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 59557dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 59657dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 59757dacad5SJay Sternberg { 59857dacad5SJay Sternberg } 59957dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 60057dacad5SJay Sternberg { 60157dacad5SJay Sternberg } 60257dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 60357dacad5SJay Sternberg { 60457dacad5SJay Sternberg } 60557dacad5SJay Sternberg #endif 60657dacad5SJay Sternberg 607d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 608d0877473SKeith Busch { 609d0877473SKeith Busch int i; 610d0877473SKeith Busch struct scatterlist *sg; 611d0877473SKeith Busch 612d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 613d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 614d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 615d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 616d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 617d0877473SKeith Busch sg_dma_len(sg)); 618d0877473SKeith Busch } 619d0877473SKeith Busch } 620d0877473SKeith Busch 621a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 622a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 62357dacad5SJay Sternberg { 624f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 62557dacad5SJay Sternberg struct dma_pool *pool; 626b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 62757dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 62857dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 62957dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6305fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 63157dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 63257dacad5SJay Sternberg __le64 *prp_list; 633a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 63457dacad5SJay Sternberg dma_addr_t prp_dma; 63557dacad5SJay Sternberg int nprps, i; 63657dacad5SJay Sternberg 63757dacad5SJay Sternberg length -= (page_size - offset); 6385228b328SJan H. Schönherr if (length <= 0) { 6395228b328SJan H. Schönherr iod->first_dma = 0; 640a7a7cbe3SChaitanya Kulkarni goto done; 6415228b328SJan H. Schönherr } 64257dacad5SJay Sternberg 64357dacad5SJay Sternberg dma_len -= (page_size - offset); 64457dacad5SJay Sternberg if (dma_len) { 64557dacad5SJay Sternberg dma_addr += (page_size - offset); 64657dacad5SJay Sternberg } else { 64757dacad5SJay Sternberg sg = sg_next(sg); 64857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 64957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65057dacad5SJay Sternberg } 65157dacad5SJay Sternberg 65257dacad5SJay Sternberg if (length <= page_size) { 65357dacad5SJay Sternberg iod->first_dma = dma_addr; 654a7a7cbe3SChaitanya Kulkarni goto done; 65557dacad5SJay Sternberg } 65657dacad5SJay Sternberg 65757dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 65857dacad5SJay Sternberg if (nprps <= (256 / 8)) { 65957dacad5SJay Sternberg pool = dev->prp_small_pool; 66057dacad5SJay Sternberg iod->npages = 0; 66157dacad5SJay Sternberg } else { 66257dacad5SJay Sternberg pool = dev->prp_page_pool; 66357dacad5SJay Sternberg iod->npages = 1; 66457dacad5SJay Sternberg } 66557dacad5SJay Sternberg 66669d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 66757dacad5SJay Sternberg if (!prp_list) { 66857dacad5SJay Sternberg iod->first_dma = dma_addr; 66957dacad5SJay Sternberg iod->npages = -1; 67086eea289SKeith Busch return BLK_STS_RESOURCE; 67157dacad5SJay Sternberg } 67257dacad5SJay Sternberg list[0] = prp_list; 67357dacad5SJay Sternberg iod->first_dma = prp_dma; 67457dacad5SJay Sternberg i = 0; 67557dacad5SJay Sternberg for (;;) { 67657dacad5SJay Sternberg if (i == page_size >> 3) { 67757dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 67869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67957dacad5SJay Sternberg if (!prp_list) 68086eea289SKeith Busch return BLK_STS_RESOURCE; 68157dacad5SJay Sternberg list[iod->npages++] = prp_list; 68257dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 68357dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 68457dacad5SJay Sternberg i = 1; 68557dacad5SJay Sternberg } 68657dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 68757dacad5SJay Sternberg dma_len -= page_size; 68857dacad5SJay Sternberg dma_addr += page_size; 68957dacad5SJay Sternberg length -= page_size; 69057dacad5SJay Sternberg if (length <= 0) 69157dacad5SJay Sternberg break; 69257dacad5SJay Sternberg if (dma_len > 0) 69357dacad5SJay Sternberg continue; 69486eea289SKeith Busch if (unlikely(dma_len < 0)) 69586eea289SKeith Busch goto bad_sgl; 69657dacad5SJay Sternberg sg = sg_next(sg); 69757dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69857dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69957dacad5SJay Sternberg } 70057dacad5SJay Sternberg 701a7a7cbe3SChaitanya Kulkarni done: 702a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 703a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 704a7a7cbe3SChaitanya Kulkarni 70586eea289SKeith Busch return BLK_STS_OK; 70686eea289SKeith Busch 70786eea289SKeith Busch bad_sgl: 708d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 709d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 710d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 71186eea289SKeith Busch return BLK_STS_IOERR; 71257dacad5SJay Sternberg } 71357dacad5SJay Sternberg 714a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 715a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 716a7a7cbe3SChaitanya Kulkarni { 717a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 718a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 719a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 720a7a7cbe3SChaitanya Kulkarni } 721a7a7cbe3SChaitanya Kulkarni 722a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 723a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 724a7a7cbe3SChaitanya Kulkarni { 725a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 726a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 727a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 728a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 729a7a7cbe3SChaitanya Kulkarni } else { 730a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 731a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 732a7a7cbe3SChaitanya Kulkarni } 733a7a7cbe3SChaitanya Kulkarni } 734a7a7cbe3SChaitanya Kulkarni 735a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 736b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 737a7a7cbe3SChaitanya Kulkarni { 738a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 739a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 740a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 741a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 742a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 743b0f2853bSChristoph Hellwig int i = 0; 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 746a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 747a7a7cbe3SChaitanya Kulkarni 748b0f2853bSChristoph Hellwig if (entries == 1) { 749a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 750a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 751a7a7cbe3SChaitanya Kulkarni } 752a7a7cbe3SChaitanya Kulkarni 753a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 754a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 755a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 756a7a7cbe3SChaitanya Kulkarni } else { 757a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 758a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 759a7a7cbe3SChaitanya Kulkarni } 760a7a7cbe3SChaitanya Kulkarni 761a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 762a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 763a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 764a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 765a7a7cbe3SChaitanya Kulkarni } 766a7a7cbe3SChaitanya Kulkarni 767a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 768a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 769a7a7cbe3SChaitanya Kulkarni 770a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 771a7a7cbe3SChaitanya Kulkarni 772a7a7cbe3SChaitanya Kulkarni do { 773a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 774a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 775a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 776a7a7cbe3SChaitanya Kulkarni 777a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 778a7a7cbe3SChaitanya Kulkarni if (!sg_list) 779a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 780a7a7cbe3SChaitanya Kulkarni 781a7a7cbe3SChaitanya Kulkarni i = 0; 782a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 783a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 784a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 785a7a7cbe3SChaitanya Kulkarni } 786a7a7cbe3SChaitanya Kulkarni 787a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 788a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 789b0f2853bSChristoph Hellwig } while (--entries > 0); 790a7a7cbe3SChaitanya Kulkarni 791a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 792a7a7cbe3SChaitanya Kulkarni } 793a7a7cbe3SChaitanya Kulkarni 794fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 795b131c61dSChristoph Hellwig struct nvme_command *cmnd) 79657dacad5SJay Sternberg { 797f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 798ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 799ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 800ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 801fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 802b0f2853bSChristoph Hellwig int nr_mapped; 80357dacad5SJay Sternberg 804f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 805ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 806ba1ca37eSChristoph Hellwig if (!iod->nents) 807ba1ca37eSChristoph Hellwig goto out; 808ba1ca37eSChristoph Hellwig 809fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 810b0f2853bSChristoph Hellwig nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 811b0f2853bSChristoph Hellwig DMA_ATTR_NO_WARN); 812b0f2853bSChristoph Hellwig if (!nr_mapped) 813ba1ca37eSChristoph Hellwig goto out; 814ba1ca37eSChristoph Hellwig 815955b1b5aSMinwoo Im if (iod->use_sgl) 816b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 817a7a7cbe3SChaitanya Kulkarni else 818a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 819a7a7cbe3SChaitanya Kulkarni 82086eea289SKeith Busch if (ret != BLK_STS_OK) 821ba1ca37eSChristoph Hellwig goto out_unmap; 822ba1ca37eSChristoph Hellwig 823fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 824ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 825ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 826ba1ca37eSChristoph Hellwig goto out_unmap; 827ba1ca37eSChristoph Hellwig 828bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 829bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 830ba1ca37eSChristoph Hellwig goto out_unmap; 831ba1ca37eSChristoph Hellwig 832b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_WRITE) 833ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 834ba1ca37eSChristoph Hellwig 835bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 836ba1ca37eSChristoph Hellwig goto out_unmap; 83757dacad5SJay Sternberg } 83857dacad5SJay Sternberg 839ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 840bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 841fc17b653SChristoph Hellwig return BLK_STS_OK; 842ba1ca37eSChristoph Hellwig 843ba1ca37eSChristoph Hellwig out_unmap: 844ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 845ba1ca37eSChristoph Hellwig out: 846ba1ca37eSChristoph Hellwig return ret; 84757dacad5SJay Sternberg } 84857dacad5SJay Sternberg 849f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 850d4f6c3abSChristoph Hellwig { 851f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 852d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 853d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 854d4f6c3abSChristoph Hellwig 855d4f6c3abSChristoph Hellwig if (iod->nents) { 856d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 857d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 858b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_READ) 859d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 860bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 861d4f6c3abSChristoph Hellwig } 862d4f6c3abSChristoph Hellwig } 863d4f6c3abSChristoph Hellwig 864f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 865f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 86657dacad5SJay Sternberg } 86757dacad5SJay Sternberg 86857dacad5SJay Sternberg /* 86957dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 87057dacad5SJay Sternberg */ 871fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 87257dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 87357dacad5SJay Sternberg { 87457dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 87557dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 87657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 87757dacad5SJay Sternberg struct request *req = bd->rq; 878ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 879ebe6d874SChristoph Hellwig blk_status_t ret; 88057dacad5SJay Sternberg 881d1f06f4aSJens Axboe /* 882d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 883d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 884d1f06f4aSJens Axboe */ 885d1f06f4aSJens Axboe if (unlikely(nvmeq->cq_vector < 0)) 886d1f06f4aSJens Axboe return BLK_STS_IOERR; 887d1f06f4aSJens Axboe 888f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 889fc17b653SChristoph Hellwig if (ret) 890f4800d6dSChristoph Hellwig return ret; 89157dacad5SJay Sternberg 892b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 893fc17b653SChristoph Hellwig if (ret) 894f9d03f96SChristoph Hellwig goto out_free_cmd; 89557dacad5SJay Sternberg 896fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 897b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 898fc17b653SChristoph Hellwig if (ret) 899f9d03f96SChristoph Hellwig goto out_cleanup_iod; 900fc17b653SChristoph Hellwig } 901ba1ca37eSChristoph Hellwig 902aae239e1SChristoph Hellwig blk_mq_start_request(req); 90390ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &cmnd); 904fc17b653SChristoph Hellwig return BLK_STS_OK; 905f9d03f96SChristoph Hellwig out_cleanup_iod: 906f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 907f9d03f96SChristoph Hellwig out_free_cmd: 908f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 909ba1ca37eSChristoph Hellwig return ret; 91057dacad5SJay Sternberg } 91157dacad5SJay Sternberg 91277f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 913eee417b0SChristoph Hellwig { 914f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 915eee417b0SChristoph Hellwig 91677f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 91777f02a7aSChristoph Hellwig nvme_complete_rq(req); 91857dacad5SJay Sternberg } 91957dacad5SJay Sternberg 920d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 921750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 922d783e0bdSMarta Rybczynska { 923750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 924750dde44SChristoph Hellwig nvmeq->cq_phase; 925d783e0bdSMarta Rybczynska } 926d783e0bdSMarta Rybczynska 927eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 92857dacad5SJay Sternberg { 929eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 93057dacad5SJay Sternberg 931eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 932eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 933eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 934eb281c82SSagi Grimberg } 935adf68f21SChristoph Hellwig 9365cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 93757dacad5SJay Sternberg { 9385cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 93957dacad5SJay Sternberg struct request *req; 940adf68f21SChristoph Hellwig 94183a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9421b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 943aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 94483a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 94583a12fb7SSagi Grimberg return; 946aae239e1SChristoph Hellwig } 947aae239e1SChristoph Hellwig 948adf68f21SChristoph Hellwig /* 949adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 950adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 951adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 952adf68f21SChristoph Hellwig * for them but rather special case them here. 953adf68f21SChristoph Hellwig */ 954adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 95538dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9567bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 95783a12fb7SSagi Grimberg cqe->status, &cqe->result); 958a0fa9647SJens Axboe return; 95957dacad5SJay Sternberg } 96057dacad5SJay Sternberg 96183a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 96283a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 96383a12fb7SSagi Grimberg } 96457dacad5SJay Sternberg 9655cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 96683a12fb7SSagi Grimberg { 9675cb525c8SJens Axboe while (start != end) { 9685cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 9695cb525c8SJens Axboe if (++start == nvmeq->q_depth) 9705cb525c8SJens Axboe start = 0; 9715cb525c8SJens Axboe } 9725cb525c8SJens Axboe } 97383a12fb7SSagi Grimberg 9745cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9755cb525c8SJens Axboe { 976920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 977920d13a8SSagi Grimberg nvmeq->cq_head = 0; 978920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 979920d13a8SSagi Grimberg } 980a0fa9647SJens Axboe } 981a0fa9647SJens Axboe 9825cb525c8SJens Axboe static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 9835cb525c8SJens Axboe u16 *end, int tag) 984a0fa9647SJens Axboe { 9855cb525c8SJens Axboe bool found = false; 98683a12fb7SSagi Grimberg 9875cb525c8SJens Axboe *start = nvmeq->cq_head; 9885cb525c8SJens Axboe while (!found && nvme_cqe_pending(nvmeq)) { 9895cb525c8SJens Axboe if (nvmeq->cqes[nvmeq->cq_head].command_id == tag) 9905cb525c8SJens Axboe found = true; 9915cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 99257dacad5SJay Sternberg } 9935cb525c8SJens Axboe *end = nvmeq->cq_head; 99457dacad5SJay Sternberg 9955cb525c8SJens Axboe if (*start != *end) 996eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 9975cb525c8SJens Axboe return found; 99857dacad5SJay Sternberg } 99957dacad5SJay Sternberg 100057dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 100157dacad5SJay Sternberg { 100257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 100368fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10045cb525c8SJens Axboe u16 start, end; 10055cb525c8SJens Axboe 10061ab0cd69SJens Axboe spin_lock(&nvmeq->cq_lock); 100768fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 100868fa9dbeSJens Axboe ret = IRQ_HANDLED; 10095cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 101068fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10111ab0cd69SJens Axboe spin_unlock(&nvmeq->cq_lock); 10125cb525c8SJens Axboe 101368fa9dbeSJens Axboe if (start != end) { 10145cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10155cb525c8SJens Axboe return IRQ_HANDLED; 101657dacad5SJay Sternberg } 101757dacad5SJay Sternberg 101868fa9dbeSJens Axboe return ret; 101957dacad5SJay Sternberg } 102057dacad5SJay Sternberg 102157dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 102257dacad5SJay Sternberg { 102357dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1024750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 102557dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1026d783e0bdSMarta Rybczynska return IRQ_NONE; 102757dacad5SJay Sternberg } 102857dacad5SJay Sternberg 10297776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 1030a0fa9647SJens Axboe { 10315cb525c8SJens Axboe u16 start, end; 10325cb525c8SJens Axboe bool found; 1033a0fa9647SJens Axboe 1034750dde44SChristoph Hellwig if (!nvme_cqe_pending(nvmeq)) 1035442e19b7SSagi Grimberg return 0; 1036442e19b7SSagi Grimberg 10371ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 10385cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10391ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 1040442e19b7SSagi Grimberg 10415cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1042442e19b7SSagi Grimberg return found; 1043a0fa9647SJens Axboe } 1044a0fa9647SJens Axboe 10457776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 10467776db1cSKeith Busch { 10477776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 10487776db1cSKeith Busch 10497776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 10507776db1cSKeith Busch } 10517776db1cSKeith Busch 1052ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 105357dacad5SJay Sternberg { 1054f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1055147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 105657dacad5SJay Sternberg struct nvme_command c; 105757dacad5SJay Sternberg 105857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 105957dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1060ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 106190ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &c); 106257dacad5SJay Sternberg } 106357dacad5SJay Sternberg 106457dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 106557dacad5SJay Sternberg { 106657dacad5SJay Sternberg struct nvme_command c; 106757dacad5SJay Sternberg 106857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 106957dacad5SJay Sternberg c.delete_queue.opcode = opcode; 107057dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 107157dacad5SJay Sternberg 10721c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 107357dacad5SJay Sternberg } 107457dacad5SJay Sternberg 107557dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1076a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 107757dacad5SJay Sternberg { 107857dacad5SJay Sternberg struct nvme_command c; 107957dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 108057dacad5SJay Sternberg 108157dacad5SJay Sternberg /* 108216772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 108357dacad5SJay Sternberg * is attached to the request. 108457dacad5SJay Sternberg */ 108557dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 108657dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 108757dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 108857dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 108957dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 109057dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1091a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 109257dacad5SJay Sternberg 10931c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 109457dacad5SJay Sternberg } 109557dacad5SJay Sternberg 109657dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 109757dacad5SJay Sternberg struct nvme_queue *nvmeq) 109857dacad5SJay Sternberg { 10999abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 110057dacad5SJay Sternberg struct nvme_command c; 110181c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 110257dacad5SJay Sternberg 110357dacad5SJay Sternberg /* 11049abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11059abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11069abd68efSJens Axboe * URGENT. 11079abd68efSJens Axboe */ 11089abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11099abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11109abd68efSJens Axboe 11119abd68efSJens Axboe /* 111216772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 111357dacad5SJay Sternberg * is attached to the request. 111457dacad5SJay Sternberg */ 111557dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 111657dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 111757dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 111857dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 111957dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 112057dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 112157dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 112257dacad5SJay Sternberg 11231c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 112457dacad5SJay Sternberg } 112557dacad5SJay Sternberg 112657dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 112757dacad5SJay Sternberg { 112857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 112957dacad5SJay Sternberg } 113057dacad5SJay Sternberg 113157dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 113257dacad5SJay Sternberg { 113357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 113457dacad5SJay Sternberg } 113557dacad5SJay Sternberg 11362a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 113757dacad5SJay Sternberg { 1138f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1139f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 114057dacad5SJay Sternberg 114127fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 114227fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1143e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1144e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 114557dacad5SJay Sternberg } 114657dacad5SJay Sternberg 1147b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1148b2a0eb1aSKeith Busch { 1149b2a0eb1aSKeith Busch 1150b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1151b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1152b2a0eb1aSKeith Busch */ 1153b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1154b2a0eb1aSKeith Busch 1155ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1156ad70062cSJianchao Wang switch (dev->ctrl.state) { 1157ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1158ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1159b2a0eb1aSKeith Busch return false; 1160ad70062cSJianchao Wang default: 1161ad70062cSJianchao Wang break; 1162ad70062cSJianchao Wang } 1163b2a0eb1aSKeith Busch 1164b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1165b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1166b2a0eb1aSKeith Busch */ 1167b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1168b2a0eb1aSKeith Busch return false; 1169b2a0eb1aSKeith Busch 1170b2a0eb1aSKeith Busch return true; 1171b2a0eb1aSKeith Busch } 1172b2a0eb1aSKeith Busch 1173b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1174b2a0eb1aSKeith Busch { 1175b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1176b2a0eb1aSKeith Busch u16 pci_status; 1177b2a0eb1aSKeith Busch int result; 1178b2a0eb1aSKeith Busch 1179b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1180b2a0eb1aSKeith Busch &pci_status); 1181b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1182b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1183b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1184b2a0eb1aSKeith Busch csts, pci_status); 1185b2a0eb1aSKeith Busch else 1186b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1187b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1188b2a0eb1aSKeith Busch csts, result); 1189b2a0eb1aSKeith Busch } 1190b2a0eb1aSKeith Busch 119131c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 119257dacad5SJay Sternberg { 1193f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1194f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 119557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 119657dacad5SJay Sternberg struct request *abort_req; 119757dacad5SJay Sternberg struct nvme_command cmd; 1198b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1199b2a0eb1aSKeith Busch 1200651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1201651438bbSWen Xiong * the recovery mechanism will surely fail. 1202651438bbSWen Xiong */ 1203651438bbSWen Xiong mb(); 1204651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1205651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1206651438bbSWen Xiong 1207b2a0eb1aSKeith Busch /* 1208b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1209b2a0eb1aSKeith Busch */ 1210b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1211b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1212b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1213d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1214db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1215b2a0eb1aSKeith Busch } 121657dacad5SJay Sternberg 121731c7c7d2SChristoph Hellwig /* 12187776db1cSKeith Busch * Did we miss an interrupt? 12197776db1cSKeith Busch */ 12207776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 12217776db1cSKeith Busch dev_warn(dev->ctrl.device, 12227776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12237776db1cSKeith Busch req->tag, nvmeq->qid); 1224db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12257776db1cSKeith Busch } 12267776db1cSKeith Busch 12277776db1cSKeith Busch /* 1228fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1229fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1230fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1231db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1232fd634f41SChristoph Hellwig */ 12334244140dSKeith Busch switch (dev->ctrl.state) { 12344244140dSKeith Busch case NVME_CTRL_CONNECTING: 12354244140dSKeith Busch case NVME_CTRL_RESETTING: 1236b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1237fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1238fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1239a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 124027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1241db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12424244140dSKeith Busch default: 12434244140dSKeith Busch break; 1244fd634f41SChristoph Hellwig } 1245fd634f41SChristoph Hellwig 1246fd634f41SChristoph Hellwig /* 1247e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1248e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1249e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 125031c7c7d2SChristoph Hellwig */ 1251f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12521b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 125357dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 125457dacad5SJay Sternberg req->tag, nvmeq->qid); 1255a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1256d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1257e1569a16SKeith Busch 125827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1259db8c48e4SChristoph Hellwig return BLK_EH_DONE; 126057dacad5SJay Sternberg } 126157dacad5SJay Sternberg 1262e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1263e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1264e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1265e7a2a87dSChristoph Hellwig } 12667bf7d778SKeith Busch iod->aborted = 1; 126757dacad5SJay Sternberg 126857dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 126957dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 127057dacad5SJay Sternberg cmd.abort.cid = req->tag; 127157dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 127257dacad5SJay Sternberg 12731b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12741b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 127557dacad5SJay Sternberg req->tag, nvmeq->qid); 1276e7a2a87dSChristoph Hellwig 1277e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1278eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12796bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12806bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 128131c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 128257dacad5SJay Sternberg } 128357dacad5SJay Sternberg 1284e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1285e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1286e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 128757dacad5SJay Sternberg 128857dacad5SJay Sternberg /* 128957dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 129057dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 129157dacad5SJay Sternberg * as the device then is in a faulty state. 129257dacad5SJay Sternberg */ 129357dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 129457dacad5SJay Sternberg } 129557dacad5SJay Sternberg 129657dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 129757dacad5SJay Sternberg { 129857dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 129957dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 130057dacad5SJay Sternberg if (nvmeq->sq_cmds) 130157dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 130257dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 130357dacad5SJay Sternberg } 130457dacad5SJay Sternberg 130557dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 130657dacad5SJay Sternberg { 130757dacad5SJay Sternberg int i; 130857dacad5SJay Sternberg 1309d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1310d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1311147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 131257dacad5SJay Sternberg } 131357dacad5SJay Sternberg } 131457dacad5SJay Sternberg 131557dacad5SJay Sternberg /** 131657dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 131757dacad5SJay Sternberg * @nvmeq - queue to suspend 131857dacad5SJay Sternberg */ 131957dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 132057dacad5SJay Sternberg { 132157dacad5SJay Sternberg int vector; 132257dacad5SJay Sternberg 13231ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 132457dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 13251ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 132657dacad5SJay Sternberg return 1; 132757dacad5SJay Sternberg } 13280ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 132957dacad5SJay Sternberg nvmeq->dev->online_queues--; 133057dacad5SJay Sternberg nvmeq->cq_vector = -1; 13311ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 133257dacad5SJay Sternberg 1333d1f06f4aSJens Axboe /* 1334d1f06f4aSJens Axboe * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without 1335d1f06f4aSJens Axboe * having to grab the lock. 1336d1f06f4aSJens Axboe */ 1337d1f06f4aSJens Axboe mb(); 133857dacad5SJay Sternberg 13391c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1340c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 134157dacad5SJay Sternberg 13420ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 134357dacad5SJay Sternberg 134457dacad5SJay Sternberg return 0; 134557dacad5SJay Sternberg } 134657dacad5SJay Sternberg 1347a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 134857dacad5SJay Sternberg { 1349147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 13505cb525c8SJens Axboe u16 start, end; 135157dacad5SJay Sternberg 1352a5cdb68cSKeith Busch if (shutdown) 1353a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1354a5cdb68cSKeith Busch else 135520d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 135657dacad5SJay Sternberg 13571ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 13585cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 13591ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 13605cb525c8SJens Axboe 13615cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 136257dacad5SJay Sternberg } 136357dacad5SJay Sternberg 136457dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 136557dacad5SJay Sternberg int entry_size) 136657dacad5SJay Sternberg { 136757dacad5SJay Sternberg int q_depth = dev->q_depth; 13685fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13695fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 137057dacad5SJay Sternberg 137157dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 137257dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13735fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 137457dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 137557dacad5SJay Sternberg 137657dacad5SJay Sternberg /* 137757dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 137857dacad5SJay Sternberg * would be better to map queues in system memory with the 137957dacad5SJay Sternberg * original depth 138057dacad5SJay Sternberg */ 138157dacad5SJay Sternberg if (q_depth < 64) 138257dacad5SJay Sternberg return -ENOMEM; 138357dacad5SJay Sternberg } 138457dacad5SJay Sternberg 138557dacad5SJay Sternberg return q_depth; 138657dacad5SJay Sternberg } 138757dacad5SJay Sternberg 138857dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 138957dacad5SJay Sternberg int qid, int depth) 139057dacad5SJay Sternberg { 1391815c6704SKeith Busch /* CMB SQEs will be mapped before creation */ 1392815c6704SKeith Busch if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) 1393815c6704SKeith Busch return 0; 1394815c6704SKeith Busch 139557dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 139657dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 139757dacad5SJay Sternberg if (!nvmeq->sq_cmds) 139857dacad5SJay Sternberg return -ENOMEM; 139957dacad5SJay Sternberg return 0; 140057dacad5SJay Sternberg } 140157dacad5SJay Sternberg 1402a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 140357dacad5SJay Sternberg { 1404147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 140557dacad5SJay Sternberg 140662314e40SKeith Busch if (dev->ctrl.queue_count > qid) 140762314e40SKeith Busch return 0; 140857dacad5SJay Sternberg 140957dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 141057dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 141157dacad5SJay Sternberg if (!nvmeq->cqes) 141257dacad5SJay Sternberg goto free_nvmeq; 141357dacad5SJay Sternberg 141457dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 141557dacad5SJay Sternberg goto free_cqdma; 141657dacad5SJay Sternberg 141757dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 141857dacad5SJay Sternberg nvmeq->dev = dev; 14191ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14201ab0cd69SJens Axboe spin_lock_init(&nvmeq->cq_lock); 142157dacad5SJay Sternberg nvmeq->cq_head = 0; 142257dacad5SJay Sternberg nvmeq->cq_phase = 1; 142357dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 142457dacad5SJay Sternberg nvmeq->q_depth = depth; 142557dacad5SJay Sternberg nvmeq->qid = qid; 142657dacad5SJay Sternberg nvmeq->cq_vector = -1; 1427d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 142857dacad5SJay Sternberg 1429147b27e4SSagi Grimberg return 0; 143057dacad5SJay Sternberg 143157dacad5SJay Sternberg free_cqdma: 143257dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 143357dacad5SJay Sternberg nvmeq->cq_dma_addr); 143457dacad5SJay Sternberg free_nvmeq: 1435147b27e4SSagi Grimberg return -ENOMEM; 143657dacad5SJay Sternberg } 143757dacad5SJay Sternberg 1438dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 143957dacad5SJay Sternberg { 14400ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14410ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14420ff199cbSChristoph Hellwig 14430ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14440ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14450ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14460ff199cbSChristoph Hellwig } else { 14470ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14480ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14490ff199cbSChristoph Hellwig } 145057dacad5SJay Sternberg } 145157dacad5SJay Sternberg 145257dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 145357dacad5SJay Sternberg { 145457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 145557dacad5SJay Sternberg 14561ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 145757dacad5SJay Sternberg nvmeq->sq_tail = 0; 145857dacad5SJay Sternberg nvmeq->cq_head = 0; 145957dacad5SJay Sternberg nvmeq->cq_phase = 1; 146057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 146157dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1462f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 146357dacad5SJay Sternberg dev->online_queues++; 14641ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 146557dacad5SJay Sternberg } 146657dacad5SJay Sternberg 146757dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 146857dacad5SJay Sternberg { 146957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 147057dacad5SJay Sternberg int result; 1471a8e3e0bbSJianchao Wang s16 vector; 147257dacad5SJay Sternberg 1473815c6704SKeith Busch if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1474815c6704SKeith Busch unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth), 1475815c6704SKeith Busch dev->ctrl.page_size); 1476815c6704SKeith Busch nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; 1477815c6704SKeith Busch nvmeq->sq_cmds_io = dev->cmb + offset; 1478815c6704SKeith Busch } 1479815c6704SKeith Busch 148022b55601SKeith Busch /* 148122b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 148222b55601SKeith Busch * has only one vector available. 148322b55601SKeith Busch */ 1484a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 1485a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1486ded45505SKeith Busch if (result) 1487ded45505SKeith Busch return result; 148857dacad5SJay Sternberg 148957dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 149057dacad5SJay Sternberg if (result < 0) 1491ded45505SKeith Busch return result; 1492ded45505SKeith Busch else if (result) 149357dacad5SJay Sternberg goto release_cq; 149457dacad5SJay Sternberg 1495a8e3e0bbSJianchao Wang /* 1496a8e3e0bbSJianchao Wang * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will 1497a8e3e0bbSJianchao Wang * invoke free_irq for it and cause a 'Trying to free already-free IRQ 1498a8e3e0bbSJianchao Wang * xxx' warning if the create CQ/SQ command times out. 1499a8e3e0bbSJianchao Wang */ 1500a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1501161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 1502dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 150357dacad5SJay Sternberg if (result < 0) 150457dacad5SJay Sternberg goto release_sq; 150557dacad5SJay Sternberg 150657dacad5SJay Sternberg return result; 150757dacad5SJay Sternberg 150857dacad5SJay Sternberg release_sq: 1509a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 1510f25a2dfcSJianchao Wang dev->online_queues--; 151157dacad5SJay Sternberg adapter_delete_sq(dev, qid); 151257dacad5SJay Sternberg release_cq: 151357dacad5SJay Sternberg adapter_delete_cq(dev, qid); 151457dacad5SJay Sternberg return result; 151557dacad5SJay Sternberg } 151657dacad5SJay Sternberg 1517f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 151857dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 151977f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 152057dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 152157dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15220350815aSChristoph Hellwig .init_request = nvme_init_request, 152357dacad5SJay Sternberg .timeout = nvme_timeout, 152457dacad5SJay Sternberg }; 152557dacad5SJay Sternberg 1526f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 152757dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 152877f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 152957dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 153057dacad5SJay Sternberg .init_request = nvme_init_request, 1531dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 153257dacad5SJay Sternberg .timeout = nvme_timeout, 1533a0fa9647SJens Axboe .poll = nvme_poll, 153457dacad5SJay Sternberg }; 153557dacad5SJay Sternberg 153657dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 153757dacad5SJay Sternberg { 15381c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 153969d9a99cSKeith Busch /* 154069d9a99cSKeith Busch * If the controller was reset during removal, it's possible 154169d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 154269d9a99cSKeith Busch * queue to flush these to completion. 154369d9a99cSKeith Busch */ 1544c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15451c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 154657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 154757dacad5SJay Sternberg } 154857dacad5SJay Sternberg } 154957dacad5SJay Sternberg 155057dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 155157dacad5SJay Sternberg { 15521c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 155357dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 155457dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1555e3e9d50cSKeith Busch 155638dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 155757dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 155857dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1559a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1560d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 156157dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 156257dacad5SJay Sternberg 156357dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 156457dacad5SJay Sternberg return -ENOMEM; 156534b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 156657dacad5SJay Sternberg 15671c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 15681c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 156957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 157057dacad5SJay Sternberg return -ENOMEM; 157157dacad5SJay Sternberg } 15721c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 157357dacad5SJay Sternberg nvme_dev_remove_admin(dev); 15741c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 157557dacad5SJay Sternberg return -ENODEV; 157657dacad5SJay Sternberg } 157757dacad5SJay Sternberg } else 1578c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 157957dacad5SJay Sternberg 158057dacad5SJay Sternberg return 0; 158157dacad5SJay Sternberg } 158257dacad5SJay Sternberg 158397f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 158497f6ef64SXu Yu { 158597f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 158697f6ef64SXu Yu } 158797f6ef64SXu Yu 158897f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 158997f6ef64SXu Yu { 159097f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 159197f6ef64SXu Yu 159297f6ef64SXu Yu if (size <= dev->bar_mapped_size) 159397f6ef64SXu Yu return 0; 159497f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 159597f6ef64SXu Yu return -ENOMEM; 159697f6ef64SXu Yu if (dev->bar) 159797f6ef64SXu Yu iounmap(dev->bar); 159897f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 159997f6ef64SXu Yu if (!dev->bar) { 160097f6ef64SXu Yu dev->bar_mapped_size = 0; 160197f6ef64SXu Yu return -ENOMEM; 160297f6ef64SXu Yu } 160397f6ef64SXu Yu dev->bar_mapped_size = size; 160497f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 160597f6ef64SXu Yu 160697f6ef64SXu Yu return 0; 160797f6ef64SXu Yu } 160897f6ef64SXu Yu 160901ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 161057dacad5SJay Sternberg { 161157dacad5SJay Sternberg int result; 161257dacad5SJay Sternberg u32 aqa; 161357dacad5SJay Sternberg struct nvme_queue *nvmeq; 161457dacad5SJay Sternberg 161597f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 161697f6ef64SXu Yu if (result < 0) 161797f6ef64SXu Yu return result; 161897f6ef64SXu Yu 16198ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 162020d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 162157dacad5SJay Sternberg 16227a67cbeaSChristoph Hellwig if (dev->subsystem && 16237a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16247a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 162557dacad5SJay Sternberg 162620d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 162757dacad5SJay Sternberg if (result < 0) 162857dacad5SJay Sternberg return result; 162957dacad5SJay Sternberg 1630a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1631147b27e4SSagi Grimberg if (result) 1632147b27e4SSagi Grimberg return result; 163357dacad5SJay Sternberg 1634147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 163557dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 163657dacad5SJay Sternberg aqa |= aqa << 16; 163757dacad5SJay Sternberg 16387a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16397a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16407a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 164157dacad5SJay Sternberg 164220d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 164357dacad5SJay Sternberg if (result) 1644d4875622SKeith Busch return result; 164557dacad5SJay Sternberg 164657dacad5SJay Sternberg nvmeq->cq_vector = 0; 1647161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1648dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 164957dacad5SJay Sternberg if (result) { 165057dacad5SJay Sternberg nvmeq->cq_vector = -1; 1651d4875622SKeith Busch return result; 165257dacad5SJay Sternberg } 165357dacad5SJay Sternberg 165457dacad5SJay Sternberg return result; 165557dacad5SJay Sternberg } 165657dacad5SJay Sternberg 1657749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 165857dacad5SJay Sternberg { 1659949928c1SKeith Busch unsigned i, max; 1660749941f2SChristoph Hellwig int ret = 0; 166157dacad5SJay Sternberg 1662d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1663a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1664749941f2SChristoph Hellwig ret = -ENOMEM; 166557dacad5SJay Sternberg break; 1666749941f2SChristoph Hellwig } 1667749941f2SChristoph Hellwig } 166857dacad5SJay Sternberg 1669d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1670949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1671147b27e4SSagi Grimberg ret = nvme_create_queue(&dev->queues[i], i); 1672d4875622SKeith Busch if (ret) 167357dacad5SJay Sternberg break; 167457dacad5SJay Sternberg } 167557dacad5SJay Sternberg 1676749941f2SChristoph Hellwig /* 1677749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 16788adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 16798adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1680749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1681749941f2SChristoph Hellwig */ 1682749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 168357dacad5SJay Sternberg } 168457dacad5SJay Sternberg 1685202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1686202021c1SStephen Bates struct device_attribute *attr, 1687202021c1SStephen Bates char *buf) 1688202021c1SStephen Bates { 1689202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1690202021c1SStephen Bates 1691c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1692202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1693202021c1SStephen Bates } 1694202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1695202021c1SStephen Bates 169688de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 169757dacad5SJay Sternberg { 169888de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 169988de4598SChristoph Hellwig 170088de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 170188de4598SChristoph Hellwig } 170288de4598SChristoph Hellwig 170388de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 170488de4598SChristoph Hellwig { 170588de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 170688de4598SChristoph Hellwig } 170788de4598SChristoph Hellwig 1708f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 170957dacad5SJay Sternberg { 171088de4598SChristoph Hellwig u64 size, offset; 171157dacad5SJay Sternberg resource_size_t bar_size; 171257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17138969f1f8SChristoph Hellwig int bar; 171457dacad5SJay Sternberg 17157a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1716f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1717f65efd6dSChristoph Hellwig return; 1718202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 171957dacad5SJay Sternberg 1720202021c1SStephen Bates if (!use_cmb_sqes) 1721f65efd6dSChristoph Hellwig return; 172257dacad5SJay Sternberg 172388de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 172488de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17258969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17268969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 172757dacad5SJay Sternberg 172857dacad5SJay Sternberg if (offset > bar_size) 1729f65efd6dSChristoph Hellwig return; 173057dacad5SJay Sternberg 173157dacad5SJay Sternberg /* 173257dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 173357dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 173457dacad5SJay Sternberg * the reported size of the BAR 173557dacad5SJay Sternberg */ 173657dacad5SJay Sternberg if (size > bar_size - offset) 173757dacad5SJay Sternberg size = bar_size - offset; 173857dacad5SJay Sternberg 1739f65efd6dSChristoph Hellwig dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); 1740f65efd6dSChristoph Hellwig if (!dev->cmb) 1741f65efd6dSChristoph Hellwig return; 17428969f1f8SChristoph Hellwig dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; 174357dacad5SJay Sternberg dev->cmb_size = size; 1744f65efd6dSChristoph Hellwig 1745f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1746f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1747f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1748f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 174957dacad5SJay Sternberg } 175057dacad5SJay Sternberg 175157dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 175257dacad5SJay Sternberg { 175357dacad5SJay Sternberg if (dev->cmb) { 175457dacad5SJay Sternberg iounmap(dev->cmb); 175557dacad5SJay Sternberg dev->cmb = NULL; 1756f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1757f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1758f63572dfSJon Derrick dev->cmbsz = 0; 1759f63572dfSJon Derrick } 176057dacad5SJay Sternberg } 176157dacad5SJay Sternberg 176287ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 176357dacad5SJay Sternberg { 17644033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 176587ad72a5SChristoph Hellwig struct nvme_command c; 176687ad72a5SChristoph Hellwig int ret; 176787ad72a5SChristoph Hellwig 176887ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 176987ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 177087ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 177187ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 177287ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 177387ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 177487ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 177587ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 177687ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 177787ad72a5SChristoph Hellwig 177887ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 177987ad72a5SChristoph Hellwig if (ret) { 178087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 178187ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 178287ad72a5SChristoph Hellwig ret, bits); 178387ad72a5SChristoph Hellwig } 178487ad72a5SChristoph Hellwig return ret; 178587ad72a5SChristoph Hellwig } 178687ad72a5SChristoph Hellwig 178787ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 178887ad72a5SChristoph Hellwig { 178987ad72a5SChristoph Hellwig int i; 179087ad72a5SChristoph Hellwig 179187ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 179287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 179387ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 179487ad72a5SChristoph Hellwig 179587ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 179687ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 179787ad72a5SChristoph Hellwig } 179887ad72a5SChristoph Hellwig 179987ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 180087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18014033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18024033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18034033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 180487ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18057e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 180687ad72a5SChristoph Hellwig } 180787ad72a5SChristoph Hellwig 180892dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 180992dc6895SChristoph Hellwig u32 chunk_size) 181087ad72a5SChristoph Hellwig { 181187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 181292dc6895SChristoph Hellwig u32 max_entries, len; 18134033f35dSChristoph Hellwig dma_addr_t descs_dma; 18142ee0e4edSDan Carpenter int i = 0; 181587ad72a5SChristoph Hellwig void **bufs; 18166fbcde66SMinwoo Im u64 size, tmp; 181787ad72a5SChristoph Hellwig 181887ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 181987ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 182087ad72a5SChristoph Hellwig max_entries = tmp; 1821044a9df1SChristoph Hellwig 1822044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1823044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1824044a9df1SChristoph Hellwig 18254033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 18264033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 182787ad72a5SChristoph Hellwig if (!descs) 182887ad72a5SChristoph Hellwig goto out; 182987ad72a5SChristoph Hellwig 183087ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 183187ad72a5SChristoph Hellwig if (!bufs) 183287ad72a5SChristoph Hellwig goto out_free_descs; 183387ad72a5SChristoph Hellwig 1834244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 183587ad72a5SChristoph Hellwig dma_addr_t dma_addr; 183687ad72a5SChristoph Hellwig 183750cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 183887ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 183987ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 184087ad72a5SChristoph Hellwig if (!bufs[i]) 184187ad72a5SChristoph Hellwig break; 184287ad72a5SChristoph Hellwig 184387ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 184487ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 184587ad72a5SChristoph Hellwig i++; 184687ad72a5SChristoph Hellwig } 184787ad72a5SChristoph Hellwig 184892dc6895SChristoph Hellwig if (!size) 184987ad72a5SChristoph Hellwig goto out_free_bufs; 185087ad72a5SChristoph Hellwig 185187ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 185287ad72a5SChristoph Hellwig dev->host_mem_size = size; 185387ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 18544033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 185587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 185687ad72a5SChristoph Hellwig return 0; 185787ad72a5SChristoph Hellwig 185887ad72a5SChristoph Hellwig out_free_bufs: 185987ad72a5SChristoph Hellwig while (--i >= 0) { 186087ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 186187ad72a5SChristoph Hellwig 186287ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 186387ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 186487ad72a5SChristoph Hellwig } 186587ad72a5SChristoph Hellwig 186687ad72a5SChristoph Hellwig kfree(bufs); 186787ad72a5SChristoph Hellwig out_free_descs: 18684033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 18694033f35dSChristoph Hellwig descs_dma); 187087ad72a5SChristoph Hellwig out: 187187ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 187287ad72a5SChristoph Hellwig return -ENOMEM; 187387ad72a5SChristoph Hellwig } 187487ad72a5SChristoph Hellwig 187592dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 187692dc6895SChristoph Hellwig { 187792dc6895SChristoph Hellwig u32 chunk_size; 187892dc6895SChristoph Hellwig 187992dc6895SChristoph Hellwig /* start big and work our way down */ 188030f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1881044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 188292dc6895SChristoph Hellwig chunk_size /= 2) { 188392dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 188492dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 188592dc6895SChristoph Hellwig return 0; 188692dc6895SChristoph Hellwig nvme_free_host_mem(dev); 188792dc6895SChristoph Hellwig } 188892dc6895SChristoph Hellwig } 188992dc6895SChristoph Hellwig 189092dc6895SChristoph Hellwig return -ENOMEM; 189192dc6895SChristoph Hellwig } 189292dc6895SChristoph Hellwig 18939620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 189487ad72a5SChristoph Hellwig { 189587ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 189687ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 189787ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 189887ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 18996fbcde66SMinwoo Im int ret; 190087ad72a5SChristoph Hellwig 190187ad72a5SChristoph Hellwig preferred = min(preferred, max); 190287ad72a5SChristoph Hellwig if (min > max) { 190387ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 190487ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 190587ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 190687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19079620cfbaSChristoph Hellwig return 0; 190887ad72a5SChristoph Hellwig } 190987ad72a5SChristoph Hellwig 191087ad72a5SChristoph Hellwig /* 191187ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 191287ad72a5SChristoph Hellwig */ 191387ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 191487ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 191587ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 191687ad72a5SChristoph Hellwig else 191787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 191887ad72a5SChristoph Hellwig } 191987ad72a5SChristoph Hellwig 192087ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 192192dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 192292dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 192392dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 19249620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 192587ad72a5SChristoph Hellwig } 192687ad72a5SChristoph Hellwig 192792dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 192892dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 192992dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 193092dc6895SChristoph Hellwig } 193192dc6895SChristoph Hellwig 19329620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 19339620cfbaSChristoph Hellwig if (ret) 193487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19359620cfbaSChristoph Hellwig return ret; 193657dacad5SJay Sternberg } 193757dacad5SJay Sternberg 193857dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 193957dacad5SJay Sternberg { 1940147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 194157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 194297f6ef64SXu Yu int result, nr_io_queues; 194397f6ef64SXu Yu unsigned long size; 194457dacad5SJay Sternberg 194522b55601SKeith Busch struct irq_affinity affd = { 194622b55601SKeith Busch .pre_vectors = 1 194722b55601SKeith Busch }; 194822b55601SKeith Busch 194916ccfff2SMing Lei nr_io_queues = num_possible_cpus(); 19509a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 19519a0be7abSChristoph Hellwig if (result < 0) 195257dacad5SJay Sternberg return result; 19539a0be7abSChristoph Hellwig 1954f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1955a5229050SKeith Busch return 0; 195657dacad5SJay Sternberg 195788de4598SChristoph Hellwig if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) { 195857dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 195957dacad5SJay Sternberg sizeof(struct nvme_command)); 196057dacad5SJay Sternberg if (result > 0) 196157dacad5SJay Sternberg dev->q_depth = result; 196257dacad5SJay Sternberg else 196357dacad5SJay Sternberg nvme_release_cmb(dev); 196457dacad5SJay Sternberg } 196557dacad5SJay Sternberg 196657dacad5SJay Sternberg do { 196797f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 196897f6ef64SXu Yu result = nvme_remap_bar(dev, size); 196997f6ef64SXu Yu if (!result) 197057dacad5SJay Sternberg break; 197157dacad5SJay Sternberg if (!--nr_io_queues) 197257dacad5SJay Sternberg return -ENOMEM; 197357dacad5SJay Sternberg } while (1); 197457dacad5SJay Sternberg adminq->q_db = dev->dbs; 197557dacad5SJay Sternberg 197657dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 19770ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 197857dacad5SJay Sternberg 197957dacad5SJay Sternberg /* 198057dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 198157dacad5SJay Sternberg * setting up the full range we need. 198257dacad5SJay Sternberg */ 1983dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 198422b55601SKeith Busch result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1, 198522b55601SKeith Busch PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 198622b55601SKeith Busch if (result <= 0) 1987dca51e78SChristoph Hellwig return -EIO; 198822b55601SKeith Busch dev->num_vecs = result; 198922b55601SKeith Busch dev->max_qid = max(result - 1, 1); 199057dacad5SJay Sternberg 199157dacad5SJay Sternberg /* 199257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 199357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 199457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 199557dacad5SJay Sternberg * number of interrupts. 199657dacad5SJay Sternberg */ 199757dacad5SJay Sternberg 1998dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 199957dacad5SJay Sternberg if (result) { 200057dacad5SJay Sternberg adminq->cq_vector = -1; 2001d4875622SKeith Busch return result; 200257dacad5SJay Sternberg } 2003749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 200457dacad5SJay Sternberg } 200557dacad5SJay Sternberg 20062a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2007db3cbfffSKeith Busch { 2008db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2009db3cbfffSKeith Busch 2010db3cbfffSKeith Busch blk_mq_free_request(req); 2011db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 2012db3cbfffSKeith Busch } 2013db3cbfffSKeith Busch 20142a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2015db3cbfffSKeith Busch { 2016db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 20175cb525c8SJens Axboe u16 start, end; 2018db3cbfffSKeith Busch 2019db3cbfffSKeith Busch if (!error) { 2020db3cbfffSKeith Busch unsigned long flags; 2021db3cbfffSKeith Busch 20220bc88192SKeith Busch spin_lock_irqsave(&nvmeq->cq_lock, flags); 20235cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 20241ab0cd69SJens Axboe spin_unlock_irqrestore(&nvmeq->cq_lock, flags); 20255cb525c8SJens Axboe 20265cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 2027db3cbfffSKeith Busch } 2028db3cbfffSKeith Busch 2029db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2030db3cbfffSKeith Busch } 2031db3cbfffSKeith Busch 2032db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2033db3cbfffSKeith Busch { 2034db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2035db3cbfffSKeith Busch struct request *req; 2036db3cbfffSKeith Busch struct nvme_command cmd; 2037db3cbfffSKeith Busch 2038db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2039db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2040db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2041db3cbfffSKeith Busch 2042eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2043db3cbfffSKeith Busch if (IS_ERR(req)) 2044db3cbfffSKeith Busch return PTR_ERR(req); 2045db3cbfffSKeith Busch 2046db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2047db3cbfffSKeith Busch req->end_io_data = nvmeq; 2048db3cbfffSKeith Busch 2049db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2050db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2051db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2052db3cbfffSKeith Busch return 0; 2053db3cbfffSKeith Busch } 2054db3cbfffSKeith Busch 2055ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 2056db3cbfffSKeith Busch { 2057ee9aebb2SKeith Busch int pass, queues = dev->online_queues - 1; 2058db3cbfffSKeith Busch unsigned long timeout; 2059db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2060db3cbfffSKeith Busch 2061db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2062014a0d60SKeith Busch int sent = 0, i = queues; 2063db3cbfffSKeith Busch 2064db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2065db3cbfffSKeith Busch retry: 2066db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2067c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2068147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2069db3cbfffSKeith Busch break; 2070c21377f8SGabriel Krisman Bertazi 2071db3cbfffSKeith Busch while (sent--) { 2072db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2073db3cbfffSKeith Busch if (timeout == 0) 2074db3cbfffSKeith Busch return; 2075db3cbfffSKeith Busch if (i) 2076db3cbfffSKeith Busch goto retry; 2077db3cbfffSKeith Busch } 2078db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2079db3cbfffSKeith Busch } 2080db3cbfffSKeith Busch } 2081db3cbfffSKeith Busch 208257dacad5SJay Sternberg /* 20832b1b7e78SJianchao Wang * return error value only when tagset allocation failed 208457dacad5SJay Sternberg */ 208557dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 208657dacad5SJay Sternberg { 20872b1b7e78SJianchao Wang int ret; 20882b1b7e78SJianchao Wang 20895bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 209057dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 209157dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 209257dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 209357dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 209457dacad5SJay Sternberg dev->tagset.queue_depth = 209557dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2096a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2097a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2098a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2099a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2100a7a7cbe3SChaitanya Kulkarni } 210157dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 210257dacad5SJay Sternberg dev->tagset.driver_data = dev; 210357dacad5SJay Sternberg 21042b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 21052b1b7e78SJianchao Wang if (ret) { 21062b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 21072b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 21082b1b7e78SJianchao Wang return ret; 21092b1b7e78SJianchao Wang } 21105bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2111f9f38e33SHelen Koike 2112f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2113949928c1SKeith Busch } else { 2114949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2115949928c1SKeith Busch 2116949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2117949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 211857dacad5SJay Sternberg } 2119949928c1SKeith Busch 212057dacad5SJay Sternberg return 0; 212157dacad5SJay Sternberg } 212257dacad5SJay Sternberg 2123b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 212457dacad5SJay Sternberg { 2125b00a726aSKeith Busch int result = -ENOMEM; 212657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 212757dacad5SJay Sternberg 212857dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 212957dacad5SJay Sternberg return result; 213057dacad5SJay Sternberg 213157dacad5SJay Sternberg pci_set_master(pdev); 213257dacad5SJay Sternberg 213357dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 213457dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 213557dacad5SJay Sternberg goto disable; 213657dacad5SJay Sternberg 21377a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 213857dacad5SJay Sternberg result = -ENODEV; 2139b00a726aSKeith Busch goto disable; 214057dacad5SJay Sternberg } 214157dacad5SJay Sternberg 214257dacad5SJay Sternberg /* 2143a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2144a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2145a5229050SKeith Busch * adjust this later. 214657dacad5SJay Sternberg */ 2147dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2148dca51e78SChristoph Hellwig if (result < 0) 2149dca51e78SChristoph Hellwig return result; 215057dacad5SJay Sternberg 215120d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 21527a67cbeaSChristoph Hellwig 215320d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2154b27c1e68Sweiping zhang io_queue_depth); 215520d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 21567a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 21571f390c1fSStephan Günther 21581f390c1fSStephan Günther /* 21591f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 21601f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 21611f390c1fSStephan Günther */ 21621f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 21631f390c1fSStephan Günther dev->q_depth = 2; 21649bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 21659bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 21661f390c1fSStephan Günther dev->q_depth); 2167d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2168d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 216920d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2170d554b5e1SMartin K. Petersen dev->q_depth = 64; 2171d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2172d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 21731f390c1fSStephan Günther } 21741f390c1fSStephan Günther 2175f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2176202021c1SStephen Bates 2177a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2178a0a3408eSKeith Busch pci_save_state(pdev); 217957dacad5SJay Sternberg return 0; 218057dacad5SJay Sternberg 218157dacad5SJay Sternberg disable: 218257dacad5SJay Sternberg pci_disable_device(pdev); 218357dacad5SJay Sternberg return result; 218457dacad5SJay Sternberg } 218557dacad5SJay Sternberg 218657dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 218757dacad5SJay Sternberg { 2188b00a726aSKeith Busch if (dev->bar) 2189b00a726aSKeith Busch iounmap(dev->bar); 2190a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2191b00a726aSKeith Busch } 2192b00a726aSKeith Busch 2193b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2194b00a726aSKeith Busch { 219557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 219657dacad5SJay Sternberg 2197f63572dfSJon Derrick nvme_release_cmb(dev); 2198dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 219957dacad5SJay Sternberg 2200a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2201a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 220257dacad5SJay Sternberg pci_disable_device(pdev); 220357dacad5SJay Sternberg } 2204a0a3408eSKeith Busch } 220557dacad5SJay Sternberg 2206a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 220757dacad5SJay Sternberg { 2208ee9aebb2SKeith Busch int i; 2209302ad8ccSKeith Busch bool dead = true; 2210302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 221157dacad5SJay Sternberg 221277bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2213302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2214302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2215302ad8ccSKeith Busch 2216ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2217ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2218302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2219302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2220302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 222157dacad5SJay Sternberg } 2222c21377f8SGabriel Krisman Bertazi 2223302ad8ccSKeith Busch /* 2224302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2225302ad8ccSKeith Busch * doing a safe shutdown. 2226302ad8ccSKeith Busch */ 222787ad72a5SChristoph Hellwig if (!dead) { 222887ad72a5SChristoph Hellwig if (shutdown) 2229302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 22309a915a5bSJianchao Wang } 223187ad72a5SChristoph Hellwig 22329a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 22339a915a5bSJianchao Wang 223464ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 2235ee9aebb2SKeith Busch nvme_disable_io_queues(dev); 2236a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 223757dacad5SJay Sternberg } 2238ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2239ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2240ee9aebb2SKeith Busch 2241b00a726aSKeith Busch nvme_pci_disable(dev); 224257dacad5SJay Sternberg 2243e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2244e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2245302ad8ccSKeith Busch 2246302ad8ccSKeith Busch /* 2247302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2248302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2249302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2250302ad8ccSKeith Busch */ 2251302ad8ccSKeith Busch if (shutdown) 2252302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 225377bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 225457dacad5SJay Sternberg } 225557dacad5SJay Sternberg 225657dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 225757dacad5SJay Sternberg { 225857dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 225957dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 226057dacad5SJay Sternberg if (!dev->prp_page_pool) 226157dacad5SJay Sternberg return -ENOMEM; 226257dacad5SJay Sternberg 226357dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 226457dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 226557dacad5SJay Sternberg 256, 256, 0); 226657dacad5SJay Sternberg if (!dev->prp_small_pool) { 226757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 226857dacad5SJay Sternberg return -ENOMEM; 226957dacad5SJay Sternberg } 227057dacad5SJay Sternberg return 0; 227157dacad5SJay Sternberg } 227257dacad5SJay Sternberg 227357dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 227457dacad5SJay Sternberg { 227557dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 227657dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 227757dacad5SJay Sternberg } 227857dacad5SJay Sternberg 22791673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 228057dacad5SJay Sternberg { 22811673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 228257dacad5SJay Sternberg 2283f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 228457dacad5SJay Sternberg put_device(dev->dev); 228557dacad5SJay Sternberg if (dev->tagset.tags) 228657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 22871c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 22881c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 228957dacad5SJay Sternberg kfree(dev->queues); 2290e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2291943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 229257dacad5SJay Sternberg kfree(dev); 229357dacad5SJay Sternberg } 229457dacad5SJay Sternberg 2295f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2296f58944e2SKeith Busch { 2297237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2298f58944e2SKeith Busch 2299d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 230069d9a99cSKeith Busch nvme_dev_disable(dev, false); 23019f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 230203e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2303f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2304f58944e2SKeith Busch } 2305f58944e2SKeith Busch 2306fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 230757dacad5SJay Sternberg { 2308d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2309d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2310a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2311f58944e2SKeith Busch int result = -ENODEV; 23122b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 231357dacad5SJay Sternberg 231482b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2315fd634f41SChristoph Hellwig goto out; 2316fd634f41SChristoph Hellwig 2317fd634f41SChristoph Hellwig /* 2318fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2319fd634f41SChristoph Hellwig * moving on. 2320fd634f41SChristoph Hellwig */ 2321b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2322a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2323fd634f41SChristoph Hellwig 2324ad70062cSJianchao Wang /* 2325ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2326ad70062cSJianchao Wang * initializing procedure here. 2327ad70062cSJianchao Wang */ 2328ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2329ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2330ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2331ad70062cSJianchao Wang goto out; 2332ad70062cSJianchao Wang } 2333ad70062cSJianchao Wang 2334b00a726aSKeith Busch result = nvme_pci_enable(dev); 233557dacad5SJay Sternberg if (result) 233657dacad5SJay Sternberg goto out; 233757dacad5SJay Sternberg 233801ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 233957dacad5SJay Sternberg if (result) 2340f58944e2SKeith Busch goto out; 234157dacad5SJay Sternberg 234257dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 234357dacad5SJay Sternberg if (result) 2344f58944e2SKeith Busch goto out; 234557dacad5SJay Sternberg 2346943e942eSJens Axboe /* 2347943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2348943e942eSJens Axboe * over a single page. 2349943e942eSJens Axboe */ 2350943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2351943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2352943e942eSJens Axboe 2353ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2354ce4541f4SChristoph Hellwig if (result) 2355f58944e2SKeith Busch goto out; 2356ce4541f4SChristoph Hellwig 2357e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2358e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 23594f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 23604f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2361e286bcfcSScott Bauer else if (was_suspend) 23624f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2363e286bcfcSScott Bauer } else { 2364e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2365e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2366e286bcfcSScott Bauer } 2367a98e58e5SScott Bauer 2368f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2369f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2370f9f38e33SHelen Koike if (result) 2371f9f38e33SHelen Koike dev_warn(dev->dev, 2372f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2373f9f38e33SHelen Koike } 2374f9f38e33SHelen Koike 23759620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 23769620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 23779620cfbaSChristoph Hellwig if (result < 0) 23789620cfbaSChristoph Hellwig goto out; 23799620cfbaSChristoph Hellwig } 238087ad72a5SChristoph Hellwig 238157dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 238257dacad5SJay Sternberg if (result) 2383f58944e2SKeith Busch goto out; 238457dacad5SJay Sternberg 238521f033f7SKeith Busch /* 238657dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 238757dacad5SJay Sternberg * any working I/O queue. 238857dacad5SJay Sternberg */ 238957dacad5SJay Sternberg if (dev->online_queues < 2) { 23901b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 23913b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 23925bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 23932b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 239457dacad5SJay Sternberg } else { 239525646264SKeith Busch nvme_start_queues(&dev->ctrl); 2396302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 23972b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 23982b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 23992b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2400302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 240157dacad5SJay Sternberg } 240257dacad5SJay Sternberg 24032b1b7e78SJianchao Wang /* 24042b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 24052b1b7e78SJianchao Wang * recovery. 24062b1b7e78SJianchao Wang */ 24072b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 24082b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 24092b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2410bb8d261eSChristoph Hellwig goto out; 2411bb8d261eSChristoph Hellwig } 241292911a55SChristoph Hellwig 2413d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 241457dacad5SJay Sternberg return; 241557dacad5SJay Sternberg 241657dacad5SJay Sternberg out: 2417f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 241857dacad5SJay Sternberg } 241957dacad5SJay Sternberg 24205c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 242157dacad5SJay Sternberg { 24225c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 242357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 242457dacad5SJay Sternberg 242557dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2426921920abSKeith Busch device_release_driver(&pdev->dev); 24271673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 242857dacad5SJay Sternberg } 242957dacad5SJay Sternberg 24301c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 243157dacad5SJay Sternberg { 24321c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 24331c63dc66SChristoph Hellwig return 0; 243457dacad5SJay Sternberg } 24351c63dc66SChristoph Hellwig 24365fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 24375fd4ce1bSChristoph Hellwig { 24385fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 24395fd4ce1bSChristoph Hellwig return 0; 24405fd4ce1bSChristoph Hellwig } 24415fd4ce1bSChristoph Hellwig 24427fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 24437fd8930fSChristoph Hellwig { 24447fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 24457fd8930fSChristoph Hellwig return 0; 24467fd8930fSChristoph Hellwig } 24477fd8930fSChristoph Hellwig 244897c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 244997c12223SKeith Busch { 245097c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 245197c12223SKeith Busch 245297c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 245397c12223SKeith Busch } 245497c12223SKeith Busch 24551c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 24561a353d85SMing Lin .name = "pcie", 2457e439bb12SSagi Grimberg .module = THIS_MODULE, 2458c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 24591c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 24605fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 24617fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 24621673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2463f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 246497c12223SKeith Busch .get_address = nvme_pci_get_address, 24651c63dc66SChristoph Hellwig }; 246657dacad5SJay Sternberg 2467b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2468b00a726aSKeith Busch { 2469b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2470b00a726aSKeith Busch 2471a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2472b00a726aSKeith Busch return -ENODEV; 2473b00a726aSKeith Busch 247497f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2475b00a726aSKeith Busch goto release; 2476b00a726aSKeith Busch 2477b00a726aSKeith Busch return 0; 2478b00a726aSKeith Busch release: 2479a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2480b00a726aSKeith Busch return -ENODEV; 2481b00a726aSKeith Busch } 2482b00a726aSKeith Busch 24838427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2484ff5350a8SAndy Lutomirski { 2485ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2486ff5350a8SAndy Lutomirski /* 2487ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2488ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2489ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2490ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2491ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2492ff5350a8SAndy Lutomirski * laptops. 2493ff5350a8SAndy Lutomirski */ 2494ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2495ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2496ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2497ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 24988427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 24998427bbc2SKai-Heng Feng /* 25008427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2501467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2502467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2503467c77d4SJarosław Janik * ASUS PRIME Z370-A 25048427bbc2SKai-Heng Feng */ 25058427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2506467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2507467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 25088427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2509ff5350a8SAndy Lutomirski } 2510ff5350a8SAndy Lutomirski 2511ff5350a8SAndy Lutomirski return 0; 2512ff5350a8SAndy Lutomirski } 2513ff5350a8SAndy Lutomirski 251418119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 251518119775SKeith Busch { 251618119775SKeith Busch struct nvme_dev *dev = data; 251780f513b5SKeith Busch 251818119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 251918119775SKeith Busch flush_work(&dev->ctrl.scan_work); 252080f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 252118119775SKeith Busch } 252218119775SKeith Busch 252357dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 252457dacad5SJay Sternberg { 252557dacad5SJay Sternberg int node, result = -ENOMEM; 252657dacad5SJay Sternberg struct nvme_dev *dev; 2527ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2528943e942eSJens Axboe size_t alloc_size; 252957dacad5SJay Sternberg 253057dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 253157dacad5SJay Sternberg if (node == NUMA_NO_NODE) 25322fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 253357dacad5SJay Sternberg 253457dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 253557dacad5SJay Sternberg if (!dev) 253657dacad5SJay Sternberg return -ENOMEM; 2537147b27e4SSagi Grimberg 2538147b27e4SSagi Grimberg dev->queues = kcalloc_node(num_possible_cpus() + 1, 2539147b27e4SSagi Grimberg sizeof(struct nvme_queue), GFP_KERNEL, node); 254057dacad5SJay Sternberg if (!dev->queues) 254157dacad5SJay Sternberg goto free; 254257dacad5SJay Sternberg 254357dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 254457dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 254557dacad5SJay Sternberg 2546b00a726aSKeith Busch result = nvme_dev_map(dev); 2547b00a726aSKeith Busch if (result) 2548b00c9b7aSChristophe JAILLET goto put_pci; 2549b00a726aSKeith Busch 2550d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 25515c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 255277bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2553db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2554f3ca80fcSChristoph Hellwig 2555f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2556f3ca80fcSChristoph Hellwig if (result) 2557b00c9b7aSChristophe JAILLET goto unmap; 2558f3ca80fcSChristoph Hellwig 25598427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2560ff5350a8SAndy Lutomirski 2561f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2562ff5350a8SAndy Lutomirski quirks); 2563f3ca80fcSChristoph Hellwig if (result) 2564f3ca80fcSChristoph Hellwig goto release_pools; 2565f3ca80fcSChristoph Hellwig 2566943e942eSJens Axboe /* 2567943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2568943e942eSJens Axboe * command we support. 2569943e942eSJens Axboe */ 2570943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2571943e942eSJens Axboe NVME_MAX_SEGS, true); 2572943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2573943e942eSJens Axboe 2574943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2575943e942eSJens Axboe mempool_kfree, 2576943e942eSJens Axboe (void *) alloc_size, 2577943e942eSJens Axboe GFP_KERNEL, node); 2578943e942eSJens Axboe if (!dev->iod_mempool) { 2579943e942eSJens Axboe result = -ENOMEM; 2580943e942eSJens Axboe goto release_pools; 2581943e942eSJens Axboe } 2582943e942eSJens Axboe 25831b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 25841b3c47c1SSagi Grimberg 258580f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 258618119775SKeith Busch async_schedule(nvme_async_probe, dev); 25874caff8fcSSagi Grimberg 258857dacad5SJay Sternberg return 0; 258957dacad5SJay Sternberg 259057dacad5SJay Sternberg release_pools: 259157dacad5SJay Sternberg nvme_release_prp_pools(dev); 2592b00c9b7aSChristophe JAILLET unmap: 2593b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 259457dacad5SJay Sternberg put_pci: 259557dacad5SJay Sternberg put_device(dev->dev); 259657dacad5SJay Sternberg free: 259757dacad5SJay Sternberg kfree(dev->queues); 259857dacad5SJay Sternberg kfree(dev); 259957dacad5SJay Sternberg return result; 260057dacad5SJay Sternberg } 260157dacad5SJay Sternberg 2602775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 260357dacad5SJay Sternberg { 260457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2605a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2606775755edSChristoph Hellwig } 260757dacad5SJay Sternberg 2608775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2609775755edSChristoph Hellwig { 2610f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 261179c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 261257dacad5SJay Sternberg } 261357dacad5SJay Sternberg 261457dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 261557dacad5SJay Sternberg { 261657dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2617a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 261857dacad5SJay Sternberg } 261957dacad5SJay Sternberg 2620f58944e2SKeith Busch /* 2621f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2622f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2623f58944e2SKeith Busch * order to proceed. 2624f58944e2SKeith Busch */ 262557dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 262657dacad5SJay Sternberg { 262757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 262857dacad5SJay Sternberg 2629bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2630bb8d261eSChristoph Hellwig 2631d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 263257dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 26330ff9d4e1SKeith Busch 26346db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 26350ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 26361d39e692SKeith Busch nvme_dev_disable(dev, true); 26376db28edaSKeith Busch } 26380ff9d4e1SKeith Busch 2639d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2640d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2641d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2642a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 264387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 264457dacad5SJay Sternberg nvme_dev_remove_admin(dev); 264557dacad5SJay Sternberg nvme_free_queues(dev, 0); 2646d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 264757dacad5SJay Sternberg nvme_release_prp_pools(dev); 2648b00a726aSKeith Busch nvme_dev_unmap(dev); 26491673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 265057dacad5SJay Sternberg } 265157dacad5SJay Sternberg 265257dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 265357dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 265457dacad5SJay Sternberg { 265557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 265657dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 265757dacad5SJay Sternberg 2658a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 265957dacad5SJay Sternberg return 0; 266057dacad5SJay Sternberg } 266157dacad5SJay Sternberg 266257dacad5SJay Sternberg static int nvme_resume(struct device *dev) 266357dacad5SJay Sternberg { 266457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 266557dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 266657dacad5SJay Sternberg 2667d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 266857dacad5SJay Sternberg return 0; 266957dacad5SJay Sternberg } 267057dacad5SJay Sternberg #endif 267157dacad5SJay Sternberg 267257dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 267357dacad5SJay Sternberg 2674a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2675a0a3408eSKeith Busch pci_channel_state_t state) 2676a0a3408eSKeith Busch { 2677a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2678a0a3408eSKeith Busch 2679a0a3408eSKeith Busch /* 2680a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2681a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2682a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2683a0a3408eSKeith Busch */ 2684a0a3408eSKeith Busch switch (state) { 2685a0a3408eSKeith Busch case pci_channel_io_normal: 2686a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2687a0a3408eSKeith Busch case pci_channel_io_frozen: 2688d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2689d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2690a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2691a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2692a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2693d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2694d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2695a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2696a0a3408eSKeith Busch } 2697a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2698a0a3408eSKeith Busch } 2699a0a3408eSKeith Busch 2700a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2701a0a3408eSKeith Busch { 2702a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2703a0a3408eSKeith Busch 27041b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2705a0a3408eSKeith Busch pci_restore_state(pdev); 2706d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2707a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2708a0a3408eSKeith Busch } 2709a0a3408eSKeith Busch 2710a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2711a0a3408eSKeith Busch { 271272cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 271372cd4cc2SKeith Busch 271472cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2715a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2716a0a3408eSKeith Busch } 2717a0a3408eSKeith Busch 271857dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 271957dacad5SJay Sternberg .error_detected = nvme_error_detected, 272057dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 272157dacad5SJay Sternberg .resume = nvme_error_resume, 2722775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2723775755edSChristoph Hellwig .reset_done = nvme_reset_done, 272457dacad5SJay Sternberg }; 272557dacad5SJay Sternberg 272657dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2727106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 272808095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2729e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 273099466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 273199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2732e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 273399466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 273499466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2735e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2736f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2737f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2738f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 273950af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 27409abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 27419abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 2742540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2743540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 27440302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 27450302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 274654adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 274754adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 27488c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 27498c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2750015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2751015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2752d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2753d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2754d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2755d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2756608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2757608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2758608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2759608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2760ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2761ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 276257dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2763c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2764124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 276557dacad5SJay Sternberg { 0, } 276657dacad5SJay Sternberg }; 276757dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 276857dacad5SJay Sternberg 276957dacad5SJay Sternberg static struct pci_driver nvme_driver = { 277057dacad5SJay Sternberg .name = "nvme", 277157dacad5SJay Sternberg .id_table = nvme_id_table, 277257dacad5SJay Sternberg .probe = nvme_probe, 277357dacad5SJay Sternberg .remove = nvme_remove, 277457dacad5SJay Sternberg .shutdown = nvme_shutdown, 277557dacad5SJay Sternberg .driver = { 277657dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 277757dacad5SJay Sternberg }, 277874d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 277957dacad5SJay Sternberg .err_handler = &nvme_err_handler, 278057dacad5SJay Sternberg }; 278157dacad5SJay Sternberg 278257dacad5SJay Sternberg static int __init nvme_init(void) 278357dacad5SJay Sternberg { 27849a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 278557dacad5SJay Sternberg } 278657dacad5SJay Sternberg 278757dacad5SJay Sternberg static void __exit nvme_exit(void) 278857dacad5SJay Sternberg { 278957dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 279003e0f3a6SMing Lei flush_workqueue(nvme_wq); 279157dacad5SJay Sternberg _nvme_check_size(); 279257dacad5SJay Sternberg } 279357dacad5SJay Sternberg 279457dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 279557dacad5SJay Sternberg MODULE_LICENSE("GPL"); 279657dacad5SJay Sternberg MODULE_VERSION("1.0"); 279757dacad5SJay Sternberg module_init(nvme_init); 279857dacad5SJay Sternberg module_exit(nvme_exit); 2799