15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 18dc90f084SChristoph Hellwig #include <linux/memremap.h> 1957dacad5SJay Sternberg #include <linux/mm.h> 2057dacad5SJay Sternberg #include <linux/module.h> 2177bf25eaSKeith Busch #include <linux/mutex.h> 22d0877473SKeith Busch #include <linux/once.h> 2357dacad5SJay Sternberg #include <linux/pci.h> 24d916b1beSKeith Busch #include <linux/suspend.h> 2557dacad5SJay Sternberg #include <linux/t10-pi.h> 2657dacad5SJay Sternberg #include <linux/types.h> 279cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2820d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 29a98e58e5SScott Bauer #include <linux/sed-opal.h> 300f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3157dacad5SJay Sternberg 32604c01d5Syupeng #include "trace.h" 3357dacad5SJay Sternberg #include "nvme.h" 3457dacad5SJay Sternberg 35c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 368a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3757dacad5SJay Sternberg 38a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39adf68f21SChristoph Hellwig 40943e942eSJens Axboe /* 41943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 42943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 43943e942eSJens Axboe */ 44943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 45943e942eSJens Axboe #define NVME_MAX_SEGS 127 46943e942eSJens Axboe 4757dacad5SJay Sternberg static int use_threaded_interrupts; 482e21e445SXin Hao module_param(use_threaded_interrupts, int, 0444); 4957dacad5SJay Sternberg 5057dacad5SJay Sternberg static bool use_cmb_sqes = true; 5169f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5257dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5357dacad5SJay Sternberg 5487ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5587ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5687ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5787ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5857dacad5SJay Sternberg 59a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 60a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 61a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 62a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 63a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 64a7a7cbe3SChaitanya Kulkarni 6527453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6627453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 7061f3b896SChaitanya Kulkarni .get = param_get_uint, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 7361f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7527453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 76b27c1e68Sweiping zhang 779c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 789c9e76d5SWeiping Zhang { 799c9e76d5SWeiping Zhang unsigned int n; 809c9e76d5SWeiping Zhang int ret; 819c9e76d5SWeiping Zhang 829c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 839c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 849c9e76d5SWeiping Zhang return -EINVAL; 859c9e76d5SWeiping Zhang return param_set_uint(val, kp); 869c9e76d5SWeiping Zhang } 879c9e76d5SWeiping Zhang 889c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 899c9e76d5SWeiping Zhang .set = io_queue_count_set, 909c9e76d5SWeiping Zhang .get = param_get_uint, 919c9e76d5SWeiping Zhang }; 929c9e76d5SWeiping Zhang 933f68baf7SKeith Busch static unsigned int write_queues; 949c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 953b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 963b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 973b6592f7SJens Axboe "will share a queue set."); 983b6592f7SJens Axboe 993f68baf7SKeith Busch static unsigned int poll_queues; 1009c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1014b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1024b04cc6aSJens Axboe 103df4f9bc4SDavid E. Box static bool noacpi; 104df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 105df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 106df4f9bc4SDavid E. Box 1071c63dc66SChristoph Hellwig struct nvme_dev; 1081c63dc66SChristoph Hellwig struct nvme_queue; 10957dacad5SJay Sternberg 110a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1118fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11257dacad5SJay Sternberg 11357dacad5SJay Sternberg /* 1141c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1151c63dc66SChristoph Hellwig */ 1161c63dc66SChristoph Hellwig struct nvme_dev { 117147b27e4SSagi Grimberg struct nvme_queue *queues; 1181c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1191c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1201c63dc66SChristoph Hellwig u32 __iomem *dbs; 1211c63dc66SChristoph Hellwig struct device *dev; 1221c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1231c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1241c63dc66SChristoph Hellwig unsigned online_queues; 1251c63dc66SChristoph Hellwig unsigned max_qid; 126e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12722b55601SKeith Busch unsigned int num_vecs; 1287442ddceSJohn Garry u32 q_depth; 129c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1301c63dc66SChristoph Hellwig u32 db_stride; 1311c63dc66SChristoph Hellwig void __iomem *bar; 13297f6ef64SXu Yu unsigned long bar_mapped_size; 1335c8809e6SChristoph Hellwig struct work_struct remove_work; 13477bf25eaSKeith Busch struct mutex shutdown_lock; 1351c63dc66SChristoph Hellwig bool subsystem; 1361c63dc66SChristoph Hellwig u64 cmb_size; 1370f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1381c63dc66SChristoph Hellwig u32 cmbsz; 139202021c1SStephen Bates u32 cmbloc; 1401c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 141d916b1beSKeith Busch u32 last_ps; 142a5df5e79SKeith Busch bool hmb; 14387ad72a5SChristoph Hellwig 144943e942eSJens Axboe mempool_t *iod_mempool; 145943e942eSJens Axboe 14687ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 147f9f38e33SHelen Koike u32 *dbbuf_dbs; 148f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 149f9f38e33SHelen Koike u32 *dbbuf_eis; 150f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15187ad72a5SChristoph Hellwig 15287ad72a5SChristoph Hellwig /* host memory buffer support: */ 15387ad72a5SChristoph Hellwig u64 host_mem_size; 15487ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1554033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15787ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1582a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1592a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1602a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 1610521905eSKeith Busch 1620521905eSKeith Busch bool attrs_added; 16357dacad5SJay Sternberg }; 16457dacad5SJay Sternberg 165b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 166b27c1e68Sweiping zhang { 16727453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16827453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 169b27c1e68Sweiping zhang } 170b27c1e68Sweiping zhang 171f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 172f9f38e33SHelen Koike { 173f9f38e33SHelen Koike return qid * 2 * stride; 174f9f38e33SHelen Koike } 175f9f38e33SHelen Koike 176f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 177f9f38e33SHelen Koike { 178f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 179f9f38e33SHelen Koike } 180f9f38e33SHelen Koike 1811c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1821c63dc66SChristoph Hellwig { 1831c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1841c63dc66SChristoph Hellwig } 1851c63dc66SChristoph Hellwig 18657dacad5SJay Sternberg /* 18757dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18857dacad5SJay Sternberg * commands and one for I/O commands). 18957dacad5SJay Sternberg */ 19057dacad5SJay Sternberg struct nvme_queue { 19157dacad5SJay Sternberg struct nvme_dev *dev; 1921ab0cd69SJens Axboe spinlock_t sq_lock; 193c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1943a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1953a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19674943d45SKeith Busch struct nvme_completion *cqes; 19757dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19857dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19957dacad5SJay Sternberg u32 __iomem *q_db; 2007442ddceSJohn Garry u32 q_depth; 2017c349ddeSKeith Busch u16 cq_vector; 20257dacad5SJay Sternberg u16 sq_tail; 20338210800SKeith Busch u16 last_sq_tail; 20457dacad5SJay Sternberg u16 cq_head; 20557dacad5SJay Sternberg u16 qid; 20657dacad5SJay Sternberg u8 cq_phase; 207c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2084e224106SChristoph Hellwig unsigned long flags; 2094e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 21063223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 211d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2127c349ddeSKeith Busch #define NVMEQ_POLLED 3 213f9f38e33SHelen Koike u32 *dbbuf_sq_db; 214f9f38e33SHelen Koike u32 *dbbuf_cq_db; 215f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 216f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 217d1ed6aa1SChristoph Hellwig struct completion delete_done; 21857dacad5SJay Sternberg }; 21957dacad5SJay Sternberg 22057dacad5SJay Sternberg /* 2219b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2229b048119SChristoph Hellwig * 2239b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2249b048119SChristoph Hellwig * to the actual struct scatterlist. 22571bd150cSChristoph Hellwig */ 22671bd150cSChristoph Hellwig struct nvme_iod { 227d49187e9SChristoph Hellwig struct nvme_request req; 228af7fae85SKeith Busch struct nvme_command cmd; 229a7a7cbe3SChaitanya Kulkarni bool use_sgl; 230*52da4f3fSKeith Busch bool aborted; 23171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 23271bd150cSChristoph Hellwig dma_addr_t first_dma; 233dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 234783b94bdSChristoph Hellwig dma_addr_t meta_dma; 23591fb2b60SLogan Gunthorpe struct sg_table sgt; 23657dacad5SJay Sternberg }; 23757dacad5SJay Sternberg 2382a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2393b6592f7SJens Axboe { 2402a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 241f9f38e33SHelen Koike } 242f9f38e33SHelen Koike 243f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 244f9f38e33SHelen Koike { 2452a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 246f9f38e33SHelen Koike 24758847f12SKeith Busch if (dev->dbbuf_dbs) { 24858847f12SKeith Busch /* 24958847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25058847f12SKeith Busch * values from the previous instantiation. 25158847f12SKeith Busch */ 25258847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 25358847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 254f9f38e33SHelen Koike return 0; 25558847f12SKeith Busch } 256f9f38e33SHelen Koike 257f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 258f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 259f9f38e33SHelen Koike GFP_KERNEL); 260f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 261f9f38e33SHelen Koike return -ENOMEM; 262f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 263f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 264f9f38e33SHelen Koike GFP_KERNEL); 265f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 266f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 267f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 268f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 269f9f38e33SHelen Koike return -ENOMEM; 270f9f38e33SHelen Koike } 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike return 0; 273f9f38e33SHelen Koike } 274f9f38e33SHelen Koike 275f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 276f9f38e33SHelen Koike { 2772a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 278f9f38e33SHelen Koike 279f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 280f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 281f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 282f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 283f9f38e33SHelen Koike } 284f9f38e33SHelen Koike if (dev->dbbuf_eis) { 285f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 286f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 287f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 288f9f38e33SHelen Koike } 289f9f38e33SHelen Koike } 290f9f38e33SHelen Koike 291f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 292f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 293f9f38e33SHelen Koike { 294f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 295f9f38e33SHelen Koike return; 296f9f38e33SHelen Koike 297f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 298f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 299f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 300f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 301f9f38e33SHelen Koike } 302f9f38e33SHelen Koike 3030f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3040f0d2c87SMinwoo Im { 3050f0d2c87SMinwoo Im if (!nvmeq->qid) 3060f0d2c87SMinwoo Im return; 3070f0d2c87SMinwoo Im 3080f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3090f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3100f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3110f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3120f0d2c87SMinwoo Im } 3130f0d2c87SMinwoo Im 314f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 315f9f38e33SHelen Koike { 316f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3170f0d2c87SMinwoo Im unsigned int i; 318f9f38e33SHelen Koike 319f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 320f9f38e33SHelen Koike return; 321f9f38e33SHelen Koike 322f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 323f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 324f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 325f9f38e33SHelen Koike 326f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3279bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 328f9f38e33SHelen Koike /* Free memory and continue on */ 329f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3300f0d2c87SMinwoo Im 3310f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3320f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 333f9f38e33SHelen Koike } 334f9f38e33SHelen Koike } 335f9f38e33SHelen Koike 336f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 337f9f38e33SHelen Koike { 338f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 339f9f38e33SHelen Koike } 340f9f38e33SHelen Koike 341f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 342f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 343f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 344f9f38e33SHelen Koike { 345f9f38e33SHelen Koike if (dbbuf_db) { 346f9f38e33SHelen Koike u16 old_value; 347f9f38e33SHelen Koike 348f9f38e33SHelen Koike /* 349f9f38e33SHelen Koike * Ensure that the queue is written before updating 350f9f38e33SHelen Koike * the doorbell in memory 351f9f38e33SHelen Koike */ 352f9f38e33SHelen Koike wmb(); 353f9f38e33SHelen Koike 354f9f38e33SHelen Koike old_value = *dbbuf_db; 355f9f38e33SHelen Koike *dbbuf_db = value; 356f9f38e33SHelen Koike 357f1ed3df2SMichal Wnukowski /* 358f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 359f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 360f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 361f1ed3df2SMichal Wnukowski * the doorbell. 362f1ed3df2SMichal Wnukowski */ 363f1ed3df2SMichal Wnukowski mb(); 364f1ed3df2SMichal Wnukowski 365f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 366f9f38e33SHelen Koike return false; 367f9f38e33SHelen Koike } 368f9f38e33SHelen Koike 369f9f38e33SHelen Koike return true; 37057dacad5SJay Sternberg } 37157dacad5SJay Sternberg 37257dacad5SJay Sternberg /* 37357dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37457dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37557dacad5SJay Sternberg * the I/O. 37657dacad5SJay Sternberg */ 377b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 37857dacad5SJay Sternberg { 379b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3806c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 38157dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38257dacad5SJay Sternberg } 38357dacad5SJay Sternberg 384a7a7cbe3SChaitanya Kulkarni /* 385a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 386a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 387a7a7cbe3SChaitanya Kulkarni */ 388b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 389f4800d6dSChristoph Hellwig { 390b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 391b13c6393SChaitanya Kulkarni PAGE_SIZE); 392f4800d6dSChristoph Hellwig } 393f4800d6dSChristoph Hellwig 394b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 39557dacad5SJay Sternberg { 396b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 397a7a7cbe3SChaitanya Kulkarni 398b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 399b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 400a7a7cbe3SChaitanya Kulkarni } 401a7a7cbe3SChaitanya Kulkarni 40257dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40357dacad5SJay Sternberg unsigned int hctx_idx) 40457dacad5SJay Sternberg { 40557dacad5SJay Sternberg struct nvme_dev *dev = data; 406147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40757dacad5SJay Sternberg 40857dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40957dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 41057dacad5SJay Sternberg 41157dacad5SJay Sternberg hctx->driver_data = nvmeq; 41257dacad5SJay Sternberg return 0; 41357dacad5SJay Sternberg } 41457dacad5SJay Sternberg 41557dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41657dacad5SJay Sternberg unsigned int hctx_idx) 41757dacad5SJay Sternberg { 41857dacad5SJay Sternberg struct nvme_dev *dev = data; 419147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 42057dacad5SJay Sternberg 42157dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 42257dacad5SJay Sternberg hctx->driver_data = nvmeq; 42357dacad5SJay Sternberg return 0; 42457dacad5SJay Sternberg } 42557dacad5SJay Sternberg 426e559398fSChristoph Hellwig static int nvme_pci_init_request(struct blk_mq_tag_set *set, 427e559398fSChristoph Hellwig struct request *req, unsigned int hctx_idx, 428e559398fSChristoph Hellwig unsigned int numa_node) 42957dacad5SJay Sternberg { 430d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 431f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 43259e29ce6SSagi Grimberg 43359e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 434f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 43557dacad5SJay Sternberg return 0; 43657dacad5SJay Sternberg } 43757dacad5SJay Sternberg 4383b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4393b6592f7SJens Axboe { 4403b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4413b6592f7SJens Axboe if (dev->num_vecs > 1) 4423b6592f7SJens Axboe return 1; 4433b6592f7SJens Axboe 4443b6592f7SJens Axboe return 0; 4453b6592f7SJens Axboe } 4463b6592f7SJens Axboe 447a4e1d0b7SBart Van Assche static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 448dca51e78SChristoph Hellwig { 449dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4503b6592f7SJens Axboe int i, qoff, offset; 451dca51e78SChristoph Hellwig 4523b6592f7SJens Axboe offset = queue_irq_offset(dev); 4533b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4543b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4553b6592f7SJens Axboe 4563b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4573b6592f7SJens Axboe if (!map->nr_queues) { 458e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4597e849dd9SChristoph Hellwig continue; 4603b6592f7SJens Axboe } 4613b6592f7SJens Axboe 4624b04cc6aSJens Axboe /* 4634b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4644b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4654b04cc6aSJens Axboe */ 4663b6592f7SJens Axboe map->queue_offset = qoff; 467cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4683b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4694b04cc6aSJens Axboe else 4704b04cc6aSJens Axboe blk_mq_map_queues(map); 4713b6592f7SJens Axboe qoff += map->nr_queues; 4723b6592f7SJens Axboe offset += map->nr_queues; 4733b6592f7SJens Axboe } 474dca51e78SChristoph Hellwig } 475dca51e78SChristoph Hellwig 47638210800SKeith Busch /* 47738210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47838210800SKeith Busch */ 47938210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 48004f3eafdSJens Axboe { 48138210800SKeith Busch if (!write_sq) { 48238210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 48338210800SKeith Busch 48438210800SKeith Busch if (next_tail == nvmeq->q_depth) 48538210800SKeith Busch next_tail = 0; 48638210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 48738210800SKeith Busch return; 48838210800SKeith Busch } 48938210800SKeith Busch 49004f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 49104f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 49204f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 49338210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 49404f3eafdSJens Axboe } 49504f3eafdSJens Axboe 4963233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 4973233b94cSJens Axboe struct nvme_command *cmd) 49857dacad5SJay Sternberg { 499c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 5003233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 50190ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 50290ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 50304f3eafdSJens Axboe } 50404f3eafdSJens Axboe 50504f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 50604f3eafdSJens Axboe { 50704f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 50804f3eafdSJens Axboe 50904f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 51038210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 51138210800SKeith Busch nvme_write_sq_db(nvmeq, true); 51290ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 51357dacad5SJay Sternberg } 51457dacad5SJay Sternberg 515a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 51657dacad5SJay Sternberg { 517f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 51891fb2b60SLogan Gunthorpe return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req)); 51957dacad5SJay Sternberg } 52057dacad5SJay Sternberg 521955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 522955b1b5aSMinwoo Im { 523a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 52420469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 525955b1b5aSMinwoo Im unsigned int avg_seg_size; 526955b1b5aSMinwoo Im 52720469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 528955b1b5aSMinwoo Im 529253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 530955b1b5aSMinwoo Im return false; 531a53232cbSKeith Busch if (!nvmeq->qid) 532955b1b5aSMinwoo Im return false; 533955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 534955b1b5aSMinwoo Im return false; 535955b1b5aSMinwoo Im return true; 536955b1b5aSMinwoo Im } 537955b1b5aSMinwoo Im 5389275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 53957dacad5SJay Sternberg { 5406c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5419275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5429275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 54357dacad5SJay Sternberg int i; 54457dacad5SJay Sternberg 5459275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5469275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5479275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5489275c206SChristoph Hellwig 5499275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5509275c206SChristoph Hellwig dma_addr = next_dma_addr; 551dff824b2SChristoph Hellwig } 5529275c206SChristoph Hellwig } 5539275c206SChristoph Hellwig 5549275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5559275c206SChristoph Hellwig { 5569275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5579275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5589275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5599275c206SChristoph Hellwig int i; 5609275c206SChristoph Hellwig 5619275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5629275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5639275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5649275c206SChristoph Hellwig 5659275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5669275c206SChristoph Hellwig dma_addr = next_dma_addr; 5679275c206SChristoph Hellwig } 5689275c206SChristoph Hellwig } 5699275c206SChristoph Hellwig 5709275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5719275c206SChristoph Hellwig { 5729275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5737fe07d14SChristoph Hellwig 5749275c206SChristoph Hellwig if (iod->dma_len) { 5759275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5769275c206SChristoph Hellwig rq_dma_dir(req)); 5779275c206SChristoph Hellwig return; 5789275c206SChristoph Hellwig } 5799275c206SChristoph Hellwig 58091fb2b60SLogan Gunthorpe WARN_ON_ONCE(!iod->sgt.nents); 5819275c206SChristoph Hellwig 58291fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 58391fb2b60SLogan Gunthorpe 58457dacad5SJay Sternberg if (iod->npages == 0) 585a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 5869275c206SChristoph Hellwig iod->first_dma); 5879275c206SChristoph Hellwig else if (iod->use_sgl) 5889275c206SChristoph Hellwig nvme_free_sgls(dev, req); 5899275c206SChristoph Hellwig else 5909275c206SChristoph Hellwig nvme_free_prps(dev, req); 59191fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 59257dacad5SJay Sternberg } 59357dacad5SJay Sternberg 594d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 595d0877473SKeith Busch { 596d0877473SKeith Busch int i; 597d0877473SKeith Busch struct scatterlist *sg; 598d0877473SKeith Busch 599d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 600d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 601d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 602d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 603d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 604d0877473SKeith Busch sg_dma_len(sg)); 605d0877473SKeith Busch } 606d0877473SKeith Busch } 607d0877473SKeith Busch 608a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 609a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 61057dacad5SJay Sternberg { 611f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 61257dacad5SJay Sternberg struct dma_pool *pool; 613b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 61491fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 61557dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 61657dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6176c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 61857dacad5SJay Sternberg __le64 *prp_list; 619a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 62057dacad5SJay Sternberg dma_addr_t prp_dma; 62157dacad5SJay Sternberg int nprps, i; 62257dacad5SJay Sternberg 6236c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6245228b328SJan H. Schönherr if (length <= 0) { 6255228b328SJan H. Schönherr iod->first_dma = 0; 626a7a7cbe3SChaitanya Kulkarni goto done; 6275228b328SJan H. Schönherr } 62857dacad5SJay Sternberg 6296c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 63057dacad5SJay Sternberg if (dma_len) { 6316c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 63257dacad5SJay Sternberg } else { 63357dacad5SJay Sternberg sg = sg_next(sg); 63457dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 63557dacad5SJay Sternberg dma_len = sg_dma_len(sg); 63657dacad5SJay Sternberg } 63757dacad5SJay Sternberg 6386c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 63957dacad5SJay Sternberg iod->first_dma = dma_addr; 640a7a7cbe3SChaitanya Kulkarni goto done; 64157dacad5SJay Sternberg } 64257dacad5SJay Sternberg 6436c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 64457dacad5SJay Sternberg if (nprps <= (256 / 8)) { 64557dacad5SJay Sternberg pool = dev->prp_small_pool; 64657dacad5SJay Sternberg iod->npages = 0; 64757dacad5SJay Sternberg } else { 64857dacad5SJay Sternberg pool = dev->prp_page_pool; 64957dacad5SJay Sternberg iod->npages = 1; 65057dacad5SJay Sternberg } 65157dacad5SJay Sternberg 65269d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65357dacad5SJay Sternberg if (!prp_list) { 65457dacad5SJay Sternberg iod->npages = -1; 65586eea289SKeith Busch return BLK_STS_RESOURCE; 65657dacad5SJay Sternberg } 65757dacad5SJay Sternberg list[0] = prp_list; 65857dacad5SJay Sternberg iod->first_dma = prp_dma; 65957dacad5SJay Sternberg i = 0; 66057dacad5SJay Sternberg for (;;) { 6616c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 66257dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 66369d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 66457dacad5SJay Sternberg if (!prp_list) 665fa073216SChristoph Hellwig goto free_prps; 66657dacad5SJay Sternberg list[iod->npages++] = prp_list; 66757dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 66857dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 66957dacad5SJay Sternberg i = 1; 67057dacad5SJay Sternberg } 67157dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6726c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6736c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6746c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 67557dacad5SJay Sternberg if (length <= 0) 67657dacad5SJay Sternberg break; 67757dacad5SJay Sternberg if (dma_len > 0) 67857dacad5SJay Sternberg continue; 67986eea289SKeith Busch if (unlikely(dma_len < 0)) 68086eea289SKeith Busch goto bad_sgl; 68157dacad5SJay Sternberg sg = sg_next(sg); 68257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 68357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 68457dacad5SJay Sternberg } 685a7a7cbe3SChaitanya Kulkarni done: 68691fb2b60SLogan Gunthorpe cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 687a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 68886eea289SKeith Busch return BLK_STS_OK; 689fa073216SChristoph Hellwig free_prps: 690fa073216SChristoph Hellwig nvme_free_prps(dev, req); 691fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 69286eea289SKeith Busch bad_sgl: 69391fb2b60SLogan Gunthorpe WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 694d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 69591fb2b60SLogan Gunthorpe blk_rq_payload_bytes(req), iod->sgt.nents); 69686eea289SKeith Busch return BLK_STS_IOERR; 69757dacad5SJay Sternberg } 69857dacad5SJay Sternberg 699a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 700a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 701a7a7cbe3SChaitanya Kulkarni { 702a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 703a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 704a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 705a7a7cbe3SChaitanya Kulkarni } 706a7a7cbe3SChaitanya Kulkarni 707a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 708a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 709a7a7cbe3SChaitanya Kulkarni { 710a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 711a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 712a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 713a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 714a7a7cbe3SChaitanya Kulkarni } else { 715a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 716a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 717a7a7cbe3SChaitanya Kulkarni } 718a7a7cbe3SChaitanya Kulkarni } 719a7a7cbe3SChaitanya Kulkarni 720a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 72191fb2b60SLogan Gunthorpe struct request *req, struct nvme_rw_command *cmd) 722a7a7cbe3SChaitanya Kulkarni { 723a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 724a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 725a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 72691fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 72791fb2b60SLogan Gunthorpe unsigned int entries = iod->sgt.nents; 728a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 729b0f2853bSChristoph Hellwig int i = 0; 730a7a7cbe3SChaitanya Kulkarni 731a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 732a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 733a7a7cbe3SChaitanya Kulkarni 734b0f2853bSChristoph Hellwig if (entries == 1) { 735a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 736a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 737a7a7cbe3SChaitanya Kulkarni } 738a7a7cbe3SChaitanya Kulkarni 739a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 740a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 741a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 742a7a7cbe3SChaitanya Kulkarni } else { 743a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 744a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 745a7a7cbe3SChaitanya Kulkarni } 746a7a7cbe3SChaitanya Kulkarni 747a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 748a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 749a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 750a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 751a7a7cbe3SChaitanya Kulkarni } 752a7a7cbe3SChaitanya Kulkarni 753a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 754a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 755a7a7cbe3SChaitanya Kulkarni 756a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 757a7a7cbe3SChaitanya Kulkarni 758a7a7cbe3SChaitanya Kulkarni do { 759a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 760a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 761a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 762a7a7cbe3SChaitanya Kulkarni 763a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 764a7a7cbe3SChaitanya Kulkarni if (!sg_list) 765fa073216SChristoph Hellwig goto free_sgls; 766a7a7cbe3SChaitanya Kulkarni 767a7a7cbe3SChaitanya Kulkarni i = 0; 768a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 769a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 770a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 771a7a7cbe3SChaitanya Kulkarni } 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 774a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 775b0f2853bSChristoph Hellwig } while (--entries > 0); 776a7a7cbe3SChaitanya Kulkarni 777a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 778fa073216SChristoph Hellwig free_sgls: 779fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 780fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 781a7a7cbe3SChaitanya Kulkarni } 782a7a7cbe3SChaitanya Kulkarni 783dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 784dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 785dff824b2SChristoph Hellwig struct bio_vec *bv) 786dff824b2SChristoph Hellwig { 787dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7886c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7896c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 790dff824b2SChristoph Hellwig 791dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 792dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 793dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 794dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 795dff824b2SChristoph Hellwig 796dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 797dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 798dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 799359c1f88SBaolin Wang return BLK_STS_OK; 800dff824b2SChristoph Hellwig } 801dff824b2SChristoph Hellwig 80229791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 80329791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 80429791057SChristoph Hellwig struct bio_vec *bv) 80529791057SChristoph Hellwig { 80629791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 80729791057SChristoph Hellwig 80829791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 80929791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 81029791057SChristoph Hellwig return BLK_STS_RESOURCE; 81129791057SChristoph Hellwig iod->dma_len = bv->bv_len; 81229791057SChristoph Hellwig 813049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 81429791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 81529791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 81629791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 817359c1f88SBaolin Wang return BLK_STS_OK; 81829791057SChristoph Hellwig } 81929791057SChristoph Hellwig 820fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 821b131c61dSChristoph Hellwig struct nvme_command *cmnd) 82257dacad5SJay Sternberg { 823f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82470479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 82591fb2b60SLogan Gunthorpe int rc; 82657dacad5SJay Sternberg 827dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 828a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 829dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 830dff824b2SChristoph Hellwig 831dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8326c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 833dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 834dff824b2SChristoph Hellwig &cmnd->rw, &bv); 83529791057SChristoph Hellwig 836a53232cbSKeith Busch if (nvmeq->qid && sgl_threshold && 837253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 83829791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 83929791057SChristoph Hellwig &cmnd->rw, &bv); 840dff824b2SChristoph Hellwig } 841dff824b2SChristoph Hellwig } 842dff824b2SChristoph Hellwig 843dff824b2SChristoph Hellwig iod->dma_len = 0; 84491fb2b60SLogan Gunthorpe iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 84591fb2b60SLogan Gunthorpe if (!iod->sgt.sgl) 8469b048119SChristoph Hellwig return BLK_STS_RESOURCE; 84791fb2b60SLogan Gunthorpe sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 84891fb2b60SLogan Gunthorpe iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 84991fb2b60SLogan Gunthorpe if (!iod->sgt.orig_nents) 850fa073216SChristoph Hellwig goto out_free_sg; 851ba1ca37eSChristoph Hellwig 85291fb2b60SLogan Gunthorpe rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 85391fb2b60SLogan Gunthorpe DMA_ATTR_NO_WARN); 85491fb2b60SLogan Gunthorpe if (rc) { 85591fb2b60SLogan Gunthorpe if (rc == -EREMOTEIO) 85691fb2b60SLogan Gunthorpe ret = BLK_STS_TARGET; 857fa073216SChristoph Hellwig goto out_free_sg; 85891fb2b60SLogan Gunthorpe } 859ba1ca37eSChristoph Hellwig 86070479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 861955b1b5aSMinwoo Im if (iod->use_sgl) 86291fb2b60SLogan Gunthorpe ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 863a7a7cbe3SChaitanya Kulkarni else 864a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8654aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 866fa073216SChristoph Hellwig goto out_unmap_sg; 867fa073216SChristoph Hellwig return BLK_STS_OK; 868fa073216SChristoph Hellwig 869fa073216SChristoph Hellwig out_unmap_sg: 87091fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 871fa073216SChristoph Hellwig out_free_sg: 87291fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 873ba1ca37eSChristoph Hellwig return ret; 87457dacad5SJay Sternberg } 87557dacad5SJay Sternberg 8764aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8774aedb705SChristoph Hellwig struct nvme_command *cmnd) 8784aedb705SChristoph Hellwig { 8794aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8804aedb705SChristoph Hellwig 8814aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8824aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8834aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8844aedb705SChristoph Hellwig return BLK_STS_IOERR; 8854aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 886359c1f88SBaolin Wang return BLK_STS_OK; 8874aedb705SChristoph Hellwig } 8884aedb705SChristoph Hellwig 88962451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 89062451a2bSJens Axboe { 89162451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 89262451a2bSJens Axboe blk_status_t ret; 89362451a2bSJens Axboe 894*52da4f3fSKeith Busch iod->aborted = false; 89562451a2bSJens Axboe iod->npages = -1; 89691fb2b60SLogan Gunthorpe iod->sgt.nents = 0; 89762451a2bSJens Axboe 89862451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 89962451a2bSJens Axboe if (ret) 90062451a2bSJens Axboe return ret; 90162451a2bSJens Axboe 90262451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 90362451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 90462451a2bSJens Axboe if (ret) 90562451a2bSJens Axboe goto out_free_cmd; 90662451a2bSJens Axboe } 90762451a2bSJens Axboe 90862451a2bSJens Axboe if (blk_integrity_rq(req)) { 90962451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 91062451a2bSJens Axboe if (ret) 91162451a2bSJens Axboe goto out_unmap_data; 91262451a2bSJens Axboe } 91362451a2bSJens Axboe 91462451a2bSJens Axboe blk_mq_start_request(req); 91562451a2bSJens Axboe return BLK_STS_OK; 91662451a2bSJens Axboe out_unmap_data: 91762451a2bSJens Axboe nvme_unmap_data(dev, req); 91862451a2bSJens Axboe out_free_cmd: 91962451a2bSJens Axboe nvme_cleanup_cmd(req); 92062451a2bSJens Axboe return ret; 92162451a2bSJens Axboe } 92262451a2bSJens Axboe 92357dacad5SJay Sternberg /* 92457dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 92557dacad5SJay Sternberg */ 926fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 92757dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 92857dacad5SJay Sternberg { 92957dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 93057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 93157dacad5SJay Sternberg struct request *req = bd->rq; 9329b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 933ebe6d874SChristoph Hellwig blk_status_t ret; 93457dacad5SJay Sternberg 935d1f06f4aSJens Axboe /* 936d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 937d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 938d1f06f4aSJens Axboe */ 9394e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 940d1f06f4aSJens Axboe return BLK_STS_IOERR; 941d1f06f4aSJens Axboe 94262451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 943d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 944d4060d2bSTao Chiu 94562451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 94662451a2bSJens Axboe if (unlikely(ret)) 947f4800d6dSChristoph Hellwig return ret; 9483233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 9493233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 9503233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 9513233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 952fc17b653SChristoph Hellwig return BLK_STS_OK; 95357dacad5SJay Sternberg } 95457dacad5SJay Sternberg 955d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 956d62cbcf6SJens Axboe { 957d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 958d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 959d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 960d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 961d62cbcf6SJens Axboe 962d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 963d62cbcf6SJens Axboe } 964d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 965d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 966d62cbcf6SJens Axboe } 967d62cbcf6SJens Axboe 968d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 969d62cbcf6SJens Axboe { 970d62cbcf6SJens Axboe /* 971d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 972d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 973d62cbcf6SJens Axboe */ 974d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 975d62cbcf6SJens Axboe return false; 976d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 977d62cbcf6SJens Axboe return false; 978d62cbcf6SJens Axboe 979d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 980d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 981d62cbcf6SJens Axboe } 982d62cbcf6SJens Axboe 983d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 984d62cbcf6SJens Axboe { 9856bfec799SKeith Busch struct request *req, *next, *prev = NULL; 986d62cbcf6SJens Axboe struct request *requeue_list = NULL; 987d62cbcf6SJens Axboe 9886bfec799SKeith Busch rq_list_for_each_safe(rqlist, req, next) { 989d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 990d62cbcf6SJens Axboe 991d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 992d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 9936bfec799SKeith Busch rq_list_move(rqlist, &requeue_list, req, prev); 9946bfec799SKeith Busch 9956bfec799SKeith Busch req = prev; 9966bfec799SKeith Busch if (!req) 9976bfec799SKeith Busch continue; 998d62cbcf6SJens Axboe } 999d62cbcf6SJens Axboe 10006bfec799SKeith Busch if (!next || req->mq_hctx != next->mq_hctx) { 1001d62cbcf6SJens Axboe /* detach rest of list, and submit */ 10026bfec799SKeith Busch req->rq_next = NULL; 1003d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 10046bfec799SKeith Busch *rqlist = next; 10056bfec799SKeith Busch prev = NULL; 10066bfec799SKeith Busch } else 10076bfec799SKeith Busch prev = req; 1008d62cbcf6SJens Axboe } 1009d62cbcf6SJens Axboe 1010d62cbcf6SJens Axboe *rqlist = requeue_list; 1011d62cbcf6SJens Axboe } 1012d62cbcf6SJens Axboe 1013c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 1014eee417b0SChristoph Hellwig { 1015a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1016a53232cbSKeith Busch struct nvme_dev *dev = nvmeq->dev; 1017eee417b0SChristoph Hellwig 1018a53232cbSKeith Busch if (blk_integrity_rq(req)) { 1019a53232cbSKeith Busch struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1020a53232cbSKeith Busch 10214aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 10224aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1023a53232cbSKeith Busch } 1024a53232cbSKeith Busch 1025b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 10264aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 1027c234a653SJens Axboe } 1028c234a653SJens Axboe 1029c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 1030c234a653SJens Axboe { 1031c234a653SJens Axboe nvme_pci_unmap_rq(req); 103277f02a7aSChristoph Hellwig nvme_complete_rq(req); 103357dacad5SJay Sternberg } 103457dacad5SJay Sternberg 1035c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1036c234a653SJens Axboe { 1037c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 1038c234a653SJens Axboe } 1039c234a653SJens Axboe 1040d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 1041750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1042d783e0bdSMarta Rybczynska { 104374943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 104474943d45SKeith Busch 104574943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1046d783e0bdSMarta Rybczynska } 1047d783e0bdSMarta Rybczynska 1048eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 104957dacad5SJay Sternberg { 1050eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 105157dacad5SJay Sternberg 1052eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1053eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1054eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1055eb281c82SSagi Grimberg } 1056adf68f21SChristoph Hellwig 1057cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1058cfa27356SChristoph Hellwig { 1059cfa27356SChristoph Hellwig if (!nvmeq->qid) 1060cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1061cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1062cfa27356SChristoph Hellwig } 1063cfa27356SChristoph Hellwig 1064c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1065c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 106657dacad5SJay Sternberg { 106774943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 106862df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 106957dacad5SJay Sternberg struct request *req; 1070adf68f21SChristoph Hellwig 1071adf68f21SChristoph Hellwig /* 1072adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1073adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1074adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1075adf68f21SChristoph Hellwig * for them but rather special case them here. 1076adf68f21SChristoph Hellwig */ 107762df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10787bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 107983a12fb7SSagi Grimberg cqe->status, &cqe->result); 1080a0fa9647SJens Axboe return; 108157dacad5SJay Sternberg } 108257dacad5SJay Sternberg 1083e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 108450b7c243SXianting Tian if (unlikely(!req)) { 108550b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 108650b7c243SXianting Tian "invalid id %d completed on queue %d\n", 108762df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 108850b7c243SXianting Tian return; 108950b7c243SXianting Tian } 109050b7c243SXianting Tian 1091604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1092c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1093c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1094c234a653SJens Axboe nvme_pci_complete_batch)) 1095ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 109683a12fb7SSagi Grimberg } 109757dacad5SJay Sternberg 10985cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10995cb525c8SJens Axboe { 1100a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1101a8de6639SAlexey Dobriyan 1102a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1103920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1104e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1105a8de6639SAlexey Dobriyan } else { 1106a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1107920d13a8SSagi Grimberg } 1108a0fa9647SJens Axboe } 1109a0fa9647SJens Axboe 1110c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1111c234a653SJens Axboe struct io_comp_batch *iob) 1112a0fa9647SJens Axboe { 11131052b8acSJens Axboe int found = 0; 111483a12fb7SSagi Grimberg 11151052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 11161052b8acSJens Axboe found++; 1117b69e2ef2SKeith Busch /* 1118b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1119b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1120b69e2ef2SKeith Busch */ 1121b69e2ef2SKeith Busch dma_rmb(); 1122c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 11235cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 112457dacad5SJay Sternberg } 112557dacad5SJay Sternberg 1126324b494cSKeith Busch if (found) 1127eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 11285cb525c8SJens Axboe return found; 112957dacad5SJay Sternberg } 113057dacad5SJay Sternberg 113157dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 113257dacad5SJay Sternberg { 113357dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11344f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 11355cb525c8SJens Axboe 11364f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 11374f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 11384f502245SJens Axboe nvme_pci_complete_batch(&iob); 113905fae499SChaitanya Kulkarni return IRQ_HANDLED; 11404f502245SJens Axboe } 114105fae499SChaitanya Kulkarni return IRQ_NONE; 114257dacad5SJay Sternberg } 114357dacad5SJay Sternberg 114457dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 114557dacad5SJay Sternberg { 114657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11474e523547SBaolin Wang 1148750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 114957dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1150d783e0bdSMarta Rybczynska return IRQ_NONE; 115157dacad5SJay Sternberg } 115257dacad5SJay Sternberg 11530b2a8a9fSChristoph Hellwig /* 1154fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11550b2a8a9fSChristoph Hellwig * Can be called from any context. 11560b2a8a9fSChristoph Hellwig */ 1157fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1158a0fa9647SJens Axboe { 11593a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1160a0fa9647SJens Axboe 1161fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1162fa059b85SKeith Busch 11633a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1164c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11653a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 116691a509f8SChristoph Hellwig } 1167442e19b7SSagi Grimberg 11685a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11697776db1cSKeith Busch { 11707776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1171dabcefabSJens Axboe bool found; 1172dabcefabSJens Axboe 1173dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1174dabcefabSJens Axboe return 0; 1175dabcefabSJens Axboe 11763a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1177c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11783a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1179dabcefabSJens Axboe 1180dabcefabSJens Axboe return found; 1181dabcefabSJens Axboe } 1182dabcefabSJens Axboe 1183ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 118457dacad5SJay Sternberg { 1185f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1186147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1187f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 118857dacad5SJay Sternberg 118957dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1190ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 11913233b94cSJens Axboe 11923233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 11933233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 11943233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 11953233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 119657dacad5SJay Sternberg } 119757dacad5SJay Sternberg 119857dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 119957dacad5SJay Sternberg { 1200f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 120157dacad5SJay Sternberg 120257dacad5SJay Sternberg c.delete_queue.opcode = opcode; 120357dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 120457dacad5SJay Sternberg 12051c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120657dacad5SJay Sternberg } 120757dacad5SJay Sternberg 120857dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1209a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 121057dacad5SJay Sternberg { 1211f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 12124b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 12134b04cc6aSJens Axboe 12147c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 12154b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 121657dacad5SJay Sternberg 121757dacad5SJay Sternberg /* 121816772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 121957dacad5SJay Sternberg * is attached to the request. 122057dacad5SJay Sternberg */ 122157dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 122257dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 122357dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 122457dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 122557dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1226a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 122757dacad5SJay Sternberg 12281c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 122957dacad5SJay Sternberg } 123057dacad5SJay Sternberg 123157dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 123257dacad5SJay Sternberg struct nvme_queue *nvmeq) 123357dacad5SJay Sternberg { 12349abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1235f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 123681c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 123757dacad5SJay Sternberg 123857dacad5SJay Sternberg /* 12399abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 12409abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 12419abd68efSJens Axboe * URGENT. 12429abd68efSJens Axboe */ 12439abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 12449abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 12459abd68efSJens Axboe 12469abd68efSJens Axboe /* 124716772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 124857dacad5SJay Sternberg * is attached to the request. 124957dacad5SJay Sternberg */ 125057dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 125157dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 125257dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 125357dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 125457dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 125557dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 125657dacad5SJay Sternberg 12571c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 125857dacad5SJay Sternberg } 125957dacad5SJay Sternberg 126057dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 126157dacad5SJay Sternberg { 126257dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 126357dacad5SJay Sternberg } 126457dacad5SJay Sternberg 126557dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 126657dacad5SJay Sternberg { 126757dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 126857dacad5SJay Sternberg } 126957dacad5SJay Sternberg 12702a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 127157dacad5SJay Sternberg { 1272a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 127357dacad5SJay Sternberg 127427fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 127527fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1276e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1277e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 127857dacad5SJay Sternberg } 127957dacad5SJay Sternberg 1280b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1281b2a0eb1aSKeith Busch { 1282b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1283b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1284b2a0eb1aSKeith Busch */ 1285b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1286b2a0eb1aSKeith Busch 1287ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1288ad70062cSJianchao Wang switch (dev->ctrl.state) { 1289ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1290ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1291b2a0eb1aSKeith Busch return false; 1292ad70062cSJianchao Wang default: 1293ad70062cSJianchao Wang break; 1294ad70062cSJianchao Wang } 1295b2a0eb1aSKeith Busch 1296b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1297b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1298b2a0eb1aSKeith Busch */ 1299b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1300b2a0eb1aSKeith Busch return false; 1301b2a0eb1aSKeith Busch 1302b2a0eb1aSKeith Busch return true; 1303b2a0eb1aSKeith Busch } 1304b2a0eb1aSKeith Busch 1305b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1306b2a0eb1aSKeith Busch { 1307b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1308b2a0eb1aSKeith Busch u16 pci_status; 1309b2a0eb1aSKeith Busch int result; 1310b2a0eb1aSKeith Busch 1311b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1312b2a0eb1aSKeith Busch &pci_status); 1313b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1314b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1315b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1316b2a0eb1aSKeith Busch csts, pci_status); 1317b2a0eb1aSKeith Busch else 1318b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1319b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1320b2a0eb1aSKeith Busch csts, result); 13214641a8e6SKeith Busch 13224641a8e6SKeith Busch if (csts != ~0) 13234641a8e6SKeith Busch return; 13244641a8e6SKeith Busch 13254641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13264641a8e6SKeith Busch "Does your device have a faulty power saving mode enabled?\n"); 13274641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13284641a8e6SKeith Busch "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1329b2a0eb1aSKeith Busch } 1330b2a0eb1aSKeith Busch 13319bdb4833SJohn Garry static enum blk_eh_timer_return nvme_timeout(struct request *req) 133257dacad5SJay Sternberg { 1333f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1334a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 133557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 133657dacad5SJay Sternberg struct request *abort_req; 1337f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1338b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1339b2a0eb1aSKeith Busch 1340651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1341651438bbSWen Xiong * the recovery mechanism will surely fail. 1342651438bbSWen Xiong */ 1343651438bbSWen Xiong mb(); 1344651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1345651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1346651438bbSWen Xiong 1347b2a0eb1aSKeith Busch /* 1348b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1349b2a0eb1aSKeith Busch */ 1350b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1351b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1352b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1353d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1354db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1355b2a0eb1aSKeith Busch } 135657dacad5SJay Sternberg 135731c7c7d2SChristoph Hellwig /* 13587776db1cSKeith Busch * Did we miss an interrupt? 13597776db1cSKeith Busch */ 1360fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13615a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1362fa059b85SKeith Busch else 1363bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1364fa059b85SKeith Busch 1365bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 13667776db1cSKeith Busch dev_warn(dev->ctrl.device, 13677776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13687776db1cSKeith Busch req->tag, nvmeq->qid); 1369db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13707776db1cSKeith Busch } 13717776db1cSKeith Busch 13727776db1cSKeith Busch /* 1373fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1374fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1375fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1376db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1377fd634f41SChristoph Hellwig */ 13784244140dSKeith Busch switch (dev->ctrl.state) { 13794244140dSKeith Busch case NVME_CTRL_CONNECTING: 13802036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1381df561f66SGustavo A. R. Silva fallthrough; 13822036f726SKeith Busch case NVME_CTRL_DELETING: 1383b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1384fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1385fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 138627fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13877ad92f65STong Zhang nvme_dev_disable(dev, true); 1388db8c48e4SChristoph Hellwig return BLK_EH_DONE; 138939a9dd81SKeith Busch case NVME_CTRL_RESETTING: 139039a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13914244140dSKeith Busch default: 13924244140dSKeith Busch break; 1393fd634f41SChristoph Hellwig } 1394fd634f41SChristoph Hellwig 1395fd634f41SChristoph Hellwig /* 1396e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1397e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1398e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 139931c7c7d2SChristoph Hellwig */ 1400f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 14011b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 140257dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 140357dacad5SJay Sternberg req->tag, nvmeq->qid); 14047ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1405a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1406d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1407e1569a16SKeith Busch 1408db8c48e4SChristoph Hellwig return BLK_EH_DONE; 140957dacad5SJay Sternberg } 141057dacad5SJay Sternberg 1411e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1412e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1413e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1414e7a2a87dSChristoph Hellwig } 1415*52da4f3fSKeith Busch iod->aborted = true; 141657dacad5SJay Sternberg 141757dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 141885f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 141957dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 142057dacad5SJay Sternberg 14211b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 142286141440SChristoph Hellwig "I/O %d (%s) QID %d timeout, aborting\n", 142386141440SChristoph Hellwig req->tag, 142486141440SChristoph Hellwig nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 142586141440SChristoph Hellwig nvmeq->qid); 1426e7a2a87dSChristoph Hellwig 1427e559398fSChristoph Hellwig abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 142839dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 14296bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 14306bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 143131c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 143257dacad5SJay Sternberg } 1433e559398fSChristoph Hellwig nvme_init_request(abort_req, &cmd); 143457dacad5SJay Sternberg 1435e2e53086SChristoph Hellwig abort_req->end_io = abort_endio; 1436e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1437128126a7SChaitanya Kulkarni abort_req->rq_flags |= RQF_QUIET; 1438e2e53086SChristoph Hellwig blk_execute_rq_nowait(abort_req, false); 143957dacad5SJay Sternberg 144057dacad5SJay Sternberg /* 144157dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 144257dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 144357dacad5SJay Sternberg * as the device then is in a faulty state. 144457dacad5SJay Sternberg */ 144557dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 144657dacad5SJay Sternberg } 144757dacad5SJay Sternberg 144857dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 144957dacad5SJay Sternberg { 14508a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 145157dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 145263223078SChristoph Hellwig if (!nvmeq->sq_cmds) 145363223078SChristoph Hellwig return; 14540f238ff5SLogan Gunthorpe 145563223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 145688a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14578a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 145863223078SChristoph Hellwig } else { 14598a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 146063223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14610f238ff5SLogan Gunthorpe } 146257dacad5SJay Sternberg } 146357dacad5SJay Sternberg 146457dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 146557dacad5SJay Sternberg { 146657dacad5SJay Sternberg int i; 146757dacad5SJay Sternberg 1468d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1469d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1470147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 147157dacad5SJay Sternberg } 147257dacad5SJay Sternberg } 147357dacad5SJay Sternberg 147457dacad5SJay Sternberg /** 147557dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 147640581d1aSBart Van Assche * @nvmeq: queue to suspend 147757dacad5SJay Sternberg */ 147857dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 147957dacad5SJay Sternberg { 14804e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 148157dacad5SJay Sternberg return 1; 148257dacad5SJay Sternberg 14834e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1484d1f06f4aSJens Axboe mb(); 148557dacad5SJay Sternberg 14864e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14871c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 14886ca1d902SMing Lei nvme_stop_admin_queue(&nvmeq->dev->ctrl); 14897c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14904e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 149157dacad5SJay Sternberg return 0; 149257dacad5SJay Sternberg } 149357dacad5SJay Sternberg 14948fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14958fae268bSKeith Busch { 14968fae268bSKeith Busch int i; 14978fae268bSKeith Busch 14988fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14998fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 15008fae268bSKeith Busch } 15018fae268bSKeith Busch 1502a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 150357dacad5SJay Sternberg { 1504147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 150557dacad5SJay Sternberg 1506a5cdb68cSKeith Busch if (shutdown) 1507a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1508a5cdb68cSKeith Busch else 1509b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 151057dacad5SJay Sternberg 1511bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 151257dacad5SJay Sternberg } 151357dacad5SJay Sternberg 1514fa46c6fbSKeith Busch /* 1515fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 15169210c075SDongli Zhang * that can check this device's completion queues have synced, except 15179210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 15189210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1519fa46c6fbSKeith Busch */ 1520fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1521fa46c6fbSKeith Busch { 1522fa46c6fbSKeith Busch int i; 1523fa46c6fbSKeith Busch 15249210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 15259210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1526c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 15279210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 15289210c075SDongli Zhang } 1529fa46c6fbSKeith Busch } 1530fa46c6fbSKeith Busch 153157dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 153257dacad5SJay Sternberg int entry_size) 153357dacad5SJay Sternberg { 153457dacad5SJay Sternberg int q_depth = dev->q_depth; 15355fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 15366c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 153757dacad5SJay Sternberg 153857dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 153957dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 15404e523547SBaolin Wang 15416c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 154257dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 154357dacad5SJay Sternberg 154457dacad5SJay Sternberg /* 154557dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 154657dacad5SJay Sternberg * would be better to map queues in system memory with the 154757dacad5SJay Sternberg * original depth 154857dacad5SJay Sternberg */ 154957dacad5SJay Sternberg if (q_depth < 64) 155057dacad5SJay Sternberg return -ENOMEM; 155157dacad5SJay Sternberg } 155257dacad5SJay Sternberg 155357dacad5SJay Sternberg return q_depth; 155457dacad5SJay Sternberg } 155557dacad5SJay Sternberg 155657dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 15578a1d09a6SBenjamin Herrenschmidt int qid) 155857dacad5SJay Sternberg { 15590f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1560815c6704SKeith Busch 15610f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 15628a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1563bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15640f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15650f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 156663223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 156763223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 156863223078SChristoph Hellwig return 0; 156963223078SChristoph Hellwig } 1570bfac8e9fSAlan Mikhak 15718a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1572bfac8e9fSAlan Mikhak } 15730f238ff5SLogan Gunthorpe } 15740f238ff5SLogan Gunthorpe 15758a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 157657dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 157757dacad5SJay Sternberg if (!nvmeq->sq_cmds) 157857dacad5SJay Sternberg return -ENOMEM; 157957dacad5SJay Sternberg return 0; 158057dacad5SJay Sternberg } 158157dacad5SJay Sternberg 1582a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 158357dacad5SJay Sternberg { 1584147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 158557dacad5SJay Sternberg 158662314e40SKeith Busch if (dev->ctrl.queue_count > qid) 158762314e40SKeith Busch return 0; 158857dacad5SJay Sternberg 1589c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15908a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15918a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 159257dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 159357dacad5SJay Sternberg if (!nvmeq->cqes) 159457dacad5SJay Sternberg goto free_nvmeq; 159557dacad5SJay Sternberg 15968a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 159757dacad5SJay Sternberg goto free_cqdma; 159857dacad5SJay Sternberg 159957dacad5SJay Sternberg nvmeq->dev = dev; 16001ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 16013a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 160257dacad5SJay Sternberg nvmeq->cq_head = 0; 160357dacad5SJay Sternberg nvmeq->cq_phase = 1; 160457dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 160557dacad5SJay Sternberg nvmeq->qid = qid; 1606d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 160757dacad5SJay Sternberg 1608147b27e4SSagi Grimberg return 0; 160957dacad5SJay Sternberg 161057dacad5SJay Sternberg free_cqdma: 16118a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 161257dacad5SJay Sternberg nvmeq->cq_dma_addr); 161357dacad5SJay Sternberg free_nvmeq: 1614147b27e4SSagi Grimberg return -ENOMEM; 161557dacad5SJay Sternberg } 161657dacad5SJay Sternberg 1617dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 161857dacad5SJay Sternberg { 16190ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 16200ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 16210ff199cbSChristoph Hellwig 16220ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 16230ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 16240ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16250ff199cbSChristoph Hellwig } else { 16260ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 16270ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16280ff199cbSChristoph Hellwig } 162957dacad5SJay Sternberg } 163057dacad5SJay Sternberg 163157dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 163257dacad5SJay Sternberg { 163357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 163457dacad5SJay Sternberg 163557dacad5SJay Sternberg nvmeq->sq_tail = 0; 163638210800SKeith Busch nvmeq->last_sq_tail = 0; 163757dacad5SJay Sternberg nvmeq->cq_head = 0; 163857dacad5SJay Sternberg nvmeq->cq_phase = 1; 163957dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 16408a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1641f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 164257dacad5SJay Sternberg dev->online_queues++; 16433a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 164457dacad5SJay Sternberg } 164557dacad5SJay Sternberg 1646e4b9852aSCasey Chen /* 1647e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1648e4b9852aSCasey Chen */ 1649e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1650e4b9852aSCasey Chen { 1651e4b9852aSCasey Chen /* 1652e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1653e4b9852aSCasey Chen */ 1654e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1655e4b9852aSCasey Chen return -ENODEV; 1656e4b9852aSCasey Chen 1657e4b9852aSCasey Chen /* 1658e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1659e4b9852aSCasey Chen */ 1660e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1661e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1662e4b9852aSCasey Chen return -ENODEV; 1663e4b9852aSCasey Chen } 1664e4b9852aSCasey Chen 1665e4b9852aSCasey Chen return 0; 1666e4b9852aSCasey Chen } 1667e4b9852aSCasey Chen 16684b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 166957dacad5SJay Sternberg { 167057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 167157dacad5SJay Sternberg int result; 16727c349ddeSKeith Busch u16 vector = 0; 167357dacad5SJay Sternberg 1674d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1675d1ed6aa1SChristoph Hellwig 167622b55601SKeith Busch /* 167722b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 167822b55601SKeith Busch * has only one vector available. 167922b55601SKeith Busch */ 16804b04cc6aSJens Axboe if (!polled) 1681a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16824b04cc6aSJens Axboe else 16837c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16844b04cc6aSJens Axboe 1685a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1686ded45505SKeith Busch if (result) 1687ded45505SKeith Busch return result; 168857dacad5SJay Sternberg 168957dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 169057dacad5SJay Sternberg if (result < 0) 1691ded45505SKeith Busch return result; 1692c80b36cdSEdmund Nadolski if (result) 169357dacad5SJay Sternberg goto release_cq; 169457dacad5SJay Sternberg 1695a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16964b04cc6aSJens Axboe 1697e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1698e4b9852aSCasey Chen if (result) 1699e4b9852aSCasey Chen return result; 1700e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 17017c349ddeSKeith Busch if (!polled) { 1702dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 170357dacad5SJay Sternberg if (result < 0) 170457dacad5SJay Sternberg goto release_sq; 17054b04cc6aSJens Axboe } 170657dacad5SJay Sternberg 17074e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1708e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 170957dacad5SJay Sternberg return result; 171057dacad5SJay Sternberg 171157dacad5SJay Sternberg release_sq: 1712f25a2dfcSJianchao Wang dev->online_queues--; 1713e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 171457dacad5SJay Sternberg adapter_delete_sq(dev, qid); 171557dacad5SJay Sternberg release_cq: 171657dacad5SJay Sternberg adapter_delete_cq(dev, qid); 171757dacad5SJay Sternberg return result; 171857dacad5SJay Sternberg } 171957dacad5SJay Sternberg 1720f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 172157dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 172277f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 172357dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 1724e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 172557dacad5SJay Sternberg .timeout = nvme_timeout, 172657dacad5SJay Sternberg }; 172757dacad5SJay Sternberg 1728f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1729376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1730d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1731376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1732376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1733376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1734e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 1735376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1736376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1737c6d962aeSChristoph Hellwig .poll = nvme_poll, 1738dabcefabSJens Axboe }; 1739dabcefabSJens Axboe 174057dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 174157dacad5SJay Sternberg { 17421c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 174369d9a99cSKeith Busch /* 174469d9a99cSKeith Busch * If the controller was reset during removal, it's possible 174569d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 174669d9a99cSKeith Busch * queue to flush these to completion. 174769d9a99cSKeith Busch */ 17486ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 17496f8191fdSChristoph Hellwig blk_mq_destroy_queue(dev->ctrl.admin_q); 175057dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 175157dacad5SJay Sternberg } 175257dacad5SJay Sternberg } 175357dacad5SJay Sternberg 1754f91b727cSChristoph Hellwig static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) 175557dacad5SJay Sternberg { 1756f91b727cSChristoph Hellwig struct blk_mq_tag_set *set = &dev->admin_tagset; 1757e3e9d50cSKeith Busch 1758f91b727cSChristoph Hellwig set->ops = &nvme_mq_admin_ops; 1759f91b727cSChristoph Hellwig set->nr_hw_queues = 1; 176057dacad5SJay Sternberg 1761f91b727cSChristoph Hellwig set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1762f91b727cSChristoph Hellwig set->timeout = NVME_ADMIN_TIMEOUT; 1763f91b727cSChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 1764f91b727cSChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 1765f91b727cSChristoph Hellwig set->flags = BLK_MQ_F_NO_SCHED; 1766f91b727cSChristoph Hellwig set->driver_data = dev; 1767f91b727cSChristoph Hellwig 1768f91b727cSChristoph Hellwig if (blk_mq_alloc_tag_set(set)) 176957dacad5SJay Sternberg return -ENOMEM; 1770f91b727cSChristoph Hellwig dev->ctrl.admin_tagset = set; 177157dacad5SJay Sternberg 1772f91b727cSChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(set); 17731c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 1774f91b727cSChristoph Hellwig blk_mq_free_tag_set(set); 1775da427611SSmith, Kyle Miller (Nimble Kernel) dev->ctrl.admin_q = NULL; 177657dacad5SJay Sternberg return -ENOMEM; 177757dacad5SJay Sternberg } 17781c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 177957dacad5SJay Sternberg nvme_dev_remove_admin(dev); 17801c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 178157dacad5SJay Sternberg return -ENODEV; 178257dacad5SJay Sternberg } 178357dacad5SJay Sternberg return 0; 178457dacad5SJay Sternberg } 178557dacad5SJay Sternberg 178697f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 178797f6ef64SXu Yu { 178897f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 178997f6ef64SXu Yu } 179097f6ef64SXu Yu 179197f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 179297f6ef64SXu Yu { 179397f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 179497f6ef64SXu Yu 179597f6ef64SXu Yu if (size <= dev->bar_mapped_size) 179697f6ef64SXu Yu return 0; 179797f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 179897f6ef64SXu Yu return -ENOMEM; 179997f6ef64SXu Yu if (dev->bar) 180097f6ef64SXu Yu iounmap(dev->bar); 180197f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 180297f6ef64SXu Yu if (!dev->bar) { 180397f6ef64SXu Yu dev->bar_mapped_size = 0; 180497f6ef64SXu Yu return -ENOMEM; 180597f6ef64SXu Yu } 180697f6ef64SXu Yu dev->bar_mapped_size = size; 180797f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 180897f6ef64SXu Yu 180997f6ef64SXu Yu return 0; 181097f6ef64SXu Yu } 181197f6ef64SXu Yu 181201ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 181357dacad5SJay Sternberg { 181457dacad5SJay Sternberg int result; 181557dacad5SJay Sternberg u32 aqa; 181657dacad5SJay Sternberg struct nvme_queue *nvmeq; 181757dacad5SJay Sternberg 181897f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 181997f6ef64SXu Yu if (result < 0) 182097f6ef64SXu Yu return result; 182197f6ef64SXu Yu 18228ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 182320d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 182457dacad5SJay Sternberg 18257a67cbeaSChristoph Hellwig if (dev->subsystem && 18267a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 18277a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 182857dacad5SJay Sternberg 1829b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 183057dacad5SJay Sternberg if (result < 0) 183157dacad5SJay Sternberg return result; 183257dacad5SJay Sternberg 1833a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1834147b27e4SSagi Grimberg if (result) 1835147b27e4SSagi Grimberg return result; 183657dacad5SJay Sternberg 1837635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1838635333e4SMax Gurtovoy 1839147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 184057dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 184157dacad5SJay Sternberg aqa |= aqa << 16; 184257dacad5SJay Sternberg 18437a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 18447a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 18457a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 184657dacad5SJay Sternberg 1847c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 184857dacad5SJay Sternberg if (result) 1849d4875622SKeith Busch return result; 185057dacad5SJay Sternberg 185157dacad5SJay Sternberg nvmeq->cq_vector = 0; 1852161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1853dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 185457dacad5SJay Sternberg if (result) { 18557c349ddeSKeith Busch dev->online_queues--; 1856d4875622SKeith Busch return result; 185757dacad5SJay Sternberg } 185857dacad5SJay Sternberg 18594e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 186057dacad5SJay Sternberg return result; 186157dacad5SJay Sternberg } 186257dacad5SJay Sternberg 1863749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 186457dacad5SJay Sternberg { 18654b04cc6aSJens Axboe unsigned i, max, rw_queues; 1866749941f2SChristoph Hellwig int ret = 0; 186757dacad5SJay Sternberg 1868d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1869a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1870749941f2SChristoph Hellwig ret = -ENOMEM; 187157dacad5SJay Sternberg break; 1872749941f2SChristoph Hellwig } 1873749941f2SChristoph Hellwig } 187457dacad5SJay Sternberg 1875d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1876e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1877e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1878e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 18794b04cc6aSJens Axboe } else { 18804b04cc6aSJens Axboe rw_queues = max; 18814b04cc6aSJens Axboe } 18824b04cc6aSJens Axboe 1883949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 18844b04cc6aSJens Axboe bool polled = i > rw_queues; 18854b04cc6aSJens Axboe 18864b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1887d4875622SKeith Busch if (ret) 188857dacad5SJay Sternberg break; 188957dacad5SJay Sternberg } 189057dacad5SJay Sternberg 1891749941f2SChristoph Hellwig /* 1892749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18938adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18948adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1895749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1896749941f2SChristoph Hellwig */ 1897749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 189857dacad5SJay Sternberg } 189957dacad5SJay Sternberg 190088de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 190157dacad5SJay Sternberg { 190288de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 190388de4598SChristoph Hellwig 190488de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 190588de4598SChristoph Hellwig } 190688de4598SChristoph Hellwig 190788de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 190888de4598SChristoph Hellwig { 190988de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 191088de4598SChristoph Hellwig } 191188de4598SChristoph Hellwig 1912f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 191357dacad5SJay Sternberg { 191488de4598SChristoph Hellwig u64 size, offset; 191557dacad5SJay Sternberg resource_size_t bar_size; 191657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 19178969f1f8SChristoph Hellwig int bar; 191857dacad5SJay Sternberg 19199fe5c59fSKeith Busch if (dev->cmb_size) 19209fe5c59fSKeith Busch return; 19219fe5c59fSKeith Busch 192220d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 192320d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 192420d3bb92SKlaus Jensen 19257a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1926f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1927f65efd6dSChristoph Hellwig return; 1928202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 192957dacad5SJay Sternberg 193088de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 193188de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 19328969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 19338969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 193457dacad5SJay Sternberg 193557dacad5SJay Sternberg if (offset > bar_size) 1936f65efd6dSChristoph Hellwig return; 193757dacad5SJay Sternberg 193857dacad5SJay Sternberg /* 193920d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 194020d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 194120d3bb92SKlaus Jensen */ 194220d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 194320d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 194420d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 194520d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 194620d3bb92SKlaus Jensen } 194720d3bb92SKlaus Jensen 194820d3bb92SKlaus Jensen /* 194957dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 195057dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 195157dacad5SJay Sternberg * the reported size of the BAR 195257dacad5SJay Sternberg */ 195357dacad5SJay Sternberg if (size > bar_size - offset) 195457dacad5SJay Sternberg size = bar_size - offset; 195557dacad5SJay Sternberg 19560f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 19570f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 19580f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1959f65efd6dSChristoph Hellwig return; 19600f238ff5SLogan Gunthorpe } 19610f238ff5SLogan Gunthorpe 196257dacad5SJay Sternberg dev->cmb_size = size; 19630f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 19640f238ff5SLogan Gunthorpe 19650f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 19660f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 19670f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 196857dacad5SJay Sternberg } 196957dacad5SJay Sternberg 197087ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 197157dacad5SJay Sternberg { 19726c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19734033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1974f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 197587ad72a5SChristoph Hellwig int ret; 197687ad72a5SChristoph Hellwig 197787ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 197887ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 197987ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19806c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 198187ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 198287ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 198387ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 198487ad72a5SChristoph Hellwig 198587ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 198687ad72a5SChristoph Hellwig if (ret) { 198787ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 198887ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 198987ad72a5SChristoph Hellwig ret, bits); 1990a5df5e79SKeith Busch } else 1991a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1992a5df5e79SKeith Busch 199387ad72a5SChristoph Hellwig return ret; 199487ad72a5SChristoph Hellwig } 199587ad72a5SChristoph Hellwig 199687ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 199787ad72a5SChristoph Hellwig { 199887ad72a5SChristoph Hellwig int i; 199987ad72a5SChristoph Hellwig 200087ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 200187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 20026c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 200387ad72a5SChristoph Hellwig 2004cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 2005cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 2006cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 200787ad72a5SChristoph Hellwig } 200887ad72a5SChristoph Hellwig 200987ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 201087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 20114033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 20124033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 20134033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 201487ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 20157e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 201687ad72a5SChristoph Hellwig } 201787ad72a5SChristoph Hellwig 201892dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 201992dc6895SChristoph Hellwig u32 chunk_size) 202087ad72a5SChristoph Hellwig { 202187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 202292dc6895SChristoph Hellwig u32 max_entries, len; 20234033f35dSChristoph Hellwig dma_addr_t descs_dma; 20242ee0e4edSDan Carpenter int i = 0; 202587ad72a5SChristoph Hellwig void **bufs; 20266fbcde66SMinwoo Im u64 size, tmp; 202787ad72a5SChristoph Hellwig 202887ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 202987ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 203087ad72a5SChristoph Hellwig max_entries = tmp; 2031044a9df1SChristoph Hellwig 2032044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2033044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 2034044a9df1SChristoph Hellwig 2035750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 20364033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 203787ad72a5SChristoph Hellwig if (!descs) 203887ad72a5SChristoph Hellwig goto out; 203987ad72a5SChristoph Hellwig 204087ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 204187ad72a5SChristoph Hellwig if (!bufs) 204287ad72a5SChristoph Hellwig goto out_free_descs; 204387ad72a5SChristoph Hellwig 2044244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 204587ad72a5SChristoph Hellwig dma_addr_t dma_addr; 204687ad72a5SChristoph Hellwig 204750cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 204887ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 204987ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 205087ad72a5SChristoph Hellwig if (!bufs[i]) 205187ad72a5SChristoph Hellwig break; 205287ad72a5SChristoph Hellwig 205387ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 20546c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 205587ad72a5SChristoph Hellwig i++; 205687ad72a5SChristoph Hellwig } 205787ad72a5SChristoph Hellwig 205892dc6895SChristoph Hellwig if (!size) 205987ad72a5SChristoph Hellwig goto out_free_bufs; 206087ad72a5SChristoph Hellwig 206187ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 206287ad72a5SChristoph Hellwig dev->host_mem_size = size; 206387ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 20644033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 206587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 206687ad72a5SChristoph Hellwig return 0; 206787ad72a5SChristoph Hellwig 206887ad72a5SChristoph Hellwig out_free_bufs: 206987ad72a5SChristoph Hellwig while (--i >= 0) { 20706c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 207187ad72a5SChristoph Hellwig 2072cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2073cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2074cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 207587ad72a5SChristoph Hellwig } 207687ad72a5SChristoph Hellwig 207787ad72a5SChristoph Hellwig kfree(bufs); 207887ad72a5SChristoph Hellwig out_free_descs: 20794033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20804033f35dSChristoph Hellwig descs_dma); 208187ad72a5SChristoph Hellwig out: 208287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 208387ad72a5SChristoph Hellwig return -ENOMEM; 208487ad72a5SChristoph Hellwig } 208587ad72a5SChristoph Hellwig 208692dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 208792dc6895SChristoph Hellwig { 20889dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20899dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20909dc54a0dSChaitanya Kulkarni u64 chunk_size; 209192dc6895SChristoph Hellwig 209292dc6895SChristoph Hellwig /* start big and work our way down */ 20939dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 209492dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 209592dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 209692dc6895SChristoph Hellwig return 0; 209792dc6895SChristoph Hellwig nvme_free_host_mem(dev); 209892dc6895SChristoph Hellwig } 209992dc6895SChristoph Hellwig } 210092dc6895SChristoph Hellwig 210192dc6895SChristoph Hellwig return -ENOMEM; 210292dc6895SChristoph Hellwig } 210392dc6895SChristoph Hellwig 21049620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 210587ad72a5SChristoph Hellwig { 210687ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 210787ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 210887ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 210987ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 21106fbcde66SMinwoo Im int ret; 211187ad72a5SChristoph Hellwig 211287ad72a5SChristoph Hellwig preferred = min(preferred, max); 211387ad72a5SChristoph Hellwig if (min > max) { 211487ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 211587ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 211687ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 211787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21189620cfbaSChristoph Hellwig return 0; 211987ad72a5SChristoph Hellwig } 212087ad72a5SChristoph Hellwig 212187ad72a5SChristoph Hellwig /* 212287ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 212387ad72a5SChristoph Hellwig */ 212487ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 212587ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 212687ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 212787ad72a5SChristoph Hellwig else 212887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 212987ad72a5SChristoph Hellwig } 213087ad72a5SChristoph Hellwig 213187ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 213292dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 213392dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 213492dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 21359620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 213687ad72a5SChristoph Hellwig } 213787ad72a5SChristoph Hellwig 213892dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 213992dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 214092dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 214192dc6895SChristoph Hellwig } 214292dc6895SChristoph Hellwig 21439620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 21449620cfbaSChristoph Hellwig if (ret) 214587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21469620cfbaSChristoph Hellwig return ret; 214757dacad5SJay Sternberg } 214857dacad5SJay Sternberg 21490521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 21500521905eSKeith Busch char *buf) 21510521905eSKeith Busch { 21520521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21530521905eSKeith Busch 21540521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 21550521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 21560521905eSKeith Busch } 21570521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 21580521905eSKeith Busch 21591751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 21601751e97aSKeith Busch char *buf) 21611751e97aSKeith Busch { 21621751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21631751e97aSKeith Busch 21641751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 21651751e97aSKeith Busch } 21661751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 21671751e97aSKeith Busch 21681751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 21691751e97aSKeith Busch char *buf) 21701751e97aSKeith Busch { 21711751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21721751e97aSKeith Busch 21731751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 21741751e97aSKeith Busch } 21751751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 21761751e97aSKeith Busch 2177a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2178a5df5e79SKeith Busch char *buf) 2179a5df5e79SKeith Busch { 2180a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2181a5df5e79SKeith Busch 2182a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2183a5df5e79SKeith Busch } 2184a5df5e79SKeith Busch 2185a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2186a5df5e79SKeith Busch const char *buf, size_t count) 2187a5df5e79SKeith Busch { 2188a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2189a5df5e79SKeith Busch bool new; 2190a5df5e79SKeith Busch int ret; 2191a5df5e79SKeith Busch 2192a5df5e79SKeith Busch if (strtobool(buf, &new) < 0) 2193a5df5e79SKeith Busch return -EINVAL; 2194a5df5e79SKeith Busch 2195a5df5e79SKeith Busch if (new == ndev->hmb) 2196a5df5e79SKeith Busch return count; 2197a5df5e79SKeith Busch 2198a5df5e79SKeith Busch if (new) { 2199a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2200a5df5e79SKeith Busch } else { 2201a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2202a5df5e79SKeith Busch if (!ret) 2203a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2204a5df5e79SKeith Busch } 2205a5df5e79SKeith Busch 2206a5df5e79SKeith Busch if (ret < 0) 2207a5df5e79SKeith Busch return ret; 2208a5df5e79SKeith Busch 2209a5df5e79SKeith Busch return count; 2210a5df5e79SKeith Busch } 2211a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2212a5df5e79SKeith Busch 22130521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 22140521905eSKeith Busch struct attribute *a, int n) 22150521905eSKeith Busch { 22160521905eSKeith Busch struct nvme_ctrl *ctrl = 22170521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 22180521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 22190521905eSKeith Busch 22201751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 22211751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 22221751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 22231751e97aSKeith Busch if (!dev->cmbsz) 22240521905eSKeith Busch return 0; 22251751e97aSKeith Busch } 2226a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2227a5df5e79SKeith Busch return 0; 2228a5df5e79SKeith Busch 22290521905eSKeith Busch return a->mode; 22300521905eSKeith Busch } 22310521905eSKeith Busch 22320521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 22330521905eSKeith Busch &dev_attr_cmb.attr, 22341751e97aSKeith Busch &dev_attr_cmbloc.attr, 22351751e97aSKeith Busch &dev_attr_cmbsz.attr, 2236a5df5e79SKeith Busch &dev_attr_hmb.attr, 22370521905eSKeith Busch NULL, 22380521905eSKeith Busch }; 22390521905eSKeith Busch 22400521905eSKeith Busch static const struct attribute_group nvme_pci_attr_group = { 22410521905eSKeith Busch .attrs = nvme_pci_attrs, 22420521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 22430521905eSKeith Busch }; 22440521905eSKeith Busch 2245612b7286SMing Lei /* 2246612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2247612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2248612b7286SMing Lei */ 2249612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 22503b6592f7SJens Axboe { 2251612b7286SMing Lei struct nvme_dev *dev = affd->priv; 22522a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2253c45b1fa2SMing Lei 22543b6592f7SJens Axboe /* 2255ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2256612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2257612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2258612b7286SMing Lei * 2259612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2260612b7286SMing Lei * write and read queues. 2261612b7286SMing Lei * 2262612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2263612b7286SMing Lei * queue. 22643b6592f7SJens Axboe */ 2265612b7286SMing Lei if (!nrirqs) { 2266612b7286SMing Lei nrirqs = 1; 2267612b7286SMing Lei nr_read_queues = 0; 22682a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2269612b7286SMing Lei nr_read_queues = 0; 22702a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2271612b7286SMing Lei nr_read_queues = 1; 22723b6592f7SJens Axboe } else { 22732a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22743b6592f7SJens Axboe } 2275612b7286SMing Lei 2276612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2277612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2278612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2279612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2280612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22813b6592f7SJens Axboe } 22823b6592f7SJens Axboe 22836451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22843b6592f7SJens Axboe { 22853b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22863b6592f7SJens Axboe struct irq_affinity affd = { 22873b6592f7SJens Axboe .pre_vectors = 1, 2288612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2289612b7286SMing Lei .priv = dev, 22903b6592f7SJens Axboe }; 229121cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22926451fe73SJens Axboe 22936451fe73SJens Axboe /* 229421cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 229521cc2f3fSJeffle Xu * left over for non-polled I/O. 22966451fe73SJens Axboe */ 229721cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 229821cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 22993b6592f7SJens Axboe 230021cc2f3fSJeffle Xu /* 230121cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 230221cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 230321cc2f3fSJeffle Xu */ 2304612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2305612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 23063b6592f7SJens Axboe 230766341331SBenjamin Herrenschmidt /* 230821cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 230921cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 231021cc2f3fSJeffle Xu * vector. 231166341331SBenjamin Herrenschmidt */ 231266341331SBenjamin Herrenschmidt irq_queues = 1; 231321cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 231421cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2315612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 23163b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 23173b6592f7SJens Axboe } 23183b6592f7SJens Axboe 23198fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 23208fae268bSKeith Busch { 23218fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 23228fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 23238fae268bSKeith Busch } 23248fae268bSKeith Busch 23252a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 23262a5bcfddSWeiping Zhang { 2327e3aef095SNiklas Schnelle /* 2328e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2329e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2330e3aef095SNiklas Schnelle */ 2331e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2332e3aef095SNiklas Schnelle return 1; 23332a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 23342a5bcfddSWeiping Zhang } 23352a5bcfddSWeiping Zhang 233657dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 233757dacad5SJay Sternberg { 2338147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 233957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 23402a5bcfddSWeiping Zhang unsigned int nr_io_queues; 234197f6ef64SXu Yu unsigned long size; 23422a5bcfddSWeiping Zhang int result; 234357dacad5SJay Sternberg 23442a5bcfddSWeiping Zhang /* 23452a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 23462a5bcfddSWeiping Zhang * stable values to work with. 23472a5bcfddSWeiping Zhang */ 23482a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 23492a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2350d38e9f04SBenjamin Herrenschmidt 2351ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 23529a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 23539a0be7abSChristoph Hellwig if (result < 0) 235457dacad5SJay Sternberg return result; 23559a0be7abSChristoph Hellwig 2356f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2357a5229050SKeith Busch return 0; 235857dacad5SJay Sternberg 2359e4b9852aSCasey Chen /* 2360e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2361e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2362e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2363e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2364e4b9852aSCasey Chen * nvme_dev_disable() path. 2365e4b9852aSCasey Chen */ 2366e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2367e4b9852aSCasey Chen if (result) 2368e4b9852aSCasey Chen return result; 2369e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2370e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 23714e224106SChristoph Hellwig 23720f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 237357dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 237457dacad5SJay Sternberg sizeof(struct nvme_command)); 237557dacad5SJay Sternberg if (result > 0) 237657dacad5SJay Sternberg dev->q_depth = result; 237757dacad5SJay Sternberg else 23780f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 237957dacad5SJay Sternberg } 238057dacad5SJay Sternberg 238157dacad5SJay Sternberg do { 238297f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 238397f6ef64SXu Yu result = nvme_remap_bar(dev, size); 238497f6ef64SXu Yu if (!result) 238557dacad5SJay Sternberg break; 2386e4b9852aSCasey Chen if (!--nr_io_queues) { 2387e4b9852aSCasey Chen result = -ENOMEM; 2388e4b9852aSCasey Chen goto out_unlock; 2389e4b9852aSCasey Chen } 239057dacad5SJay Sternberg } while (1); 239157dacad5SJay Sternberg adminq->q_db = dev->dbs; 239257dacad5SJay Sternberg 23938fae268bSKeith Busch retry: 239457dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2395e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23960ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 239757dacad5SJay Sternberg 239857dacad5SJay Sternberg /* 239957dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 240057dacad5SJay Sternberg * setting up the full range we need. 240157dacad5SJay Sternberg */ 2402dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 24033b6592f7SJens Axboe 24043b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2405e4b9852aSCasey Chen if (result <= 0) { 2406e4b9852aSCasey Chen result = -EIO; 2407e4b9852aSCasey Chen goto out_unlock; 2408e4b9852aSCasey Chen } 24093b6592f7SJens Axboe 241022b55601SKeith Busch dev->num_vecs = result; 24114b04cc6aSJens Axboe result = max(result - 1, 1); 2412e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 241357dacad5SJay Sternberg 241457dacad5SJay Sternberg /* 241557dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 241657dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 241757dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 241857dacad5SJay Sternberg * number of interrupts. 241957dacad5SJay Sternberg */ 2420dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 24217c349ddeSKeith Busch if (result) 2422e4b9852aSCasey Chen goto out_unlock; 24234e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2424e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 24258fae268bSKeith Busch 24268fae268bSKeith Busch result = nvme_create_io_queues(dev); 24278fae268bSKeith Busch if (result || dev->online_queues < 2) 24288fae268bSKeith Busch return result; 24298fae268bSKeith Busch 24308fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 24318fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 24328fae268bSKeith Busch nvme_disable_io_queues(dev); 2433e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2434e4b9852aSCasey Chen if (result) 2435e4b9852aSCasey Chen return result; 24368fae268bSKeith Busch nvme_suspend_io_queues(dev); 24378fae268bSKeith Busch goto retry; 24388fae268bSKeith Busch } 24398fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 24408fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 24418fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 24428fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 24438fae268bSKeith Busch return 0; 2444e4b9852aSCasey Chen out_unlock: 2445e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2446e4b9852aSCasey Chen return result; 244757dacad5SJay Sternberg } 244857dacad5SJay Sternberg 24492a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2450db3cbfffSKeith Busch { 2451db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2452db3cbfffSKeith Busch 2453db3cbfffSKeith Busch blk_mq_free_request(req); 2454d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2455db3cbfffSKeith Busch } 2456db3cbfffSKeith Busch 24572a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2458db3cbfffSKeith Busch { 2459db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2460db3cbfffSKeith Busch 2461d1ed6aa1SChristoph Hellwig if (error) 2462d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2463db3cbfffSKeith Busch 2464db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2465db3cbfffSKeith Busch } 2466db3cbfffSKeith Busch 2467db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2468db3cbfffSKeith Busch { 2469db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2470db3cbfffSKeith Busch struct request *req; 2471f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2472db3cbfffSKeith Busch 2473db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2474db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2475db3cbfffSKeith Busch 2476e559398fSChristoph Hellwig req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2477db3cbfffSKeith Busch if (IS_ERR(req)) 2478db3cbfffSKeith Busch return PTR_ERR(req); 2479e559398fSChristoph Hellwig nvme_init_request(req, &cmd); 2480db3cbfffSKeith Busch 2481e2e53086SChristoph Hellwig if (opcode == nvme_admin_delete_cq) 2482e2e53086SChristoph Hellwig req->end_io = nvme_del_cq_end; 2483e2e53086SChristoph Hellwig else 2484e2e53086SChristoph Hellwig req->end_io = nvme_del_queue_end; 2485db3cbfffSKeith Busch req->end_io_data = nvmeq; 2486db3cbfffSKeith Busch 2487d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2488128126a7SChaitanya Kulkarni req->rq_flags |= RQF_QUIET; 2489e2e53086SChristoph Hellwig blk_execute_rq_nowait(req, false); 2490db3cbfffSKeith Busch return 0; 2491db3cbfffSKeith Busch } 2492db3cbfffSKeith Busch 24938fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2494db3cbfffSKeith Busch { 24955271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2496db3cbfffSKeith Busch unsigned long timeout; 2497db3cbfffSKeith Busch 2498db3cbfffSKeith Busch retry: 2499dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 25005271edd4SChristoph Hellwig while (nr_queues > 0) { 25015271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2502db3cbfffSKeith Busch break; 25035271edd4SChristoph Hellwig nr_queues--; 25045271edd4SChristoph Hellwig sent++; 25055271edd4SChristoph Hellwig } 2506d1ed6aa1SChristoph Hellwig while (sent) { 2507d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2508d1ed6aa1SChristoph Hellwig 2509d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 25105271edd4SChristoph Hellwig timeout); 2511db3cbfffSKeith Busch if (timeout == 0) 25125271edd4SChristoph Hellwig return false; 2513d1ed6aa1SChristoph Hellwig 2514d1ed6aa1SChristoph Hellwig sent--; 25155271edd4SChristoph Hellwig if (nr_queues) 2516db3cbfffSKeith Busch goto retry; 2517db3cbfffSKeith Busch } 25185271edd4SChristoph Hellwig return true; 2519db3cbfffSKeith Busch } 2520db3cbfffSKeith Busch 25212455a4b7SChristoph Hellwig static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) 252257dacad5SJay Sternberg { 25232455a4b7SChristoph Hellwig struct blk_mq_tag_set * set = &dev->tagset; 25242b1b7e78SJianchao Wang int ret; 25252b1b7e78SJianchao Wang 25262455a4b7SChristoph Hellwig set->ops = &nvme_mq_ops; 25272455a4b7SChristoph Hellwig set->nr_hw_queues = dev->online_queues - 1; 25282455a4b7SChristoph Hellwig set->nr_maps = 2; /* default + read */ 2529ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 25302455a4b7SChristoph Hellwig set->nr_maps++; 25312455a4b7SChristoph Hellwig set->timeout = NVME_IO_TIMEOUT; 25322455a4b7SChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 25332455a4b7SChristoph Hellwig set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 25342455a4b7SChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 25352455a4b7SChristoph Hellwig set->flags = BLK_MQ_F_SHOULD_MERGE; 25362455a4b7SChristoph Hellwig set->driver_data = dev; 253757dacad5SJay Sternberg 2538d38e9f04SBenjamin Herrenschmidt /* 2539d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2540d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2541d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2542d38e9f04SBenjamin Herrenschmidt */ 2543d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 25442455a4b7SChristoph Hellwig set->reserved_tags = NVME_AQ_DEPTH; 2545d38e9f04SBenjamin Herrenschmidt 25462455a4b7SChristoph Hellwig ret = blk_mq_alloc_tag_set(set); 25472b1b7e78SJianchao Wang if (ret) { 25482b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25492b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 25505d02a5c1SKeith Busch return; 25512b1b7e78SJianchao Wang } 25522455a4b7SChristoph Hellwig dev->ctrl.tagset = set; 255357dacad5SJay Sternberg } 2554949928c1SKeith Busch 25552455a4b7SChristoph Hellwig static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 25562455a4b7SChristoph Hellwig { 25572455a4b7SChristoph Hellwig blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 25582455a4b7SChristoph Hellwig /* free previously allocated queues that are no longer usable */ 25592455a4b7SChristoph Hellwig nvme_free_queues(dev, dev->online_queues); 256057dacad5SJay Sternberg } 256157dacad5SJay Sternberg 2562b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 256357dacad5SJay Sternberg { 2564b00a726aSKeith Busch int result = -ENOMEM; 256557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 25664bdf2603SFilippo Sironi int dma_address_bits = 64; 256757dacad5SJay Sternberg 256857dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 256957dacad5SJay Sternberg return result; 257057dacad5SJay Sternberg 257157dacad5SJay Sternberg pci_set_master(pdev); 257257dacad5SJay Sternberg 25734bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 25744bdf2603SFilippo Sironi dma_address_bits = 48; 25754bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 257657dacad5SJay Sternberg goto disable; 257757dacad5SJay Sternberg 25787a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 257957dacad5SJay Sternberg result = -ENODEV; 2580b00a726aSKeith Busch goto disable; 258157dacad5SJay Sternberg } 258257dacad5SJay Sternberg 258357dacad5SJay Sternberg /* 2584a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2585a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2586a5229050SKeith Busch * adjust this later. 258757dacad5SJay Sternberg */ 2588dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2589dca51e78SChristoph Hellwig if (result < 0) 2590dca51e78SChristoph Hellwig return result; 259157dacad5SJay Sternberg 259220d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 25937a67cbeaSChristoph Hellwig 25947442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2595b27c1e68Sweiping zhang io_queue_depth); 2596aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 259720d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 25987a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 25991f390c1fSStephan Günther 26001f390c1fSStephan Günther /* 260166341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 260266341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 260366341331SBenjamin Herrenschmidt * so we don't bother updating it here. 260466341331SBenjamin Herrenschmidt */ 260566341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 260666341331SBenjamin Herrenschmidt dev->io_sqes = 7; 260766341331SBenjamin Herrenschmidt else 2608c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 26091f390c1fSStephan Günther 26101f390c1fSStephan Günther /* 26111f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 26121f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 26131f390c1fSStephan Günther */ 26141f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 26151f390c1fSStephan Günther dev->q_depth = 2; 26169bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 26179bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 26181f390c1fSStephan Günther dev->q_depth); 2619d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2620d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 262120d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2622d554b5e1SMartin K. Petersen dev->q_depth = 64; 2623d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2624d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 26251f390c1fSStephan Günther } 26261f390c1fSStephan Günther 2627d38e9f04SBenjamin Herrenschmidt /* 2628d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2629d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2630d38e9f04SBenjamin Herrenschmidt */ 2631d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2632d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2633d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2634d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2635d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2636d38e9f04SBenjamin Herrenschmidt } 2637d38e9f04SBenjamin Herrenschmidt 2638d38e9f04SBenjamin Herrenschmidt 2639f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2640202021c1SStephen Bates 2641a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2642a0a3408eSKeith Busch pci_save_state(pdev); 264357dacad5SJay Sternberg return 0; 264457dacad5SJay Sternberg 264557dacad5SJay Sternberg disable: 264657dacad5SJay Sternberg pci_disable_device(pdev); 264757dacad5SJay Sternberg return result; 264857dacad5SJay Sternberg } 264957dacad5SJay Sternberg 265057dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 265157dacad5SJay Sternberg { 2652b00a726aSKeith Busch if (dev->bar) 2653b00a726aSKeith Busch iounmap(dev->bar); 2654a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2655b00a726aSKeith Busch } 2656b00a726aSKeith Busch 2657b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2658b00a726aSKeith Busch { 265957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 266057dacad5SJay Sternberg 2661dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 266257dacad5SJay Sternberg 2663a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2664a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 266557dacad5SJay Sternberg pci_disable_device(pdev); 266657dacad5SJay Sternberg } 2667a0a3408eSKeith Busch } 266857dacad5SJay Sternberg 2669a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 267057dacad5SJay Sternberg { 2671e43269e6SKeith Busch bool dead = true, freeze = false; 2672302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 267357dacad5SJay Sternberg 267477bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2675081f5e75SKeith Busch if (pci_is_enabled(pdev)) { 2676081f5e75SKeith Busch u32 csts; 2677081f5e75SKeith Busch 2678081f5e75SKeith Busch if (pci_device_is_present(pdev)) 2679081f5e75SKeith Busch csts = readl(dev->bar + NVME_REG_CSTS); 2680081f5e75SKeith Busch else 2681081f5e75SKeith Busch csts = ~0; 2682302ad8ccSKeith Busch 2683ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2684e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2685e43269e6SKeith Busch freeze = true; 2686302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2687e43269e6SKeith Busch } 2688302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2689302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 269057dacad5SJay Sternberg } 2691c21377f8SGabriel Krisman Bertazi 2692302ad8ccSKeith Busch /* 2693302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2694302ad8ccSKeith Busch * doing a safe shutdown. 2695302ad8ccSKeith Busch */ 2696e43269e6SKeith Busch if (!dead && shutdown && freeze) 2697302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 269887ad72a5SChristoph Hellwig 26999a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 27009a915a5bSJianchao Wang 270164ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 27028fae268bSKeith Busch nvme_disable_io_queues(dev); 2703a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 270457dacad5SJay Sternberg } 27058fae268bSKeith Busch nvme_suspend_io_queues(dev); 27068fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2707b00a726aSKeith Busch nvme_pci_disable(dev); 2708fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 270957dacad5SJay Sternberg 27101fcfca78SGuixin Liu nvme_cancel_tagset(&dev->ctrl); 27111fcfca78SGuixin Liu nvme_cancel_admin_tagset(&dev->ctrl); 2712302ad8ccSKeith Busch 2713302ad8ccSKeith Busch /* 2714302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2715302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2716302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2717302ad8ccSKeith Busch */ 2718c8e9e9b7SKeith Busch if (shutdown) { 2719302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2720c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 27216ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 2722c8e9e9b7SKeith Busch } 272377bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 272457dacad5SJay Sternberg } 272557dacad5SJay Sternberg 2726c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2727c1ac9a4bSKeith Busch { 2728c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2729c1ac9a4bSKeith Busch return -EBUSY; 2730c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2731c1ac9a4bSKeith Busch return 0; 2732c1ac9a4bSKeith Busch } 2733c1ac9a4bSKeith Busch 273457dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 273557dacad5SJay Sternberg { 273657dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2737c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2738c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 273957dacad5SJay Sternberg if (!dev->prp_page_pool) 274057dacad5SJay Sternberg return -ENOMEM; 274157dacad5SJay Sternberg 274257dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 274357dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 274457dacad5SJay Sternberg 256, 256, 0); 274557dacad5SJay Sternberg if (!dev->prp_small_pool) { 274657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 274757dacad5SJay Sternberg return -ENOMEM; 274857dacad5SJay Sternberg } 274957dacad5SJay Sternberg return 0; 275057dacad5SJay Sternberg } 275157dacad5SJay Sternberg 275257dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 275357dacad5SJay Sternberg { 275457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 275557dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 275657dacad5SJay Sternberg } 275757dacad5SJay Sternberg 2758770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2759770597ecSKeith Busch { 2760770597ecSKeith Busch if (dev->tagset.tags) 2761770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2762770597ecSKeith Busch dev->ctrl.tagset = NULL; 2763770597ecSKeith Busch } 2764770597ecSKeith Busch 27651673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 276657dacad5SJay Sternberg { 27671673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 276857dacad5SJay Sternberg 2769f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2770770597ecSKeith Busch nvme_free_tagset(dev); 27711c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 27721c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2773e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2774943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2775253fd4acSIsrael Rukshin put_device(dev->dev); 2776253fd4acSIsrael Rukshin kfree(dev->queues); 277757dacad5SJay Sternberg kfree(dev); 277857dacad5SJay Sternberg } 277957dacad5SJay Sternberg 27807c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2781f58944e2SKeith Busch { 2782c1ac9a4bSKeith Busch /* 2783c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2784c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2785c1ac9a4bSKeith Busch */ 2786c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2787d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 278869d9a99cSKeith Busch nvme_dev_disable(dev, false); 27899f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 279003e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2791f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2792f58944e2SKeith Busch } 2793f58944e2SKeith Busch 2794fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 279557dacad5SJay Sternberg { 2796d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2797d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2798a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2799e71afda4SChaitanya Kulkarni int result; 280057dacad5SJay Sternberg 28017764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 28027764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 28037764656bSZhihao Cheng dev->ctrl.state); 2804e71afda4SChaitanya Kulkarni result = -ENODEV; 2805fd634f41SChristoph Hellwig goto out; 2806e71afda4SChaitanya Kulkarni } 2807fd634f41SChristoph Hellwig 2808fd634f41SChristoph Hellwig /* 2809fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2810fd634f41SChristoph Hellwig * moving on. 2811fd634f41SChristoph Hellwig */ 2812b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2813a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2814d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2815fd634f41SChristoph Hellwig 28165c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2817b00a726aSKeith Busch result = nvme_pci_enable(dev); 281857dacad5SJay Sternberg if (result) 28194726bcf3SKeith Busch goto out_unlock; 282057dacad5SJay Sternberg 282101ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 282257dacad5SJay Sternberg if (result) 28234726bcf3SKeith Busch goto out_unlock; 282457dacad5SJay Sternberg 2825f91b727cSChristoph Hellwig if (!dev->ctrl.admin_q) { 2826f91b727cSChristoph Hellwig result = nvme_pci_alloc_admin_tag_set(dev); 282757dacad5SJay Sternberg if (result) 28284726bcf3SKeith Busch goto out_unlock; 2829f91b727cSChristoph Hellwig } else { 2830f91b727cSChristoph Hellwig nvme_start_admin_queue(&dev->ctrl); 2831f91b727cSChristoph Hellwig } 283257dacad5SJay Sternberg 2833943e942eSJens Axboe /* 2834943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2835943e942eSJens Axboe * over a single page. 2836943e942eSJens Axboe */ 28377637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 28387637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2839943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2840a48bc520SChristoph Hellwig 2841a48bc520SChristoph Hellwig /* 2842a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2843a48bc520SChristoph Hellwig */ 2844a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 28453d2d861eSJianxiong Gao dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2846a48bc520SChristoph Hellwig 28475c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 28485c959d73SKeith Busch 28495c959d73SKeith Busch /* 28505c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 28515c959d73SKeith Busch * initializing procedure here. 28525c959d73SKeith Busch */ 28535c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 28545c959d73SKeith Busch dev_warn(dev->ctrl.device, 28555c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2856cee6c269SMinwoo Im result = -EBUSY; 28575c959d73SKeith Busch goto out; 28585c959d73SKeith Busch } 2859943e942eSJens Axboe 286095093350SMax Gurtovoy /* 286195093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 286295093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 286395093350SMax Gurtovoy */ 286495093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 286595093350SMax Gurtovoy 2866f21c4769SChaitanya Kulkarni result = nvme_init_ctrl_finish(&dev->ctrl); 2867ce4541f4SChristoph Hellwig if (result) 2868f58944e2SKeith Busch goto out; 2869ce4541f4SChristoph Hellwig 2870e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2871e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 28724f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 28734f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2874e286bcfcSScott Bauer else if (was_suspend) 28754f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2876e286bcfcSScott Bauer } else { 2877e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2878e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2879e286bcfcSScott Bauer } 2880a98e58e5SScott Bauer 2881f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2882f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2883f9f38e33SHelen Koike if (result) 2884f9f38e33SHelen Koike dev_warn(dev->dev, 2885f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2886f9f38e33SHelen Koike } 2887f9f38e33SHelen Koike 28889620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 28899620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 28909620cfbaSChristoph Hellwig if (result < 0) 28919620cfbaSChristoph Hellwig goto out; 28929620cfbaSChristoph Hellwig } 289387ad72a5SChristoph Hellwig 289457dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 289557dacad5SJay Sternberg if (result) 2896f58944e2SKeith Busch goto out; 289757dacad5SJay Sternberg 289821f033f7SKeith Busch /* 289957dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 290057dacad5SJay Sternberg * any working I/O queue. 290157dacad5SJay Sternberg */ 290257dacad5SJay Sternberg if (dev->online_queues < 2) { 29031b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 29043b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 29055bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2906770597ecSKeith Busch nvme_free_tagset(dev); 290757dacad5SJay Sternberg } else { 290825646264SKeith Busch nvme_start_queues(&dev->ctrl); 2909302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 29102455a4b7SChristoph Hellwig if (!dev->ctrl.tagset) 29112455a4b7SChristoph Hellwig nvme_pci_alloc_tag_set(dev); 29122455a4b7SChristoph Hellwig else 29132455a4b7SChristoph Hellwig nvme_pci_update_nr_queues(dev); 29142455a4b7SChristoph Hellwig nvme_dbbuf_set(dev); 2915302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 291657dacad5SJay Sternberg } 291757dacad5SJay Sternberg 29182b1b7e78SJianchao Wang /* 29192b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 29202b1b7e78SJianchao Wang * recovery. 29212b1b7e78SJianchao Wang */ 29225d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 29232b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 29245d02a5c1SKeith Busch "failed to mark controller live state\n"); 2925e71afda4SChaitanya Kulkarni result = -ENODEV; 2926bb8d261eSChristoph Hellwig goto out; 2927bb8d261eSChristoph Hellwig } 292892911a55SChristoph Hellwig 29290521905eSKeith Busch if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, 29300521905eSKeith Busch &nvme_pci_attr_group)) 29310521905eSKeith Busch dev->attrs_added = true; 29320521905eSKeith Busch 2933d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 293457dacad5SJay Sternberg return; 293557dacad5SJay Sternberg 29364726bcf3SKeith Busch out_unlock: 29374726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 293857dacad5SJay Sternberg out: 29397c1ce408SChaitanya Kulkarni if (result) 29407c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 29417c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 29427c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 294357dacad5SJay Sternberg } 294457dacad5SJay Sternberg 29455c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 294657dacad5SJay Sternberg { 29475c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 294857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 294957dacad5SJay Sternberg 295057dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2951921920abSKeith Busch device_release_driver(&pdev->dev); 29521673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 295357dacad5SJay Sternberg } 295457dacad5SJay Sternberg 29551c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 295657dacad5SJay Sternberg { 29571c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 29581c63dc66SChristoph Hellwig return 0; 295957dacad5SJay Sternberg } 29601c63dc66SChristoph Hellwig 29615fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 29625fd4ce1bSChristoph Hellwig { 29635fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 29645fd4ce1bSChristoph Hellwig return 0; 29655fd4ce1bSChristoph Hellwig } 29665fd4ce1bSChristoph Hellwig 29677fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 29687fd8930fSChristoph Hellwig { 29693a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 29707fd8930fSChristoph Hellwig return 0; 29717fd8930fSChristoph Hellwig } 29727fd8930fSChristoph Hellwig 297397c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 297497c12223SKeith Busch { 297597c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 297697c12223SKeith Busch 29772db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 297897c12223SKeith Busch } 297997c12223SKeith Busch 29802f0dad17SKeith Busch static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 29812f0dad17SKeith Busch { 29822f0dad17SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 29832f0dad17SKeith Busch struct nvme_subsystem *subsys = ctrl->subsys; 29842f0dad17SKeith Busch 29852f0dad17SKeith Busch dev_err(ctrl->device, 29862f0dad17SKeith Busch "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 29872f0dad17SKeith Busch pdev->vendor, pdev->device, 29882f0dad17SKeith Busch nvme_strlen(subsys->model, sizeof(subsys->model)), 29892f0dad17SKeith Busch subsys->model, nvme_strlen(subsys->firmware_rev, 29902f0dad17SKeith Busch sizeof(subsys->firmware_rev)), 29912f0dad17SKeith Busch subsys->firmware_rev); 29922f0dad17SKeith Busch } 29932f0dad17SKeith Busch 29942f859441SLogan Gunthorpe static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 29952f859441SLogan Gunthorpe { 29962f859441SLogan Gunthorpe struct nvme_dev *dev = to_nvme_dev(ctrl); 29972f859441SLogan Gunthorpe 29982f859441SLogan Gunthorpe return dma_pci_p2pdma_supported(dev->dev); 29992f859441SLogan Gunthorpe } 30002f859441SLogan Gunthorpe 30011c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 30021a353d85SMing Lin .name = "pcie", 3003e439bb12SSagi Grimberg .module = THIS_MODULE, 30042f859441SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED, 30051c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 30065fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 30077fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 30081673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 3009f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 301097c12223SKeith Busch .get_address = nvme_pci_get_address, 30112f0dad17SKeith Busch .print_device_info = nvme_pci_print_device_info, 30122f859441SLogan Gunthorpe .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 30131c63dc66SChristoph Hellwig }; 301457dacad5SJay Sternberg 3015b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 3016b00a726aSKeith Busch { 3017b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 3018b00a726aSKeith Busch 3019a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 3020b00a726aSKeith Busch return -ENODEV; 3021b00a726aSKeith Busch 302297f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 3023b00a726aSKeith Busch goto release; 3024b00a726aSKeith Busch 3025b00a726aSKeith Busch return 0; 3026b00a726aSKeith Busch release: 3027a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 3028b00a726aSKeith Busch return -ENODEV; 3029b00a726aSKeith Busch } 3030b00a726aSKeith Busch 30318427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 3032ff5350a8SAndy Lutomirski { 3033ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 3034ff5350a8SAndy Lutomirski /* 3035ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 3036ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 3037ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 3038ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 3039ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 3040ff5350a8SAndy Lutomirski * laptops. 3041ff5350a8SAndy Lutomirski */ 3042ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 3043ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 3044ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 3045ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 30468427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 30478427bbc2SKai-Heng Feng /* 30488427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 3049467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 3050467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 3051467c77d4SJarosław Janik * ASUS PRIME Z370-A 30528427bbc2SKai-Heng Feng */ 30538427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3054467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3055467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 30568427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 30571fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 30581fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 30591fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 30601fae37acSShyjumon N /* 30611fae37acSShyjumon N * Forcing to use host managed nvme power settings for 30621fae37acSShyjumon N * lowest idle power with quick resume latency on 30631fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 30641fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 30651fae37acSShyjumon N */ 30661fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 30671fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 30681fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 3069ff5350a8SAndy Lutomirski } 3070ff5350a8SAndy Lutomirski 3071ff5350a8SAndy Lutomirski return 0; 3072ff5350a8SAndy Lutomirski } 3073ff5350a8SAndy Lutomirski 307418119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 307518119775SKeith Busch { 307618119775SKeith Busch struct nvme_dev *dev = data; 307780f513b5SKeith Busch 3078bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 307918119775SKeith Busch flush_work(&dev->ctrl.scan_work); 308080f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 308118119775SKeith Busch } 308218119775SKeith Busch 308357dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 308457dacad5SJay Sternberg { 308557dacad5SJay Sternberg int node, result = -ENOMEM; 308657dacad5SJay Sternberg struct nvme_dev *dev; 3087ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 3088943e942eSJens Axboe size_t alloc_size; 308957dacad5SJay Sternberg 309057dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 309157dacad5SJay Sternberg if (node == NUMA_NO_NODE) 30922fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 309357dacad5SJay Sternberg 309457dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 309557dacad5SJay Sternberg if (!dev) 309657dacad5SJay Sternberg return -ENOMEM; 3097147b27e4SSagi Grimberg 30982a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 30992a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 31002a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 31012a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 31022a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 310357dacad5SJay Sternberg if (!dev->queues) 310457dacad5SJay Sternberg goto free; 310557dacad5SJay Sternberg 310657dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 310757dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 310857dacad5SJay Sternberg 3109b00a726aSKeith Busch result = nvme_dev_map(dev); 3110b00a726aSKeith Busch if (result) 3111b00c9b7aSChristophe JAILLET goto put_pci; 3112b00a726aSKeith Busch 3113d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 31145c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 311577bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 3116f3ca80fcSChristoph Hellwig 3117f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 3118f3ca80fcSChristoph Hellwig if (result) 3119b00c9b7aSChristophe JAILLET goto unmap; 3120f3ca80fcSChristoph Hellwig 31218427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 3122ff5350a8SAndy Lutomirski 31232744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3124df4f9bc4SDavid E. Box /* 3125df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3126df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3127df4f9bc4SDavid E. Box */ 3128df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3129df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3130df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3131df4f9bc4SDavid E. Box } 3132df4f9bc4SDavid E. Box 3133943e942eSJens Axboe /* 3134943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 3135943e942eSJens Axboe * command we support. 3136943e942eSJens Axboe */ 3137b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 3138943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 3139943e942eSJens Axboe 3140943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 3141943e942eSJens Axboe mempool_kfree, 3142943e942eSJens Axboe (void *) alloc_size, 3143943e942eSJens Axboe GFP_KERNEL, node); 3144943e942eSJens Axboe if (!dev->iod_mempool) { 3145943e942eSJens Axboe result = -ENOMEM; 3146943e942eSJens Axboe goto release_pools; 3147943e942eSJens Axboe } 3148943e942eSJens Axboe 3149b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3150b6e44b4cSKeith Busch quirks); 3151b6e44b4cSKeith Busch if (result) 3152b6e44b4cSKeith Busch goto release_mempool; 3153b6e44b4cSKeith Busch 31541b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 31551b3c47c1SSagi Grimberg 3156bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 315718119775SKeith Busch async_schedule(nvme_async_probe, dev); 31584caff8fcSSagi Grimberg 315957dacad5SJay Sternberg return 0; 316057dacad5SJay Sternberg 3161b6e44b4cSKeith Busch release_mempool: 3162b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 316357dacad5SJay Sternberg release_pools: 316457dacad5SJay Sternberg nvme_release_prp_pools(dev); 3165b00c9b7aSChristophe JAILLET unmap: 3166b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 316757dacad5SJay Sternberg put_pci: 316857dacad5SJay Sternberg put_device(dev->dev); 316957dacad5SJay Sternberg free: 317057dacad5SJay Sternberg kfree(dev->queues); 317157dacad5SJay Sternberg kfree(dev); 317257dacad5SJay Sternberg return result; 317357dacad5SJay Sternberg } 317457dacad5SJay Sternberg 3175775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 317657dacad5SJay Sternberg { 317757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3178c1ac9a4bSKeith Busch 3179c1ac9a4bSKeith Busch /* 3180c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3181c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3182c1ac9a4bSKeith Busch * with ->remove(). 3183c1ac9a4bSKeith Busch */ 3184c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3185c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3186775755edSChristoph Hellwig } 318757dacad5SJay Sternberg 3188775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3189775755edSChristoph Hellwig { 3190f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3191c1ac9a4bSKeith Busch 3192c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3193c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 319457dacad5SJay Sternberg } 319557dacad5SJay Sternberg 319657dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 319757dacad5SJay Sternberg { 319857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 31994e523547SBaolin Wang 3200c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 320157dacad5SJay Sternberg } 320257dacad5SJay Sternberg 32030521905eSKeith Busch static void nvme_remove_attrs(struct nvme_dev *dev) 32040521905eSKeith Busch { 32050521905eSKeith Busch if (dev->attrs_added) 32060521905eSKeith Busch sysfs_remove_group(&dev->ctrl.device->kobj, 32070521905eSKeith Busch &nvme_pci_attr_group); 32080521905eSKeith Busch } 32090521905eSKeith Busch 3210f58944e2SKeith Busch /* 3211f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3212f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3213f58944e2SKeith Busch * order to proceed. 3214f58944e2SKeith Busch */ 321557dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 321657dacad5SJay Sternberg { 321757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 321857dacad5SJay Sternberg 3219bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 322057dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 32210ff9d4e1SKeith Busch 32226db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 32230ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 32241d39e692SKeith Busch nvme_dev_disable(dev, true); 32256db28edaSKeith Busch } 32260ff9d4e1SKeith Busch 3227d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3228d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3229d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3230a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 32310521905eSKeith Busch nvme_remove_attrs(dev); 323287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 323357dacad5SJay Sternberg nvme_dev_remove_admin(dev); 323457dacad5SJay Sternberg nvme_free_queues(dev, 0); 323557dacad5SJay Sternberg nvme_release_prp_pools(dev); 3236b00a726aSKeith Busch nvme_dev_unmap(dev); 3237726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 323857dacad5SJay Sternberg } 323957dacad5SJay Sternberg 324057dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3241d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3242d916b1beSKeith Busch { 3243d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3244d916b1beSKeith Busch } 3245d916b1beSKeith Busch 3246d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3247d916b1beSKeith Busch { 3248d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3249d916b1beSKeith Busch } 3250d916b1beSKeith Busch 3251d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3252d916b1beSKeith Busch { 3253d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3254d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3255d916b1beSKeith Busch 32564eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3257d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3258e5ad96f3SKeith Busch goto reset; 3259e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3260e5ad96f3SKeith Busch goto reset; 3261e5ad96f3SKeith Busch 3262d916b1beSKeith Busch return 0; 3263e5ad96f3SKeith Busch reset: 3264e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3265d916b1beSKeith Busch } 3266d916b1beSKeith Busch 326757dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 326857dacad5SJay Sternberg { 326957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 327057dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3271d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3272d916b1beSKeith Busch int ret = -EBUSY; 3273d916b1beSKeith Busch 32744eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 32754eaefe8cSRafael J. Wysocki 3276d916b1beSKeith Busch /* 3277d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3278d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3279d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3280d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3281d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3282d916b1beSKeith Busch * device fully. 32834eaefe8cSRafael J. Wysocki * 32844eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 32854eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 32864eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 32874eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3288d916b1beSKeith Busch */ 32894eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3290cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3291c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3292c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3293d916b1beSKeith Busch 3294d916b1beSKeith Busch nvme_start_freeze(ctrl); 3295d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3296d916b1beSKeith Busch nvme_sync_queues(ctrl); 3297d916b1beSKeith Busch 32985d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3299d916b1beSKeith Busch goto unfreeze; 3300d916b1beSKeith Busch 3301e5ad96f3SKeith Busch /* 3302e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3303e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3304e5ad96f3SKeith Busch * non-operational power state. 3305e5ad96f3SKeith Busch */ 3306e5ad96f3SKeith Busch if (ndev->hmb) { 3307e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3308e5ad96f3SKeith Busch if (ret < 0) 3309e5ad96f3SKeith Busch goto unfreeze; 3310e5ad96f3SKeith Busch } 3311e5ad96f3SKeith Busch 3312d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3313d916b1beSKeith Busch if (ret < 0) 3314d916b1beSKeith Busch goto unfreeze; 3315d916b1beSKeith Busch 33167cbb5c6fSMario Limonciello /* 33177cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 33187cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 33197cbb5c6fSMario Limonciello * want pci interfering. 33207cbb5c6fSMario Limonciello */ 33217cbb5c6fSMario Limonciello pci_save_state(pdev); 33227cbb5c6fSMario Limonciello 3323d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3324d916b1beSKeith Busch if (ret < 0) 3325d916b1beSKeith Busch goto unfreeze; 3326d916b1beSKeith Busch 3327d916b1beSKeith Busch if (ret) { 33287cbb5c6fSMario Limonciello /* discard the saved state */ 33297cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 33307cbb5c6fSMario Limonciello 3331d916b1beSKeith Busch /* 3332d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 333305d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3334d916b1beSKeith Busch */ 3335c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3336d916b1beSKeith Busch ctrl->npss = 0; 3337d916b1beSKeith Busch } 3338d916b1beSKeith Busch unfreeze: 3339d916b1beSKeith Busch nvme_unfreeze(ctrl); 3340d916b1beSKeith Busch return ret; 3341d916b1beSKeith Busch } 3342d916b1beSKeith Busch 3343d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3344d916b1beSKeith Busch { 3345d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 33464e523547SBaolin Wang 3347c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 334857dacad5SJay Sternberg } 334957dacad5SJay Sternberg 3350d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 335157dacad5SJay Sternberg { 335257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 335357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 335457dacad5SJay Sternberg 3355c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 335657dacad5SJay Sternberg } 335757dacad5SJay Sternberg 335821774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3359d916b1beSKeith Busch .suspend = nvme_suspend, 3360d916b1beSKeith Busch .resume = nvme_resume, 3361d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3362d916b1beSKeith Busch .thaw = nvme_simple_resume, 3363d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3364d916b1beSKeith Busch .restore = nvme_simple_resume, 3365d916b1beSKeith Busch }; 3366d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 336757dacad5SJay Sternberg 3368a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3369a0a3408eSKeith Busch pci_channel_state_t state) 3370a0a3408eSKeith Busch { 3371a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3372a0a3408eSKeith Busch 3373a0a3408eSKeith Busch /* 3374a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3375a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3376a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3377a0a3408eSKeith Busch */ 3378a0a3408eSKeith Busch switch (state) { 3379a0a3408eSKeith Busch case pci_channel_io_normal: 3380a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3381a0a3408eSKeith Busch case pci_channel_io_frozen: 3382d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3383d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3384a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3385a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3386a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3387d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3388d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3389a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3390a0a3408eSKeith Busch } 3391a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3392a0a3408eSKeith Busch } 3393a0a3408eSKeith Busch 3394a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3395a0a3408eSKeith Busch { 3396a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3397a0a3408eSKeith Busch 33981b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3399a0a3408eSKeith Busch pci_restore_state(pdev); 3400d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3401a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3402a0a3408eSKeith Busch } 3403a0a3408eSKeith Busch 3404a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3405a0a3408eSKeith Busch { 340672cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 340772cd4cc2SKeith Busch 340872cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3409a0a3408eSKeith Busch } 3410a0a3408eSKeith Busch 341157dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 341257dacad5SJay Sternberg .error_detected = nvme_error_detected, 341357dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 341457dacad5SJay Sternberg .resume = nvme_error_resume, 3415775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3416775755edSChristoph Hellwig .reset_done = nvme_reset_done, 341757dacad5SJay Sternberg }; 341857dacad5SJay Sternberg 341957dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3420972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 342108095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3422e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3423972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 342499466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3425e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3426972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 342799466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 342825e58af4SWu Zheng NVME_QUIRK_DEALLOCATE_ZEROES | 342925e58af4SWu Zheng NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3430972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3431f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3432f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 343350af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 34349abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 34356c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3436ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3437ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34386299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 34396299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3440540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 34417b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 344266dd346bSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES | 344366dd346bSChristoph Hellwig NVME_QUIRK_BOGUS_NID, }, 344466dd346bSChristoph Hellwig { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 344566dd346bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 34465bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3447c98a8793SKeith Busch .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3448c98a8793SKeith Busch NVME_QUIRK_BOGUS_NID, }, 34490302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 34505e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 34515e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 345254adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 345354adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 34548c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 34558c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3456015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3457015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3458d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3459d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3460d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 34617ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3462abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 34637ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34642cf7a77eSKeith Busch { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 34652cf7a77eSKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 3466c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 346773029c9bSKeith Busch .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 346873029c9bSKeith Busch NVME_QUIRK_BOGUS_NID, }, 34696e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 34706e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 34716e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3472e1c70d79SLamarque Vieira Souza { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3473e1c70d79SLamarque Vieira Souza .driver_data = NVME_QUIRK_BOGUS_NID, }, 347408b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 34751629de0eSPablo Greco .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 34761629de0eSPablo Greco NVME_QUIRK_BOGUS_NID, }, 3477f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3478f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3479f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 348041f38043SLeo Savernik { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 348141f38043SLeo Savernik .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 34825611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 34835611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3484c4f01a77SKeith Busch { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3485c4f01a77SKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 348602ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 348702ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 348889919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 348989919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349043047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 349143047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349243047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 349343047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349443047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 349543047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349643047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 349743047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3498dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3499dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3500538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3501538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 350270ce3455SChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 350370ce3455SChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3504a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3505a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3506a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3507a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 35083765fad5SStefan Reiter { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 35093765fad5SStefan Reiter .driver_data = NVME_QUIRK_BOGUS_NID, }, 3510f37527a0SDennis P. Kliem { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3511f37527a0SDennis P. Kliem .driver_data = NVME_QUIRK_BOGUS_NID, }, 35126b961bceSNing Wang { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 35136b961bceSNing Wang .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3514d6c52fa3STobias Gruetzmacher { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3515d6c52fa3STobias Gruetzmacher .driver_data = NVME_QUIRK_BOGUS_NID, }, 35164bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 35174bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35184bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 35194bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35204bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 35214bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35224bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 35234bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35244bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 35254bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35264bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 35274bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 352898f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 352998f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3530124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 353166341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 353266341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3533d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3534a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3535a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 35360b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 353757dacad5SJay Sternberg { 0, } 353857dacad5SJay Sternberg }; 353957dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 354057dacad5SJay Sternberg 354157dacad5SJay Sternberg static struct pci_driver nvme_driver = { 354257dacad5SJay Sternberg .name = "nvme", 354357dacad5SJay Sternberg .id_table = nvme_id_table, 354457dacad5SJay Sternberg .probe = nvme_probe, 354557dacad5SJay Sternberg .remove = nvme_remove, 354657dacad5SJay Sternberg .shutdown = nvme_shutdown, 3547d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 354857dacad5SJay Sternberg .driver = { 354957dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 355057dacad5SJay Sternberg }, 3551d916b1beSKeith Busch #endif 355274d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 355357dacad5SJay Sternberg .err_handler = &nvme_err_handler, 355457dacad5SJay Sternberg }; 355557dacad5SJay Sternberg 355657dacad5SJay Sternberg static int __init nvme_init(void) 355757dacad5SJay Sternberg { 355881101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 355981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 356081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3561612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 356217c33167SKeith Busch 35639a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 356457dacad5SJay Sternberg } 356557dacad5SJay Sternberg 356657dacad5SJay Sternberg static void __exit nvme_exit(void) 356757dacad5SJay Sternberg { 356857dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 356903e0f3a6SMing Lei flush_workqueue(nvme_wq); 357057dacad5SJay Sternberg } 357157dacad5SJay Sternberg 357257dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 357357dacad5SJay Sternberg MODULE_LICENSE("GPL"); 357457dacad5SJay Sternberg MODULE_VERSION("1.0"); 357557dacad5SJay Sternberg module_init(nvme_init); 357657dacad5SJay Sternberg module_exit(nvme_exit); 3577