157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1657dacad5SJay Sternberg #include <linux/bitops.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 2757dacad5SJay Sternberg #include <linux/pci.h> 2857dacad5SJay Sternberg #include <linux/poison.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 302d55cd5fSChristoph Hellwig #include <linux/timer.h> 3157dacad5SJay Sternberg #include <linux/types.h> 329cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 331d277a63SKeith Busch #include <asm/unaligned.h> 34a98e58e5SScott Bauer #include <linux/sed-opal.h> 3557dacad5SJay Sternberg 3657dacad5SJay Sternberg #include "nvme.h" 3757dacad5SJay Sternberg 3857dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3957dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 4057dacad5SJay Sternberg 41adf68f21SChristoph Hellwig /* 42adf68f21SChristoph Hellwig * We handle AEN commands ourselves and don't even let the 43adf68f21SChristoph Hellwig * block layer know about them. 44adf68f21SChristoph Hellwig */ 45f866fc42SChristoph Hellwig #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) 46adf68f21SChristoph Hellwig 4757dacad5SJay Sternberg static int use_threaded_interrupts; 4857dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4957dacad5SJay Sternberg 5057dacad5SJay Sternberg static bool use_cmb_sqes = true; 5157dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 5257dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5357dacad5SJay Sternberg 5487ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5587ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5687ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5787ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5857dacad5SJay Sternberg 59b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 60b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 61b27c1e68Sweiping zhang .set = io_queue_depth_set, 62b27c1e68Sweiping zhang .get = param_get_int, 63b27c1e68Sweiping zhang }; 64b27c1e68Sweiping zhang 65b27c1e68Sweiping zhang static int io_queue_depth = 1024; 66b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 67b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 68b27c1e68Sweiping zhang 691c63dc66SChristoph Hellwig struct nvme_dev; 701c63dc66SChristoph Hellwig struct nvme_queue; 7157dacad5SJay Sternberg 72a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq); 73a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 7457dacad5SJay Sternberg 7557dacad5SJay Sternberg /* 761c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 771c63dc66SChristoph Hellwig */ 781c63dc66SChristoph Hellwig struct nvme_dev { 791c63dc66SChristoph Hellwig struct nvme_queue **queues; 801c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 811c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 821c63dc66SChristoph Hellwig u32 __iomem *dbs; 831c63dc66SChristoph Hellwig struct device *dev; 841c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 851c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 861c63dc66SChristoph Hellwig unsigned online_queues; 871c63dc66SChristoph Hellwig unsigned max_qid; 881c63dc66SChristoph Hellwig int q_depth; 891c63dc66SChristoph Hellwig u32 db_stride; 901c63dc66SChristoph Hellwig void __iomem *bar; 9197f6ef64SXu Yu unsigned long bar_mapped_size; 925c8809e6SChristoph Hellwig struct work_struct remove_work; 9377bf25eaSKeith Busch struct mutex shutdown_lock; 941c63dc66SChristoph Hellwig bool subsystem; 951c63dc66SChristoph Hellwig void __iomem *cmb; 961c63dc66SChristoph Hellwig dma_addr_t cmb_dma_addr; 971c63dc66SChristoph Hellwig u64 cmb_size; 981c63dc66SChristoph Hellwig u32 cmbsz; 99202021c1SStephen Bates u32 cmbloc; 1001c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 101db3cbfffSKeith Busch struct completion ioq_wait; 10287ad72a5SChristoph Hellwig 10387ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 104f9f38e33SHelen Koike u32 *dbbuf_dbs; 105f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 106f9f38e33SHelen Koike u32 *dbbuf_eis; 107f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 10887ad72a5SChristoph Hellwig 10987ad72a5SChristoph Hellwig /* host memory buffer support: */ 11087ad72a5SChristoph Hellwig u64 host_mem_size; 11187ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 11287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 11387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 11457dacad5SJay Sternberg }; 11557dacad5SJay Sternberg 116b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 117b27c1e68Sweiping zhang { 118b27c1e68Sweiping zhang int n = 0, ret; 119b27c1e68Sweiping zhang 120b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 121b27c1e68Sweiping zhang if (ret != 0 || n < 2) 122b27c1e68Sweiping zhang return -EINVAL; 123b27c1e68Sweiping zhang 124b27c1e68Sweiping zhang return param_set_int(val, kp); 125b27c1e68Sweiping zhang } 126b27c1e68Sweiping zhang 127f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 128f9f38e33SHelen Koike { 129f9f38e33SHelen Koike return qid * 2 * stride; 130f9f38e33SHelen Koike } 131f9f38e33SHelen Koike 132f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 133f9f38e33SHelen Koike { 134f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 135f9f38e33SHelen Koike } 136f9f38e33SHelen Koike 1371c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1381c63dc66SChristoph Hellwig { 1391c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1401c63dc66SChristoph Hellwig } 1411c63dc66SChristoph Hellwig 14257dacad5SJay Sternberg /* 14357dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14457dacad5SJay Sternberg * commands and one for I/O commands). 14557dacad5SJay Sternberg */ 14657dacad5SJay Sternberg struct nvme_queue { 14757dacad5SJay Sternberg struct device *q_dmadev; 14857dacad5SJay Sternberg struct nvme_dev *dev; 14957dacad5SJay Sternberg spinlock_t q_lock; 15057dacad5SJay Sternberg struct nvme_command *sq_cmds; 15157dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 15257dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15357dacad5SJay Sternberg struct blk_mq_tags **tags; 15457dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15557dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15657dacad5SJay Sternberg u32 __iomem *q_db; 15757dacad5SJay Sternberg u16 q_depth; 15857dacad5SJay Sternberg s16 cq_vector; 15957dacad5SJay Sternberg u16 sq_tail; 16057dacad5SJay Sternberg u16 cq_head; 16157dacad5SJay Sternberg u16 qid; 16257dacad5SJay Sternberg u8 cq_phase; 16357dacad5SJay Sternberg u8 cqe_seen; 164f9f38e33SHelen Koike u32 *dbbuf_sq_db; 165f9f38e33SHelen Koike u32 *dbbuf_cq_db; 166f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 167f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 16857dacad5SJay Sternberg }; 16957dacad5SJay Sternberg 17057dacad5SJay Sternberg /* 17171bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 17271bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 173f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17471bd150cSChristoph Hellwig * allocated to store the PRP list. 17571bd150cSChristoph Hellwig */ 17671bd150cSChristoph Hellwig struct nvme_iod { 177d49187e9SChristoph Hellwig struct nvme_request req; 178f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 179f4800d6dSChristoph Hellwig int aborted; 18071bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 18171bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 18271bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18371bd150cSChristoph Hellwig dma_addr_t first_dma; 184bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 185f4800d6dSChristoph Hellwig struct scatterlist *sg; 186f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 18757dacad5SJay Sternberg }; 18857dacad5SJay Sternberg 18957dacad5SJay Sternberg /* 19057dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 19157dacad5SJay Sternberg */ 19257dacad5SJay Sternberg static inline void _nvme_check_size(void) 19357dacad5SJay Sternberg { 19457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2020add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2030add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 20457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 206f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 207f9f38e33SHelen Koike } 208f9f38e33SHelen Koike 209f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 210f9f38e33SHelen Koike { 211f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 212f9f38e33SHelen Koike } 213f9f38e33SHelen Koike 214f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 215f9f38e33SHelen Koike { 216f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 217f9f38e33SHelen Koike 218f9f38e33SHelen Koike if (dev->dbbuf_dbs) 219f9f38e33SHelen Koike return 0; 220f9f38e33SHelen Koike 221f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 222f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 223f9f38e33SHelen Koike GFP_KERNEL); 224f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 225f9f38e33SHelen Koike return -ENOMEM; 226f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 227f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 228f9f38e33SHelen Koike GFP_KERNEL); 229f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 230f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 231f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 232f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 233f9f38e33SHelen Koike return -ENOMEM; 234f9f38e33SHelen Koike } 235f9f38e33SHelen Koike 236f9f38e33SHelen Koike return 0; 237f9f38e33SHelen Koike } 238f9f38e33SHelen Koike 239f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 240f9f38e33SHelen Koike { 241f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 242f9f38e33SHelen Koike 243f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 244f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 245f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 246f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 247f9f38e33SHelen Koike } 248f9f38e33SHelen Koike if (dev->dbbuf_eis) { 249f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 250f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 251f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 252f9f38e33SHelen Koike } 253f9f38e33SHelen Koike } 254f9f38e33SHelen Koike 255f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 256f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 257f9f38e33SHelen Koike { 258f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 259f9f38e33SHelen Koike return; 260f9f38e33SHelen Koike 261f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 262f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 263f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 264f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 265f9f38e33SHelen Koike } 266f9f38e33SHelen Koike 267f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 268f9f38e33SHelen Koike { 269f9f38e33SHelen Koike struct nvme_command c; 270f9f38e33SHelen Koike 271f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 272f9f38e33SHelen Koike return; 273f9f38e33SHelen Koike 274f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 275f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 276f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 277f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 278f9f38e33SHelen Koike 279f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2809bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 281f9f38e33SHelen Koike /* Free memory and continue on */ 282f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 283f9f38e33SHelen Koike } 284f9f38e33SHelen Koike } 285f9f38e33SHelen Koike 286f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 287f9f38e33SHelen Koike { 288f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 289f9f38e33SHelen Koike } 290f9f38e33SHelen Koike 291f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 292f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 293f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 294f9f38e33SHelen Koike { 295f9f38e33SHelen Koike if (dbbuf_db) { 296f9f38e33SHelen Koike u16 old_value; 297f9f38e33SHelen Koike 298f9f38e33SHelen Koike /* 299f9f38e33SHelen Koike * Ensure that the queue is written before updating 300f9f38e33SHelen Koike * the doorbell in memory 301f9f38e33SHelen Koike */ 302f9f38e33SHelen Koike wmb(); 303f9f38e33SHelen Koike 304f9f38e33SHelen Koike old_value = *dbbuf_db; 305f9f38e33SHelen Koike *dbbuf_db = value; 306f9f38e33SHelen Koike 307f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 308f9f38e33SHelen Koike return false; 309f9f38e33SHelen Koike } 310f9f38e33SHelen Koike 311f9f38e33SHelen Koike return true; 31257dacad5SJay Sternberg } 31357dacad5SJay Sternberg 31457dacad5SJay Sternberg /* 31557dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31657dacad5SJay Sternberg */ 31757dacad5SJay Sternberg #define NVME_INT_PAGES 2 3185fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 31957dacad5SJay Sternberg 32057dacad5SJay Sternberg /* 32157dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 32257dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32357dacad5SJay Sternberg * the I/O. 32457dacad5SJay Sternberg */ 32557dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32657dacad5SJay Sternberg { 3275fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3285fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 32957dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 33057dacad5SJay Sternberg } 33157dacad5SJay Sternberg 332f4800d6dSChristoph Hellwig static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, 333f4800d6dSChristoph Hellwig unsigned int size, unsigned int nseg) 334f4800d6dSChristoph Hellwig { 335f4800d6dSChristoph Hellwig return sizeof(__le64 *) * nvme_npages(size, dev) + 336f4800d6dSChristoph Hellwig sizeof(struct scatterlist) * nseg; 337f4800d6dSChristoph Hellwig } 338f4800d6dSChristoph Hellwig 33957dacad5SJay Sternberg static unsigned int nvme_cmd_size(struct nvme_dev *dev) 34057dacad5SJay Sternberg { 341f4800d6dSChristoph Hellwig return sizeof(struct nvme_iod) + 342f4800d6dSChristoph Hellwig nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); 34357dacad5SJay Sternberg } 34457dacad5SJay Sternberg 34557dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 34657dacad5SJay Sternberg unsigned int hctx_idx) 34757dacad5SJay Sternberg { 34857dacad5SJay Sternberg struct nvme_dev *dev = data; 34957dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[0]; 35057dacad5SJay Sternberg 35157dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 35257dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 35357dacad5SJay Sternberg WARN_ON(nvmeq->tags); 35457dacad5SJay Sternberg 35557dacad5SJay Sternberg hctx->driver_data = nvmeq; 35657dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 35757dacad5SJay Sternberg return 0; 35857dacad5SJay Sternberg } 35957dacad5SJay Sternberg 36057dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 36157dacad5SJay Sternberg { 36257dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 36357dacad5SJay Sternberg 36457dacad5SJay Sternberg nvmeq->tags = NULL; 36557dacad5SJay Sternberg } 36657dacad5SJay Sternberg 36757dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 36857dacad5SJay Sternberg unsigned int hctx_idx) 36957dacad5SJay Sternberg { 37057dacad5SJay Sternberg struct nvme_dev *dev = data; 37157dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 37257dacad5SJay Sternberg 37357dacad5SJay Sternberg if (!nvmeq->tags) 37457dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 37757dacad5SJay Sternberg hctx->driver_data = nvmeq; 37857dacad5SJay Sternberg return 0; 37957dacad5SJay Sternberg } 38057dacad5SJay Sternberg 381d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 382d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 38357dacad5SJay Sternberg { 384d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 385f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 3860350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 3870350815aSChristoph Hellwig struct nvme_queue *nvmeq = dev->queues[queue_idx]; 38857dacad5SJay Sternberg 38957dacad5SJay Sternberg BUG_ON(!nvmeq); 390f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 39157dacad5SJay Sternberg return 0; 39257dacad5SJay Sternberg } 39357dacad5SJay Sternberg 394dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 395dca51e78SChristoph Hellwig { 396dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 397dca51e78SChristoph Hellwig 398dca51e78SChristoph Hellwig return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); 399dca51e78SChristoph Hellwig } 400dca51e78SChristoph Hellwig 40157dacad5SJay Sternberg /** 402adf68f21SChristoph Hellwig * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 40357dacad5SJay Sternberg * @nvmeq: The queue to use 40457dacad5SJay Sternberg * @cmd: The command to send 40557dacad5SJay Sternberg * 40657dacad5SJay Sternberg * Safe to use from interrupt context 40757dacad5SJay Sternberg */ 40857dacad5SJay Sternberg static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 40957dacad5SJay Sternberg struct nvme_command *cmd) 41057dacad5SJay Sternberg { 41157dacad5SJay Sternberg u16 tail = nvmeq->sq_tail; 41257dacad5SJay Sternberg 41357dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 41457dacad5SJay Sternberg memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 41557dacad5SJay Sternberg else 41657dacad5SJay Sternberg memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 41757dacad5SJay Sternberg 41857dacad5SJay Sternberg if (++tail == nvmeq->q_depth) 41957dacad5SJay Sternberg tail = 0; 420f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 421f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei)) 42257dacad5SJay Sternberg writel(tail, nvmeq->q_db); 42357dacad5SJay Sternberg nvmeq->sq_tail = tail; 42457dacad5SJay Sternberg } 42557dacad5SJay Sternberg 426f4800d6dSChristoph Hellwig static __le64 **iod_list(struct request *req) 42757dacad5SJay Sternberg { 428f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 429f9d03f96SChristoph Hellwig return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); 43057dacad5SJay Sternberg } 43157dacad5SJay Sternberg 432fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 43357dacad5SJay Sternberg { 434f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 435f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 436b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 437f4800d6dSChristoph Hellwig 438f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 439f4800d6dSChristoph Hellwig iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); 440f4800d6dSChristoph Hellwig if (!iod->sg) 441fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 442f4800d6dSChristoph Hellwig } else { 443f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 44457dacad5SJay Sternberg } 44557dacad5SJay Sternberg 446f4800d6dSChristoph Hellwig iod->aborted = 0; 44757dacad5SJay Sternberg iod->npages = -1; 44857dacad5SJay Sternberg iod->nents = 0; 449f4800d6dSChristoph Hellwig iod->length = size; 450f80ec966SKeith Busch 451fc17b653SChristoph Hellwig return BLK_STS_OK; 45257dacad5SJay Sternberg } 45357dacad5SJay Sternberg 454f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 45557dacad5SJay Sternberg { 456f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4575fd4ce1bSChristoph Hellwig const int last_prp = dev->ctrl.page_size / 8 - 1; 45857dacad5SJay Sternberg int i; 459f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 46057dacad5SJay Sternberg dma_addr_t prp_dma = iod->first_dma; 46157dacad5SJay Sternberg 46257dacad5SJay Sternberg if (iod->npages == 0) 46357dacad5SJay Sternberg dma_pool_free(dev->prp_small_pool, list[0], prp_dma); 46457dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 46557dacad5SJay Sternberg __le64 *prp_list = list[i]; 46657dacad5SJay Sternberg dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); 46757dacad5SJay Sternberg dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); 46857dacad5SJay Sternberg prp_dma = next_prp_dma; 46957dacad5SJay Sternberg } 47057dacad5SJay Sternberg 471f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 472f4800d6dSChristoph Hellwig kfree(iod->sg); 47357dacad5SJay Sternberg } 47457dacad5SJay Sternberg 47557dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 47657dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 47757dacad5SJay Sternberg { 47857dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 47957dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 48057dacad5SJay Sternberg } 48157dacad5SJay Sternberg 48257dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 48357dacad5SJay Sternberg { 48457dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 48557dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 48657dacad5SJay Sternberg } 48757dacad5SJay Sternberg 48857dacad5SJay Sternberg /** 48957dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 49057dacad5SJay Sternberg * 49157dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 49257dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 49357dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 49457dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 49557dacad5SJay Sternberg * 49657dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 49757dacad5SJay Sternberg */ 49857dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 49957dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 50057dacad5SJay Sternberg { 50157dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 50257dacad5SJay Sternberg struct bio_integrity_payload *bip; 50357dacad5SJay Sternberg struct t10_pi_tuple *pi; 50457dacad5SJay Sternberg void *p, *pmap; 50557dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 50657dacad5SJay Sternberg 50757dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 50857dacad5SJay Sternberg return; 50957dacad5SJay Sternberg 51057dacad5SJay Sternberg bip = bio_integrity(req->bio); 51157dacad5SJay Sternberg if (!bip) 51257dacad5SJay Sternberg return; 51357dacad5SJay Sternberg 51457dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 51557dacad5SJay Sternberg 51657dacad5SJay Sternberg p = pmap; 51757dacad5SJay Sternberg virt = bip_get_seed(bip); 51857dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 51957dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 520ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 52157dacad5SJay Sternberg 52257dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 52357dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 52457dacad5SJay Sternberg dif_swap(phys, virt, pi); 52557dacad5SJay Sternberg p += ts; 52657dacad5SJay Sternberg } 52757dacad5SJay Sternberg kunmap_atomic(pmap); 52857dacad5SJay Sternberg } 52957dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 53057dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 53157dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 53257dacad5SJay Sternberg { 53357dacad5SJay Sternberg } 53457dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 53557dacad5SJay Sternberg { 53657dacad5SJay Sternberg } 53757dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 53857dacad5SJay Sternberg { 53957dacad5SJay Sternberg } 54057dacad5SJay Sternberg #endif 54157dacad5SJay Sternberg 54286eea289SKeith Busch static blk_status_t nvme_setup_prps(struct nvme_dev *dev, struct request *req) 54357dacad5SJay Sternberg { 544f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 54557dacad5SJay Sternberg struct dma_pool *pool; 546b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 54757dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 54857dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 54957dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5505fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 55157dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 55257dacad5SJay Sternberg __le64 *prp_list; 553f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 55457dacad5SJay Sternberg dma_addr_t prp_dma; 55557dacad5SJay Sternberg int nprps, i; 55657dacad5SJay Sternberg 55757dacad5SJay Sternberg length -= (page_size - offset); 558*5228b328SJan H. Schönherr if (length <= 0) { 559*5228b328SJan H. Schönherr iod->first_dma = 0; 56086eea289SKeith Busch return BLK_STS_OK; 561*5228b328SJan H. Schönherr } 56257dacad5SJay Sternberg 56357dacad5SJay Sternberg dma_len -= (page_size - offset); 56457dacad5SJay Sternberg if (dma_len) { 56557dacad5SJay Sternberg dma_addr += (page_size - offset); 56657dacad5SJay Sternberg } else { 56757dacad5SJay Sternberg sg = sg_next(sg); 56857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 56957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 57057dacad5SJay Sternberg } 57157dacad5SJay Sternberg 57257dacad5SJay Sternberg if (length <= page_size) { 57357dacad5SJay Sternberg iod->first_dma = dma_addr; 57486eea289SKeith Busch return BLK_STS_OK; 57557dacad5SJay Sternberg } 57657dacad5SJay Sternberg 57757dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 57857dacad5SJay Sternberg if (nprps <= (256 / 8)) { 57957dacad5SJay Sternberg pool = dev->prp_small_pool; 58057dacad5SJay Sternberg iod->npages = 0; 58157dacad5SJay Sternberg } else { 58257dacad5SJay Sternberg pool = dev->prp_page_pool; 58357dacad5SJay Sternberg iod->npages = 1; 58457dacad5SJay Sternberg } 58557dacad5SJay Sternberg 58669d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 58757dacad5SJay Sternberg if (!prp_list) { 58857dacad5SJay Sternberg iod->first_dma = dma_addr; 58957dacad5SJay Sternberg iod->npages = -1; 59086eea289SKeith Busch return BLK_STS_RESOURCE; 59157dacad5SJay Sternberg } 59257dacad5SJay Sternberg list[0] = prp_list; 59357dacad5SJay Sternberg iod->first_dma = prp_dma; 59457dacad5SJay Sternberg i = 0; 59557dacad5SJay Sternberg for (;;) { 59657dacad5SJay Sternberg if (i == page_size >> 3) { 59757dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 59869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 59957dacad5SJay Sternberg if (!prp_list) 60086eea289SKeith Busch return BLK_STS_RESOURCE; 60157dacad5SJay Sternberg list[iod->npages++] = prp_list; 60257dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 60357dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 60457dacad5SJay Sternberg i = 1; 60557dacad5SJay Sternberg } 60657dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 60757dacad5SJay Sternberg dma_len -= page_size; 60857dacad5SJay Sternberg dma_addr += page_size; 60957dacad5SJay Sternberg length -= page_size; 61057dacad5SJay Sternberg if (length <= 0) 61157dacad5SJay Sternberg break; 61257dacad5SJay Sternberg if (dma_len > 0) 61357dacad5SJay Sternberg continue; 61486eea289SKeith Busch if (unlikely(dma_len < 0)) 61586eea289SKeith Busch goto bad_sgl; 61657dacad5SJay Sternberg sg = sg_next(sg); 61757dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 61857dacad5SJay Sternberg dma_len = sg_dma_len(sg); 61957dacad5SJay Sternberg } 62057dacad5SJay Sternberg 62186eea289SKeith Busch return BLK_STS_OK; 62286eea289SKeith Busch 62386eea289SKeith Busch bad_sgl: 62486eea289SKeith Busch if (WARN_ONCE(1, "Invalid SGL for payload:%d nents:%d\n", 62586eea289SKeith Busch blk_rq_payload_bytes(req), iod->nents)) { 62686eea289SKeith Busch for_each_sg(iod->sg, sg, iod->nents, i) { 62786eea289SKeith Busch dma_addr_t phys = sg_phys(sg); 62886eea289SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 62986eea289SKeith Busch "dma_address:%pad dma_length:%d\n", i, &phys, 63086eea289SKeith Busch sg->offset, sg->length, 63186eea289SKeith Busch &sg_dma_address(sg), 63286eea289SKeith Busch sg_dma_len(sg)); 63386eea289SKeith Busch } 63486eea289SKeith Busch } 63586eea289SKeith Busch return BLK_STS_IOERR; 63686eea289SKeith Busch 63757dacad5SJay Sternberg } 63857dacad5SJay Sternberg 639fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 640b131c61dSChristoph Hellwig struct nvme_command *cmnd) 64157dacad5SJay Sternberg { 642f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 643ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 644ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 645ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 646fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 64757dacad5SJay Sternberg 648f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 649ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 650ba1ca37eSChristoph Hellwig if (!iod->nents) 651ba1ca37eSChristoph Hellwig goto out; 652ba1ca37eSChristoph Hellwig 653fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 6542b6b535dSMauricio Faria de Oliveira if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 6552b6b535dSMauricio Faria de Oliveira DMA_ATTR_NO_WARN)) 656ba1ca37eSChristoph Hellwig goto out; 657ba1ca37eSChristoph Hellwig 65886eea289SKeith Busch ret = nvme_setup_prps(dev, req); 65986eea289SKeith Busch if (ret != BLK_STS_OK) 660ba1ca37eSChristoph Hellwig goto out_unmap; 661ba1ca37eSChristoph Hellwig 662fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 663ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 664ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 665ba1ca37eSChristoph Hellwig goto out_unmap; 666ba1ca37eSChristoph Hellwig 667bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 668bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 669ba1ca37eSChristoph Hellwig goto out_unmap; 670ba1ca37eSChristoph Hellwig 671ba1ca37eSChristoph Hellwig if (rq_data_dir(req)) 672ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 673ba1ca37eSChristoph Hellwig 674bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 675ba1ca37eSChristoph Hellwig goto out_unmap; 67657dacad5SJay Sternberg } 67757dacad5SJay Sternberg 678eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 679eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); 680ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 681bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 682fc17b653SChristoph Hellwig return BLK_STS_OK; 683ba1ca37eSChristoph Hellwig 684ba1ca37eSChristoph Hellwig out_unmap: 685ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 686ba1ca37eSChristoph Hellwig out: 687ba1ca37eSChristoph Hellwig return ret; 68857dacad5SJay Sternberg } 68957dacad5SJay Sternberg 690f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 691d4f6c3abSChristoph Hellwig { 692f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 693d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 694d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 695d4f6c3abSChristoph Hellwig 696d4f6c3abSChristoph Hellwig if (iod->nents) { 697d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 698d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 699d4f6c3abSChristoph Hellwig if (!rq_data_dir(req)) 700d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 701bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 702d4f6c3abSChristoph Hellwig } 703d4f6c3abSChristoph Hellwig } 704d4f6c3abSChristoph Hellwig 705f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 706f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 70757dacad5SJay Sternberg } 70857dacad5SJay Sternberg 70957dacad5SJay Sternberg /* 71057dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 71157dacad5SJay Sternberg */ 712fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 71357dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 71457dacad5SJay Sternberg { 71557dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 71657dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 71757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 71857dacad5SJay Sternberg struct request *req = bd->rq; 719ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 720ebe6d874SChristoph Hellwig blk_status_t ret; 72157dacad5SJay Sternberg 722f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 723fc17b653SChristoph Hellwig if (ret) 724f4800d6dSChristoph Hellwig return ret; 72557dacad5SJay Sternberg 726b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 727fc17b653SChristoph Hellwig if (ret) 728f9d03f96SChristoph Hellwig goto out_free_cmd; 72957dacad5SJay Sternberg 730fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 731b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 732fc17b653SChristoph Hellwig if (ret) 733f9d03f96SChristoph Hellwig goto out_cleanup_iod; 734fc17b653SChristoph Hellwig } 735ba1ca37eSChristoph Hellwig 736aae239e1SChristoph Hellwig blk_mq_start_request(req); 737ba1ca37eSChristoph Hellwig 738ba1ca37eSChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 739ae1fba20SKeith Busch if (unlikely(nvmeq->cq_vector < 0)) { 740fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 741ae1fba20SKeith Busch spin_unlock_irq(&nvmeq->q_lock); 742f9d03f96SChristoph Hellwig goto out_cleanup_iod; 743ae1fba20SKeith Busch } 744ba1ca37eSChristoph Hellwig __nvme_submit_cmd(nvmeq, &cmnd); 74557dacad5SJay Sternberg nvme_process_cq(nvmeq); 74657dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 747fc17b653SChristoph Hellwig return BLK_STS_OK; 748f9d03f96SChristoph Hellwig out_cleanup_iod: 749f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 750f9d03f96SChristoph Hellwig out_free_cmd: 751f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 752ba1ca37eSChristoph Hellwig return ret; 75357dacad5SJay Sternberg } 75457dacad5SJay Sternberg 75577f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 756eee417b0SChristoph Hellwig { 757f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 758eee417b0SChristoph Hellwig 75977f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 76077f02a7aSChristoph Hellwig nvme_complete_rq(req); 76157dacad5SJay Sternberg } 76257dacad5SJay Sternberg 763d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 764d783e0bdSMarta Rybczynska static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, 765d783e0bdSMarta Rybczynska u16 phase) 766d783e0bdSMarta Rybczynska { 767d783e0bdSMarta Rybczynska return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; 768d783e0bdSMarta Rybczynska } 769d783e0bdSMarta Rybczynska 770eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 77157dacad5SJay Sternberg { 772eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 77357dacad5SJay Sternberg 774eb281c82SSagi Grimberg if (likely(nvmeq->cq_vector >= 0)) { 775eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 776eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 777eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 778eb281c82SSagi Grimberg } 77957dacad5SJay Sternberg } 780adf68f21SChristoph Hellwig 78183a12fb7SSagi Grimberg static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 78283a12fb7SSagi Grimberg struct nvme_completion *cqe) 78357dacad5SJay Sternberg { 78457dacad5SJay Sternberg struct request *req; 785adf68f21SChristoph Hellwig 78683a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 7871b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 788aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 78983a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 79083a12fb7SSagi Grimberg return; 791aae239e1SChristoph Hellwig } 792aae239e1SChristoph Hellwig 793adf68f21SChristoph Hellwig /* 794adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 795adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 796adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 797adf68f21SChristoph Hellwig * for them but rather special case them here. 798adf68f21SChristoph Hellwig */ 799adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 80083a12fb7SSagi Grimberg cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) { 8017bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 80283a12fb7SSagi Grimberg cqe->status, &cqe->result); 803a0fa9647SJens Axboe return; 80457dacad5SJay Sternberg } 80557dacad5SJay Sternberg 806e9d8a0fdSKeith Busch nvmeq->cqe_seen = 1; 80783a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 80883a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 80983a12fb7SSagi Grimberg } 81057dacad5SJay Sternberg 811920d13a8SSagi Grimberg static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, 812920d13a8SSagi Grimberg struct nvme_completion *cqe) 81383a12fb7SSagi Grimberg { 814920d13a8SSagi Grimberg if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { 815920d13a8SSagi Grimberg *cqe = nvmeq->cqes[nvmeq->cq_head]; 81683a12fb7SSagi Grimberg 817920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 818920d13a8SSagi Grimberg nvmeq->cq_head = 0; 819920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 820920d13a8SSagi Grimberg } 821920d13a8SSagi Grimberg return true; 822920d13a8SSagi Grimberg } 823920d13a8SSagi Grimberg return false; 824a0fa9647SJens Axboe } 825a0fa9647SJens Axboe 826a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq) 827a0fa9647SJens Axboe { 828920d13a8SSagi Grimberg struct nvme_completion cqe; 829920d13a8SSagi Grimberg int consumed = 0; 83083a12fb7SSagi Grimberg 831920d13a8SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 83283a12fb7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 833920d13a8SSagi Grimberg consumed++; 83457dacad5SJay Sternberg } 83557dacad5SJay Sternberg 836e9d8a0fdSKeith Busch if (consumed) 837eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 83857dacad5SJay Sternberg } 83957dacad5SJay Sternberg 84057dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 84157dacad5SJay Sternberg { 84257dacad5SJay Sternberg irqreturn_t result; 84357dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 84457dacad5SJay Sternberg spin_lock(&nvmeq->q_lock); 84557dacad5SJay Sternberg nvme_process_cq(nvmeq); 84657dacad5SJay Sternberg result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 84757dacad5SJay Sternberg nvmeq->cqe_seen = 0; 84857dacad5SJay Sternberg spin_unlock(&nvmeq->q_lock); 84957dacad5SJay Sternberg return result; 85057dacad5SJay Sternberg } 85157dacad5SJay Sternberg 85257dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 85357dacad5SJay Sternberg { 85457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 855d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 85657dacad5SJay Sternberg return IRQ_WAKE_THREAD; 857d783e0bdSMarta Rybczynska return IRQ_NONE; 85857dacad5SJay Sternberg } 85957dacad5SJay Sternberg 8607776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 861a0fa9647SJens Axboe { 862442e19b7SSagi Grimberg struct nvme_completion cqe; 863442e19b7SSagi Grimberg int found = 0, consumed = 0; 864a0fa9647SJens Axboe 865442e19b7SSagi Grimberg if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 866442e19b7SSagi Grimberg return 0; 867442e19b7SSagi Grimberg 868442e19b7SSagi Grimberg spin_lock_irq(&nvmeq->q_lock); 869442e19b7SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 870442e19b7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 871442e19b7SSagi Grimberg consumed++; 872442e19b7SSagi Grimberg 873442e19b7SSagi Grimberg if (tag == cqe.command_id) { 874442e19b7SSagi Grimberg found = 1; 875442e19b7SSagi Grimberg break; 876442e19b7SSagi Grimberg } 877a0fa9647SJens Axboe } 878a0fa9647SJens Axboe 879442e19b7SSagi Grimberg if (consumed) 880442e19b7SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 881442e19b7SSagi Grimberg spin_unlock_irq(&nvmeq->q_lock); 882442e19b7SSagi Grimberg 883442e19b7SSagi Grimberg return found; 884a0fa9647SJens Axboe } 885a0fa9647SJens Axboe 8867776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 8877776db1cSKeith Busch { 8887776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 8897776db1cSKeith Busch 8907776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 8917776db1cSKeith Busch } 8927776db1cSKeith Busch 893f866fc42SChristoph Hellwig static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) 89457dacad5SJay Sternberg { 895f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 8969396dec9SChristoph Hellwig struct nvme_queue *nvmeq = dev->queues[0]; 89757dacad5SJay Sternberg struct nvme_command c; 89857dacad5SJay Sternberg 89957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 90057dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 901f866fc42SChristoph Hellwig c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; 90257dacad5SJay Sternberg 9039396dec9SChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 9049396dec9SChristoph Hellwig __nvme_submit_cmd(nvmeq, &c); 9059396dec9SChristoph Hellwig spin_unlock_irq(&nvmeq->q_lock); 90657dacad5SJay Sternberg } 90757dacad5SJay Sternberg 90857dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 90957dacad5SJay Sternberg { 91057dacad5SJay Sternberg struct nvme_command c; 91157dacad5SJay Sternberg 91257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 91357dacad5SJay Sternberg c.delete_queue.opcode = opcode; 91457dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 91557dacad5SJay Sternberg 9161c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 91757dacad5SJay Sternberg } 91857dacad5SJay Sternberg 91957dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 92057dacad5SJay Sternberg struct nvme_queue *nvmeq) 92157dacad5SJay Sternberg { 92257dacad5SJay Sternberg struct nvme_command c; 92357dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 92457dacad5SJay Sternberg 92557dacad5SJay Sternberg /* 92657dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 92757dacad5SJay Sternberg * is attached to the request. 92857dacad5SJay Sternberg */ 92957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 93057dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 93157dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 93257dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 93357dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 93457dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 93557dacad5SJay Sternberg c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 93657dacad5SJay Sternberg 9371c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 93857dacad5SJay Sternberg } 93957dacad5SJay Sternberg 94057dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 94157dacad5SJay Sternberg struct nvme_queue *nvmeq) 94257dacad5SJay Sternberg { 94357dacad5SJay Sternberg struct nvme_command c; 94481c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 94557dacad5SJay Sternberg 94657dacad5SJay Sternberg /* 94757dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 94857dacad5SJay Sternberg * is attached to the request. 94957dacad5SJay Sternberg */ 95057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 95157dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 95257dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 95357dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 95457dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 95557dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 95657dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 95757dacad5SJay Sternberg 9581c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 95957dacad5SJay Sternberg } 96057dacad5SJay Sternberg 96157dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 96257dacad5SJay Sternberg { 96357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 96457dacad5SJay Sternberg } 96557dacad5SJay Sternberg 96657dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 96757dacad5SJay Sternberg { 96857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 96957dacad5SJay Sternberg } 97057dacad5SJay Sternberg 9712a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 97257dacad5SJay Sternberg { 973f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 974f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 97557dacad5SJay Sternberg 97627fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 97727fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 978e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 979e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 98057dacad5SJay Sternberg } 98157dacad5SJay Sternberg 982b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 983b2a0eb1aSKeith Busch { 984b2a0eb1aSKeith Busch 985b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 986b2a0eb1aSKeith Busch * NVMe Subsystem reset. 987b2a0eb1aSKeith Busch */ 988b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 989b2a0eb1aSKeith Busch 990b2a0eb1aSKeith Busch /* If there is a reset ongoing, we shouldn't reset again. */ 991b2a0eb1aSKeith Busch if (dev->ctrl.state == NVME_CTRL_RESETTING) 992b2a0eb1aSKeith Busch return false; 993b2a0eb1aSKeith Busch 994b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 995b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 996b2a0eb1aSKeith Busch */ 997b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 998b2a0eb1aSKeith Busch return false; 999b2a0eb1aSKeith Busch 1000b2a0eb1aSKeith Busch /* If PCI error recovery process is happening, we cannot reset or 1001b2a0eb1aSKeith Busch * the recovery mechanism will surely fail. 1002b2a0eb1aSKeith Busch */ 1003b2a0eb1aSKeith Busch if (pci_channel_offline(to_pci_dev(dev->dev))) 1004b2a0eb1aSKeith Busch return false; 1005b2a0eb1aSKeith Busch 1006b2a0eb1aSKeith Busch return true; 1007b2a0eb1aSKeith Busch } 1008b2a0eb1aSKeith Busch 1009b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1010b2a0eb1aSKeith Busch { 1011b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1012b2a0eb1aSKeith Busch u16 pci_status; 1013b2a0eb1aSKeith Busch int result; 1014b2a0eb1aSKeith Busch 1015b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1016b2a0eb1aSKeith Busch &pci_status); 1017b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1018b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1019b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1020b2a0eb1aSKeith Busch csts, pci_status); 1021b2a0eb1aSKeith Busch else 1022b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1023b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1024b2a0eb1aSKeith Busch csts, result); 1025b2a0eb1aSKeith Busch } 1026b2a0eb1aSKeith Busch 102731c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 102857dacad5SJay Sternberg { 1029f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1030f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 103157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 103257dacad5SJay Sternberg struct request *abort_req; 103357dacad5SJay Sternberg struct nvme_command cmd; 1034b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1035b2a0eb1aSKeith Busch 1036b2a0eb1aSKeith Busch /* 1037b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1038b2a0eb1aSKeith Busch */ 1039b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1040b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1041b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1042d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1043b2a0eb1aSKeith Busch return BLK_EH_HANDLED; 1044b2a0eb1aSKeith Busch } 104557dacad5SJay Sternberg 104631c7c7d2SChristoph Hellwig /* 10477776db1cSKeith Busch * Did we miss an interrupt? 10487776db1cSKeith Busch */ 10497776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 10507776db1cSKeith Busch dev_warn(dev->ctrl.device, 10517776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 10527776db1cSKeith Busch req->tag, nvmeq->qid); 10537776db1cSKeith Busch return BLK_EH_HANDLED; 10547776db1cSKeith Busch } 10557776db1cSKeith Busch 10567776db1cSKeith Busch /* 1057fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1058fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1059fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1060fd634f41SChristoph Hellwig * shutdown, so we return BLK_EH_HANDLED. 1061fd634f41SChristoph Hellwig */ 1062bb8d261eSChristoph Hellwig if (dev->ctrl.state == NVME_CTRL_RESETTING) { 10631b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 1064fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1065fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1066a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 106727fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1068fd634f41SChristoph Hellwig return BLK_EH_HANDLED; 1069fd634f41SChristoph Hellwig } 1070fd634f41SChristoph Hellwig 1071fd634f41SChristoph Hellwig /* 1072e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1073e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1074e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 107531c7c7d2SChristoph Hellwig */ 1076f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 10771b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 107857dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 107957dacad5SJay Sternberg req->tag, nvmeq->qid); 1080a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1081d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1082e1569a16SKeith Busch 1083e1569a16SKeith Busch /* 1084e1569a16SKeith Busch * Mark the request as handled, since the inline shutdown 1085e1569a16SKeith Busch * forces all outstanding requests to complete. 1086e1569a16SKeith Busch */ 108727fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1088e1569a16SKeith Busch return BLK_EH_HANDLED; 108957dacad5SJay Sternberg } 109057dacad5SJay Sternberg 1091e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1092e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1093e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1094e7a2a87dSChristoph Hellwig } 10957bf7d778SKeith Busch iod->aborted = 1; 109657dacad5SJay Sternberg 109757dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 109857dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 109957dacad5SJay Sternberg cmd.abort.cid = req->tag; 110057dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 110157dacad5SJay Sternberg 11021b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 11031b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 110457dacad5SJay Sternberg req->tag, nvmeq->qid); 1105e7a2a87dSChristoph Hellwig 1106e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1107eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 11086bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 11096bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 111031c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 111157dacad5SJay Sternberg } 111257dacad5SJay Sternberg 1113e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1114e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1115e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 111657dacad5SJay Sternberg 111757dacad5SJay Sternberg /* 111857dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 111957dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 112057dacad5SJay Sternberg * as the device then is in a faulty state. 112157dacad5SJay Sternberg */ 112257dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 112357dacad5SJay Sternberg } 112457dacad5SJay Sternberg 112557dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 112657dacad5SJay Sternberg { 112757dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 112857dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 112957dacad5SJay Sternberg if (nvmeq->sq_cmds) 113057dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 113157dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 113257dacad5SJay Sternberg kfree(nvmeq); 113357dacad5SJay Sternberg } 113457dacad5SJay Sternberg 113557dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 113657dacad5SJay Sternberg { 113757dacad5SJay Sternberg int i; 113857dacad5SJay Sternberg 1139d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 114057dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[i]; 1141d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 114257dacad5SJay Sternberg dev->queues[i] = NULL; 114357dacad5SJay Sternberg nvme_free_queue(nvmeq); 114457dacad5SJay Sternberg } 114557dacad5SJay Sternberg } 114657dacad5SJay Sternberg 114757dacad5SJay Sternberg /** 114857dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 114957dacad5SJay Sternberg * @nvmeq - queue to suspend 115057dacad5SJay Sternberg */ 115157dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 115257dacad5SJay Sternberg { 115357dacad5SJay Sternberg int vector; 115457dacad5SJay Sternberg 115557dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 115657dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 115757dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 115857dacad5SJay Sternberg return 1; 115957dacad5SJay Sternberg } 11600ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 116157dacad5SJay Sternberg nvmeq->dev->online_queues--; 116257dacad5SJay Sternberg nvmeq->cq_vector = -1; 116357dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 116457dacad5SJay Sternberg 11651c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1166c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 116757dacad5SJay Sternberg 11680ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 116957dacad5SJay Sternberg 117057dacad5SJay Sternberg return 0; 117157dacad5SJay Sternberg } 117257dacad5SJay Sternberg 1173a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 117457dacad5SJay Sternberg { 1175a5cdb68cSKeith Busch struct nvme_queue *nvmeq = dev->queues[0]; 117657dacad5SJay Sternberg 117757dacad5SJay Sternberg if (!nvmeq) 117857dacad5SJay Sternberg return; 117957dacad5SJay Sternberg if (nvme_suspend_queue(nvmeq)) 118057dacad5SJay Sternberg return; 118157dacad5SJay Sternberg 1182a5cdb68cSKeith Busch if (shutdown) 1183a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1184a5cdb68cSKeith Busch else 118520d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 118657dacad5SJay Sternberg 118757dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 118857dacad5SJay Sternberg nvme_process_cq(nvmeq); 118957dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 119057dacad5SJay Sternberg } 119157dacad5SJay Sternberg 119257dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 119357dacad5SJay Sternberg int entry_size) 119457dacad5SJay Sternberg { 119557dacad5SJay Sternberg int q_depth = dev->q_depth; 11965fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 11975fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 119857dacad5SJay Sternberg 119957dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 120057dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 12015fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 120257dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 120357dacad5SJay Sternberg 120457dacad5SJay Sternberg /* 120557dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 120657dacad5SJay Sternberg * would be better to map queues in system memory with the 120757dacad5SJay Sternberg * original depth 120857dacad5SJay Sternberg */ 120957dacad5SJay Sternberg if (q_depth < 64) 121057dacad5SJay Sternberg return -ENOMEM; 121157dacad5SJay Sternberg } 121257dacad5SJay Sternberg 121357dacad5SJay Sternberg return q_depth; 121457dacad5SJay Sternberg } 121557dacad5SJay Sternberg 121657dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 121757dacad5SJay Sternberg int qid, int depth) 121857dacad5SJay Sternberg { 121957dacad5SJay Sternberg if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 12205fd4ce1bSChristoph Hellwig unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 12215fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 122257dacad5SJay Sternberg nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; 122357dacad5SJay Sternberg nvmeq->sq_cmds_io = dev->cmb + offset; 122457dacad5SJay Sternberg } else { 122557dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 122657dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 122757dacad5SJay Sternberg if (!nvmeq->sq_cmds) 122857dacad5SJay Sternberg return -ENOMEM; 122957dacad5SJay Sternberg } 123057dacad5SJay Sternberg 123157dacad5SJay Sternberg return 0; 123257dacad5SJay Sternberg } 123357dacad5SJay Sternberg 123457dacad5SJay Sternberg static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, 1235d3af3ecdSShaohua Li int depth, int node) 123657dacad5SJay Sternberg { 1237d3af3ecdSShaohua Li struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, 1238d3af3ecdSShaohua Li node); 123957dacad5SJay Sternberg if (!nvmeq) 124057dacad5SJay Sternberg return NULL; 124157dacad5SJay Sternberg 124257dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 124357dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 124457dacad5SJay Sternberg if (!nvmeq->cqes) 124557dacad5SJay Sternberg goto free_nvmeq; 124657dacad5SJay Sternberg 124757dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 124857dacad5SJay Sternberg goto free_cqdma; 124957dacad5SJay Sternberg 125057dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 125157dacad5SJay Sternberg nvmeq->dev = dev; 125257dacad5SJay Sternberg spin_lock_init(&nvmeq->q_lock); 125357dacad5SJay Sternberg nvmeq->cq_head = 0; 125457dacad5SJay Sternberg nvmeq->cq_phase = 1; 125557dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 125657dacad5SJay Sternberg nvmeq->q_depth = depth; 125757dacad5SJay Sternberg nvmeq->qid = qid; 125857dacad5SJay Sternberg nvmeq->cq_vector = -1; 125957dacad5SJay Sternberg dev->queues[qid] = nvmeq; 1260d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 126157dacad5SJay Sternberg 126257dacad5SJay Sternberg return nvmeq; 126357dacad5SJay Sternberg 126457dacad5SJay Sternberg free_cqdma: 126557dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 126657dacad5SJay Sternberg nvmeq->cq_dma_addr); 126757dacad5SJay Sternberg free_nvmeq: 126857dacad5SJay Sternberg kfree(nvmeq); 126957dacad5SJay Sternberg return NULL; 127057dacad5SJay Sternberg } 127157dacad5SJay Sternberg 1272dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 127357dacad5SJay Sternberg { 12740ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 12750ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 12760ff199cbSChristoph Hellwig 12770ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 12780ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 12790ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12800ff199cbSChristoph Hellwig } else { 12810ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 12820ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12830ff199cbSChristoph Hellwig } 128457dacad5SJay Sternberg } 128557dacad5SJay Sternberg 128657dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 128757dacad5SJay Sternberg { 128857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 128957dacad5SJay Sternberg 129057dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 129157dacad5SJay Sternberg nvmeq->sq_tail = 0; 129257dacad5SJay Sternberg nvmeq->cq_head = 0; 129357dacad5SJay Sternberg nvmeq->cq_phase = 1; 129457dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 129557dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1296f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 129757dacad5SJay Sternberg dev->online_queues++; 129857dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 129957dacad5SJay Sternberg } 130057dacad5SJay Sternberg 130157dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 130257dacad5SJay Sternberg { 130357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 130457dacad5SJay Sternberg int result; 130557dacad5SJay Sternberg 130657dacad5SJay Sternberg nvmeq->cq_vector = qid - 1; 130757dacad5SJay Sternberg result = adapter_alloc_cq(dev, qid, nvmeq); 130857dacad5SJay Sternberg if (result < 0) 130957dacad5SJay Sternberg return result; 131057dacad5SJay Sternberg 131157dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 131257dacad5SJay Sternberg if (result < 0) 131357dacad5SJay Sternberg goto release_cq; 131457dacad5SJay Sternberg 1315dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 131657dacad5SJay Sternberg if (result < 0) 131757dacad5SJay Sternberg goto release_sq; 131857dacad5SJay Sternberg 131957dacad5SJay Sternberg nvme_init_queue(nvmeq, qid); 132057dacad5SJay Sternberg return result; 132157dacad5SJay Sternberg 132257dacad5SJay Sternberg release_sq: 132357dacad5SJay Sternberg adapter_delete_sq(dev, qid); 132457dacad5SJay Sternberg release_cq: 132557dacad5SJay Sternberg adapter_delete_cq(dev, qid); 132657dacad5SJay Sternberg return result; 132757dacad5SJay Sternberg } 132857dacad5SJay Sternberg 1329f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 133057dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 133177f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 133257dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 133357dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 13340350815aSChristoph Hellwig .init_request = nvme_init_request, 133557dacad5SJay Sternberg .timeout = nvme_timeout, 133657dacad5SJay Sternberg }; 133757dacad5SJay Sternberg 1338f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 133957dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 134077f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 134157dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 134257dacad5SJay Sternberg .init_request = nvme_init_request, 1343dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 134457dacad5SJay Sternberg .timeout = nvme_timeout, 1345a0fa9647SJens Axboe .poll = nvme_poll, 134657dacad5SJay Sternberg }; 134757dacad5SJay Sternberg 134857dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 134957dacad5SJay Sternberg { 13501c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 135169d9a99cSKeith Busch /* 135269d9a99cSKeith Busch * If the controller was reset during removal, it's possible 135369d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 135469d9a99cSKeith Busch * queue to flush these to completion. 135569d9a99cSKeith Busch */ 1356c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 13571c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 135857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 135957dacad5SJay Sternberg } 136057dacad5SJay Sternberg } 136157dacad5SJay Sternberg 136257dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 136357dacad5SJay Sternberg { 13641c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 136557dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 136657dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1367e3e9d50cSKeith Busch 1368e3e9d50cSKeith Busch /* 1369e3e9d50cSKeith Busch * Subtract one to leave an empty queue entry for 'Full Queue' 1370e3e9d50cSKeith Busch * condition. See NVM-Express 1.2 specification, section 4.1.2. 1371e3e9d50cSKeith Busch */ 1372e3e9d50cSKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; 137357dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 137457dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 137557dacad5SJay Sternberg dev->admin_tagset.cmd_size = nvme_cmd_size(dev); 1376d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 137757dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 137857dacad5SJay Sternberg 137957dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 138057dacad5SJay Sternberg return -ENOMEM; 138134b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 138257dacad5SJay Sternberg 13831c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 13841c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 138557dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 138657dacad5SJay Sternberg return -ENOMEM; 138757dacad5SJay Sternberg } 13881c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 138957dacad5SJay Sternberg nvme_dev_remove_admin(dev); 13901c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 139157dacad5SJay Sternberg return -ENODEV; 139257dacad5SJay Sternberg } 139357dacad5SJay Sternberg } else 1394c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 139557dacad5SJay Sternberg 139657dacad5SJay Sternberg return 0; 139757dacad5SJay Sternberg } 139857dacad5SJay Sternberg 139997f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 140097f6ef64SXu Yu { 140197f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 140297f6ef64SXu Yu } 140397f6ef64SXu Yu 140497f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 140597f6ef64SXu Yu { 140697f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 140797f6ef64SXu Yu 140897f6ef64SXu Yu if (size <= dev->bar_mapped_size) 140997f6ef64SXu Yu return 0; 141097f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 141197f6ef64SXu Yu return -ENOMEM; 141297f6ef64SXu Yu if (dev->bar) 141397f6ef64SXu Yu iounmap(dev->bar); 141497f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 141597f6ef64SXu Yu if (!dev->bar) { 141697f6ef64SXu Yu dev->bar_mapped_size = 0; 141797f6ef64SXu Yu return -ENOMEM; 141897f6ef64SXu Yu } 141997f6ef64SXu Yu dev->bar_mapped_size = size; 142097f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 142197f6ef64SXu Yu 142297f6ef64SXu Yu return 0; 142397f6ef64SXu Yu } 142497f6ef64SXu Yu 142501ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 142657dacad5SJay Sternberg { 142757dacad5SJay Sternberg int result; 142857dacad5SJay Sternberg u32 aqa; 142957dacad5SJay Sternberg struct nvme_queue *nvmeq; 143057dacad5SJay Sternberg 143197f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 143297f6ef64SXu Yu if (result < 0) 143397f6ef64SXu Yu return result; 143497f6ef64SXu Yu 14358ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 143620d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 143757dacad5SJay Sternberg 14387a67cbeaSChristoph Hellwig if (dev->subsystem && 14397a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 14407a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 144157dacad5SJay Sternberg 144220d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 144357dacad5SJay Sternberg if (result < 0) 144457dacad5SJay Sternberg return result; 144557dacad5SJay Sternberg 144657dacad5SJay Sternberg nvmeq = dev->queues[0]; 144757dacad5SJay Sternberg if (!nvmeq) { 1448d3af3ecdSShaohua Li nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 1449d3af3ecdSShaohua Li dev_to_node(dev->dev)); 145057dacad5SJay Sternberg if (!nvmeq) 145157dacad5SJay Sternberg return -ENOMEM; 145257dacad5SJay Sternberg } 145357dacad5SJay Sternberg 145457dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 145557dacad5SJay Sternberg aqa |= aqa << 16; 145657dacad5SJay Sternberg 14577a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 14587a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 14597a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 146057dacad5SJay Sternberg 146120d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 146257dacad5SJay Sternberg if (result) 1463d4875622SKeith Busch return result; 146457dacad5SJay Sternberg 146557dacad5SJay Sternberg nvmeq->cq_vector = 0; 1466dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 146757dacad5SJay Sternberg if (result) { 146857dacad5SJay Sternberg nvmeq->cq_vector = -1; 1469d4875622SKeith Busch return result; 147057dacad5SJay Sternberg } 147157dacad5SJay Sternberg 147257dacad5SJay Sternberg return result; 147357dacad5SJay Sternberg } 147457dacad5SJay Sternberg 1475749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 147657dacad5SJay Sternberg { 1477949928c1SKeith Busch unsigned i, max; 1478749941f2SChristoph Hellwig int ret = 0; 147957dacad5SJay Sternberg 1480d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1481d3af3ecdSShaohua Li /* vector == qid - 1, match nvme_create_queue */ 1482d3af3ecdSShaohua Li if (!nvme_alloc_queue(dev, i, dev->q_depth, 1483d3af3ecdSShaohua Li pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { 1484749941f2SChristoph Hellwig ret = -ENOMEM; 148557dacad5SJay Sternberg break; 1486749941f2SChristoph Hellwig } 1487749941f2SChristoph Hellwig } 148857dacad5SJay Sternberg 1489d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1490949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1491749941f2SChristoph Hellwig ret = nvme_create_queue(dev->queues[i], i); 1492d4875622SKeith Busch if (ret) 149357dacad5SJay Sternberg break; 149457dacad5SJay Sternberg } 149557dacad5SJay Sternberg 1496749941f2SChristoph Hellwig /* 1497749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 1498749941f2SChristoph Hellwig * than the desired aount of queues, and even a controller without 1499749941f2SChristoph Hellwig * I/O queues an still be used to issue admin commands. This might 1500749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1501749941f2SChristoph Hellwig */ 1502749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 150357dacad5SJay Sternberg } 150457dacad5SJay Sternberg 1505202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1506202021c1SStephen Bates struct device_attribute *attr, 1507202021c1SStephen Bates char *buf) 1508202021c1SStephen Bates { 1509202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1510202021c1SStephen Bates 1511c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1512202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1513202021c1SStephen Bates } 1514202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1515202021c1SStephen Bates 151657dacad5SJay Sternberg static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 151757dacad5SJay Sternberg { 151857dacad5SJay Sternberg u64 szu, size, offset; 151957dacad5SJay Sternberg resource_size_t bar_size; 152057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 152157dacad5SJay Sternberg void __iomem *cmb; 152257dacad5SJay Sternberg dma_addr_t dma_addr; 152357dacad5SJay Sternberg 15247a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 152557dacad5SJay Sternberg if (!(NVME_CMB_SZ(dev->cmbsz))) 152657dacad5SJay Sternberg return NULL; 1527202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 152857dacad5SJay Sternberg 1529202021c1SStephen Bates if (!use_cmb_sqes) 1530202021c1SStephen Bates return NULL; 153157dacad5SJay Sternberg 153257dacad5SJay Sternberg szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 153357dacad5SJay Sternberg size = szu * NVME_CMB_SZ(dev->cmbsz); 1534202021c1SStephen Bates offset = szu * NVME_CMB_OFST(dev->cmbloc); 1535202021c1SStephen Bates bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); 153657dacad5SJay Sternberg 153757dacad5SJay Sternberg if (offset > bar_size) 153857dacad5SJay Sternberg return NULL; 153957dacad5SJay Sternberg 154057dacad5SJay Sternberg /* 154157dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 154257dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 154357dacad5SJay Sternberg * the reported size of the BAR 154457dacad5SJay Sternberg */ 154557dacad5SJay Sternberg if (size > bar_size - offset) 154657dacad5SJay Sternberg size = bar_size - offset; 154757dacad5SJay Sternberg 1548202021c1SStephen Bates dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; 154957dacad5SJay Sternberg cmb = ioremap_wc(dma_addr, size); 155057dacad5SJay Sternberg if (!cmb) 155157dacad5SJay Sternberg return NULL; 155257dacad5SJay Sternberg 155357dacad5SJay Sternberg dev->cmb_dma_addr = dma_addr; 155457dacad5SJay Sternberg dev->cmb_size = size; 155557dacad5SJay Sternberg return cmb; 155657dacad5SJay Sternberg } 155757dacad5SJay Sternberg 155857dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 155957dacad5SJay Sternberg { 156057dacad5SJay Sternberg if (dev->cmb) { 156157dacad5SJay Sternberg iounmap(dev->cmb); 156257dacad5SJay Sternberg dev->cmb = NULL; 1563f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1564f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1565f63572dfSJon Derrick dev->cmbsz = 0; 1566f63572dfSJon Derrick } 156757dacad5SJay Sternberg } 156857dacad5SJay Sternberg 156987ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 157057dacad5SJay Sternberg { 157187ad72a5SChristoph Hellwig size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs); 157287ad72a5SChristoph Hellwig struct nvme_command c; 157387ad72a5SChristoph Hellwig u64 dma_addr; 157487ad72a5SChristoph Hellwig int ret; 157587ad72a5SChristoph Hellwig 157687ad72a5SChristoph Hellwig dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len, 157787ad72a5SChristoph Hellwig DMA_TO_DEVICE); 157887ad72a5SChristoph Hellwig if (dma_mapping_error(dev->dev, dma_addr)) 157987ad72a5SChristoph Hellwig return -ENOMEM; 158087ad72a5SChristoph Hellwig 158187ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 158287ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 158387ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 158487ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 158587ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 158687ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 158787ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 158887ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 158987ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 159087ad72a5SChristoph Hellwig 159187ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 159287ad72a5SChristoph Hellwig if (ret) { 159387ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 159487ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 159587ad72a5SChristoph Hellwig ret, bits); 159687ad72a5SChristoph Hellwig } 159787ad72a5SChristoph Hellwig dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE); 159887ad72a5SChristoph Hellwig return ret; 159987ad72a5SChristoph Hellwig } 160087ad72a5SChristoph Hellwig 160187ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 160287ad72a5SChristoph Hellwig { 160387ad72a5SChristoph Hellwig int i; 160487ad72a5SChristoph Hellwig 160587ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 160687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 160787ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 160887ad72a5SChristoph Hellwig 160987ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 161087ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 161187ad72a5SChristoph Hellwig } 161287ad72a5SChristoph Hellwig 161387ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 161487ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 161587ad72a5SChristoph Hellwig kfree(dev->host_mem_descs); 161687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 161787ad72a5SChristoph Hellwig } 161887ad72a5SChristoph Hellwig 161987ad72a5SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 162087ad72a5SChristoph Hellwig { 162187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 162250cdb7c6SChristoph Hellwig u32 chunk_size, max_entries, len; 16232ee0e4edSDan Carpenter int i = 0; 162487ad72a5SChristoph Hellwig void **bufs; 16252ee0e4edSDan Carpenter u64 size = 0, tmp; 162687ad72a5SChristoph Hellwig 162787ad72a5SChristoph Hellwig /* start big and work our way down */ 162887ad72a5SChristoph Hellwig chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER); 162987ad72a5SChristoph Hellwig retry: 163087ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 163187ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 163287ad72a5SChristoph Hellwig max_entries = tmp; 163387ad72a5SChristoph Hellwig descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL); 163487ad72a5SChristoph Hellwig if (!descs) 163587ad72a5SChristoph Hellwig goto out; 163687ad72a5SChristoph Hellwig 163787ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 163887ad72a5SChristoph Hellwig if (!bufs) 163987ad72a5SChristoph Hellwig goto out_free_descs; 164087ad72a5SChristoph Hellwig 164150cdb7c6SChristoph Hellwig for (size = 0; size < preferred; size += len) { 164287ad72a5SChristoph Hellwig dma_addr_t dma_addr; 164387ad72a5SChristoph Hellwig 164450cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 164587ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 164687ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 164787ad72a5SChristoph Hellwig if (!bufs[i]) 164887ad72a5SChristoph Hellwig break; 164987ad72a5SChristoph Hellwig 165087ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 165187ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 165287ad72a5SChristoph Hellwig i++; 165387ad72a5SChristoph Hellwig } 165487ad72a5SChristoph Hellwig 165587ad72a5SChristoph Hellwig if (!size || (min && size < min)) { 165687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 165787ad72a5SChristoph Hellwig "failed to allocate host memory buffer.\n"); 165887ad72a5SChristoph Hellwig goto out_free_bufs; 165987ad72a5SChristoph Hellwig } 166087ad72a5SChristoph Hellwig 166187ad72a5SChristoph Hellwig dev_info(dev->ctrl.device, 166287ad72a5SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 166387ad72a5SChristoph Hellwig size >> ilog2(SZ_1M)); 166487ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 166587ad72a5SChristoph Hellwig dev->host_mem_size = size; 166687ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 166787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 166887ad72a5SChristoph Hellwig return 0; 166987ad72a5SChristoph Hellwig 167087ad72a5SChristoph Hellwig out_free_bufs: 167187ad72a5SChristoph Hellwig while (--i >= 0) { 167287ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 167387ad72a5SChristoph Hellwig 167487ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 167587ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 167687ad72a5SChristoph Hellwig } 167787ad72a5SChristoph Hellwig 167887ad72a5SChristoph Hellwig kfree(bufs); 167987ad72a5SChristoph Hellwig out_free_descs: 168087ad72a5SChristoph Hellwig kfree(descs); 168187ad72a5SChristoph Hellwig out: 168287ad72a5SChristoph Hellwig /* try a smaller chunk size if we failed early */ 168387ad72a5SChristoph Hellwig if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) { 168487ad72a5SChristoph Hellwig chunk_size /= 2; 168587ad72a5SChristoph Hellwig goto retry; 168687ad72a5SChristoph Hellwig } 168787ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 168887ad72a5SChristoph Hellwig return -ENOMEM; 168987ad72a5SChristoph Hellwig } 169087ad72a5SChristoph Hellwig 169187ad72a5SChristoph Hellwig static void nvme_setup_host_mem(struct nvme_dev *dev) 169287ad72a5SChristoph Hellwig { 169387ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 169487ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 169587ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 169687ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 169787ad72a5SChristoph Hellwig 169887ad72a5SChristoph Hellwig preferred = min(preferred, max); 169987ad72a5SChristoph Hellwig if (min > max) { 170087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 170187ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 170287ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 170387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 170487ad72a5SChristoph Hellwig return; 170587ad72a5SChristoph Hellwig } 170687ad72a5SChristoph Hellwig 170787ad72a5SChristoph Hellwig /* 170887ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 170987ad72a5SChristoph Hellwig */ 171087ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 171187ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 171287ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 171387ad72a5SChristoph Hellwig else 171487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 171587ad72a5SChristoph Hellwig } 171687ad72a5SChristoph Hellwig 171787ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 171887ad72a5SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) 171987ad72a5SChristoph Hellwig return; 172087ad72a5SChristoph Hellwig } 172187ad72a5SChristoph Hellwig 172287ad72a5SChristoph Hellwig if (nvme_set_host_mem(dev, enable_bits)) 172387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 172457dacad5SJay Sternberg } 172557dacad5SJay Sternberg 172657dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 172757dacad5SJay Sternberg { 172857dacad5SJay Sternberg struct nvme_queue *adminq = dev->queues[0]; 172957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 173097f6ef64SXu Yu int result, nr_io_queues; 173197f6ef64SXu Yu unsigned long size; 173257dacad5SJay Sternberg 1733425a17cbSChristoph Hellwig nr_io_queues = num_present_cpus(); 17349a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 17359a0be7abSChristoph Hellwig if (result < 0) 173657dacad5SJay Sternberg return result; 17379a0be7abSChristoph Hellwig 1738f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1739a5229050SKeith Busch return 0; 174057dacad5SJay Sternberg 174157dacad5SJay Sternberg if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 174257dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 174357dacad5SJay Sternberg sizeof(struct nvme_command)); 174457dacad5SJay Sternberg if (result > 0) 174557dacad5SJay Sternberg dev->q_depth = result; 174657dacad5SJay Sternberg else 174757dacad5SJay Sternberg nvme_release_cmb(dev); 174857dacad5SJay Sternberg } 174957dacad5SJay Sternberg 175057dacad5SJay Sternberg do { 175197f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 175297f6ef64SXu Yu result = nvme_remap_bar(dev, size); 175397f6ef64SXu Yu if (!result) 175457dacad5SJay Sternberg break; 175557dacad5SJay Sternberg if (!--nr_io_queues) 175657dacad5SJay Sternberg return -ENOMEM; 175757dacad5SJay Sternberg } while (1); 175857dacad5SJay Sternberg adminq->q_db = dev->dbs; 175957dacad5SJay Sternberg 176057dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 17610ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 176257dacad5SJay Sternberg 176357dacad5SJay Sternberg /* 176457dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 176557dacad5SJay Sternberg * setting up the full range we need. 176657dacad5SJay Sternberg */ 1767dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 1768dca51e78SChristoph Hellwig nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, 1769dca51e78SChristoph Hellwig PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); 1770dca51e78SChristoph Hellwig if (nr_io_queues <= 0) 1771dca51e78SChristoph Hellwig return -EIO; 1772dca51e78SChristoph Hellwig dev->max_qid = nr_io_queues; 177357dacad5SJay Sternberg 177457dacad5SJay Sternberg /* 177557dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 177657dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 177757dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 177857dacad5SJay Sternberg * number of interrupts. 177957dacad5SJay Sternberg */ 178057dacad5SJay Sternberg 1781dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 178257dacad5SJay Sternberg if (result) { 178357dacad5SJay Sternberg adminq->cq_vector = -1; 1784d4875622SKeith Busch return result; 178557dacad5SJay Sternberg } 1786749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 178757dacad5SJay Sternberg } 178857dacad5SJay Sternberg 17892a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1790db3cbfffSKeith Busch { 1791db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1792db3cbfffSKeith Busch 1793db3cbfffSKeith Busch blk_mq_free_request(req); 1794db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1795db3cbfffSKeith Busch } 1796db3cbfffSKeith Busch 17972a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1798db3cbfffSKeith Busch { 1799db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1800db3cbfffSKeith Busch 1801db3cbfffSKeith Busch if (!error) { 1802db3cbfffSKeith Busch unsigned long flags; 1803db3cbfffSKeith Busch 18042e39e0f6SMing Lin /* 18052e39e0f6SMing Lin * We might be called with the AQ q_lock held 18062e39e0f6SMing Lin * and the I/O queue q_lock should always 18072e39e0f6SMing Lin * nest inside the AQ one. 18082e39e0f6SMing Lin */ 18092e39e0f6SMing Lin spin_lock_irqsave_nested(&nvmeq->q_lock, flags, 18102e39e0f6SMing Lin SINGLE_DEPTH_NESTING); 1811db3cbfffSKeith Busch nvme_process_cq(nvmeq); 1812db3cbfffSKeith Busch spin_unlock_irqrestore(&nvmeq->q_lock, flags); 1813db3cbfffSKeith Busch } 1814db3cbfffSKeith Busch 1815db3cbfffSKeith Busch nvme_del_queue_end(req, error); 1816db3cbfffSKeith Busch } 1817db3cbfffSKeith Busch 1818db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1819db3cbfffSKeith Busch { 1820db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1821db3cbfffSKeith Busch struct request *req; 1822db3cbfffSKeith Busch struct nvme_command cmd; 1823db3cbfffSKeith Busch 1824db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 1825db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 1826db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1827db3cbfffSKeith Busch 1828eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1829db3cbfffSKeith Busch if (IS_ERR(req)) 1830db3cbfffSKeith Busch return PTR_ERR(req); 1831db3cbfffSKeith Busch 1832db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 1833db3cbfffSKeith Busch req->end_io_data = nvmeq; 1834db3cbfffSKeith Busch 1835db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 1836db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 1837db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 1838db3cbfffSKeith Busch return 0; 1839db3cbfffSKeith Busch } 1840db3cbfffSKeith Busch 184170659060SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) 1842db3cbfffSKeith Busch { 184370659060SKeith Busch int pass; 1844db3cbfffSKeith Busch unsigned long timeout; 1845db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 1846db3cbfffSKeith Busch 1847db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 1848014a0d60SKeith Busch int sent = 0, i = queues; 1849db3cbfffSKeith Busch 1850db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 1851db3cbfffSKeith Busch retry: 1852db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 1853c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 1854c21377f8SGabriel Krisman Bertazi if (nvme_delete_queue(dev->queues[i], opcode)) 1855db3cbfffSKeith Busch break; 1856c21377f8SGabriel Krisman Bertazi 1857db3cbfffSKeith Busch while (sent--) { 1858db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 1859db3cbfffSKeith Busch if (timeout == 0) 1860db3cbfffSKeith Busch return; 1861db3cbfffSKeith Busch if (i) 1862db3cbfffSKeith Busch goto retry; 1863db3cbfffSKeith Busch } 1864db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 1865db3cbfffSKeith Busch } 1866db3cbfffSKeith Busch } 1867db3cbfffSKeith Busch 186857dacad5SJay Sternberg /* 186957dacad5SJay Sternberg * Return: error value if an error occurred setting up the queues or calling 187057dacad5SJay Sternberg * Identify Device. 0 if these succeeded, even if adding some of the 187157dacad5SJay Sternberg * namespaces failed. At the moment, these failures are silent. TBD which 187257dacad5SJay Sternberg * failures should be reported. 187357dacad5SJay Sternberg */ 187457dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 187557dacad5SJay Sternberg { 18765bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 187757dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 187857dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 187957dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 188057dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 188157dacad5SJay Sternberg dev->tagset.queue_depth = 188257dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 188357dacad5SJay Sternberg dev->tagset.cmd_size = nvme_cmd_size(dev); 188457dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 188557dacad5SJay Sternberg dev->tagset.driver_data = dev; 188657dacad5SJay Sternberg 188757dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->tagset)) 188857dacad5SJay Sternberg return 0; 18895bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 1890f9f38e33SHelen Koike 1891f9f38e33SHelen Koike nvme_dbbuf_set(dev); 1892949928c1SKeith Busch } else { 1893949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 1894949928c1SKeith Busch 1895949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 1896949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 189757dacad5SJay Sternberg } 1898949928c1SKeith Busch 189957dacad5SJay Sternberg return 0; 190057dacad5SJay Sternberg } 190157dacad5SJay Sternberg 1902b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 190357dacad5SJay Sternberg { 1904b00a726aSKeith Busch int result = -ENOMEM; 190557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 190657dacad5SJay Sternberg 190757dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 190857dacad5SJay Sternberg return result; 190957dacad5SJay Sternberg 191057dacad5SJay Sternberg pci_set_master(pdev); 191157dacad5SJay Sternberg 191257dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 191357dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 191457dacad5SJay Sternberg goto disable; 191557dacad5SJay Sternberg 19167a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 191757dacad5SJay Sternberg result = -ENODEV; 1918b00a726aSKeith Busch goto disable; 191957dacad5SJay Sternberg } 192057dacad5SJay Sternberg 192157dacad5SJay Sternberg /* 1922a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 1923a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 1924a5229050SKeith Busch * adjust this later. 192557dacad5SJay Sternberg */ 1926dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1927dca51e78SChristoph Hellwig if (result < 0) 1928dca51e78SChristoph Hellwig return result; 192957dacad5SJay Sternberg 193020d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 19317a67cbeaSChristoph Hellwig 193220d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 1933b27c1e68Sweiping zhang io_queue_depth); 193420d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 19357a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 19361f390c1fSStephan Günther 19371f390c1fSStephan Günther /* 19381f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 19391f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 19401f390c1fSStephan Günther */ 19411f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 19421f390c1fSStephan Günther dev->q_depth = 2; 19439bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 19449bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 19451f390c1fSStephan Günther dev->q_depth); 1946d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 1947d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 194820d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 1949d554b5e1SMartin K. Petersen dev->q_depth = 64; 1950d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 1951d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 19521f390c1fSStephan Günther } 19531f390c1fSStephan Günther 1954202021c1SStephen Bates /* 1955202021c1SStephen Bates * CMBs can currently only exist on >=1.2 PCIe devices. We only 19561c78f773SMax Gurtovoy * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group 19571c78f773SMax Gurtovoy * has no name we can pass NULL as final argument to 19581c78f773SMax Gurtovoy * sysfs_add_file_to_group. 1959202021c1SStephen Bates */ 1960202021c1SStephen Bates 19618ef2074dSGabriel Krisman Bertazi if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { 196257dacad5SJay Sternberg dev->cmb = nvme_map_cmb(dev); 19631c78f773SMax Gurtovoy if (dev->cmb) { 1964202021c1SStephen Bates if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1965202021c1SStephen Bates &dev_attr_cmb.attr, NULL)) 19669bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 1967202021c1SStephen Bates "failed to add sysfs attribute for CMB\n"); 1968202021c1SStephen Bates } 1969202021c1SStephen Bates } 1970202021c1SStephen Bates 1971a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 1972a0a3408eSKeith Busch pci_save_state(pdev); 197357dacad5SJay Sternberg return 0; 197457dacad5SJay Sternberg 197557dacad5SJay Sternberg disable: 197657dacad5SJay Sternberg pci_disable_device(pdev); 197757dacad5SJay Sternberg return result; 197857dacad5SJay Sternberg } 197957dacad5SJay Sternberg 198057dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 198157dacad5SJay Sternberg { 1982b00a726aSKeith Busch if (dev->bar) 1983b00a726aSKeith Busch iounmap(dev->bar); 1984a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 1985b00a726aSKeith Busch } 1986b00a726aSKeith Busch 1987b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 1988b00a726aSKeith Busch { 198957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 199057dacad5SJay Sternberg 1991f63572dfSJon Derrick nvme_release_cmb(dev); 1992dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 199357dacad5SJay Sternberg 1994a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 1995a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 199657dacad5SJay Sternberg pci_disable_device(pdev); 199757dacad5SJay Sternberg } 1998a0a3408eSKeith Busch } 199957dacad5SJay Sternberg 2000a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 200157dacad5SJay Sternberg { 200270659060SKeith Busch int i, queues; 2003302ad8ccSKeith Busch bool dead = true; 2004302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 200557dacad5SJay Sternberg 200677bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2007302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2008302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2009302ad8ccSKeith Busch 2010ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2011ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2012302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2013302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2014302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 201557dacad5SJay Sternberg } 2016c21377f8SGabriel Krisman Bertazi 2017302ad8ccSKeith Busch /* 2018302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2019302ad8ccSKeith Busch * doing a safe shutdown. 2020302ad8ccSKeith Busch */ 202187ad72a5SChristoph Hellwig if (!dead) { 202287ad72a5SChristoph Hellwig if (shutdown) 2023302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 202487ad72a5SChristoph Hellwig 202587ad72a5SChristoph Hellwig /* 202687ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 202787ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 202887ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 202987ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 203087ad72a5SChristoph Hellwig */ 203187ad72a5SChristoph Hellwig if (dev->host_mem_descs) 203287ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 203387ad72a5SChristoph Hellwig 203487ad72a5SChristoph Hellwig } 2035302ad8ccSKeith Busch nvme_stop_queues(&dev->ctrl); 2036302ad8ccSKeith Busch 203770659060SKeith Busch queues = dev->online_queues - 1; 2038d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i > 0; i--) 2039c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[i]); 2040c21377f8SGabriel Krisman Bertazi 2041302ad8ccSKeith Busch if (dead) { 204282469c59SGabriel Krisman Bertazi /* A device might become IO incapable very soon during 204382469c59SGabriel Krisman Bertazi * probe, before the admin queue is configured. Thus, 204482469c59SGabriel Krisman Bertazi * queue_count can be 0 here. 204582469c59SGabriel Krisman Bertazi */ 2046d858e5f0SSagi Grimberg if (dev->ctrl.queue_count) 2047c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[0]); 204857dacad5SJay Sternberg } else { 204970659060SKeith Busch nvme_disable_io_queues(dev, queues); 2050a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 205157dacad5SJay Sternberg } 2052b00a726aSKeith Busch nvme_pci_disable(dev); 205357dacad5SJay Sternberg 2054e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2055e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2056302ad8ccSKeith Busch 2057302ad8ccSKeith Busch /* 2058302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2059302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2060302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2061302ad8ccSKeith Busch */ 2062302ad8ccSKeith Busch if (shutdown) 2063302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 206477bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 206557dacad5SJay Sternberg } 206657dacad5SJay Sternberg 206757dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 206857dacad5SJay Sternberg { 206957dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 207057dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 207157dacad5SJay Sternberg if (!dev->prp_page_pool) 207257dacad5SJay Sternberg return -ENOMEM; 207357dacad5SJay Sternberg 207457dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 207557dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 207657dacad5SJay Sternberg 256, 256, 0); 207757dacad5SJay Sternberg if (!dev->prp_small_pool) { 207857dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 207957dacad5SJay Sternberg return -ENOMEM; 208057dacad5SJay Sternberg } 208157dacad5SJay Sternberg return 0; 208257dacad5SJay Sternberg } 208357dacad5SJay Sternberg 208457dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 208557dacad5SJay Sternberg { 208657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 208757dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 208857dacad5SJay Sternberg } 208957dacad5SJay Sternberg 20901673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 209157dacad5SJay Sternberg { 20921673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 209357dacad5SJay Sternberg 2094f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 209557dacad5SJay Sternberg put_device(dev->dev); 209657dacad5SJay Sternberg if (dev->tagset.tags) 209757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 20981c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 20991c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 210057dacad5SJay Sternberg kfree(dev->queues); 2101e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 210257dacad5SJay Sternberg kfree(dev); 210357dacad5SJay Sternberg } 210457dacad5SJay Sternberg 2105f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2106f58944e2SKeith Busch { 2107237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2108f58944e2SKeith Busch 2109f58944e2SKeith Busch kref_get(&dev->ctrl.kref); 211069d9a99cSKeith Busch nvme_dev_disable(dev, false); 2111f58944e2SKeith Busch if (!schedule_work(&dev->remove_work)) 2112f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2113f58944e2SKeith Busch } 2114f58944e2SKeith Busch 2115fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 211657dacad5SJay Sternberg { 2117d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2118d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2119a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2120f58944e2SKeith Busch int result = -ENODEV; 212157dacad5SJay Sternberg 212282b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2123fd634f41SChristoph Hellwig goto out; 2124fd634f41SChristoph Hellwig 2125fd634f41SChristoph Hellwig /* 2126fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2127fd634f41SChristoph Hellwig * moving on. 2128fd634f41SChristoph Hellwig */ 2129b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2130a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2131fd634f41SChristoph Hellwig 2132b00a726aSKeith Busch result = nvme_pci_enable(dev); 213357dacad5SJay Sternberg if (result) 213457dacad5SJay Sternberg goto out; 213557dacad5SJay Sternberg 213601ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 213757dacad5SJay Sternberg if (result) 2138f58944e2SKeith Busch goto out; 213957dacad5SJay Sternberg 214057dacad5SJay Sternberg nvme_init_queue(dev->queues[0], 0); 214157dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 214257dacad5SJay Sternberg if (result) 2143f58944e2SKeith Busch goto out; 214457dacad5SJay Sternberg 2145ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2146ce4541f4SChristoph Hellwig if (result) 2147f58944e2SKeith Busch goto out; 2148ce4541f4SChristoph Hellwig 2149e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2150e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 21514f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 21524f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2153e286bcfcSScott Bauer else if (was_suspend) 21544f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2155e286bcfcSScott Bauer } else { 2156e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2157e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2158e286bcfcSScott Bauer } 2159a98e58e5SScott Bauer 2160f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2161f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2162f9f38e33SHelen Koike if (result) 2163f9f38e33SHelen Koike dev_warn(dev->dev, 2164f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2165f9f38e33SHelen Koike } 2166f9f38e33SHelen Koike 216787ad72a5SChristoph Hellwig if (dev->ctrl.hmpre) 216887ad72a5SChristoph Hellwig nvme_setup_host_mem(dev); 216987ad72a5SChristoph Hellwig 217057dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 217157dacad5SJay Sternberg if (result) 2172f58944e2SKeith Busch goto out; 217357dacad5SJay Sternberg 217421f033f7SKeith Busch /* 217557dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 217657dacad5SJay Sternberg * any working I/O queue. 217757dacad5SJay Sternberg */ 217857dacad5SJay Sternberg if (dev->online_queues < 2) { 21791b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 21803b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 21815bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 218257dacad5SJay Sternberg } else { 218325646264SKeith Busch nvme_start_queues(&dev->ctrl); 2184302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 218557dacad5SJay Sternberg nvme_dev_add(dev); 2186302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 218757dacad5SJay Sternberg } 218857dacad5SJay Sternberg 2189bb8d261eSChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2190bb8d261eSChristoph Hellwig dev_warn(dev->ctrl.device, "failed to mark controller live\n"); 2191bb8d261eSChristoph Hellwig goto out; 2192bb8d261eSChristoph Hellwig } 219392911a55SChristoph Hellwig 2194d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 219557dacad5SJay Sternberg return; 219657dacad5SJay Sternberg 219757dacad5SJay Sternberg out: 2198f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 219957dacad5SJay Sternberg } 220057dacad5SJay Sternberg 22015c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 220257dacad5SJay Sternberg { 22035c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 220457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 220557dacad5SJay Sternberg 220669d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 220757dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2208921920abSKeith Busch device_release_driver(&pdev->dev); 22091673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 221057dacad5SJay Sternberg } 221157dacad5SJay Sternberg 22121c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 221357dacad5SJay Sternberg { 22141c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 22151c63dc66SChristoph Hellwig return 0; 221657dacad5SJay Sternberg } 22171c63dc66SChristoph Hellwig 22185fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 22195fd4ce1bSChristoph Hellwig { 22205fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 22215fd4ce1bSChristoph Hellwig return 0; 22225fd4ce1bSChristoph Hellwig } 22235fd4ce1bSChristoph Hellwig 22247fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 22257fd8930fSChristoph Hellwig { 22267fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 22277fd8930fSChristoph Hellwig return 0; 22287fd8930fSChristoph Hellwig } 22297fd8930fSChristoph Hellwig 22301c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 22311a353d85SMing Lin .name = "pcie", 2232e439bb12SSagi Grimberg .module = THIS_MODULE, 2233c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 22341c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 22355fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 22367fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 22371673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2238f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 22391c63dc66SChristoph Hellwig }; 224057dacad5SJay Sternberg 2241b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2242b00a726aSKeith Busch { 2243b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2244b00a726aSKeith Busch 2245a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2246b00a726aSKeith Busch return -ENODEV; 2247b00a726aSKeith Busch 224897f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2249b00a726aSKeith Busch goto release; 2250b00a726aSKeith Busch 2251b00a726aSKeith Busch return 0; 2252b00a726aSKeith Busch release: 2253a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2254b00a726aSKeith Busch return -ENODEV; 2255b00a726aSKeith Busch } 2256b00a726aSKeith Busch 2257ff5350a8SAndy Lutomirski static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) 2258ff5350a8SAndy Lutomirski { 2259ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2260ff5350a8SAndy Lutomirski /* 2261ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2262ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2263ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2264ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2265ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2266ff5350a8SAndy Lutomirski * laptops. 2267ff5350a8SAndy Lutomirski */ 2268ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2269ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2270ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2271ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 2272ff5350a8SAndy Lutomirski } 2273ff5350a8SAndy Lutomirski 2274ff5350a8SAndy Lutomirski return 0; 2275ff5350a8SAndy Lutomirski } 2276ff5350a8SAndy Lutomirski 227757dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 227857dacad5SJay Sternberg { 227957dacad5SJay Sternberg int node, result = -ENOMEM; 228057dacad5SJay Sternberg struct nvme_dev *dev; 2281ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 228257dacad5SJay Sternberg 228357dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 228457dacad5SJay Sternberg if (node == NUMA_NO_NODE) 22852fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 228657dacad5SJay Sternberg 228757dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 228857dacad5SJay Sternberg if (!dev) 228957dacad5SJay Sternberg return -ENOMEM; 229057dacad5SJay Sternberg dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), 229157dacad5SJay Sternberg GFP_KERNEL, node); 229257dacad5SJay Sternberg if (!dev->queues) 229357dacad5SJay Sternberg goto free; 229457dacad5SJay Sternberg 229557dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 229657dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 229757dacad5SJay Sternberg 2298b00a726aSKeith Busch result = nvme_dev_map(dev); 2299b00a726aSKeith Busch if (result) 2300b00c9b7aSChristophe JAILLET goto put_pci; 2301b00a726aSKeith Busch 2302d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 23035c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 230477bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2305db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2306f3ca80fcSChristoph Hellwig 2307f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2308f3ca80fcSChristoph Hellwig if (result) 2309b00c9b7aSChristophe JAILLET goto unmap; 2310f3ca80fcSChristoph Hellwig 2311ff5350a8SAndy Lutomirski quirks |= check_dell_samsung_bug(pdev); 2312ff5350a8SAndy Lutomirski 2313f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2314ff5350a8SAndy Lutomirski quirks); 2315f3ca80fcSChristoph Hellwig if (result) 2316f3ca80fcSChristoph Hellwig goto release_pools; 2317f3ca80fcSChristoph Hellwig 231882b057caSRakesh Pandit nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); 23191b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 23201b3c47c1SSagi Grimberg 2321d86c4d8eSChristoph Hellwig queue_work(nvme_wq, &dev->ctrl.reset_work); 232257dacad5SJay Sternberg return 0; 232357dacad5SJay Sternberg 232457dacad5SJay Sternberg release_pools: 232557dacad5SJay Sternberg nvme_release_prp_pools(dev); 2326b00c9b7aSChristophe JAILLET unmap: 2327b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 232857dacad5SJay Sternberg put_pci: 232957dacad5SJay Sternberg put_device(dev->dev); 233057dacad5SJay Sternberg free: 233157dacad5SJay Sternberg kfree(dev->queues); 233257dacad5SJay Sternberg kfree(dev); 233357dacad5SJay Sternberg return result; 233457dacad5SJay Sternberg } 233557dacad5SJay Sternberg 2336775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 233757dacad5SJay Sternberg { 233857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2339a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2340775755edSChristoph Hellwig } 234157dacad5SJay Sternberg 2342775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2343775755edSChristoph Hellwig { 2344f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2345d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 234657dacad5SJay Sternberg } 234757dacad5SJay Sternberg 234857dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 234957dacad5SJay Sternberg { 235057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2351a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 235257dacad5SJay Sternberg } 235357dacad5SJay Sternberg 2354f58944e2SKeith Busch /* 2355f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2356f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2357f58944e2SKeith Busch * order to proceed. 2358f58944e2SKeith Busch */ 235957dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 236057dacad5SJay Sternberg { 236157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 236257dacad5SJay Sternberg 2363bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2364bb8d261eSChristoph Hellwig 2365d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 236657dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 23670ff9d4e1SKeith Busch 23686db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 23690ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 23706db28edaSKeith Busch nvme_dev_disable(dev, false); 23716db28edaSKeith Busch } 23720ff9d4e1SKeith Busch 2373d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2374d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2375d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2376a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 237787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 237857dacad5SJay Sternberg nvme_dev_remove_admin(dev); 237957dacad5SJay Sternberg nvme_free_queues(dev, 0); 2380d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 238157dacad5SJay Sternberg nvme_release_prp_pools(dev); 2382b00a726aSKeith Busch nvme_dev_unmap(dev); 23831673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 238457dacad5SJay Sternberg } 238557dacad5SJay Sternberg 238613880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 238713880f5bSKeith Busch { 238813880f5bSKeith Busch int ret = 0; 238913880f5bSKeith Busch 239013880f5bSKeith Busch if (numvfs == 0) { 239113880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 239213880f5bSKeith Busch dev_warn(&pdev->dev, 239313880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 239413880f5bSKeith Busch return -EPERM; 239513880f5bSKeith Busch } 239613880f5bSKeith Busch pci_disable_sriov(pdev); 239713880f5bSKeith Busch return 0; 239813880f5bSKeith Busch } 239913880f5bSKeith Busch 240013880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 240113880f5bSKeith Busch return ret ? ret : numvfs; 240213880f5bSKeith Busch } 240313880f5bSKeith Busch 240457dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 240557dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 240657dacad5SJay Sternberg { 240757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 240857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 240957dacad5SJay Sternberg 2410a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 241157dacad5SJay Sternberg return 0; 241257dacad5SJay Sternberg } 241357dacad5SJay Sternberg 241457dacad5SJay Sternberg static int nvme_resume(struct device *dev) 241557dacad5SJay Sternberg { 241657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 241757dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 241857dacad5SJay Sternberg 2419d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 242057dacad5SJay Sternberg return 0; 242157dacad5SJay Sternberg } 242257dacad5SJay Sternberg #endif 242357dacad5SJay Sternberg 242457dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 242557dacad5SJay Sternberg 2426a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2427a0a3408eSKeith Busch pci_channel_state_t state) 2428a0a3408eSKeith Busch { 2429a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2430a0a3408eSKeith Busch 2431a0a3408eSKeith Busch /* 2432a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2433a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2434a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2435a0a3408eSKeith Busch */ 2436a0a3408eSKeith Busch switch (state) { 2437a0a3408eSKeith Busch case pci_channel_io_normal: 2438a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2439a0a3408eSKeith Busch case pci_channel_io_frozen: 2440d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2441d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2442a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2443a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2444a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2445d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2446d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2447a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2448a0a3408eSKeith Busch } 2449a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2450a0a3408eSKeith Busch } 2451a0a3408eSKeith Busch 2452a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2453a0a3408eSKeith Busch { 2454a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2455a0a3408eSKeith Busch 24561b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2457a0a3408eSKeith Busch pci_restore_state(pdev); 2458d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2459a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2460a0a3408eSKeith Busch } 2461a0a3408eSKeith Busch 2462a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2463a0a3408eSKeith Busch { 2464a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2465a0a3408eSKeith Busch } 2466a0a3408eSKeith Busch 246757dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 246857dacad5SJay Sternberg .error_detected = nvme_error_detected, 246957dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 247057dacad5SJay Sternberg .resume = nvme_error_resume, 2471775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2472775755edSChristoph Hellwig .reset_done = nvme_reset_done, 247357dacad5SJay Sternberg }; 247457dacad5SJay Sternberg 247557dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2476106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 247708095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2478e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 247999466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 248099466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2481e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 248299466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 248399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2484e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2485f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2486f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2487f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 248850af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 248950af47d0SAndy Lutomirski .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, 2490540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2491540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 249254adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 249354adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2494015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2495015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2496d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2497d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2498d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2499d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 250057dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2501c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2502124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 250357dacad5SJay Sternberg { 0, } 250457dacad5SJay Sternberg }; 250557dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 250657dacad5SJay Sternberg 250757dacad5SJay Sternberg static struct pci_driver nvme_driver = { 250857dacad5SJay Sternberg .name = "nvme", 250957dacad5SJay Sternberg .id_table = nvme_id_table, 251057dacad5SJay Sternberg .probe = nvme_probe, 251157dacad5SJay Sternberg .remove = nvme_remove, 251257dacad5SJay Sternberg .shutdown = nvme_shutdown, 251357dacad5SJay Sternberg .driver = { 251457dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 251557dacad5SJay Sternberg }, 251613880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 251757dacad5SJay Sternberg .err_handler = &nvme_err_handler, 251857dacad5SJay Sternberg }; 251957dacad5SJay Sternberg 252057dacad5SJay Sternberg static int __init nvme_init(void) 252157dacad5SJay Sternberg { 25229a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 252357dacad5SJay Sternberg } 252457dacad5SJay Sternberg 252557dacad5SJay Sternberg static void __exit nvme_exit(void) 252657dacad5SJay Sternberg { 252757dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 252857dacad5SJay Sternberg _nvme_check_size(); 252957dacad5SJay Sternberg } 253057dacad5SJay Sternberg 253157dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 253257dacad5SJay Sternberg MODULE_LICENSE("GPL"); 253357dacad5SJay Sternberg MODULE_VERSION("1.0"); 253457dacad5SJay Sternberg module_init(nvme_init); 253557dacad5SJay Sternberg module_exit(nvme_exit); 2536