157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 330f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3457dacad5SJay Sternberg 3557dacad5SJay Sternberg #include "nvme.h" 3657dacad5SJay Sternberg 3757dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3857dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3957dacad5SJay Sternberg 40a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 41adf68f21SChristoph Hellwig 42943e942eSJens Axboe /* 43943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 44943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 45943e942eSJens Axboe */ 46943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 47943e942eSJens Axboe #define NVME_MAX_SEGS 127 48943e942eSJens Axboe 4957dacad5SJay Sternberg static int use_threaded_interrupts; 5057dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 5157dacad5SJay Sternberg 5257dacad5SJay Sternberg static bool use_cmb_sqes = true; 5369f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5457dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5557dacad5SJay Sternberg 5687ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5787ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5887ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5987ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 6057dacad5SJay Sternberg 61a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 62a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 63a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 64a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 65a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 66a7a7cbe3SChaitanya Kulkarni 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 70b27c1e68Sweiping zhang .get = param_get_int, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 73b27c1e68Sweiping zhang static int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 75b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 76b27c1e68Sweiping zhang 773b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 783b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 793b6592f7SJens Axboe .set = queue_count_set, 803b6592f7SJens Axboe .get = param_get_int, 813b6592f7SJens Axboe }; 823b6592f7SJens Axboe 833b6592f7SJens Axboe static int write_queues; 843b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 853b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 863b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 873b6592f7SJens Axboe "will share a queue set."); 883b6592f7SJens Axboe 894b04cc6aSJens Axboe static int poll_queues = 1; 904b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 914b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 924b04cc6aSJens Axboe 931c63dc66SChristoph Hellwig struct nvme_dev; 941c63dc66SChristoph Hellwig struct nvme_queue; 9557dacad5SJay Sternberg 96a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 9757dacad5SJay Sternberg 983b6592f7SJens Axboe enum { 993b6592f7SJens Axboe NVMEQ_TYPE_READ, 1003b6592f7SJens Axboe NVMEQ_TYPE_WRITE, 1014b04cc6aSJens Axboe NVMEQ_TYPE_POLL, 1023b6592f7SJens Axboe NVMEQ_TYPE_NR, 1033b6592f7SJens Axboe }; 1043b6592f7SJens Axboe 10557dacad5SJay Sternberg /* 1061c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1071c63dc66SChristoph Hellwig */ 1081c63dc66SChristoph Hellwig struct nvme_dev { 109147b27e4SSagi Grimberg struct nvme_queue *queues; 1101c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1111c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1121c63dc66SChristoph Hellwig u32 __iomem *dbs; 1131c63dc66SChristoph Hellwig struct device *dev; 1141c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1151c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1161c63dc66SChristoph Hellwig unsigned online_queues; 1171c63dc66SChristoph Hellwig unsigned max_qid; 1183b6592f7SJens Axboe unsigned io_queues[NVMEQ_TYPE_NR]; 11922b55601SKeith Busch unsigned int num_vecs; 1201c63dc66SChristoph Hellwig int q_depth; 1211c63dc66SChristoph Hellwig u32 db_stride; 1221c63dc66SChristoph Hellwig void __iomem *bar; 12397f6ef64SXu Yu unsigned long bar_mapped_size; 1245c8809e6SChristoph Hellwig struct work_struct remove_work; 12577bf25eaSKeith Busch struct mutex shutdown_lock; 1261c63dc66SChristoph Hellwig bool subsystem; 1271c63dc66SChristoph Hellwig u64 cmb_size; 1280f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1291c63dc66SChristoph Hellwig u32 cmbsz; 130202021c1SStephen Bates u32 cmbloc; 1311c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 132db3cbfffSKeith Busch struct completion ioq_wait; 13387ad72a5SChristoph Hellwig 134943e942eSJens Axboe mempool_t *iod_mempool; 135943e942eSJens Axboe 13687ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 137f9f38e33SHelen Koike u32 *dbbuf_dbs; 138f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 139f9f38e33SHelen Koike u32 *dbbuf_eis; 140f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 14187ad72a5SChristoph Hellwig 14287ad72a5SChristoph Hellwig /* host memory buffer support: */ 14387ad72a5SChristoph Hellwig u64 host_mem_size; 14487ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1454033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 14687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 14787ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 14857dacad5SJay Sternberg }; 14957dacad5SJay Sternberg 150b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 151b27c1e68Sweiping zhang { 152b27c1e68Sweiping zhang int n = 0, ret; 153b27c1e68Sweiping zhang 154b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 155b27c1e68Sweiping zhang if (ret != 0 || n < 2) 156b27c1e68Sweiping zhang return -EINVAL; 157b27c1e68Sweiping zhang 158b27c1e68Sweiping zhang return param_set_int(val, kp); 159b27c1e68Sweiping zhang } 160b27c1e68Sweiping zhang 1613b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1623b6592f7SJens Axboe { 1633b6592f7SJens Axboe int n = 0, ret; 1643b6592f7SJens Axboe 1653b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 1663b6592f7SJens Axboe if (n > num_possible_cpus()) 1673b6592f7SJens Axboe n = num_possible_cpus(); 1683b6592f7SJens Axboe 1693b6592f7SJens Axboe return param_set_int(val, kp); 1703b6592f7SJens Axboe } 1713b6592f7SJens Axboe 172f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 173f9f38e33SHelen Koike { 174f9f38e33SHelen Koike return qid * 2 * stride; 175f9f38e33SHelen Koike } 176f9f38e33SHelen Koike 177f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 178f9f38e33SHelen Koike { 179f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 180f9f38e33SHelen Koike } 181f9f38e33SHelen Koike 1821c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1831c63dc66SChristoph Hellwig { 1841c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1851c63dc66SChristoph Hellwig } 1861c63dc66SChristoph Hellwig 18757dacad5SJay Sternberg /* 18857dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18957dacad5SJay Sternberg * commands and one for I/O commands). 19057dacad5SJay Sternberg */ 19157dacad5SJay Sternberg struct nvme_queue { 19257dacad5SJay Sternberg struct device *q_dmadev; 19357dacad5SJay Sternberg struct nvme_dev *dev; 1941ab0cd69SJens Axboe spinlock_t sq_lock; 19557dacad5SJay Sternberg struct nvme_command *sq_cmds; 1960f238ff5SLogan Gunthorpe bool sq_cmds_is_io; 1971ab0cd69SJens Axboe spinlock_t cq_lock ____cacheline_aligned_in_smp; 19857dacad5SJay Sternberg volatile struct nvme_completion *cqes; 19957dacad5SJay Sternberg struct blk_mq_tags **tags; 20057dacad5SJay Sternberg dma_addr_t sq_dma_addr; 20157dacad5SJay Sternberg dma_addr_t cq_dma_addr; 20257dacad5SJay Sternberg u32 __iomem *q_db; 20357dacad5SJay Sternberg u16 q_depth; 20457dacad5SJay Sternberg s16 cq_vector; 20557dacad5SJay Sternberg u16 sq_tail; 20657dacad5SJay Sternberg u16 cq_head; 20768fa9dbeSJens Axboe u16 last_cq_head; 20857dacad5SJay Sternberg u16 qid; 20957dacad5SJay Sternberg u8 cq_phase; 2104b04cc6aSJens Axboe u8 polled; 211f9f38e33SHelen Koike u32 *dbbuf_sq_db; 212f9f38e33SHelen Koike u32 *dbbuf_cq_db; 213f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 214f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 21557dacad5SJay Sternberg }; 21657dacad5SJay Sternberg 21757dacad5SJay Sternberg /* 21871bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 21971bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 220f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 22171bd150cSChristoph Hellwig * allocated to store the PRP list. 22271bd150cSChristoph Hellwig */ 22371bd150cSChristoph Hellwig struct nvme_iod { 224d49187e9SChristoph Hellwig struct nvme_request req; 225f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 226a7a7cbe3SChaitanya Kulkarni bool use_sgl; 227f4800d6dSChristoph Hellwig int aborted; 22871bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22971bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 23071bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 23171bd150cSChristoph Hellwig dma_addr_t first_dma; 232bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 233f4800d6dSChristoph Hellwig struct scatterlist *sg; 234f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 23557dacad5SJay Sternberg }; 23657dacad5SJay Sternberg 23757dacad5SJay Sternberg /* 23857dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 23957dacad5SJay Sternberg */ 24057dacad5SJay Sternberg static inline void _nvme_check_size(void) 24157dacad5SJay Sternberg { 24257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 24357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 24457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 24557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 24657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 24757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 24857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 24957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2500add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2510add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 25257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 25357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 254f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 255f9f38e33SHelen Koike } 256f9f38e33SHelen Koike 2573b6592f7SJens Axboe static unsigned int max_io_queues(void) 2583b6592f7SJens Axboe { 2594b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2603b6592f7SJens Axboe } 2613b6592f7SJens Axboe 2623b6592f7SJens Axboe static unsigned int max_queue_count(void) 2633b6592f7SJens Axboe { 2643b6592f7SJens Axboe /* IO queues + admin queue */ 2653b6592f7SJens Axboe return 1 + max_io_queues(); 2663b6592f7SJens Axboe } 2673b6592f7SJens Axboe 268f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 269f9f38e33SHelen Koike { 2703b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 271f9f38e33SHelen Koike } 272f9f38e33SHelen Koike 273f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 274f9f38e33SHelen Koike { 275f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 276f9f38e33SHelen Koike 277f9f38e33SHelen Koike if (dev->dbbuf_dbs) 278f9f38e33SHelen Koike return 0; 279f9f38e33SHelen Koike 280f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 281f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 282f9f38e33SHelen Koike GFP_KERNEL); 283f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 284f9f38e33SHelen Koike return -ENOMEM; 285f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 286f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 287f9f38e33SHelen Koike GFP_KERNEL); 288f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 289f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 290f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 291f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 292f9f38e33SHelen Koike return -ENOMEM; 293f9f38e33SHelen Koike } 294f9f38e33SHelen Koike 295f9f38e33SHelen Koike return 0; 296f9f38e33SHelen Koike } 297f9f38e33SHelen Koike 298f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 299f9f38e33SHelen Koike { 300f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 301f9f38e33SHelen Koike 302f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 303f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 304f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 305f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 306f9f38e33SHelen Koike } 307f9f38e33SHelen Koike if (dev->dbbuf_eis) { 308f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 309f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 310f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 311f9f38e33SHelen Koike } 312f9f38e33SHelen Koike } 313f9f38e33SHelen Koike 314f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 315f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 316f9f38e33SHelen Koike { 317f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 318f9f38e33SHelen Koike return; 319f9f38e33SHelen Koike 320f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 321f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 322f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 323f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 324f9f38e33SHelen Koike } 325f9f38e33SHelen Koike 326f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 327f9f38e33SHelen Koike { 328f9f38e33SHelen Koike struct nvme_command c; 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 331f9f38e33SHelen Koike return; 332f9f38e33SHelen Koike 333f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 334f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 335f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 336f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 337f9f38e33SHelen Koike 338f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3399bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 340f9f38e33SHelen Koike /* Free memory and continue on */ 341f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 342f9f38e33SHelen Koike } 343f9f38e33SHelen Koike } 344f9f38e33SHelen Koike 345f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 346f9f38e33SHelen Koike { 347f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 348f9f38e33SHelen Koike } 349f9f38e33SHelen Koike 350f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 351f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 352f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 353f9f38e33SHelen Koike { 354f9f38e33SHelen Koike if (dbbuf_db) { 355f9f38e33SHelen Koike u16 old_value; 356f9f38e33SHelen Koike 357f9f38e33SHelen Koike /* 358f9f38e33SHelen Koike * Ensure that the queue is written before updating 359f9f38e33SHelen Koike * the doorbell in memory 360f9f38e33SHelen Koike */ 361f9f38e33SHelen Koike wmb(); 362f9f38e33SHelen Koike 363f9f38e33SHelen Koike old_value = *dbbuf_db; 364f9f38e33SHelen Koike *dbbuf_db = value; 365f9f38e33SHelen Koike 366f1ed3df2SMichal Wnukowski /* 367f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 368f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 369f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 370f1ed3df2SMichal Wnukowski * the doorbell. 371f1ed3df2SMichal Wnukowski */ 372f1ed3df2SMichal Wnukowski mb(); 373f1ed3df2SMichal Wnukowski 374f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 375f9f38e33SHelen Koike return false; 376f9f38e33SHelen Koike } 377f9f38e33SHelen Koike 378f9f38e33SHelen Koike return true; 37957dacad5SJay Sternberg } 38057dacad5SJay Sternberg 38157dacad5SJay Sternberg /* 38257dacad5SJay Sternberg * Max size of iod being embedded in the request payload 38357dacad5SJay Sternberg */ 38457dacad5SJay Sternberg #define NVME_INT_PAGES 2 3855fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 38657dacad5SJay Sternberg 38757dacad5SJay Sternberg /* 38857dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 38957dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 39057dacad5SJay Sternberg * the I/O. 39157dacad5SJay Sternberg */ 39257dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 39357dacad5SJay Sternberg { 3945fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3955fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 39657dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 39757dacad5SJay Sternberg } 39857dacad5SJay Sternberg 399a7a7cbe3SChaitanya Kulkarni /* 400a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 401a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 402a7a7cbe3SChaitanya Kulkarni */ 403a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 404f4800d6dSChristoph Hellwig { 405a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 406f4800d6dSChristoph Hellwig } 407f4800d6dSChristoph Hellwig 408a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 409a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 41057dacad5SJay Sternberg { 411a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 412a7a7cbe3SChaitanya Kulkarni 413a7a7cbe3SChaitanya Kulkarni if (use_sgl) 414a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 415a7a7cbe3SChaitanya Kulkarni else 416a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 417a7a7cbe3SChaitanya Kulkarni 418a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 419a7a7cbe3SChaitanya Kulkarni } 420a7a7cbe3SChaitanya Kulkarni 421a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 422a7a7cbe3SChaitanya Kulkarni { 423a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 424a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 425a7a7cbe3SChaitanya Kulkarni use_sgl); 426a7a7cbe3SChaitanya Kulkarni 427a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 42857dacad5SJay Sternberg } 42957dacad5SJay Sternberg 43057dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 43157dacad5SJay Sternberg unsigned int hctx_idx) 43257dacad5SJay Sternberg { 43357dacad5SJay Sternberg struct nvme_dev *dev = data; 434147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 43557dacad5SJay Sternberg 43657dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 43757dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 43857dacad5SJay Sternberg WARN_ON(nvmeq->tags); 43957dacad5SJay Sternberg 44057dacad5SJay Sternberg hctx->driver_data = nvmeq; 44157dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 44257dacad5SJay Sternberg return 0; 44357dacad5SJay Sternberg } 44457dacad5SJay Sternberg 44557dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 44657dacad5SJay Sternberg { 44757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 44857dacad5SJay Sternberg 44957dacad5SJay Sternberg nvmeq->tags = NULL; 45057dacad5SJay Sternberg } 45157dacad5SJay Sternberg 45257dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 45357dacad5SJay Sternberg unsigned int hctx_idx) 45457dacad5SJay Sternberg { 45557dacad5SJay Sternberg struct nvme_dev *dev = data; 456147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 45757dacad5SJay Sternberg 45857dacad5SJay Sternberg if (!nvmeq->tags) 45957dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 46057dacad5SJay Sternberg 46157dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 46257dacad5SJay Sternberg hctx->driver_data = nvmeq; 46357dacad5SJay Sternberg return 0; 46457dacad5SJay Sternberg } 46557dacad5SJay Sternberg 466d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 467d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 46857dacad5SJay Sternberg { 469d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 470f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4710350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 472147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 47357dacad5SJay Sternberg 47457dacad5SJay Sternberg BUG_ON(!nvmeq); 475f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 47659e29ce6SSagi Grimberg 47759e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 47857dacad5SJay Sternberg return 0; 47957dacad5SJay Sternberg } 48057dacad5SJay Sternberg 4813b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4823b6592f7SJens Axboe { 4833b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4843b6592f7SJens Axboe if (dev->num_vecs > 1) 4853b6592f7SJens Axboe return 1; 4863b6592f7SJens Axboe 4873b6592f7SJens Axboe return 0; 4883b6592f7SJens Axboe } 4893b6592f7SJens Axboe 490dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 491dca51e78SChristoph Hellwig { 492dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4933b6592f7SJens Axboe int i, qoff, offset; 494dca51e78SChristoph Hellwig 4953b6592f7SJens Axboe offset = queue_irq_offset(dev); 4963b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4973b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4983b6592f7SJens Axboe 4993b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 5003b6592f7SJens Axboe if (!map->nr_queues) { 5013b6592f7SJens Axboe BUG_ON(i == NVMEQ_TYPE_READ); 5023b6592f7SJens Axboe 5033b6592f7SJens Axboe /* shared set, resuse read set parameters */ 5043b6592f7SJens Axboe map->nr_queues = dev->io_queues[NVMEQ_TYPE_READ]; 5053b6592f7SJens Axboe qoff = 0; 5063b6592f7SJens Axboe offset = queue_irq_offset(dev); 5073b6592f7SJens Axboe } 5083b6592f7SJens Axboe 5094b04cc6aSJens Axboe /* 5104b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 5114b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 5124b04cc6aSJens Axboe */ 5133b6592f7SJens Axboe map->queue_offset = qoff; 5144b04cc6aSJens Axboe if (i != NVMEQ_TYPE_POLL) 5153b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 5164b04cc6aSJens Axboe else 5174b04cc6aSJens Axboe blk_mq_map_queues(map); 5183b6592f7SJens Axboe qoff += map->nr_queues; 5193b6592f7SJens Axboe offset += map->nr_queues; 5203b6592f7SJens Axboe } 5213b6592f7SJens Axboe 5223b6592f7SJens Axboe return 0; 523dca51e78SChristoph Hellwig } 524dca51e78SChristoph Hellwig 52557dacad5SJay Sternberg /** 52690ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 52757dacad5SJay Sternberg * @nvmeq: The queue to use 52857dacad5SJay Sternberg * @cmd: The command to send 52957dacad5SJay Sternberg */ 53090ea5ca4SChristoph Hellwig static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 53157dacad5SJay Sternberg { 53290ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 5330f238ff5SLogan Gunthorpe 53490ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 53557dacad5SJay Sternberg 53690ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 53790ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 53890ea5ca4SChristoph Hellwig if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 53990ea5ca4SChristoph Hellwig nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 54090ea5ca4SChristoph Hellwig writel(nvmeq->sq_tail, nvmeq->q_db); 54190ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 54257dacad5SJay Sternberg } 54357dacad5SJay Sternberg 544a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 54557dacad5SJay Sternberg { 546f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 547a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 54857dacad5SJay Sternberg } 54957dacad5SJay Sternberg 550955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 551955b1b5aSMinwoo Im { 552955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 55320469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 554955b1b5aSMinwoo Im unsigned int avg_seg_size; 555955b1b5aSMinwoo Im 55620469a37SKeith Busch if (nseg == 0) 55720469a37SKeith Busch return false; 55820469a37SKeith Busch 55920469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 560955b1b5aSMinwoo Im 561955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 562955b1b5aSMinwoo Im return false; 563955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 564955b1b5aSMinwoo Im return false; 565955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 566955b1b5aSMinwoo Im return false; 567955b1b5aSMinwoo Im return true; 568955b1b5aSMinwoo Im } 569955b1b5aSMinwoo Im 570fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 57157dacad5SJay Sternberg { 572f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 573f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 574b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 575f4800d6dSChristoph Hellwig 576955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 577955b1b5aSMinwoo Im 578f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 579943e942eSJens Axboe iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 580f4800d6dSChristoph Hellwig if (!iod->sg) 581fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 582f4800d6dSChristoph Hellwig } else { 583f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 58457dacad5SJay Sternberg } 58557dacad5SJay Sternberg 586f4800d6dSChristoph Hellwig iod->aborted = 0; 58757dacad5SJay Sternberg iod->npages = -1; 58857dacad5SJay Sternberg iod->nents = 0; 589f4800d6dSChristoph Hellwig iod->length = size; 590f80ec966SKeith Busch 591fc17b653SChristoph Hellwig return BLK_STS_OK; 59257dacad5SJay Sternberg } 59357dacad5SJay Sternberg 594f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 59557dacad5SJay Sternberg { 596f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 597a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 598a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 599a7a7cbe3SChaitanya Kulkarni 60057dacad5SJay Sternberg int i; 60157dacad5SJay Sternberg 60257dacad5SJay Sternberg if (iod->npages == 0) 603a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 604a7a7cbe3SChaitanya Kulkarni dma_addr); 605a7a7cbe3SChaitanya Kulkarni 60657dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 607a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 608a7a7cbe3SChaitanya Kulkarni 609a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 610a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 611a7a7cbe3SChaitanya Kulkarni 612a7a7cbe3SChaitanya Kulkarni next_dma_addr = 613a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 614a7a7cbe3SChaitanya Kulkarni } else { 615a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 616a7a7cbe3SChaitanya Kulkarni 617a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 618a7a7cbe3SChaitanya Kulkarni } 619a7a7cbe3SChaitanya Kulkarni 620a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 621a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 62257dacad5SJay Sternberg } 62357dacad5SJay Sternberg 624f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 625943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 62657dacad5SJay Sternberg } 62757dacad5SJay Sternberg 628d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 629d0877473SKeith Busch { 630d0877473SKeith Busch int i; 631d0877473SKeith Busch struct scatterlist *sg; 632d0877473SKeith Busch 633d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 634d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 635d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 636d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 637d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 638d0877473SKeith Busch sg_dma_len(sg)); 639d0877473SKeith Busch } 640d0877473SKeith Busch } 641d0877473SKeith Busch 642a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 643a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 64457dacad5SJay Sternberg { 645f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 64657dacad5SJay Sternberg struct dma_pool *pool; 647b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 64857dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 64957dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 65057dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6515fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 65257dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 65357dacad5SJay Sternberg __le64 *prp_list; 654a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 65557dacad5SJay Sternberg dma_addr_t prp_dma; 65657dacad5SJay Sternberg int nprps, i; 65757dacad5SJay Sternberg 65857dacad5SJay Sternberg length -= (page_size - offset); 6595228b328SJan H. Schönherr if (length <= 0) { 6605228b328SJan H. Schönherr iod->first_dma = 0; 661a7a7cbe3SChaitanya Kulkarni goto done; 6625228b328SJan H. Schönherr } 66357dacad5SJay Sternberg 66457dacad5SJay Sternberg dma_len -= (page_size - offset); 66557dacad5SJay Sternberg if (dma_len) { 66657dacad5SJay Sternberg dma_addr += (page_size - offset); 66757dacad5SJay Sternberg } else { 66857dacad5SJay Sternberg sg = sg_next(sg); 66957dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 67057dacad5SJay Sternberg dma_len = sg_dma_len(sg); 67157dacad5SJay Sternberg } 67257dacad5SJay Sternberg 67357dacad5SJay Sternberg if (length <= page_size) { 67457dacad5SJay Sternberg iod->first_dma = dma_addr; 675a7a7cbe3SChaitanya Kulkarni goto done; 67657dacad5SJay Sternberg } 67757dacad5SJay Sternberg 67857dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 67957dacad5SJay Sternberg if (nprps <= (256 / 8)) { 68057dacad5SJay Sternberg pool = dev->prp_small_pool; 68157dacad5SJay Sternberg iod->npages = 0; 68257dacad5SJay Sternberg } else { 68357dacad5SJay Sternberg pool = dev->prp_page_pool; 68457dacad5SJay Sternberg iod->npages = 1; 68557dacad5SJay Sternberg } 68657dacad5SJay Sternberg 68769d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68857dacad5SJay Sternberg if (!prp_list) { 68957dacad5SJay Sternberg iod->first_dma = dma_addr; 69057dacad5SJay Sternberg iod->npages = -1; 69186eea289SKeith Busch return BLK_STS_RESOURCE; 69257dacad5SJay Sternberg } 69357dacad5SJay Sternberg list[0] = prp_list; 69457dacad5SJay Sternberg iod->first_dma = prp_dma; 69557dacad5SJay Sternberg i = 0; 69657dacad5SJay Sternberg for (;;) { 69757dacad5SJay Sternberg if (i == page_size >> 3) { 69857dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 69969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 70057dacad5SJay Sternberg if (!prp_list) 70186eea289SKeith Busch return BLK_STS_RESOURCE; 70257dacad5SJay Sternberg list[iod->npages++] = prp_list; 70357dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 70457dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 70557dacad5SJay Sternberg i = 1; 70657dacad5SJay Sternberg } 70757dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 70857dacad5SJay Sternberg dma_len -= page_size; 70957dacad5SJay Sternberg dma_addr += page_size; 71057dacad5SJay Sternberg length -= page_size; 71157dacad5SJay Sternberg if (length <= 0) 71257dacad5SJay Sternberg break; 71357dacad5SJay Sternberg if (dma_len > 0) 71457dacad5SJay Sternberg continue; 71586eea289SKeith Busch if (unlikely(dma_len < 0)) 71686eea289SKeith Busch goto bad_sgl; 71757dacad5SJay Sternberg sg = sg_next(sg); 71857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 71957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 72057dacad5SJay Sternberg } 72157dacad5SJay Sternberg 722a7a7cbe3SChaitanya Kulkarni done: 723a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 724a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 725a7a7cbe3SChaitanya Kulkarni 72686eea289SKeith Busch return BLK_STS_OK; 72786eea289SKeith Busch 72886eea289SKeith Busch bad_sgl: 729d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 730d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 731d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 73286eea289SKeith Busch return BLK_STS_IOERR; 73357dacad5SJay Sternberg } 73457dacad5SJay Sternberg 735a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 736a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 737a7a7cbe3SChaitanya Kulkarni { 738a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 739a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 740a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 741a7a7cbe3SChaitanya Kulkarni } 742a7a7cbe3SChaitanya Kulkarni 743a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 744a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 745a7a7cbe3SChaitanya Kulkarni { 746a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 747a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 748a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 749a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 750a7a7cbe3SChaitanya Kulkarni } else { 751a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 752a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 753a7a7cbe3SChaitanya Kulkarni } 754a7a7cbe3SChaitanya Kulkarni } 755a7a7cbe3SChaitanya Kulkarni 756a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 757b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 758a7a7cbe3SChaitanya Kulkarni { 759a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 760a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 761a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 762a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 763a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 764b0f2853bSChristoph Hellwig int i = 0; 765a7a7cbe3SChaitanya Kulkarni 766a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 767a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 768a7a7cbe3SChaitanya Kulkarni 769b0f2853bSChristoph Hellwig if (entries == 1) { 770a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 771a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 772a7a7cbe3SChaitanya Kulkarni } 773a7a7cbe3SChaitanya Kulkarni 774a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 775a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 776a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 777a7a7cbe3SChaitanya Kulkarni } else { 778a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 779a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 780a7a7cbe3SChaitanya Kulkarni } 781a7a7cbe3SChaitanya Kulkarni 782a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 783a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 784a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 785a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 786a7a7cbe3SChaitanya Kulkarni } 787a7a7cbe3SChaitanya Kulkarni 788a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 789a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 790a7a7cbe3SChaitanya Kulkarni 791a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 792a7a7cbe3SChaitanya Kulkarni 793a7a7cbe3SChaitanya Kulkarni do { 794a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 795a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 796a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 797a7a7cbe3SChaitanya Kulkarni 798a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 799a7a7cbe3SChaitanya Kulkarni if (!sg_list) 800a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 801a7a7cbe3SChaitanya Kulkarni 802a7a7cbe3SChaitanya Kulkarni i = 0; 803a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 804a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 805a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 806a7a7cbe3SChaitanya Kulkarni } 807a7a7cbe3SChaitanya Kulkarni 808a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 809a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 810b0f2853bSChristoph Hellwig } while (--entries > 0); 811a7a7cbe3SChaitanya Kulkarni 812a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 813a7a7cbe3SChaitanya Kulkarni } 814a7a7cbe3SChaitanya Kulkarni 815fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 816b131c61dSChristoph Hellwig struct nvme_command *cmnd) 81757dacad5SJay Sternberg { 818f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 819ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 820ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 821ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 822fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 823b0f2853bSChristoph Hellwig int nr_mapped; 82457dacad5SJay Sternberg 825f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 826ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 827ba1ca37eSChristoph Hellwig if (!iod->nents) 828ba1ca37eSChristoph Hellwig goto out; 829ba1ca37eSChristoph Hellwig 830fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 831e0596ab2SLogan Gunthorpe 832e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 833e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 834e0596ab2SLogan Gunthorpe dma_dir); 835e0596ab2SLogan Gunthorpe else 836e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 837e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 838b0f2853bSChristoph Hellwig if (!nr_mapped) 839ba1ca37eSChristoph Hellwig goto out; 840ba1ca37eSChristoph Hellwig 841955b1b5aSMinwoo Im if (iod->use_sgl) 842b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 843a7a7cbe3SChaitanya Kulkarni else 844a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 845a7a7cbe3SChaitanya Kulkarni 84686eea289SKeith Busch if (ret != BLK_STS_OK) 847ba1ca37eSChristoph Hellwig goto out_unmap; 848ba1ca37eSChristoph Hellwig 849fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 850ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 851ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 852ba1ca37eSChristoph Hellwig goto out_unmap; 853ba1ca37eSChristoph Hellwig 854bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 855bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 856ba1ca37eSChristoph Hellwig goto out_unmap; 857ba1ca37eSChristoph Hellwig 858bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 859ba1ca37eSChristoph Hellwig goto out_unmap; 8603045c0d0SChaitanya Kulkarni 8613045c0d0SChaitanya Kulkarni cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 86257dacad5SJay Sternberg } 86357dacad5SJay Sternberg 864fc17b653SChristoph Hellwig return BLK_STS_OK; 865ba1ca37eSChristoph Hellwig 866ba1ca37eSChristoph Hellwig out_unmap: 867ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 868ba1ca37eSChristoph Hellwig out: 869ba1ca37eSChristoph Hellwig return ret; 87057dacad5SJay Sternberg } 87157dacad5SJay Sternberg 872f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 873d4f6c3abSChristoph Hellwig { 874f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 875d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 876d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 877d4f6c3abSChristoph Hellwig 878d4f6c3abSChristoph Hellwig if (iod->nents) { 879e0596ab2SLogan Gunthorpe /* P2PDMA requests do not need to be unmapped */ 880e0596ab2SLogan Gunthorpe if (!is_pci_p2pdma_page(sg_page(iod->sg))) 881d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 882e0596ab2SLogan Gunthorpe 883f7f1fc36SMax Gurtovoy if (blk_integrity_rq(req)) 884bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 885d4f6c3abSChristoph Hellwig } 886d4f6c3abSChristoph Hellwig 887f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 888f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 88957dacad5SJay Sternberg } 89057dacad5SJay Sternberg 89157dacad5SJay Sternberg /* 89257dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 89357dacad5SJay Sternberg */ 894fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 89557dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 89657dacad5SJay Sternberg { 89757dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 89857dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 89957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 90057dacad5SJay Sternberg struct request *req = bd->rq; 901ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 902ebe6d874SChristoph Hellwig blk_status_t ret; 90357dacad5SJay Sternberg 904d1f06f4aSJens Axboe /* 905d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 906d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 907d1f06f4aSJens Axboe */ 9084b04cc6aSJens Axboe if (unlikely(nvmeq->cq_vector < 0 && !nvmeq->polled)) 909d1f06f4aSJens Axboe return BLK_STS_IOERR; 910d1f06f4aSJens Axboe 911f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 912fc17b653SChristoph Hellwig if (ret) 913f4800d6dSChristoph Hellwig return ret; 91457dacad5SJay Sternberg 915b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 916fc17b653SChristoph Hellwig if (ret) 917f9d03f96SChristoph Hellwig goto out_free_cmd; 91857dacad5SJay Sternberg 919fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 920b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 921fc17b653SChristoph Hellwig if (ret) 922f9d03f96SChristoph Hellwig goto out_cleanup_iod; 923fc17b653SChristoph Hellwig } 924ba1ca37eSChristoph Hellwig 925aae239e1SChristoph Hellwig blk_mq_start_request(req); 92690ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &cmnd); 927fc17b653SChristoph Hellwig return BLK_STS_OK; 928f9d03f96SChristoph Hellwig out_cleanup_iod: 929f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 930f9d03f96SChristoph Hellwig out_free_cmd: 931f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 932ba1ca37eSChristoph Hellwig return ret; 93357dacad5SJay Sternberg } 93457dacad5SJay Sternberg 9353b6592f7SJens Axboe static int nvme_rq_flags_to_type(struct request_queue *q, unsigned int flags) 9363b6592f7SJens Axboe { 9374b04cc6aSJens Axboe if ((flags & REQ_HIPRI) && test_bit(QUEUE_FLAG_POLL, &q->queue_flags)) 9384b04cc6aSJens Axboe return NVMEQ_TYPE_POLL; 9393b6592f7SJens Axboe if ((flags & REQ_OP_MASK) == REQ_OP_READ) 9403b6592f7SJens Axboe return NVMEQ_TYPE_READ; 9413b6592f7SJens Axboe 9423b6592f7SJens Axboe return NVMEQ_TYPE_WRITE; 9433b6592f7SJens Axboe } 9443b6592f7SJens Axboe 94577f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 946eee417b0SChristoph Hellwig { 947f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 948eee417b0SChristoph Hellwig 94977f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 95077f02a7aSChristoph Hellwig nvme_complete_rq(req); 95157dacad5SJay Sternberg } 95257dacad5SJay Sternberg 953d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 954750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 955d783e0bdSMarta Rybczynska { 956750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 957750dde44SChristoph Hellwig nvmeq->cq_phase; 958d783e0bdSMarta Rybczynska } 959d783e0bdSMarta Rybczynska 960eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 96157dacad5SJay Sternberg { 962eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 96357dacad5SJay Sternberg 964eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 965eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 966eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 967eb281c82SSagi Grimberg } 968adf68f21SChristoph Hellwig 9695cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 97057dacad5SJay Sternberg { 9715cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 97257dacad5SJay Sternberg struct request *req; 973adf68f21SChristoph Hellwig 97483a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9751b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 976aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 97783a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 97883a12fb7SSagi Grimberg return; 979aae239e1SChristoph Hellwig } 980aae239e1SChristoph Hellwig 981adf68f21SChristoph Hellwig /* 982adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 983adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 984adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 985adf68f21SChristoph Hellwig * for them but rather special case them here. 986adf68f21SChristoph Hellwig */ 987adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 98838dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9897bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 99083a12fb7SSagi Grimberg cqe->status, &cqe->result); 991a0fa9647SJens Axboe return; 99257dacad5SJay Sternberg } 99357dacad5SJay Sternberg 99483a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 99583a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 99683a12fb7SSagi Grimberg } 99757dacad5SJay Sternberg 9985cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 99983a12fb7SSagi Grimberg { 10005cb525c8SJens Axboe while (start != end) { 10015cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 10025cb525c8SJens Axboe if (++start == nvmeq->q_depth) 10035cb525c8SJens Axboe start = 0; 10045cb525c8SJens Axboe } 10055cb525c8SJens Axboe } 100683a12fb7SSagi Grimberg 10075cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10085cb525c8SJens Axboe { 1009920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 1010920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1011920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1012920d13a8SSagi Grimberg } 1013a0fa9647SJens Axboe } 1014a0fa9647SJens Axboe 10155cb525c8SJens Axboe static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10165cb525c8SJens Axboe u16 *end, int tag) 1017a0fa9647SJens Axboe { 10185cb525c8SJens Axboe bool found = false; 101983a12fb7SSagi Grimberg 10205cb525c8SJens Axboe *start = nvmeq->cq_head; 10215cb525c8SJens Axboe while (!found && nvme_cqe_pending(nvmeq)) { 10225cb525c8SJens Axboe if (nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10235cb525c8SJens Axboe found = true; 10245cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 102557dacad5SJay Sternberg } 10265cb525c8SJens Axboe *end = nvmeq->cq_head; 102757dacad5SJay Sternberg 10285cb525c8SJens Axboe if (*start != *end) 1029eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10305cb525c8SJens Axboe return found; 103157dacad5SJay Sternberg } 103257dacad5SJay Sternberg 103357dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 103457dacad5SJay Sternberg { 103557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 103668fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10375cb525c8SJens Axboe u16 start, end; 10385cb525c8SJens Axboe 10391ab0cd69SJens Axboe spin_lock(&nvmeq->cq_lock); 104068fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 104168fa9dbeSJens Axboe ret = IRQ_HANDLED; 10425cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 104368fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10441ab0cd69SJens Axboe spin_unlock(&nvmeq->cq_lock); 10455cb525c8SJens Axboe 104668fa9dbeSJens Axboe if (start != end) { 10475cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10485cb525c8SJens Axboe return IRQ_HANDLED; 104957dacad5SJay Sternberg } 105057dacad5SJay Sternberg 105168fa9dbeSJens Axboe return ret; 105257dacad5SJay Sternberg } 105357dacad5SJay Sternberg 105457dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 105557dacad5SJay Sternberg { 105657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1057750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 105857dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1059d783e0bdSMarta Rybczynska return IRQ_NONE; 106057dacad5SJay Sternberg } 106157dacad5SJay Sternberg 10627776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 1063a0fa9647SJens Axboe { 10645cb525c8SJens Axboe u16 start, end; 10655cb525c8SJens Axboe bool found; 1066a0fa9647SJens Axboe 1067750dde44SChristoph Hellwig if (!nvme_cqe_pending(nvmeq)) 1068442e19b7SSagi Grimberg return 0; 1069442e19b7SSagi Grimberg 10701ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 10715cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10721ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 1073442e19b7SSagi Grimberg 10745cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1075442e19b7SSagi Grimberg return found; 1076a0fa9647SJens Axboe } 1077a0fa9647SJens Axboe 10787776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 10797776db1cSKeith Busch { 10807776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 10817776db1cSKeith Busch 10827776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 10837776db1cSKeith Busch } 10847776db1cSKeith Busch 1085ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 108657dacad5SJay Sternberg { 1087f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1088147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 108957dacad5SJay Sternberg struct nvme_command c; 109057dacad5SJay Sternberg 109157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 109257dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1093ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 109490ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &c); 109557dacad5SJay Sternberg } 109657dacad5SJay Sternberg 109757dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 109857dacad5SJay Sternberg { 109957dacad5SJay Sternberg struct nvme_command c; 110057dacad5SJay Sternberg 110157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 110257dacad5SJay Sternberg c.delete_queue.opcode = opcode; 110357dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 110457dacad5SJay Sternberg 11051c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 110657dacad5SJay Sternberg } 110757dacad5SJay Sternberg 110857dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1109a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 111057dacad5SJay Sternberg { 111157dacad5SJay Sternberg struct nvme_command c; 11124b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11134b04cc6aSJens Axboe 11144b04cc6aSJens Axboe if (vector != -1) 11154b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 111657dacad5SJay Sternberg 111757dacad5SJay Sternberg /* 111816772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 111957dacad5SJay Sternberg * is attached to the request. 112057dacad5SJay Sternberg */ 112157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112257dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 112357dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 112457dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 112557dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 112657dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 11274b04cc6aSJens Axboe if (vector != -1) 1128a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 11294b04cc6aSJens Axboe else 11304b04cc6aSJens Axboe c.create_cq.irq_vector = 0; 113157dacad5SJay Sternberg 11321c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 113357dacad5SJay Sternberg } 113457dacad5SJay Sternberg 113557dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 113657dacad5SJay Sternberg struct nvme_queue *nvmeq) 113757dacad5SJay Sternberg { 11389abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 113957dacad5SJay Sternberg struct nvme_command c; 114081c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 114157dacad5SJay Sternberg 114257dacad5SJay Sternberg /* 11439abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11449abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11459abd68efSJens Axboe * URGENT. 11469abd68efSJens Axboe */ 11479abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11489abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11499abd68efSJens Axboe 11509abd68efSJens Axboe /* 115116772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 115257dacad5SJay Sternberg * is attached to the request. 115357dacad5SJay Sternberg */ 115457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 115557dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 115657dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 115757dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 115857dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 115957dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 116057dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 116157dacad5SJay Sternberg 11621c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 116357dacad5SJay Sternberg } 116457dacad5SJay Sternberg 116557dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 116657dacad5SJay Sternberg { 116757dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 116857dacad5SJay Sternberg } 116957dacad5SJay Sternberg 117057dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 117157dacad5SJay Sternberg { 117257dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 117357dacad5SJay Sternberg } 117457dacad5SJay Sternberg 11752a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 117657dacad5SJay Sternberg { 1177f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1178f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 117957dacad5SJay Sternberg 118027fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 118127fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1182e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1183e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 118457dacad5SJay Sternberg } 118557dacad5SJay Sternberg 1186b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1187b2a0eb1aSKeith Busch { 1188b2a0eb1aSKeith Busch 1189b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1190b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1191b2a0eb1aSKeith Busch */ 1192b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1193b2a0eb1aSKeith Busch 1194ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1195ad70062cSJianchao Wang switch (dev->ctrl.state) { 1196ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1197ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1198b2a0eb1aSKeith Busch return false; 1199ad70062cSJianchao Wang default: 1200ad70062cSJianchao Wang break; 1201ad70062cSJianchao Wang } 1202b2a0eb1aSKeith Busch 1203b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1204b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1205b2a0eb1aSKeith Busch */ 1206b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1207b2a0eb1aSKeith Busch return false; 1208b2a0eb1aSKeith Busch 1209b2a0eb1aSKeith Busch return true; 1210b2a0eb1aSKeith Busch } 1211b2a0eb1aSKeith Busch 1212b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1213b2a0eb1aSKeith Busch { 1214b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1215b2a0eb1aSKeith Busch u16 pci_status; 1216b2a0eb1aSKeith Busch int result; 1217b2a0eb1aSKeith Busch 1218b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1219b2a0eb1aSKeith Busch &pci_status); 1220b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1221b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1222b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1223b2a0eb1aSKeith Busch csts, pci_status); 1224b2a0eb1aSKeith Busch else 1225b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1226b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1227b2a0eb1aSKeith Busch csts, result); 1228b2a0eb1aSKeith Busch } 1229b2a0eb1aSKeith Busch 123031c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 123157dacad5SJay Sternberg { 1232f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1233f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 123457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 123557dacad5SJay Sternberg struct request *abort_req; 123657dacad5SJay Sternberg struct nvme_command cmd; 1237b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1238b2a0eb1aSKeith Busch 1239651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1240651438bbSWen Xiong * the recovery mechanism will surely fail. 1241651438bbSWen Xiong */ 1242651438bbSWen Xiong mb(); 1243651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1244651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1245651438bbSWen Xiong 1246b2a0eb1aSKeith Busch /* 1247b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1248b2a0eb1aSKeith Busch */ 1249b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1250b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1251b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1252d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1253db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1254b2a0eb1aSKeith Busch } 125557dacad5SJay Sternberg 125631c7c7d2SChristoph Hellwig /* 12577776db1cSKeith Busch * Did we miss an interrupt? 12587776db1cSKeith Busch */ 12597776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 12607776db1cSKeith Busch dev_warn(dev->ctrl.device, 12617776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12627776db1cSKeith Busch req->tag, nvmeq->qid); 1263db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12647776db1cSKeith Busch } 12657776db1cSKeith Busch 12667776db1cSKeith Busch /* 1267fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1268fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1269fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1270db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1271fd634f41SChristoph Hellwig */ 12724244140dSKeith Busch switch (dev->ctrl.state) { 12734244140dSKeith Busch case NVME_CTRL_CONNECTING: 12744244140dSKeith Busch case NVME_CTRL_RESETTING: 1275b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1276fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1277fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1278a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 127927fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1280db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12814244140dSKeith Busch default: 12824244140dSKeith Busch break; 1283fd634f41SChristoph Hellwig } 1284fd634f41SChristoph Hellwig 1285fd634f41SChristoph Hellwig /* 1286e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1287e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1288e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 128931c7c7d2SChristoph Hellwig */ 1290f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12911b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 129257dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 129357dacad5SJay Sternberg req->tag, nvmeq->qid); 1294a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1295d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1296e1569a16SKeith Busch 129727fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1298db8c48e4SChristoph Hellwig return BLK_EH_DONE; 129957dacad5SJay Sternberg } 130057dacad5SJay Sternberg 1301e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1302e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1303e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1304e7a2a87dSChristoph Hellwig } 13057bf7d778SKeith Busch iod->aborted = 1; 130657dacad5SJay Sternberg 130757dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 130857dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 130957dacad5SJay Sternberg cmd.abort.cid = req->tag; 131057dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 131157dacad5SJay Sternberg 13121b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13131b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 131457dacad5SJay Sternberg req->tag, nvmeq->qid); 1315e7a2a87dSChristoph Hellwig 1316e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1317eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13186bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13196bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 132031c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 132157dacad5SJay Sternberg } 132257dacad5SJay Sternberg 1323e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1324e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1325e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 132657dacad5SJay Sternberg 132757dacad5SJay Sternberg /* 132857dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 132957dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 133057dacad5SJay Sternberg * as the device then is in a faulty state. 133157dacad5SJay Sternberg */ 133257dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 133357dacad5SJay Sternberg } 133457dacad5SJay Sternberg 133557dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 133657dacad5SJay Sternberg { 133757dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 133857dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 13390f238ff5SLogan Gunthorpe 13400f238ff5SLogan Gunthorpe if (nvmeq->sq_cmds) { 13410f238ff5SLogan Gunthorpe if (nvmeq->sq_cmds_is_io) 13420f238ff5SLogan Gunthorpe pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev), 13430f238ff5SLogan Gunthorpe nvmeq->sq_cmds, 13440f238ff5SLogan Gunthorpe SQ_SIZE(nvmeq->q_depth)); 13450f238ff5SLogan Gunthorpe else 13460f238ff5SLogan Gunthorpe dma_free_coherent(nvmeq->q_dmadev, 13470f238ff5SLogan Gunthorpe SQ_SIZE(nvmeq->q_depth), 13480f238ff5SLogan Gunthorpe nvmeq->sq_cmds, 13490f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr); 13500f238ff5SLogan Gunthorpe } 135157dacad5SJay Sternberg } 135257dacad5SJay Sternberg 135357dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 135457dacad5SJay Sternberg { 135557dacad5SJay Sternberg int i; 135657dacad5SJay Sternberg 1357d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1358d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1359147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 136057dacad5SJay Sternberg } 136157dacad5SJay Sternberg } 136257dacad5SJay Sternberg 136357dacad5SJay Sternberg /** 136457dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 136540581d1aSBart Van Assche * @nvmeq: queue to suspend 136657dacad5SJay Sternberg */ 136757dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 136857dacad5SJay Sternberg { 136957dacad5SJay Sternberg int vector; 137057dacad5SJay Sternberg 13711ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 13724b04cc6aSJens Axboe if (nvmeq->cq_vector == -1 && !nvmeq->polled) { 13731ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 137457dacad5SJay Sternberg return 1; 137557dacad5SJay Sternberg } 13760ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 137757dacad5SJay Sternberg nvmeq->dev->online_queues--; 137857dacad5SJay Sternberg nvmeq->cq_vector = -1; 13794b04cc6aSJens Axboe nvmeq->polled = false; 13801ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 138157dacad5SJay Sternberg 1382d1f06f4aSJens Axboe /* 1383d1f06f4aSJens Axboe * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without 1384d1f06f4aSJens Axboe * having to grab the lock. 1385d1f06f4aSJens Axboe */ 1386d1f06f4aSJens Axboe mb(); 138757dacad5SJay Sternberg 13881c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1389c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 139057dacad5SJay Sternberg 13914b04cc6aSJens Axboe if (vector != -1) 13920ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 139357dacad5SJay Sternberg 139457dacad5SJay Sternberg return 0; 139557dacad5SJay Sternberg } 139657dacad5SJay Sternberg 1397a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 139857dacad5SJay Sternberg { 1399147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 14005cb525c8SJens Axboe u16 start, end; 140157dacad5SJay Sternberg 1402a5cdb68cSKeith Busch if (shutdown) 1403a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1404a5cdb68cSKeith Busch else 140520d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 140657dacad5SJay Sternberg 14071ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 14085cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 14091ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 14105cb525c8SJens Axboe 14115cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 141257dacad5SJay Sternberg } 141357dacad5SJay Sternberg 141457dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 141557dacad5SJay Sternberg int entry_size) 141657dacad5SJay Sternberg { 141757dacad5SJay Sternberg int q_depth = dev->q_depth; 14185fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14195fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 142057dacad5SJay Sternberg 142157dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 142257dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14235fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 142457dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 142557dacad5SJay Sternberg 142657dacad5SJay Sternberg /* 142757dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 142857dacad5SJay Sternberg * would be better to map queues in system memory with the 142957dacad5SJay Sternberg * original depth 143057dacad5SJay Sternberg */ 143157dacad5SJay Sternberg if (q_depth < 64) 143257dacad5SJay Sternberg return -ENOMEM; 143357dacad5SJay Sternberg } 143457dacad5SJay Sternberg 143557dacad5SJay Sternberg return q_depth; 143657dacad5SJay Sternberg } 143757dacad5SJay Sternberg 143857dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 143957dacad5SJay Sternberg int qid, int depth) 144057dacad5SJay Sternberg { 14410f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1442815c6704SKeith Busch 14430f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14440f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14450f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14460f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 14470f238ff5SLogan Gunthorpe nvmeq->sq_cmds_is_io = true; 14480f238ff5SLogan Gunthorpe } 14490f238ff5SLogan Gunthorpe 14500f238ff5SLogan Gunthorpe if (!nvmeq->sq_cmds) { 145157dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 145257dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 14530f238ff5SLogan Gunthorpe nvmeq->sq_cmds_is_io = false; 14540f238ff5SLogan Gunthorpe } 14550f238ff5SLogan Gunthorpe 145657dacad5SJay Sternberg if (!nvmeq->sq_cmds) 145757dacad5SJay Sternberg return -ENOMEM; 145857dacad5SJay Sternberg return 0; 145957dacad5SJay Sternberg } 146057dacad5SJay Sternberg 1461a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 146257dacad5SJay Sternberg { 1463147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 146457dacad5SJay Sternberg 146562314e40SKeith Busch if (dev->ctrl.queue_count > qid) 146662314e40SKeith Busch return 0; 146757dacad5SJay Sternberg 146857dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 146957dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 147057dacad5SJay Sternberg if (!nvmeq->cqes) 147157dacad5SJay Sternberg goto free_nvmeq; 147257dacad5SJay Sternberg 147357dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 147457dacad5SJay Sternberg goto free_cqdma; 147557dacad5SJay Sternberg 147657dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 147757dacad5SJay Sternberg nvmeq->dev = dev; 14781ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14791ab0cd69SJens Axboe spin_lock_init(&nvmeq->cq_lock); 148057dacad5SJay Sternberg nvmeq->cq_head = 0; 148157dacad5SJay Sternberg nvmeq->cq_phase = 1; 148257dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 148357dacad5SJay Sternberg nvmeq->q_depth = depth; 148457dacad5SJay Sternberg nvmeq->qid = qid; 148557dacad5SJay Sternberg nvmeq->cq_vector = -1; 1486d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 148757dacad5SJay Sternberg 1488147b27e4SSagi Grimberg return 0; 148957dacad5SJay Sternberg 149057dacad5SJay Sternberg free_cqdma: 149157dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 149257dacad5SJay Sternberg nvmeq->cq_dma_addr); 149357dacad5SJay Sternberg free_nvmeq: 1494147b27e4SSagi Grimberg return -ENOMEM; 149557dacad5SJay Sternberg } 149657dacad5SJay Sternberg 1497dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 149857dacad5SJay Sternberg { 14990ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15000ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15010ff199cbSChristoph Hellwig 15020ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15030ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15040ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15050ff199cbSChristoph Hellwig } else { 15060ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15070ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15080ff199cbSChristoph Hellwig } 150957dacad5SJay Sternberg } 151057dacad5SJay Sternberg 151157dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 151257dacad5SJay Sternberg { 151357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 151457dacad5SJay Sternberg 15151ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 151657dacad5SJay Sternberg nvmeq->sq_tail = 0; 151757dacad5SJay Sternberg nvmeq->cq_head = 0; 151857dacad5SJay Sternberg nvmeq->cq_phase = 1; 151957dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 152057dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1521f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 152257dacad5SJay Sternberg dev->online_queues++; 15231ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 152457dacad5SJay Sternberg } 152557dacad5SJay Sternberg 15264b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 152757dacad5SJay Sternberg { 152857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 152957dacad5SJay Sternberg int result; 1530a8e3e0bbSJianchao Wang s16 vector; 153157dacad5SJay Sternberg 153222b55601SKeith Busch /* 153322b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 153422b55601SKeith Busch * has only one vector available. 153522b55601SKeith Busch */ 15364b04cc6aSJens Axboe if (!polled) 1537a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15384b04cc6aSJens Axboe else 15394b04cc6aSJens Axboe vector = -1; 15404b04cc6aSJens Axboe 1541a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1542ded45505SKeith Busch if (result) 1543ded45505SKeith Busch return result; 154457dacad5SJay Sternberg 154557dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 154657dacad5SJay Sternberg if (result < 0) 1547ded45505SKeith Busch return result; 1548ded45505SKeith Busch else if (result) 154957dacad5SJay Sternberg goto release_cq; 155057dacad5SJay Sternberg 1551a8e3e0bbSJianchao Wang /* 1552a8e3e0bbSJianchao Wang * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will 1553a8e3e0bbSJianchao Wang * invoke free_irq for it and cause a 'Trying to free already-free IRQ 1554a8e3e0bbSJianchao Wang * xxx' warning if the create CQ/SQ command times out. 1555a8e3e0bbSJianchao Wang */ 1556a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 15574b04cc6aSJens Axboe nvmeq->polled = polled; 1558161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15594b04cc6aSJens Axboe 15604b04cc6aSJens Axboe if (vector != -1) { 1561dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 156257dacad5SJay Sternberg if (result < 0) 156357dacad5SJay Sternberg goto release_sq; 15644b04cc6aSJens Axboe } 156557dacad5SJay Sternberg 156657dacad5SJay Sternberg return result; 156757dacad5SJay Sternberg 156857dacad5SJay Sternberg release_sq: 1569a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 15704b04cc6aSJens Axboe nvmeq->polled = false; 1571f25a2dfcSJianchao Wang dev->online_queues--; 157257dacad5SJay Sternberg adapter_delete_sq(dev, qid); 157357dacad5SJay Sternberg release_cq: 157457dacad5SJay Sternberg adapter_delete_cq(dev, qid); 157557dacad5SJay Sternberg return result; 157657dacad5SJay Sternberg } 157757dacad5SJay Sternberg 1578f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 157957dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 158077f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 158157dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 158257dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15830350815aSChristoph Hellwig .init_request = nvme_init_request, 158457dacad5SJay Sternberg .timeout = nvme_timeout, 158557dacad5SJay Sternberg }; 158657dacad5SJay Sternberg 1587f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 158857dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 15893b6592f7SJens Axboe .rq_flags_to_type = nvme_rq_flags_to_type, 159077f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 159157dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 159257dacad5SJay Sternberg .init_request = nvme_init_request, 1593dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 159457dacad5SJay Sternberg .timeout = nvme_timeout, 1595a0fa9647SJens Axboe .poll = nvme_poll, 159657dacad5SJay Sternberg }; 159757dacad5SJay Sternberg 159857dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 159957dacad5SJay Sternberg { 16001c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 160169d9a99cSKeith Busch /* 160269d9a99cSKeith Busch * If the controller was reset during removal, it's possible 160369d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 160469d9a99cSKeith Busch * queue to flush these to completion. 160569d9a99cSKeith Busch */ 1606c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16071c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 160857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 160957dacad5SJay Sternberg } 161057dacad5SJay Sternberg } 161157dacad5SJay Sternberg 161257dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 161357dacad5SJay Sternberg { 16141c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 161557dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 161657dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1617e3e9d50cSKeith Busch 161838dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 161957dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 162057dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1621a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1622d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 162357dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 162457dacad5SJay Sternberg 162557dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 162657dacad5SJay Sternberg return -ENOMEM; 162734b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 162857dacad5SJay Sternberg 16291c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16301c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 163157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 163257dacad5SJay Sternberg return -ENOMEM; 163357dacad5SJay Sternberg } 16341c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 163557dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16361c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 163757dacad5SJay Sternberg return -ENODEV; 163857dacad5SJay Sternberg } 163957dacad5SJay Sternberg } else 1640c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 164157dacad5SJay Sternberg 164257dacad5SJay Sternberg return 0; 164357dacad5SJay Sternberg } 164457dacad5SJay Sternberg 164597f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 164697f6ef64SXu Yu { 164797f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 164897f6ef64SXu Yu } 164997f6ef64SXu Yu 165097f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 165197f6ef64SXu Yu { 165297f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 165397f6ef64SXu Yu 165497f6ef64SXu Yu if (size <= dev->bar_mapped_size) 165597f6ef64SXu Yu return 0; 165697f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 165797f6ef64SXu Yu return -ENOMEM; 165897f6ef64SXu Yu if (dev->bar) 165997f6ef64SXu Yu iounmap(dev->bar); 166097f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 166197f6ef64SXu Yu if (!dev->bar) { 166297f6ef64SXu Yu dev->bar_mapped_size = 0; 166397f6ef64SXu Yu return -ENOMEM; 166497f6ef64SXu Yu } 166597f6ef64SXu Yu dev->bar_mapped_size = size; 166697f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 166797f6ef64SXu Yu 166897f6ef64SXu Yu return 0; 166997f6ef64SXu Yu } 167097f6ef64SXu Yu 167101ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 167257dacad5SJay Sternberg { 167357dacad5SJay Sternberg int result; 167457dacad5SJay Sternberg u32 aqa; 167557dacad5SJay Sternberg struct nvme_queue *nvmeq; 167657dacad5SJay Sternberg 167797f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 167897f6ef64SXu Yu if (result < 0) 167997f6ef64SXu Yu return result; 168097f6ef64SXu Yu 16818ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 168220d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 168357dacad5SJay Sternberg 16847a67cbeaSChristoph Hellwig if (dev->subsystem && 16857a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16867a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 168757dacad5SJay Sternberg 168820d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 168957dacad5SJay Sternberg if (result < 0) 169057dacad5SJay Sternberg return result; 169157dacad5SJay Sternberg 1692a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1693147b27e4SSagi Grimberg if (result) 1694147b27e4SSagi Grimberg return result; 169557dacad5SJay Sternberg 1696147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 169757dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 169857dacad5SJay Sternberg aqa |= aqa << 16; 169957dacad5SJay Sternberg 17007a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17017a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17027a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 170357dacad5SJay Sternberg 170420d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 170557dacad5SJay Sternberg if (result) 1706d4875622SKeith Busch return result; 170757dacad5SJay Sternberg 170857dacad5SJay Sternberg nvmeq->cq_vector = 0; 1709161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1710dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 171157dacad5SJay Sternberg if (result) { 171257dacad5SJay Sternberg nvmeq->cq_vector = -1; 1713d4875622SKeith Busch return result; 171457dacad5SJay Sternberg } 171557dacad5SJay Sternberg 171657dacad5SJay Sternberg return result; 171757dacad5SJay Sternberg } 171857dacad5SJay Sternberg 1719749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 172057dacad5SJay Sternberg { 17214b04cc6aSJens Axboe unsigned i, max, rw_queues; 1722749941f2SChristoph Hellwig int ret = 0; 172357dacad5SJay Sternberg 1724d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1725a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1726749941f2SChristoph Hellwig ret = -ENOMEM; 172757dacad5SJay Sternberg break; 1728749941f2SChristoph Hellwig } 1729749941f2SChristoph Hellwig } 173057dacad5SJay Sternberg 1731d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 17324b04cc6aSJens Axboe if (max != 1 && dev->io_queues[NVMEQ_TYPE_POLL]) { 17334b04cc6aSJens Axboe rw_queues = dev->io_queues[NVMEQ_TYPE_READ] + 17344b04cc6aSJens Axboe dev->io_queues[NVMEQ_TYPE_WRITE]; 17354b04cc6aSJens Axboe } else { 17364b04cc6aSJens Axboe rw_queues = max; 17374b04cc6aSJens Axboe } 17384b04cc6aSJens Axboe 1739949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17404b04cc6aSJens Axboe bool polled = i > rw_queues; 17414b04cc6aSJens Axboe 17424b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1743d4875622SKeith Busch if (ret) 174457dacad5SJay Sternberg break; 174557dacad5SJay Sternberg } 174657dacad5SJay Sternberg 1747749941f2SChristoph Hellwig /* 1748749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17498adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17508adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1751749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1752749941f2SChristoph Hellwig */ 1753749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 175457dacad5SJay Sternberg } 175557dacad5SJay Sternberg 1756202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1757202021c1SStephen Bates struct device_attribute *attr, 1758202021c1SStephen Bates char *buf) 1759202021c1SStephen Bates { 1760202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1761202021c1SStephen Bates 1762c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1763202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1764202021c1SStephen Bates } 1765202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1766202021c1SStephen Bates 176788de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 176857dacad5SJay Sternberg { 176988de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 177088de4598SChristoph Hellwig 177188de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 177288de4598SChristoph Hellwig } 177388de4598SChristoph Hellwig 177488de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 177588de4598SChristoph Hellwig { 177688de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 177788de4598SChristoph Hellwig } 177888de4598SChristoph Hellwig 1779f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 178057dacad5SJay Sternberg { 178188de4598SChristoph Hellwig u64 size, offset; 178257dacad5SJay Sternberg resource_size_t bar_size; 178357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17848969f1f8SChristoph Hellwig int bar; 178557dacad5SJay Sternberg 17869fe5c59fSKeith Busch if (dev->cmb_size) 17879fe5c59fSKeith Busch return; 17889fe5c59fSKeith Busch 17897a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1790f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1791f65efd6dSChristoph Hellwig return; 1792202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 179357dacad5SJay Sternberg 179488de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 179588de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17968969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17978969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 179857dacad5SJay Sternberg 179957dacad5SJay Sternberg if (offset > bar_size) 1800f65efd6dSChristoph Hellwig return; 180157dacad5SJay Sternberg 180257dacad5SJay Sternberg /* 180357dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 180457dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 180557dacad5SJay Sternberg * the reported size of the BAR 180657dacad5SJay Sternberg */ 180757dacad5SJay Sternberg if (size > bar_size - offset) 180857dacad5SJay Sternberg size = bar_size - offset; 180957dacad5SJay Sternberg 18100f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18110f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18120f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1813f65efd6dSChristoph Hellwig return; 18140f238ff5SLogan Gunthorpe } 18150f238ff5SLogan Gunthorpe 181657dacad5SJay Sternberg dev->cmb_size = size; 18170f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18180f238ff5SLogan Gunthorpe 18190f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18200f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18210f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1822f65efd6dSChristoph Hellwig 1823f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1824f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1825f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1826f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 182757dacad5SJay Sternberg } 182857dacad5SJay Sternberg 182957dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 183057dacad5SJay Sternberg { 18310f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1832f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1833f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18340f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1835f63572dfSJon Derrick } 183657dacad5SJay Sternberg } 183757dacad5SJay Sternberg 183887ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 183957dacad5SJay Sternberg { 18404033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 184187ad72a5SChristoph Hellwig struct nvme_command c; 184287ad72a5SChristoph Hellwig int ret; 184387ad72a5SChristoph Hellwig 184487ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 184587ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 184687ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 184787ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 184887ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 184987ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 185087ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 185187ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 185287ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 185387ad72a5SChristoph Hellwig 185487ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 185587ad72a5SChristoph Hellwig if (ret) { 185687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 185787ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 185887ad72a5SChristoph Hellwig ret, bits); 185987ad72a5SChristoph Hellwig } 186087ad72a5SChristoph Hellwig return ret; 186187ad72a5SChristoph Hellwig } 186287ad72a5SChristoph Hellwig 186387ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 186487ad72a5SChristoph Hellwig { 186587ad72a5SChristoph Hellwig int i; 186687ad72a5SChristoph Hellwig 186787ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 186887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 186987ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 187087ad72a5SChristoph Hellwig 187187ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 187287ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 187387ad72a5SChristoph Hellwig } 187487ad72a5SChristoph Hellwig 187587ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 187687ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18774033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18784033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18794033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 188087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18817e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 188287ad72a5SChristoph Hellwig } 188387ad72a5SChristoph Hellwig 188492dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 188592dc6895SChristoph Hellwig u32 chunk_size) 188687ad72a5SChristoph Hellwig { 188787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 188892dc6895SChristoph Hellwig u32 max_entries, len; 18894033f35dSChristoph Hellwig dma_addr_t descs_dma; 18902ee0e4edSDan Carpenter int i = 0; 189187ad72a5SChristoph Hellwig void **bufs; 18926fbcde66SMinwoo Im u64 size, tmp; 189387ad72a5SChristoph Hellwig 189487ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 189587ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 189687ad72a5SChristoph Hellwig max_entries = tmp; 1897044a9df1SChristoph Hellwig 1898044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1899044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1900044a9df1SChristoph Hellwig 19014033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 19024033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 190387ad72a5SChristoph Hellwig if (!descs) 190487ad72a5SChristoph Hellwig goto out; 190587ad72a5SChristoph Hellwig 190687ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 190787ad72a5SChristoph Hellwig if (!bufs) 190887ad72a5SChristoph Hellwig goto out_free_descs; 190987ad72a5SChristoph Hellwig 1910244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 191187ad72a5SChristoph Hellwig dma_addr_t dma_addr; 191287ad72a5SChristoph Hellwig 191350cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 191487ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 191587ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 191687ad72a5SChristoph Hellwig if (!bufs[i]) 191787ad72a5SChristoph Hellwig break; 191887ad72a5SChristoph Hellwig 191987ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 192087ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 192187ad72a5SChristoph Hellwig i++; 192287ad72a5SChristoph Hellwig } 192387ad72a5SChristoph Hellwig 192492dc6895SChristoph Hellwig if (!size) 192587ad72a5SChristoph Hellwig goto out_free_bufs; 192687ad72a5SChristoph Hellwig 192787ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 192887ad72a5SChristoph Hellwig dev->host_mem_size = size; 192987ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19304033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 193187ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 193287ad72a5SChristoph Hellwig return 0; 193387ad72a5SChristoph Hellwig 193487ad72a5SChristoph Hellwig out_free_bufs: 193587ad72a5SChristoph Hellwig while (--i >= 0) { 193687ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 193787ad72a5SChristoph Hellwig 193887ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 193987ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 194087ad72a5SChristoph Hellwig } 194187ad72a5SChristoph Hellwig 194287ad72a5SChristoph Hellwig kfree(bufs); 194387ad72a5SChristoph Hellwig out_free_descs: 19444033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19454033f35dSChristoph Hellwig descs_dma); 194687ad72a5SChristoph Hellwig out: 194787ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 194887ad72a5SChristoph Hellwig return -ENOMEM; 194987ad72a5SChristoph Hellwig } 195087ad72a5SChristoph Hellwig 195192dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 195292dc6895SChristoph Hellwig { 195392dc6895SChristoph Hellwig u32 chunk_size; 195492dc6895SChristoph Hellwig 195592dc6895SChristoph Hellwig /* start big and work our way down */ 195630f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1957044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 195892dc6895SChristoph Hellwig chunk_size /= 2) { 195992dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 196092dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 196192dc6895SChristoph Hellwig return 0; 196292dc6895SChristoph Hellwig nvme_free_host_mem(dev); 196392dc6895SChristoph Hellwig } 196492dc6895SChristoph Hellwig } 196592dc6895SChristoph Hellwig 196692dc6895SChristoph Hellwig return -ENOMEM; 196792dc6895SChristoph Hellwig } 196892dc6895SChristoph Hellwig 19699620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 197087ad72a5SChristoph Hellwig { 197187ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 197287ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 197387ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 197487ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19756fbcde66SMinwoo Im int ret; 197687ad72a5SChristoph Hellwig 197787ad72a5SChristoph Hellwig preferred = min(preferred, max); 197887ad72a5SChristoph Hellwig if (min > max) { 197987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 198087ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 198187ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 198287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19839620cfbaSChristoph Hellwig return 0; 198487ad72a5SChristoph Hellwig } 198587ad72a5SChristoph Hellwig 198687ad72a5SChristoph Hellwig /* 198787ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 198887ad72a5SChristoph Hellwig */ 198987ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 199087ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 199187ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 199287ad72a5SChristoph Hellwig else 199387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 199487ad72a5SChristoph Hellwig } 199587ad72a5SChristoph Hellwig 199687ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 199792dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 199892dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 199992dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20009620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 200187ad72a5SChristoph Hellwig } 200287ad72a5SChristoph Hellwig 200392dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 200492dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 200592dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 200692dc6895SChristoph Hellwig } 200792dc6895SChristoph Hellwig 20089620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20099620cfbaSChristoph Hellwig if (ret) 201087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20119620cfbaSChristoph Hellwig return ret; 201257dacad5SJay Sternberg } 201357dacad5SJay Sternberg 20143b6592f7SJens Axboe static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int nr_io_queues) 20153b6592f7SJens Axboe { 20163b6592f7SJens Axboe unsigned int this_w_queues = write_queues; 20174b04cc6aSJens Axboe unsigned int this_p_queues = poll_queues; 20183b6592f7SJens Axboe 20193b6592f7SJens Axboe /* 20203b6592f7SJens Axboe * Setup read/write queue split 20213b6592f7SJens Axboe */ 20223b6592f7SJens Axboe if (nr_io_queues == 1) { 20233b6592f7SJens Axboe dev->io_queues[NVMEQ_TYPE_READ] = 1; 20243b6592f7SJens Axboe dev->io_queues[NVMEQ_TYPE_WRITE] = 0; 20254b04cc6aSJens Axboe dev->io_queues[NVMEQ_TYPE_POLL] = 0; 20263b6592f7SJens Axboe return; 20273b6592f7SJens Axboe } 20283b6592f7SJens Axboe 20293b6592f7SJens Axboe /* 20304b04cc6aSJens Axboe * Configure number of poll queues, if set 20314b04cc6aSJens Axboe */ 20324b04cc6aSJens Axboe if (this_p_queues) { 20334b04cc6aSJens Axboe /* 20344b04cc6aSJens Axboe * We need at least one queue left. With just one queue, we'll 20354b04cc6aSJens Axboe * have a single shared read/write set. 20364b04cc6aSJens Axboe */ 20374b04cc6aSJens Axboe if (this_p_queues >= nr_io_queues) { 20384b04cc6aSJens Axboe this_w_queues = 0; 20394b04cc6aSJens Axboe this_p_queues = nr_io_queues - 1; 20404b04cc6aSJens Axboe } 20414b04cc6aSJens Axboe 20424b04cc6aSJens Axboe dev->io_queues[NVMEQ_TYPE_POLL] = this_p_queues; 20434b04cc6aSJens Axboe nr_io_queues -= this_p_queues; 20444b04cc6aSJens Axboe } else 20454b04cc6aSJens Axboe dev->io_queues[NVMEQ_TYPE_POLL] = 0; 20464b04cc6aSJens Axboe 20474b04cc6aSJens Axboe /* 20483b6592f7SJens Axboe * If 'write_queues' is set, ensure it leaves room for at least 20493b6592f7SJens Axboe * one read queue 20503b6592f7SJens Axboe */ 20513b6592f7SJens Axboe if (this_w_queues >= nr_io_queues) 20523b6592f7SJens Axboe this_w_queues = nr_io_queues - 1; 20533b6592f7SJens Axboe 20543b6592f7SJens Axboe /* 20553b6592f7SJens Axboe * If 'write_queues' is set to zero, reads and writes will share 20563b6592f7SJens Axboe * a queue set. 20573b6592f7SJens Axboe */ 20583b6592f7SJens Axboe if (!this_w_queues) { 20593b6592f7SJens Axboe dev->io_queues[NVMEQ_TYPE_WRITE] = 0; 20603b6592f7SJens Axboe dev->io_queues[NVMEQ_TYPE_READ] = nr_io_queues; 20613b6592f7SJens Axboe } else { 20623b6592f7SJens Axboe dev->io_queues[NVMEQ_TYPE_WRITE] = this_w_queues; 20633b6592f7SJens Axboe dev->io_queues[NVMEQ_TYPE_READ] = nr_io_queues - this_w_queues; 20643b6592f7SJens Axboe } 20653b6592f7SJens Axboe } 20663b6592f7SJens Axboe 20673b6592f7SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, int nr_io_queues) 20683b6592f7SJens Axboe { 20693b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20703b6592f7SJens Axboe int irq_sets[2]; 20713b6592f7SJens Axboe struct irq_affinity affd = { 20723b6592f7SJens Axboe .pre_vectors = 1, 20733b6592f7SJens Axboe .nr_sets = ARRAY_SIZE(irq_sets), 20743b6592f7SJens Axboe .sets = irq_sets, 20753b6592f7SJens Axboe }; 20763b6592f7SJens Axboe int result; 20773b6592f7SJens Axboe 20783b6592f7SJens Axboe /* 20793b6592f7SJens Axboe * For irq sets, we have to ask for minvec == maxvec. This passes 20803b6592f7SJens Axboe * any reduction back to us, so we can adjust our queue counts and 20813b6592f7SJens Axboe * IRQ vector needs. 20823b6592f7SJens Axboe */ 20833b6592f7SJens Axboe do { 20843b6592f7SJens Axboe nvme_calc_io_queues(dev, nr_io_queues); 20853b6592f7SJens Axboe irq_sets[0] = dev->io_queues[NVMEQ_TYPE_READ]; 20863b6592f7SJens Axboe irq_sets[1] = dev->io_queues[NVMEQ_TYPE_WRITE]; 20873b6592f7SJens Axboe if (!irq_sets[1]) 20883b6592f7SJens Axboe affd.nr_sets = 1; 20893b6592f7SJens Axboe 20903b6592f7SJens Axboe /* 20913b6592f7SJens Axboe * Need IRQs for read+write queues, and one for the admin queue 20923b6592f7SJens Axboe */ 20933b6592f7SJens Axboe nr_io_queues = irq_sets[0] + irq_sets[1] + 1; 20943b6592f7SJens Axboe 20953b6592f7SJens Axboe result = pci_alloc_irq_vectors_affinity(pdev, nr_io_queues, 20963b6592f7SJens Axboe nr_io_queues, 20973b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20983b6592f7SJens Axboe 20993b6592f7SJens Axboe /* 21003b6592f7SJens Axboe * Need to reduce our vec counts 21013b6592f7SJens Axboe */ 21023b6592f7SJens Axboe if (result == -ENOSPC) { 21033b6592f7SJens Axboe nr_io_queues--; 21043b6592f7SJens Axboe if (!nr_io_queues) 21053b6592f7SJens Axboe return result; 21063b6592f7SJens Axboe continue; 21073b6592f7SJens Axboe } else if (result <= 0) 21083b6592f7SJens Axboe return -EIO; 21093b6592f7SJens Axboe break; 21103b6592f7SJens Axboe } while (1); 21113b6592f7SJens Axboe 21123b6592f7SJens Axboe return result; 21133b6592f7SJens Axboe } 21143b6592f7SJens Axboe 211557dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 211657dacad5SJay Sternberg { 2117147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 211857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 211997f6ef64SXu Yu int result, nr_io_queues; 212097f6ef64SXu Yu unsigned long size; 212157dacad5SJay Sternberg 21223b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21239a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21249a0be7abSChristoph Hellwig if (result < 0) 212557dacad5SJay Sternberg return result; 21269a0be7abSChristoph Hellwig 2127f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2128a5229050SKeith Busch return 0; 212957dacad5SJay Sternberg 21300f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 213157dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 213257dacad5SJay Sternberg sizeof(struct nvme_command)); 213357dacad5SJay Sternberg if (result > 0) 213457dacad5SJay Sternberg dev->q_depth = result; 213557dacad5SJay Sternberg else 21360f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 213757dacad5SJay Sternberg } 213857dacad5SJay Sternberg 213957dacad5SJay Sternberg do { 214097f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 214197f6ef64SXu Yu result = nvme_remap_bar(dev, size); 214297f6ef64SXu Yu if (!result) 214357dacad5SJay Sternberg break; 214457dacad5SJay Sternberg if (!--nr_io_queues) 214557dacad5SJay Sternberg return -ENOMEM; 214657dacad5SJay Sternberg } while (1); 214757dacad5SJay Sternberg adminq->q_db = dev->dbs; 214857dacad5SJay Sternberg 214957dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21500ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 215157dacad5SJay Sternberg 215257dacad5SJay Sternberg /* 215357dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 215457dacad5SJay Sternberg * setting up the full range we need. 215557dacad5SJay Sternberg */ 2156dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21573b6592f7SJens Axboe 21583b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 215922b55601SKeith Busch if (result <= 0) 2160dca51e78SChristoph Hellwig return -EIO; 21613b6592f7SJens Axboe 216222b55601SKeith Busch dev->num_vecs = result; 21634b04cc6aSJens Axboe result = max(result - 1, 1); 21644b04cc6aSJens Axboe dev->max_qid = result + dev->io_queues[NVMEQ_TYPE_POLL]; 216557dacad5SJay Sternberg 21664b04cc6aSJens Axboe dev_info(dev->ctrl.device, "%d/%d/%d read/write/poll queues\n", 21673b6592f7SJens Axboe dev->io_queues[NVMEQ_TYPE_READ], 21684b04cc6aSJens Axboe dev->io_queues[NVMEQ_TYPE_WRITE], 21694b04cc6aSJens Axboe dev->io_queues[NVMEQ_TYPE_POLL]); 21703b6592f7SJens Axboe 217157dacad5SJay Sternberg /* 217257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 217357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 217457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 217557dacad5SJay Sternberg * number of interrupts. 217657dacad5SJay Sternberg */ 217757dacad5SJay Sternberg 2178dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 217957dacad5SJay Sternberg if (result) { 218057dacad5SJay Sternberg adminq->cq_vector = -1; 2181d4875622SKeith Busch return result; 218257dacad5SJay Sternberg } 2183749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 218457dacad5SJay Sternberg } 218557dacad5SJay Sternberg 21862a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2187db3cbfffSKeith Busch { 2188db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2189db3cbfffSKeith Busch 2190db3cbfffSKeith Busch blk_mq_free_request(req); 2191db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 2192db3cbfffSKeith Busch } 2193db3cbfffSKeith Busch 21942a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2195db3cbfffSKeith Busch { 2196db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 21975cb525c8SJens Axboe u16 start, end; 2198db3cbfffSKeith Busch 2199db3cbfffSKeith Busch if (!error) { 2200db3cbfffSKeith Busch unsigned long flags; 2201db3cbfffSKeith Busch 22020bc88192SKeith Busch spin_lock_irqsave(&nvmeq->cq_lock, flags); 22035cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 22041ab0cd69SJens Axboe spin_unlock_irqrestore(&nvmeq->cq_lock, flags); 22055cb525c8SJens Axboe 22065cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 2207db3cbfffSKeith Busch } 2208db3cbfffSKeith Busch 2209db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2210db3cbfffSKeith Busch } 2211db3cbfffSKeith Busch 2212db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2213db3cbfffSKeith Busch { 2214db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2215db3cbfffSKeith Busch struct request *req; 2216db3cbfffSKeith Busch struct nvme_command cmd; 2217db3cbfffSKeith Busch 2218db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2219db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2220db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2221db3cbfffSKeith Busch 2222eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2223db3cbfffSKeith Busch if (IS_ERR(req)) 2224db3cbfffSKeith Busch return PTR_ERR(req); 2225db3cbfffSKeith Busch 2226db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2227db3cbfffSKeith Busch req->end_io_data = nvmeq; 2228db3cbfffSKeith Busch 2229db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2230db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2231db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2232db3cbfffSKeith Busch return 0; 2233db3cbfffSKeith Busch } 2234db3cbfffSKeith Busch 2235ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 2236db3cbfffSKeith Busch { 2237ee9aebb2SKeith Busch int pass, queues = dev->online_queues - 1; 2238db3cbfffSKeith Busch unsigned long timeout; 2239db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2240db3cbfffSKeith Busch 2241db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2242014a0d60SKeith Busch int sent = 0, i = queues; 2243db3cbfffSKeith Busch 2244db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2245db3cbfffSKeith Busch retry: 2246db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2247c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2248147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2249db3cbfffSKeith Busch break; 2250c21377f8SGabriel Krisman Bertazi 2251db3cbfffSKeith Busch while (sent--) { 2252db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2253db3cbfffSKeith Busch if (timeout == 0) 2254db3cbfffSKeith Busch return; 2255db3cbfffSKeith Busch if (i) 2256db3cbfffSKeith Busch goto retry; 2257db3cbfffSKeith Busch } 2258db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2259db3cbfffSKeith Busch } 2260db3cbfffSKeith Busch } 2261db3cbfffSKeith Busch 226257dacad5SJay Sternberg /* 22632b1b7e78SJianchao Wang * return error value only when tagset allocation failed 226457dacad5SJay Sternberg */ 226557dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 226657dacad5SJay Sternberg { 22672b1b7e78SJianchao Wang int ret; 22682b1b7e78SJianchao Wang 22695bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 227057dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 227157dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 22723b6592f7SJens Axboe dev->tagset.nr_maps = NVMEQ_TYPE_NR; 227357dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 227457dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 227557dacad5SJay Sternberg dev->tagset.queue_depth = 227657dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2277a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2278a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2279a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2280a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2281a7a7cbe3SChaitanya Kulkarni } 228257dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 228357dacad5SJay Sternberg dev->tagset.driver_data = dev; 228457dacad5SJay Sternberg 22852b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22862b1b7e78SJianchao Wang if (ret) { 22872b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22882b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22892b1b7e78SJianchao Wang return ret; 22902b1b7e78SJianchao Wang } 22915bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2292f9f38e33SHelen Koike 2293f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2294949928c1SKeith Busch } else { 2295949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2296949928c1SKeith Busch 2297949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2298949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 229957dacad5SJay Sternberg } 2300949928c1SKeith Busch 230157dacad5SJay Sternberg return 0; 230257dacad5SJay Sternberg } 230357dacad5SJay Sternberg 2304b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 230557dacad5SJay Sternberg { 2306b00a726aSKeith Busch int result = -ENOMEM; 230757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 230857dacad5SJay Sternberg 230957dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 231057dacad5SJay Sternberg return result; 231157dacad5SJay Sternberg 231257dacad5SJay Sternberg pci_set_master(pdev); 231357dacad5SJay Sternberg 231457dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 231557dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 231657dacad5SJay Sternberg goto disable; 231757dacad5SJay Sternberg 23187a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 231957dacad5SJay Sternberg result = -ENODEV; 2320b00a726aSKeith Busch goto disable; 232157dacad5SJay Sternberg } 232257dacad5SJay Sternberg 232357dacad5SJay Sternberg /* 2324a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2325a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2326a5229050SKeith Busch * adjust this later. 232757dacad5SJay Sternberg */ 2328dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2329dca51e78SChristoph Hellwig if (result < 0) 2330dca51e78SChristoph Hellwig return result; 233157dacad5SJay Sternberg 233220d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23337a67cbeaSChristoph Hellwig 233420d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2335b27c1e68Sweiping zhang io_queue_depth); 233620d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23377a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23381f390c1fSStephan Günther 23391f390c1fSStephan Günther /* 23401f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23411f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23421f390c1fSStephan Günther */ 23431f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23441f390c1fSStephan Günther dev->q_depth = 2; 23459bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23469bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23471f390c1fSStephan Günther dev->q_depth); 2348d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2349d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 235020d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2351d554b5e1SMartin K. Petersen dev->q_depth = 64; 2352d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2353d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23541f390c1fSStephan Günther } 23551f390c1fSStephan Günther 2356f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2357202021c1SStephen Bates 2358a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2359a0a3408eSKeith Busch pci_save_state(pdev); 236057dacad5SJay Sternberg return 0; 236157dacad5SJay Sternberg 236257dacad5SJay Sternberg disable: 236357dacad5SJay Sternberg pci_disable_device(pdev); 236457dacad5SJay Sternberg return result; 236557dacad5SJay Sternberg } 236657dacad5SJay Sternberg 236757dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 236857dacad5SJay Sternberg { 2369b00a726aSKeith Busch if (dev->bar) 2370b00a726aSKeith Busch iounmap(dev->bar); 2371a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2372b00a726aSKeith Busch } 2373b00a726aSKeith Busch 2374b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2375b00a726aSKeith Busch { 237657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 237757dacad5SJay Sternberg 2378dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 237957dacad5SJay Sternberg 2380a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2381a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 238257dacad5SJay Sternberg pci_disable_device(pdev); 238357dacad5SJay Sternberg } 2384a0a3408eSKeith Busch } 238557dacad5SJay Sternberg 2386a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 238757dacad5SJay Sternberg { 2388ee9aebb2SKeith Busch int i; 2389302ad8ccSKeith Busch bool dead = true; 2390302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 239157dacad5SJay Sternberg 239277bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2393302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2394302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2395302ad8ccSKeith Busch 2396ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2397ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2398302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2399302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2400302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 240157dacad5SJay Sternberg } 2402c21377f8SGabriel Krisman Bertazi 2403302ad8ccSKeith Busch /* 2404302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2405302ad8ccSKeith Busch * doing a safe shutdown. 2406302ad8ccSKeith Busch */ 240787ad72a5SChristoph Hellwig if (!dead) { 240887ad72a5SChristoph Hellwig if (shutdown) 2409302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 24109a915a5bSJianchao Wang } 241187ad72a5SChristoph Hellwig 24129a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24139a915a5bSJianchao Wang 241464ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 2415ee9aebb2SKeith Busch nvme_disable_io_queues(dev); 2416a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 241757dacad5SJay Sternberg } 2418ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2419ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2420ee9aebb2SKeith Busch 2421b00a726aSKeith Busch nvme_pci_disable(dev); 242257dacad5SJay Sternberg 2423e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2424e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2425302ad8ccSKeith Busch 2426302ad8ccSKeith Busch /* 2427302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2428302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2429302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2430302ad8ccSKeith Busch */ 2431302ad8ccSKeith Busch if (shutdown) 2432302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 243377bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 243457dacad5SJay Sternberg } 243557dacad5SJay Sternberg 243657dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 243757dacad5SJay Sternberg { 243857dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 243957dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 244057dacad5SJay Sternberg if (!dev->prp_page_pool) 244157dacad5SJay Sternberg return -ENOMEM; 244257dacad5SJay Sternberg 244357dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 244457dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 244557dacad5SJay Sternberg 256, 256, 0); 244657dacad5SJay Sternberg if (!dev->prp_small_pool) { 244757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 244857dacad5SJay Sternberg return -ENOMEM; 244957dacad5SJay Sternberg } 245057dacad5SJay Sternberg return 0; 245157dacad5SJay Sternberg } 245257dacad5SJay Sternberg 245357dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 245457dacad5SJay Sternberg { 245557dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 245657dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 245757dacad5SJay Sternberg } 245857dacad5SJay Sternberg 24591673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 246057dacad5SJay Sternberg { 24611673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 246257dacad5SJay Sternberg 2463f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 246457dacad5SJay Sternberg put_device(dev->dev); 246557dacad5SJay Sternberg if (dev->tagset.tags) 246657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24671c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24681c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 246957dacad5SJay Sternberg kfree(dev->queues); 2470e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2471943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 247257dacad5SJay Sternberg kfree(dev); 247357dacad5SJay Sternberg } 247457dacad5SJay Sternberg 2475f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2476f58944e2SKeith Busch { 2477237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2478f58944e2SKeith Busch 2479d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 248069d9a99cSKeith Busch nvme_dev_disable(dev, false); 24819f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 248203e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2483f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2484f58944e2SKeith Busch } 2485f58944e2SKeith Busch 2486fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 248757dacad5SJay Sternberg { 2488d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2489d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2490a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2491f58944e2SKeith Busch int result = -ENODEV; 24922b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 249357dacad5SJay Sternberg 249482b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2495fd634f41SChristoph Hellwig goto out; 2496fd634f41SChristoph Hellwig 2497fd634f41SChristoph Hellwig /* 2498fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2499fd634f41SChristoph Hellwig * moving on. 2500fd634f41SChristoph Hellwig */ 2501b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2502a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2503fd634f41SChristoph Hellwig 2504ad70062cSJianchao Wang /* 2505ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2506ad70062cSJianchao Wang * initializing procedure here. 2507ad70062cSJianchao Wang */ 2508ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2509ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2510ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2511ad70062cSJianchao Wang goto out; 2512ad70062cSJianchao Wang } 2513ad70062cSJianchao Wang 2514b00a726aSKeith Busch result = nvme_pci_enable(dev); 251557dacad5SJay Sternberg if (result) 251657dacad5SJay Sternberg goto out; 251757dacad5SJay Sternberg 251801ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 251957dacad5SJay Sternberg if (result) 2520f58944e2SKeith Busch goto out; 252157dacad5SJay Sternberg 252257dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 252357dacad5SJay Sternberg if (result) 2524f58944e2SKeith Busch goto out; 252557dacad5SJay Sternberg 2526943e942eSJens Axboe /* 2527943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2528943e942eSJens Axboe * over a single page. 2529943e942eSJens Axboe */ 2530943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2531943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2532943e942eSJens Axboe 2533ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2534ce4541f4SChristoph Hellwig if (result) 2535f58944e2SKeith Busch goto out; 2536ce4541f4SChristoph Hellwig 2537e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2538e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25394f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25404f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2541e286bcfcSScott Bauer else if (was_suspend) 25424f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2543e286bcfcSScott Bauer } else { 2544e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2545e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2546e286bcfcSScott Bauer } 2547a98e58e5SScott Bauer 2548f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2549f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2550f9f38e33SHelen Koike if (result) 2551f9f38e33SHelen Koike dev_warn(dev->dev, 2552f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2553f9f38e33SHelen Koike } 2554f9f38e33SHelen Koike 25559620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25569620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25579620cfbaSChristoph Hellwig if (result < 0) 25589620cfbaSChristoph Hellwig goto out; 25599620cfbaSChristoph Hellwig } 256087ad72a5SChristoph Hellwig 256157dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 256257dacad5SJay Sternberg if (result) 2563f58944e2SKeith Busch goto out; 256457dacad5SJay Sternberg 256521f033f7SKeith Busch /* 256657dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 256757dacad5SJay Sternberg * any working I/O queue. 256857dacad5SJay Sternberg */ 256957dacad5SJay Sternberg if (dev->online_queues < 2) { 25701b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25713b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25725bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 25732b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 257457dacad5SJay Sternberg } else { 257525646264SKeith Busch nvme_start_queues(&dev->ctrl); 2576302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 25772b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 25782b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 25792b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2580302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 258157dacad5SJay Sternberg } 258257dacad5SJay Sternberg 25832b1b7e78SJianchao Wang /* 25842b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 25852b1b7e78SJianchao Wang * recovery. 25862b1b7e78SJianchao Wang */ 25872b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 25882b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25892b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2590bb8d261eSChristoph Hellwig goto out; 2591bb8d261eSChristoph Hellwig } 259292911a55SChristoph Hellwig 2593d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 259457dacad5SJay Sternberg return; 259557dacad5SJay Sternberg 259657dacad5SJay Sternberg out: 2597f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 259857dacad5SJay Sternberg } 259957dacad5SJay Sternberg 26005c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 260157dacad5SJay Sternberg { 26025c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 260357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 260457dacad5SJay Sternberg 260557dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2606921920abSKeith Busch device_release_driver(&pdev->dev); 26071673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 260857dacad5SJay Sternberg } 260957dacad5SJay Sternberg 26101c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 261157dacad5SJay Sternberg { 26121c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26131c63dc66SChristoph Hellwig return 0; 261457dacad5SJay Sternberg } 26151c63dc66SChristoph Hellwig 26165fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26175fd4ce1bSChristoph Hellwig { 26185fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26195fd4ce1bSChristoph Hellwig return 0; 26205fd4ce1bSChristoph Hellwig } 26215fd4ce1bSChristoph Hellwig 26227fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26237fd8930fSChristoph Hellwig { 26247fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26257fd8930fSChristoph Hellwig return 0; 26267fd8930fSChristoph Hellwig } 26277fd8930fSChristoph Hellwig 262897c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 262997c12223SKeith Busch { 263097c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 263197c12223SKeith Busch 263297c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 263397c12223SKeith Busch } 263497c12223SKeith Busch 26351c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26361a353d85SMing Lin .name = "pcie", 2637e439bb12SSagi Grimberg .module = THIS_MODULE, 2638e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2639e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26401c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26415fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26427fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26431673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2644f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 264597c12223SKeith Busch .get_address = nvme_pci_get_address, 26461c63dc66SChristoph Hellwig }; 264757dacad5SJay Sternberg 2648b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2649b00a726aSKeith Busch { 2650b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2651b00a726aSKeith Busch 2652a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2653b00a726aSKeith Busch return -ENODEV; 2654b00a726aSKeith Busch 265597f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2656b00a726aSKeith Busch goto release; 2657b00a726aSKeith Busch 2658b00a726aSKeith Busch return 0; 2659b00a726aSKeith Busch release: 2660a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2661b00a726aSKeith Busch return -ENODEV; 2662b00a726aSKeith Busch } 2663b00a726aSKeith Busch 26648427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2665ff5350a8SAndy Lutomirski { 2666ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2667ff5350a8SAndy Lutomirski /* 2668ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2669ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2670ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2671ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2672ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2673ff5350a8SAndy Lutomirski * laptops. 2674ff5350a8SAndy Lutomirski */ 2675ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2676ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2677ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2678ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 26798427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 26808427bbc2SKai-Heng Feng /* 26818427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2682467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2683467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2684467c77d4SJarosław Janik * ASUS PRIME Z370-A 26858427bbc2SKai-Heng Feng */ 26868427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2687467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2688467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 26898427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2690ff5350a8SAndy Lutomirski } 2691ff5350a8SAndy Lutomirski 2692ff5350a8SAndy Lutomirski return 0; 2693ff5350a8SAndy Lutomirski } 2694ff5350a8SAndy Lutomirski 269518119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 269618119775SKeith Busch { 269718119775SKeith Busch struct nvme_dev *dev = data; 269880f513b5SKeith Busch 269918119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 270018119775SKeith Busch flush_work(&dev->ctrl.scan_work); 270180f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 270218119775SKeith Busch } 270318119775SKeith Busch 270457dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 270557dacad5SJay Sternberg { 270657dacad5SJay Sternberg int node, result = -ENOMEM; 270757dacad5SJay Sternberg struct nvme_dev *dev; 2708ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2709943e942eSJens Axboe size_t alloc_size; 271057dacad5SJay Sternberg 271157dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 271257dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27132fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 271457dacad5SJay Sternberg 271557dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 271657dacad5SJay Sternberg if (!dev) 271757dacad5SJay Sternberg return -ENOMEM; 2718147b27e4SSagi Grimberg 27193b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27203b6592f7SJens Axboe GFP_KERNEL, node); 272157dacad5SJay Sternberg if (!dev->queues) 272257dacad5SJay Sternberg goto free; 272357dacad5SJay Sternberg 272457dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 272557dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 272657dacad5SJay Sternberg 2727b00a726aSKeith Busch result = nvme_dev_map(dev); 2728b00a726aSKeith Busch if (result) 2729b00c9b7aSChristophe JAILLET goto put_pci; 2730b00a726aSKeith Busch 2731d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27325c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 273377bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2734db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2735f3ca80fcSChristoph Hellwig 2736f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2737f3ca80fcSChristoph Hellwig if (result) 2738b00c9b7aSChristophe JAILLET goto unmap; 2739f3ca80fcSChristoph Hellwig 27408427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2741ff5350a8SAndy Lutomirski 2742943e942eSJens Axboe /* 2743943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2744943e942eSJens Axboe * command we support. 2745943e942eSJens Axboe */ 2746943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2747943e942eSJens Axboe NVME_MAX_SEGS, true); 2748943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2749943e942eSJens Axboe 2750943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2751943e942eSJens Axboe mempool_kfree, 2752943e942eSJens Axboe (void *) alloc_size, 2753943e942eSJens Axboe GFP_KERNEL, node); 2754943e942eSJens Axboe if (!dev->iod_mempool) { 2755943e942eSJens Axboe result = -ENOMEM; 2756943e942eSJens Axboe goto release_pools; 2757943e942eSJens Axboe } 2758943e942eSJens Axboe 2759b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2760b6e44b4cSKeith Busch quirks); 2761b6e44b4cSKeith Busch if (result) 2762b6e44b4cSKeith Busch goto release_mempool; 2763b6e44b4cSKeith Busch 27641b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27651b3c47c1SSagi Grimberg 276680f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 276718119775SKeith Busch async_schedule(nvme_async_probe, dev); 27684caff8fcSSagi Grimberg 276957dacad5SJay Sternberg return 0; 277057dacad5SJay Sternberg 2771b6e44b4cSKeith Busch release_mempool: 2772b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 277357dacad5SJay Sternberg release_pools: 277457dacad5SJay Sternberg nvme_release_prp_pools(dev); 2775b00c9b7aSChristophe JAILLET unmap: 2776b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 277757dacad5SJay Sternberg put_pci: 277857dacad5SJay Sternberg put_device(dev->dev); 277957dacad5SJay Sternberg free: 278057dacad5SJay Sternberg kfree(dev->queues); 278157dacad5SJay Sternberg kfree(dev); 278257dacad5SJay Sternberg return result; 278357dacad5SJay Sternberg } 278457dacad5SJay Sternberg 2785775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 278657dacad5SJay Sternberg { 278757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2788a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2789775755edSChristoph Hellwig } 279057dacad5SJay Sternberg 2791775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2792775755edSChristoph Hellwig { 2793f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 279479c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 279557dacad5SJay Sternberg } 279657dacad5SJay Sternberg 279757dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 279857dacad5SJay Sternberg { 279957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2800a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 280157dacad5SJay Sternberg } 280257dacad5SJay Sternberg 2803f58944e2SKeith Busch /* 2804f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2805f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2806f58944e2SKeith Busch * order to proceed. 2807f58944e2SKeith Busch */ 280857dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 280957dacad5SJay Sternberg { 281057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 281157dacad5SJay Sternberg 2812bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 281357dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28140ff9d4e1SKeith Busch 28156db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28160ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28171d39e692SKeith Busch nvme_dev_disable(dev, true); 2818cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28196db28edaSKeith Busch } 28200ff9d4e1SKeith Busch 2821d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2822d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2823d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2824a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28259fe5c59fSKeith Busch nvme_release_cmb(dev); 282687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 282757dacad5SJay Sternberg nvme_dev_remove_admin(dev); 282857dacad5SJay Sternberg nvme_free_queues(dev, 0); 2829d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 283057dacad5SJay Sternberg nvme_release_prp_pools(dev); 2831b00a726aSKeith Busch nvme_dev_unmap(dev); 28321673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 283357dacad5SJay Sternberg } 283457dacad5SJay Sternberg 283557dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 283657dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 283757dacad5SJay Sternberg { 283857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 283957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 284057dacad5SJay Sternberg 2841a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 284257dacad5SJay Sternberg return 0; 284357dacad5SJay Sternberg } 284457dacad5SJay Sternberg 284557dacad5SJay Sternberg static int nvme_resume(struct device *dev) 284657dacad5SJay Sternberg { 284757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 284857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 284957dacad5SJay Sternberg 2850d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 285157dacad5SJay Sternberg return 0; 285257dacad5SJay Sternberg } 285357dacad5SJay Sternberg #endif 285457dacad5SJay Sternberg 285557dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 285657dacad5SJay Sternberg 2857a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2858a0a3408eSKeith Busch pci_channel_state_t state) 2859a0a3408eSKeith Busch { 2860a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2861a0a3408eSKeith Busch 2862a0a3408eSKeith Busch /* 2863a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2864a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2865a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2866a0a3408eSKeith Busch */ 2867a0a3408eSKeith Busch switch (state) { 2868a0a3408eSKeith Busch case pci_channel_io_normal: 2869a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2870a0a3408eSKeith Busch case pci_channel_io_frozen: 2871d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2872d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2873a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2874a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2875a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2876d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2877d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2878a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2879a0a3408eSKeith Busch } 2880a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2881a0a3408eSKeith Busch } 2882a0a3408eSKeith Busch 2883a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2884a0a3408eSKeith Busch { 2885a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2886a0a3408eSKeith Busch 28871b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2888a0a3408eSKeith Busch pci_restore_state(pdev); 2889d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2890a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2891a0a3408eSKeith Busch } 2892a0a3408eSKeith Busch 2893a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2894a0a3408eSKeith Busch { 289572cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 289672cd4cc2SKeith Busch 289772cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2898a0a3408eSKeith Busch } 2899a0a3408eSKeith Busch 290057dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 290157dacad5SJay Sternberg .error_detected = nvme_error_detected, 290257dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 290357dacad5SJay Sternberg .resume = nvme_error_resume, 2904775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2905775755edSChristoph Hellwig .reset_done = nvme_reset_done, 290657dacad5SJay Sternberg }; 290757dacad5SJay Sternberg 290857dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2909106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 291008095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2911e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 291299466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 291399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2914e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 291599466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 291699466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2917e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2918f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2919f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2920f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 292150af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 29229abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 29239abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 2924540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2925540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 29260302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 29270302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 292854adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 292954adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 29308c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 29318c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2932015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2933015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2934d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2935d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2936d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2937d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2938608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2939608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2940608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2941608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2942ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2943ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 294457dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2945c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2946124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 294757dacad5SJay Sternberg { 0, } 294857dacad5SJay Sternberg }; 294957dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 295057dacad5SJay Sternberg 295157dacad5SJay Sternberg static struct pci_driver nvme_driver = { 295257dacad5SJay Sternberg .name = "nvme", 295357dacad5SJay Sternberg .id_table = nvme_id_table, 295457dacad5SJay Sternberg .probe = nvme_probe, 295557dacad5SJay Sternberg .remove = nvme_remove, 295657dacad5SJay Sternberg .shutdown = nvme_shutdown, 295757dacad5SJay Sternberg .driver = { 295857dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 295957dacad5SJay Sternberg }, 296074d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 296157dacad5SJay Sternberg .err_handler = &nvme_err_handler, 296257dacad5SJay Sternberg }; 296357dacad5SJay Sternberg 296457dacad5SJay Sternberg static int __init nvme_init(void) 296557dacad5SJay Sternberg { 29669a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 296757dacad5SJay Sternberg } 296857dacad5SJay Sternberg 296957dacad5SJay Sternberg static void __exit nvme_exit(void) 297057dacad5SJay Sternberg { 297157dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 297203e0f3a6SMing Lei flush_workqueue(nvme_wq); 297357dacad5SJay Sternberg _nvme_check_size(); 297457dacad5SJay Sternberg } 297557dacad5SJay Sternberg 297657dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 297757dacad5SJay Sternberg MODULE_LICENSE("GPL"); 297857dacad5SJay Sternberg MODULE_VERSION("1.0"); 297957dacad5SJay Sternberg module_init(nvme_init); 298057dacad5SJay Sternberg module_exit(nvme_exit); 2981