157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 330f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3457dacad5SJay Sternberg 3557dacad5SJay Sternberg #include "nvme.h" 3657dacad5SJay Sternberg 3757dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3857dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3957dacad5SJay Sternberg 40a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 41adf68f21SChristoph Hellwig 42943e942eSJens Axboe /* 43943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 44943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 45943e942eSJens Axboe */ 46943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 47943e942eSJens Axboe #define NVME_MAX_SEGS 127 48943e942eSJens Axboe 4957dacad5SJay Sternberg static int use_threaded_interrupts; 5057dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 5157dacad5SJay Sternberg 5257dacad5SJay Sternberg static bool use_cmb_sqes = true; 5369f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5457dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5557dacad5SJay Sternberg 5687ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5787ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5887ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5987ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 6057dacad5SJay Sternberg 61a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 62a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 63a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 64a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 65a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 66a7a7cbe3SChaitanya Kulkarni 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 70b27c1e68Sweiping zhang .get = param_get_int, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 73b27c1e68Sweiping zhang static int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 75b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 76b27c1e68Sweiping zhang 773b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 783b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 793b6592f7SJens Axboe .set = queue_count_set, 803b6592f7SJens Axboe .get = param_get_int, 813b6592f7SJens Axboe }; 823b6592f7SJens Axboe 833b6592f7SJens Axboe static int write_queues; 843b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 853b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 863b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 873b6592f7SJens Axboe "will share a queue set."); 883b6592f7SJens Axboe 89a4668d9bSJens Axboe static int poll_queues = 0; 904b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 914b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 924b04cc6aSJens Axboe 931c63dc66SChristoph Hellwig struct nvme_dev; 941c63dc66SChristoph Hellwig struct nvme_queue; 9557dacad5SJay Sternberg 96a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 9757dacad5SJay Sternberg 9857dacad5SJay Sternberg /* 991c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1001c63dc66SChristoph Hellwig */ 1011c63dc66SChristoph Hellwig struct nvme_dev { 102147b27e4SSagi Grimberg struct nvme_queue *queues; 1031c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1041c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1051c63dc66SChristoph Hellwig u32 __iomem *dbs; 1061c63dc66SChristoph Hellwig struct device *dev; 1071c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1081c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1091c63dc66SChristoph Hellwig unsigned online_queues; 1101c63dc66SChristoph Hellwig unsigned max_qid; 111e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 11222b55601SKeith Busch unsigned int num_vecs; 1131c63dc66SChristoph Hellwig int q_depth; 1141c63dc66SChristoph Hellwig u32 db_stride; 1151c63dc66SChristoph Hellwig void __iomem *bar; 11697f6ef64SXu Yu unsigned long bar_mapped_size; 1175c8809e6SChristoph Hellwig struct work_struct remove_work; 11877bf25eaSKeith Busch struct mutex shutdown_lock; 1191c63dc66SChristoph Hellwig bool subsystem; 1201c63dc66SChristoph Hellwig u64 cmb_size; 1210f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1221c63dc66SChristoph Hellwig u32 cmbsz; 123202021c1SStephen Bates u32 cmbloc; 1241c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 12587ad72a5SChristoph Hellwig 126943e942eSJens Axboe mempool_t *iod_mempool; 127943e942eSJens Axboe 12887ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 129f9f38e33SHelen Koike u32 *dbbuf_dbs; 130f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 131f9f38e33SHelen Koike u32 *dbbuf_eis; 132f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 13387ad72a5SChristoph Hellwig 13487ad72a5SChristoph Hellwig /* host memory buffer support: */ 13587ad72a5SChristoph Hellwig u64 host_mem_size; 13687ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1374033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 13887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13987ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 14057dacad5SJay Sternberg }; 14157dacad5SJay Sternberg 142b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 143b27c1e68Sweiping zhang { 144b27c1e68Sweiping zhang int n = 0, ret; 145b27c1e68Sweiping zhang 146b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 147b27c1e68Sweiping zhang if (ret != 0 || n < 2) 148b27c1e68Sweiping zhang return -EINVAL; 149b27c1e68Sweiping zhang 150b27c1e68Sweiping zhang return param_set_int(val, kp); 151b27c1e68Sweiping zhang } 152b27c1e68Sweiping zhang 1533b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1543b6592f7SJens Axboe { 1553b6592f7SJens Axboe int n = 0, ret; 1563b6592f7SJens Axboe 1573b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 1583b6592f7SJens Axboe if (n > num_possible_cpus()) 1593b6592f7SJens Axboe n = num_possible_cpus(); 1603b6592f7SJens Axboe 1613b6592f7SJens Axboe return param_set_int(val, kp); 1623b6592f7SJens Axboe } 1633b6592f7SJens Axboe 164f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 165f9f38e33SHelen Koike { 166f9f38e33SHelen Koike return qid * 2 * stride; 167f9f38e33SHelen Koike } 168f9f38e33SHelen Koike 169f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 170f9f38e33SHelen Koike { 171f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 172f9f38e33SHelen Koike } 173f9f38e33SHelen Koike 1741c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1751c63dc66SChristoph Hellwig { 1761c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1771c63dc66SChristoph Hellwig } 1781c63dc66SChristoph Hellwig 17957dacad5SJay Sternberg /* 18057dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18157dacad5SJay Sternberg * commands and one for I/O commands). 18257dacad5SJay Sternberg */ 18357dacad5SJay Sternberg struct nvme_queue { 18457dacad5SJay Sternberg struct device *q_dmadev; 18557dacad5SJay Sternberg struct nvme_dev *dev; 1861ab0cd69SJens Axboe spinlock_t sq_lock; 18757dacad5SJay Sternberg struct nvme_command *sq_cmds; 1883a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1893a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19057dacad5SJay Sternberg volatile struct nvme_completion *cqes; 19157dacad5SJay Sternberg struct blk_mq_tags **tags; 19257dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19357dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19457dacad5SJay Sternberg u32 __iomem *q_db; 19557dacad5SJay Sternberg u16 q_depth; 19657dacad5SJay Sternberg s16 cq_vector; 19757dacad5SJay Sternberg u16 sq_tail; 19804f3eafdSJens Axboe u16 last_sq_tail; 19957dacad5SJay Sternberg u16 cq_head; 20068fa9dbeSJens Axboe u16 last_cq_head; 20157dacad5SJay Sternberg u16 qid; 20257dacad5SJay Sternberg u8 cq_phase; 2034e224106SChristoph Hellwig unsigned long flags; 2044e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20563223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 206d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 207f9f38e33SHelen Koike u32 *dbbuf_sq_db; 208f9f38e33SHelen Koike u32 *dbbuf_cq_db; 209f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 210f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 211d1ed6aa1SChristoph Hellwig struct completion delete_done; 21257dacad5SJay Sternberg }; 21357dacad5SJay Sternberg 21457dacad5SJay Sternberg /* 21571bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 21671bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 217f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 21871bd150cSChristoph Hellwig * allocated to store the PRP list. 21971bd150cSChristoph Hellwig */ 22071bd150cSChristoph Hellwig struct nvme_iod { 221d49187e9SChristoph Hellwig struct nvme_request req; 222f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 223a7a7cbe3SChaitanya Kulkarni bool use_sgl; 224f4800d6dSChristoph Hellwig int aborted; 22571bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22671bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22771bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 22871bd150cSChristoph Hellwig dma_addr_t first_dma; 229bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 230f4800d6dSChristoph Hellwig struct scatterlist *sg; 231f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 23257dacad5SJay Sternberg }; 23357dacad5SJay Sternberg 23457dacad5SJay Sternberg /* 23557dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 23657dacad5SJay Sternberg */ 23757dacad5SJay Sternberg static inline void _nvme_check_size(void) 23857dacad5SJay Sternberg { 23957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 24057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 24157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 24257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 24357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 24457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 24557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 24657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2470add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2480add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 24957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 25057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 251f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 252f9f38e33SHelen Koike } 253f9f38e33SHelen Koike 2543b6592f7SJens Axboe static unsigned int max_io_queues(void) 2553b6592f7SJens Axboe { 2564b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2573b6592f7SJens Axboe } 2583b6592f7SJens Axboe 2593b6592f7SJens Axboe static unsigned int max_queue_count(void) 2603b6592f7SJens Axboe { 2613b6592f7SJens Axboe /* IO queues + admin queue */ 2623b6592f7SJens Axboe return 1 + max_io_queues(); 2633b6592f7SJens Axboe } 2643b6592f7SJens Axboe 265f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 266f9f38e33SHelen Koike { 2673b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 268f9f38e33SHelen Koike } 269f9f38e33SHelen Koike 270f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 271f9f38e33SHelen Koike { 272f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 273f9f38e33SHelen Koike 274f9f38e33SHelen Koike if (dev->dbbuf_dbs) 275f9f38e33SHelen Koike return 0; 276f9f38e33SHelen Koike 277f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 278f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 279f9f38e33SHelen Koike GFP_KERNEL); 280f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 281f9f38e33SHelen Koike return -ENOMEM; 282f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 283f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 284f9f38e33SHelen Koike GFP_KERNEL); 285f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 286f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 287f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 288f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 289f9f38e33SHelen Koike return -ENOMEM; 290f9f38e33SHelen Koike } 291f9f38e33SHelen Koike 292f9f38e33SHelen Koike return 0; 293f9f38e33SHelen Koike } 294f9f38e33SHelen Koike 295f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 296f9f38e33SHelen Koike { 297f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 298f9f38e33SHelen Koike 299f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 300f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 301f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 302f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike if (dev->dbbuf_eis) { 305f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 306f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 307f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 308f9f38e33SHelen Koike } 309f9f38e33SHelen Koike } 310f9f38e33SHelen Koike 311f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 312f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 313f9f38e33SHelen Koike { 314f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 315f9f38e33SHelen Koike return; 316f9f38e33SHelen Koike 317f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 318f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 319f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 320f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 321f9f38e33SHelen Koike } 322f9f38e33SHelen Koike 323f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 324f9f38e33SHelen Koike { 325f9f38e33SHelen Koike struct nvme_command c; 326f9f38e33SHelen Koike 327f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 328f9f38e33SHelen Koike return; 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 331f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 332f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 333f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 334f9f38e33SHelen Koike 335f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3369bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 337f9f38e33SHelen Koike /* Free memory and continue on */ 338f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 339f9f38e33SHelen Koike } 340f9f38e33SHelen Koike } 341f9f38e33SHelen Koike 342f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 343f9f38e33SHelen Koike { 344f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 345f9f38e33SHelen Koike } 346f9f38e33SHelen Koike 347f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 348f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 349f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 350f9f38e33SHelen Koike { 351f9f38e33SHelen Koike if (dbbuf_db) { 352f9f38e33SHelen Koike u16 old_value; 353f9f38e33SHelen Koike 354f9f38e33SHelen Koike /* 355f9f38e33SHelen Koike * Ensure that the queue is written before updating 356f9f38e33SHelen Koike * the doorbell in memory 357f9f38e33SHelen Koike */ 358f9f38e33SHelen Koike wmb(); 359f9f38e33SHelen Koike 360f9f38e33SHelen Koike old_value = *dbbuf_db; 361f9f38e33SHelen Koike *dbbuf_db = value; 362f9f38e33SHelen Koike 363f1ed3df2SMichal Wnukowski /* 364f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 365f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 366f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 367f1ed3df2SMichal Wnukowski * the doorbell. 368f1ed3df2SMichal Wnukowski */ 369f1ed3df2SMichal Wnukowski mb(); 370f1ed3df2SMichal Wnukowski 371f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 372f9f38e33SHelen Koike return false; 373f9f38e33SHelen Koike } 374f9f38e33SHelen Koike 375f9f38e33SHelen Koike return true; 37657dacad5SJay Sternberg } 37757dacad5SJay Sternberg 37857dacad5SJay Sternberg /* 37957dacad5SJay Sternberg * Max size of iod being embedded in the request payload 38057dacad5SJay Sternberg */ 38157dacad5SJay Sternberg #define NVME_INT_PAGES 2 3825fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 38357dacad5SJay Sternberg 38457dacad5SJay Sternberg /* 38557dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 38657dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 38757dacad5SJay Sternberg * the I/O. 38857dacad5SJay Sternberg */ 38957dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 39057dacad5SJay Sternberg { 3915fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3925fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 39357dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 39457dacad5SJay Sternberg } 39557dacad5SJay Sternberg 396a7a7cbe3SChaitanya Kulkarni /* 397a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 398a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 399a7a7cbe3SChaitanya Kulkarni */ 400a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 401f4800d6dSChristoph Hellwig { 402a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 403f4800d6dSChristoph Hellwig } 404f4800d6dSChristoph Hellwig 405a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 406a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 40757dacad5SJay Sternberg { 408a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 409a7a7cbe3SChaitanya Kulkarni 410a7a7cbe3SChaitanya Kulkarni if (use_sgl) 411a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 412a7a7cbe3SChaitanya Kulkarni else 413a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 414a7a7cbe3SChaitanya Kulkarni 415a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 416a7a7cbe3SChaitanya Kulkarni } 417a7a7cbe3SChaitanya Kulkarni 418a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 419a7a7cbe3SChaitanya Kulkarni { 420a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 421a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 422a7a7cbe3SChaitanya Kulkarni use_sgl); 423a7a7cbe3SChaitanya Kulkarni 424a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 42557dacad5SJay Sternberg } 42657dacad5SJay Sternberg 42757dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 42857dacad5SJay Sternberg unsigned int hctx_idx) 42957dacad5SJay Sternberg { 43057dacad5SJay Sternberg struct nvme_dev *dev = data; 431147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 43257dacad5SJay Sternberg 43357dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 43457dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 43557dacad5SJay Sternberg WARN_ON(nvmeq->tags); 43657dacad5SJay Sternberg 43757dacad5SJay Sternberg hctx->driver_data = nvmeq; 43857dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 43957dacad5SJay Sternberg return 0; 44057dacad5SJay Sternberg } 44157dacad5SJay Sternberg 44257dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 44357dacad5SJay Sternberg { 44457dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 44557dacad5SJay Sternberg 44657dacad5SJay Sternberg nvmeq->tags = NULL; 44757dacad5SJay Sternberg } 44857dacad5SJay Sternberg 44957dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 45057dacad5SJay Sternberg unsigned int hctx_idx) 45157dacad5SJay Sternberg { 45257dacad5SJay Sternberg struct nvme_dev *dev = data; 453147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 45457dacad5SJay Sternberg 45557dacad5SJay Sternberg if (!nvmeq->tags) 45657dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 45757dacad5SJay Sternberg 45857dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 45957dacad5SJay Sternberg hctx->driver_data = nvmeq; 46057dacad5SJay Sternberg return 0; 46157dacad5SJay Sternberg } 46257dacad5SJay Sternberg 463d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 464d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 46557dacad5SJay Sternberg { 466d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 467f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4680350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 469147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 47057dacad5SJay Sternberg 47157dacad5SJay Sternberg BUG_ON(!nvmeq); 472f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 47359e29ce6SSagi Grimberg 47459e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 47557dacad5SJay Sternberg return 0; 47657dacad5SJay Sternberg } 47757dacad5SJay Sternberg 4783b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4793b6592f7SJens Axboe { 4803b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4813b6592f7SJens Axboe if (dev->num_vecs > 1) 4823b6592f7SJens Axboe return 1; 4833b6592f7SJens Axboe 4843b6592f7SJens Axboe return 0; 4853b6592f7SJens Axboe } 4863b6592f7SJens Axboe 487dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 488dca51e78SChristoph Hellwig { 489dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4903b6592f7SJens Axboe int i, qoff, offset; 491dca51e78SChristoph Hellwig 4923b6592f7SJens Axboe offset = queue_irq_offset(dev); 4933b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4943b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4953b6592f7SJens Axboe 4963b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4973b6592f7SJens Axboe if (!map->nr_queues) { 498e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4993b6592f7SJens Axboe 5003b6592f7SJens Axboe /* shared set, resuse read set parameters */ 501e20ba6e1SChristoph Hellwig map->nr_queues = dev->io_queues[HCTX_TYPE_DEFAULT]; 5023b6592f7SJens Axboe qoff = 0; 5033b6592f7SJens Axboe offset = queue_irq_offset(dev); 5043b6592f7SJens Axboe } 5053b6592f7SJens Axboe 5064b04cc6aSJens Axboe /* 5074b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 5084b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 5094b04cc6aSJens Axboe */ 5103b6592f7SJens Axboe map->queue_offset = qoff; 511e20ba6e1SChristoph Hellwig if (i != HCTX_TYPE_POLL) 5123b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 5134b04cc6aSJens Axboe else 5144b04cc6aSJens Axboe blk_mq_map_queues(map); 5153b6592f7SJens Axboe qoff += map->nr_queues; 5163b6592f7SJens Axboe offset += map->nr_queues; 5173b6592f7SJens Axboe } 5183b6592f7SJens Axboe 5193b6592f7SJens Axboe return 0; 520dca51e78SChristoph Hellwig } 521dca51e78SChristoph Hellwig 52204f3eafdSJens Axboe /* 52304f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 52404f3eafdSJens Axboe */ 52504f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 52604f3eafdSJens Axboe { 52704f3eafdSJens Axboe if (!write_sq) { 52804f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 52904f3eafdSJens Axboe 53004f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 53104f3eafdSJens Axboe next_tail = 0; 53204f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 53304f3eafdSJens Axboe return; 53404f3eafdSJens Axboe } 53504f3eafdSJens Axboe 53604f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 53704f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 53804f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 53904f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 54004f3eafdSJens Axboe } 54104f3eafdSJens Axboe 54257dacad5SJay Sternberg /** 54390ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 54457dacad5SJay Sternberg * @nvmeq: The queue to use 54557dacad5SJay Sternberg * @cmd: The command to send 54604f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 54757dacad5SJay Sternberg */ 54804f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 54904f3eafdSJens Axboe bool write_sq) 55057dacad5SJay Sternberg { 55190ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 55290ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 55390ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 55490ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 55504f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 55604f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 55704f3eafdSJens Axboe } 55804f3eafdSJens Axboe 55904f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 56004f3eafdSJens Axboe { 56104f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 56204f3eafdSJens Axboe 56304f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 56404f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 56504f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 56690ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 56757dacad5SJay Sternberg } 56857dacad5SJay Sternberg 569a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 57057dacad5SJay Sternberg { 571f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 572a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 57357dacad5SJay Sternberg } 57457dacad5SJay Sternberg 575955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 576955b1b5aSMinwoo Im { 577955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 57820469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 579955b1b5aSMinwoo Im unsigned int avg_seg_size; 580955b1b5aSMinwoo Im 58120469a37SKeith Busch if (nseg == 0) 58220469a37SKeith Busch return false; 58320469a37SKeith Busch 58420469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 585955b1b5aSMinwoo Im 586955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 587955b1b5aSMinwoo Im return false; 588955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 589955b1b5aSMinwoo Im return false; 590955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 591955b1b5aSMinwoo Im return false; 592955b1b5aSMinwoo Im return true; 593955b1b5aSMinwoo Im } 594955b1b5aSMinwoo Im 595fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 59657dacad5SJay Sternberg { 597f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 598f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 599b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 600f4800d6dSChristoph Hellwig 601955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 602955b1b5aSMinwoo Im 603f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 604943e942eSJens Axboe iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 605f4800d6dSChristoph Hellwig if (!iod->sg) 606fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 607f4800d6dSChristoph Hellwig } else { 608f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 60957dacad5SJay Sternberg } 61057dacad5SJay Sternberg 611f4800d6dSChristoph Hellwig iod->aborted = 0; 61257dacad5SJay Sternberg iod->npages = -1; 61357dacad5SJay Sternberg iod->nents = 0; 614f4800d6dSChristoph Hellwig iod->length = size; 615f80ec966SKeith Busch 616fc17b653SChristoph Hellwig return BLK_STS_OK; 61757dacad5SJay Sternberg } 61857dacad5SJay Sternberg 619f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 62057dacad5SJay Sternberg { 621f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 622a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 623a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 624a7a7cbe3SChaitanya Kulkarni 62557dacad5SJay Sternberg int i; 62657dacad5SJay Sternberg 62757dacad5SJay Sternberg if (iod->npages == 0) 628a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 629a7a7cbe3SChaitanya Kulkarni dma_addr); 630a7a7cbe3SChaitanya Kulkarni 63157dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 632a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 633a7a7cbe3SChaitanya Kulkarni 634a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 635a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 636a7a7cbe3SChaitanya Kulkarni 637a7a7cbe3SChaitanya Kulkarni next_dma_addr = 638a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 639a7a7cbe3SChaitanya Kulkarni } else { 640a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 641a7a7cbe3SChaitanya Kulkarni 642a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 643a7a7cbe3SChaitanya Kulkarni } 644a7a7cbe3SChaitanya Kulkarni 645a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 646a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 64757dacad5SJay Sternberg } 64857dacad5SJay Sternberg 649f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 650943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 65157dacad5SJay Sternberg } 65257dacad5SJay Sternberg 653d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 654d0877473SKeith Busch { 655d0877473SKeith Busch int i; 656d0877473SKeith Busch struct scatterlist *sg; 657d0877473SKeith Busch 658d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 659d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 660d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 661d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 662d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 663d0877473SKeith Busch sg_dma_len(sg)); 664d0877473SKeith Busch } 665d0877473SKeith Busch } 666d0877473SKeith Busch 667a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 668a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 66957dacad5SJay Sternberg { 670f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 67157dacad5SJay Sternberg struct dma_pool *pool; 672b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 67357dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 67457dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 67557dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6765fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 67757dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 67857dacad5SJay Sternberg __le64 *prp_list; 679a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 68057dacad5SJay Sternberg dma_addr_t prp_dma; 68157dacad5SJay Sternberg int nprps, i; 68257dacad5SJay Sternberg 68357dacad5SJay Sternberg length -= (page_size - offset); 6845228b328SJan H. Schönherr if (length <= 0) { 6855228b328SJan H. Schönherr iod->first_dma = 0; 686a7a7cbe3SChaitanya Kulkarni goto done; 6875228b328SJan H. Schönherr } 68857dacad5SJay Sternberg 68957dacad5SJay Sternberg dma_len -= (page_size - offset); 69057dacad5SJay Sternberg if (dma_len) { 69157dacad5SJay Sternberg dma_addr += (page_size - offset); 69257dacad5SJay Sternberg } else { 69357dacad5SJay Sternberg sg = sg_next(sg); 69457dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69557dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69657dacad5SJay Sternberg } 69757dacad5SJay Sternberg 69857dacad5SJay Sternberg if (length <= page_size) { 69957dacad5SJay Sternberg iod->first_dma = dma_addr; 700a7a7cbe3SChaitanya Kulkarni goto done; 70157dacad5SJay Sternberg } 70257dacad5SJay Sternberg 70357dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 70457dacad5SJay Sternberg if (nprps <= (256 / 8)) { 70557dacad5SJay Sternberg pool = dev->prp_small_pool; 70657dacad5SJay Sternberg iod->npages = 0; 70757dacad5SJay Sternberg } else { 70857dacad5SJay Sternberg pool = dev->prp_page_pool; 70957dacad5SJay Sternberg iod->npages = 1; 71057dacad5SJay Sternberg } 71157dacad5SJay Sternberg 71269d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 71357dacad5SJay Sternberg if (!prp_list) { 71457dacad5SJay Sternberg iod->first_dma = dma_addr; 71557dacad5SJay Sternberg iod->npages = -1; 71686eea289SKeith Busch return BLK_STS_RESOURCE; 71757dacad5SJay Sternberg } 71857dacad5SJay Sternberg list[0] = prp_list; 71957dacad5SJay Sternberg iod->first_dma = prp_dma; 72057dacad5SJay Sternberg i = 0; 72157dacad5SJay Sternberg for (;;) { 72257dacad5SJay Sternberg if (i == page_size >> 3) { 72357dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 72469d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 72557dacad5SJay Sternberg if (!prp_list) 72686eea289SKeith Busch return BLK_STS_RESOURCE; 72757dacad5SJay Sternberg list[iod->npages++] = prp_list; 72857dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 72957dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 73057dacad5SJay Sternberg i = 1; 73157dacad5SJay Sternberg } 73257dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 73357dacad5SJay Sternberg dma_len -= page_size; 73457dacad5SJay Sternberg dma_addr += page_size; 73557dacad5SJay Sternberg length -= page_size; 73657dacad5SJay Sternberg if (length <= 0) 73757dacad5SJay Sternberg break; 73857dacad5SJay Sternberg if (dma_len > 0) 73957dacad5SJay Sternberg continue; 74086eea289SKeith Busch if (unlikely(dma_len < 0)) 74186eea289SKeith Busch goto bad_sgl; 74257dacad5SJay Sternberg sg = sg_next(sg); 74357dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 74457dacad5SJay Sternberg dma_len = sg_dma_len(sg); 74557dacad5SJay Sternberg } 74657dacad5SJay Sternberg 747a7a7cbe3SChaitanya Kulkarni done: 748a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 749a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 750a7a7cbe3SChaitanya Kulkarni 75186eea289SKeith Busch return BLK_STS_OK; 75286eea289SKeith Busch 75386eea289SKeith Busch bad_sgl: 754d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 755d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 756d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 75786eea289SKeith Busch return BLK_STS_IOERR; 75857dacad5SJay Sternberg } 75957dacad5SJay Sternberg 760a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 761a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 762a7a7cbe3SChaitanya Kulkarni { 763a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 764a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 765a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 766a7a7cbe3SChaitanya Kulkarni } 767a7a7cbe3SChaitanya Kulkarni 768a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 769a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 770a7a7cbe3SChaitanya Kulkarni { 771a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 772a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 773a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 774a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 775a7a7cbe3SChaitanya Kulkarni } else { 776a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 777a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 778a7a7cbe3SChaitanya Kulkarni } 779a7a7cbe3SChaitanya Kulkarni } 780a7a7cbe3SChaitanya Kulkarni 781a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 782b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 783a7a7cbe3SChaitanya Kulkarni { 784a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 785a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 786a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 787a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 788a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 789b0f2853bSChristoph Hellwig int i = 0; 790a7a7cbe3SChaitanya Kulkarni 791a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 792a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 793a7a7cbe3SChaitanya Kulkarni 794b0f2853bSChristoph Hellwig if (entries == 1) { 795a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 796a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 797a7a7cbe3SChaitanya Kulkarni } 798a7a7cbe3SChaitanya Kulkarni 799a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 800a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 801a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 802a7a7cbe3SChaitanya Kulkarni } else { 803a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 804a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 805a7a7cbe3SChaitanya Kulkarni } 806a7a7cbe3SChaitanya Kulkarni 807a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 808a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 809a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 810a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 811a7a7cbe3SChaitanya Kulkarni } 812a7a7cbe3SChaitanya Kulkarni 813a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 814a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 815a7a7cbe3SChaitanya Kulkarni 816a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 817a7a7cbe3SChaitanya Kulkarni 818a7a7cbe3SChaitanya Kulkarni do { 819a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 820a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 821a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 822a7a7cbe3SChaitanya Kulkarni 823a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 824a7a7cbe3SChaitanya Kulkarni if (!sg_list) 825a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 826a7a7cbe3SChaitanya Kulkarni 827a7a7cbe3SChaitanya Kulkarni i = 0; 828a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 829a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 830a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 831a7a7cbe3SChaitanya Kulkarni } 832a7a7cbe3SChaitanya Kulkarni 833a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 834a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 835b0f2853bSChristoph Hellwig } while (--entries > 0); 836a7a7cbe3SChaitanya Kulkarni 837a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 838a7a7cbe3SChaitanya Kulkarni } 839a7a7cbe3SChaitanya Kulkarni 840fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 841b131c61dSChristoph Hellwig struct nvme_command *cmnd) 84257dacad5SJay Sternberg { 843f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 844ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 845ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 846ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 847fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 848b0f2853bSChristoph Hellwig int nr_mapped; 84957dacad5SJay Sternberg 850f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 851ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 852ba1ca37eSChristoph Hellwig if (!iod->nents) 853ba1ca37eSChristoph Hellwig goto out; 854ba1ca37eSChristoph Hellwig 855fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 856e0596ab2SLogan Gunthorpe 857e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 858e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 859e0596ab2SLogan Gunthorpe dma_dir); 860e0596ab2SLogan Gunthorpe else 861e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 862e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 863b0f2853bSChristoph Hellwig if (!nr_mapped) 864ba1ca37eSChristoph Hellwig goto out; 865ba1ca37eSChristoph Hellwig 866955b1b5aSMinwoo Im if (iod->use_sgl) 867b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 868a7a7cbe3SChaitanya Kulkarni else 869a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 870a7a7cbe3SChaitanya Kulkarni 87186eea289SKeith Busch if (ret != BLK_STS_OK) 872ba1ca37eSChristoph Hellwig goto out_unmap; 873ba1ca37eSChristoph Hellwig 874fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 875ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 876ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 877ba1ca37eSChristoph Hellwig goto out_unmap; 878ba1ca37eSChristoph Hellwig 879bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 880bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 881ba1ca37eSChristoph Hellwig goto out_unmap; 882ba1ca37eSChristoph Hellwig 883bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 884ba1ca37eSChristoph Hellwig goto out_unmap; 8853045c0d0SChaitanya Kulkarni 8863045c0d0SChaitanya Kulkarni cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 88757dacad5SJay Sternberg } 88857dacad5SJay Sternberg 889fc17b653SChristoph Hellwig return BLK_STS_OK; 890ba1ca37eSChristoph Hellwig 891ba1ca37eSChristoph Hellwig out_unmap: 892ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 893ba1ca37eSChristoph Hellwig out: 894ba1ca37eSChristoph Hellwig return ret; 89557dacad5SJay Sternberg } 89657dacad5SJay Sternberg 897f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 898d4f6c3abSChristoph Hellwig { 899f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 900d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 901d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 902d4f6c3abSChristoph Hellwig 903d4f6c3abSChristoph Hellwig if (iod->nents) { 904e0596ab2SLogan Gunthorpe /* P2PDMA requests do not need to be unmapped */ 905e0596ab2SLogan Gunthorpe if (!is_pci_p2pdma_page(sg_page(iod->sg))) 906d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 907e0596ab2SLogan Gunthorpe 908f7f1fc36SMax Gurtovoy if (blk_integrity_rq(req)) 909bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 910d4f6c3abSChristoph Hellwig } 911d4f6c3abSChristoph Hellwig 912f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 913f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 91457dacad5SJay Sternberg } 91557dacad5SJay Sternberg 91657dacad5SJay Sternberg /* 91757dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 91857dacad5SJay Sternberg */ 919fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 92057dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 92157dacad5SJay Sternberg { 92257dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 92357dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 92457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 92557dacad5SJay Sternberg struct request *req = bd->rq; 926ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 927ebe6d874SChristoph Hellwig blk_status_t ret; 92857dacad5SJay Sternberg 929d1f06f4aSJens Axboe /* 930d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 931d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 932d1f06f4aSJens Axboe */ 9334e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 934d1f06f4aSJens Axboe return BLK_STS_IOERR; 935d1f06f4aSJens Axboe 936f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 937fc17b653SChristoph Hellwig if (ret) 938f4800d6dSChristoph Hellwig return ret; 93957dacad5SJay Sternberg 940b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 941fc17b653SChristoph Hellwig if (ret) 942f9d03f96SChristoph Hellwig goto out_free_cmd; 94357dacad5SJay Sternberg 944fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 945b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 946fc17b653SChristoph Hellwig if (ret) 947f9d03f96SChristoph Hellwig goto out_cleanup_iod; 948fc17b653SChristoph Hellwig } 949ba1ca37eSChristoph Hellwig 950aae239e1SChristoph Hellwig blk_mq_start_request(req); 95104f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 952fc17b653SChristoph Hellwig return BLK_STS_OK; 953f9d03f96SChristoph Hellwig out_cleanup_iod: 954f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 955f9d03f96SChristoph Hellwig out_free_cmd: 956f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 957ba1ca37eSChristoph Hellwig return ret; 95857dacad5SJay Sternberg } 95957dacad5SJay Sternberg 96077f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 961eee417b0SChristoph Hellwig { 962f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 963eee417b0SChristoph Hellwig 96477f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 96577f02a7aSChristoph Hellwig nvme_complete_rq(req); 96657dacad5SJay Sternberg } 96757dacad5SJay Sternberg 968d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 969750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 970d783e0bdSMarta Rybczynska { 971750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 972750dde44SChristoph Hellwig nvmeq->cq_phase; 973d783e0bdSMarta Rybczynska } 974d783e0bdSMarta Rybczynska 975eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 97657dacad5SJay Sternberg { 977eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 97857dacad5SJay Sternberg 979eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 980eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 981eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 982eb281c82SSagi Grimberg } 983adf68f21SChristoph Hellwig 9845cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 98557dacad5SJay Sternberg { 9865cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 98757dacad5SJay Sternberg struct request *req; 988adf68f21SChristoph Hellwig 98983a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9901b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 991aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 99283a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 99383a12fb7SSagi Grimberg return; 994aae239e1SChristoph Hellwig } 995aae239e1SChristoph Hellwig 996adf68f21SChristoph Hellwig /* 997adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 998adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 999adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1000adf68f21SChristoph Hellwig * for them but rather special case them here. 1001adf68f21SChristoph Hellwig */ 1002adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 100338dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 10047bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 100583a12fb7SSagi Grimberg cqe->status, &cqe->result); 1006a0fa9647SJens Axboe return; 100757dacad5SJay Sternberg } 100857dacad5SJay Sternberg 100983a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 101083a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 101183a12fb7SSagi Grimberg } 101257dacad5SJay Sternberg 10135cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 101483a12fb7SSagi Grimberg { 10155cb525c8SJens Axboe while (start != end) { 10165cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 10175cb525c8SJens Axboe if (++start == nvmeq->q_depth) 10185cb525c8SJens Axboe start = 0; 10195cb525c8SJens Axboe } 10205cb525c8SJens Axboe } 102183a12fb7SSagi Grimberg 10225cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10235cb525c8SJens Axboe { 1024920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 1025920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1026920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1027920d13a8SSagi Grimberg } 1028a0fa9647SJens Axboe } 1029a0fa9647SJens Axboe 10301052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10311052b8acSJens Axboe u16 *end, unsigned int tag) 1032a0fa9647SJens Axboe { 10331052b8acSJens Axboe int found = 0; 103483a12fb7SSagi Grimberg 10355cb525c8SJens Axboe *start = nvmeq->cq_head; 10361052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10371052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10381052b8acSJens Axboe found++; 10395cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 104057dacad5SJay Sternberg } 10415cb525c8SJens Axboe *end = nvmeq->cq_head; 104257dacad5SJay Sternberg 10435cb525c8SJens Axboe if (*start != *end) 1044eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10455cb525c8SJens Axboe return found; 104657dacad5SJay Sternberg } 104757dacad5SJay Sternberg 104857dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 104957dacad5SJay Sternberg { 105057dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 105168fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10525cb525c8SJens Axboe u16 start, end; 10535cb525c8SJens Axboe 10543a7afd8eSChristoph Hellwig /* 10553a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10563a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10573a7afd8eSChristoph Hellwig */ 10583a7afd8eSChristoph Hellwig rmb(); 105968fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 106068fa9dbeSJens Axboe ret = IRQ_HANDLED; 10615cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 106268fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10633a7afd8eSChristoph Hellwig wmb(); 10645cb525c8SJens Axboe 106568fa9dbeSJens Axboe if (start != end) { 10665cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10675cb525c8SJens Axboe return IRQ_HANDLED; 106857dacad5SJay Sternberg } 106957dacad5SJay Sternberg 107068fa9dbeSJens Axboe return ret; 107157dacad5SJay Sternberg } 107257dacad5SJay Sternberg 107357dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 107457dacad5SJay Sternberg { 107557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1076750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 107757dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1078d783e0bdSMarta Rybczynska return IRQ_NONE; 107957dacad5SJay Sternberg } 108057dacad5SJay Sternberg 10810b2a8a9fSChristoph Hellwig /* 10820b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10830b2a8a9fSChristoph Hellwig * Can be called from any context. 10840b2a8a9fSChristoph Hellwig */ 10850b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1086a0fa9647SJens Axboe { 10873a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10885cb525c8SJens Axboe u16 start, end; 10891052b8acSJens Axboe int found; 1090a0fa9647SJens Axboe 10913a7afd8eSChristoph Hellwig /* 10923a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10933a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10943a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10953a7afd8eSChristoph Hellwig */ 10963a7afd8eSChristoph Hellwig if (nvmeq->cq_vector == -1) 10973a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 10983a7afd8eSChristoph Hellwig else 10993a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 11005cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 11013a7afd8eSChristoph Hellwig if (nvmeq->cq_vector == -1) 11023a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 11033a7afd8eSChristoph Hellwig else 11043a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1105442e19b7SSagi Grimberg 11065cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1107442e19b7SSagi Grimberg return found; 1108a0fa9647SJens Axboe } 1109a0fa9647SJens Axboe 11109743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 11117776db1cSKeith Busch { 11127776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1113dabcefabSJens Axboe u16 start, end; 1114dabcefabSJens Axboe bool found; 1115dabcefabSJens Axboe 1116dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1117dabcefabSJens Axboe return 0; 1118dabcefabSJens Axboe 11193a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 11209743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 11213a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1122dabcefabSJens Axboe 1123dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1124dabcefabSJens Axboe return found; 1125dabcefabSJens Axboe } 1126dabcefabSJens Axboe 1127ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 112857dacad5SJay Sternberg { 1129f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1130147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 113157dacad5SJay Sternberg struct nvme_command c; 113257dacad5SJay Sternberg 113357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 113457dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1135ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 113604f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 113757dacad5SJay Sternberg } 113857dacad5SJay Sternberg 113957dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 114057dacad5SJay Sternberg { 114157dacad5SJay Sternberg struct nvme_command c; 114257dacad5SJay Sternberg 114357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 114457dacad5SJay Sternberg c.delete_queue.opcode = opcode; 114557dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 114657dacad5SJay Sternberg 11471c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 114857dacad5SJay Sternberg } 114957dacad5SJay Sternberg 115057dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1151a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 115257dacad5SJay Sternberg { 115357dacad5SJay Sternberg struct nvme_command c; 11544b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11554b04cc6aSJens Axboe 11564b04cc6aSJens Axboe if (vector != -1) 11574b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 115857dacad5SJay Sternberg 115957dacad5SJay Sternberg /* 116016772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 116157dacad5SJay Sternberg * is attached to the request. 116257dacad5SJay Sternberg */ 116357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 116457dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 116557dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 116657dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 116757dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 116857dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 11694b04cc6aSJens Axboe if (vector != -1) 1170a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 11714b04cc6aSJens Axboe else 11724b04cc6aSJens Axboe c.create_cq.irq_vector = 0; 117357dacad5SJay Sternberg 11741c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 117557dacad5SJay Sternberg } 117657dacad5SJay Sternberg 117757dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 117857dacad5SJay Sternberg struct nvme_queue *nvmeq) 117957dacad5SJay Sternberg { 11809abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 118157dacad5SJay Sternberg struct nvme_command c; 118281c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 118357dacad5SJay Sternberg 118457dacad5SJay Sternberg /* 11859abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11869abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11879abd68efSJens Axboe * URGENT. 11889abd68efSJens Axboe */ 11899abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11909abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11919abd68efSJens Axboe 11929abd68efSJens Axboe /* 119316772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 119457dacad5SJay Sternberg * is attached to the request. 119557dacad5SJay Sternberg */ 119657dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 119757dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 119857dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 119957dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 120057dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 120157dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 120257dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 120357dacad5SJay Sternberg 12041c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120557dacad5SJay Sternberg } 120657dacad5SJay Sternberg 120757dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 120857dacad5SJay Sternberg { 120957dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 121057dacad5SJay Sternberg } 121157dacad5SJay Sternberg 121257dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 121357dacad5SJay Sternberg { 121457dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 121557dacad5SJay Sternberg } 121657dacad5SJay Sternberg 12172a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 121857dacad5SJay Sternberg { 1219f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1220f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 122157dacad5SJay Sternberg 122227fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 122327fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1224e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1225e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 122657dacad5SJay Sternberg } 122757dacad5SJay Sternberg 1228b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1229b2a0eb1aSKeith Busch { 1230b2a0eb1aSKeith Busch 1231b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1232b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1233b2a0eb1aSKeith Busch */ 1234b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1235b2a0eb1aSKeith Busch 1236ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1237ad70062cSJianchao Wang switch (dev->ctrl.state) { 1238ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1239ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1240b2a0eb1aSKeith Busch return false; 1241ad70062cSJianchao Wang default: 1242ad70062cSJianchao Wang break; 1243ad70062cSJianchao Wang } 1244b2a0eb1aSKeith Busch 1245b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1246b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1247b2a0eb1aSKeith Busch */ 1248b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1249b2a0eb1aSKeith Busch return false; 1250b2a0eb1aSKeith Busch 1251b2a0eb1aSKeith Busch return true; 1252b2a0eb1aSKeith Busch } 1253b2a0eb1aSKeith Busch 1254b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1255b2a0eb1aSKeith Busch { 1256b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1257b2a0eb1aSKeith Busch u16 pci_status; 1258b2a0eb1aSKeith Busch int result; 1259b2a0eb1aSKeith Busch 1260b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1261b2a0eb1aSKeith Busch &pci_status); 1262b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1263b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1264b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1265b2a0eb1aSKeith Busch csts, pci_status); 1266b2a0eb1aSKeith Busch else 1267b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1268b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1269b2a0eb1aSKeith Busch csts, result); 1270b2a0eb1aSKeith Busch } 1271b2a0eb1aSKeith Busch 127231c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 127357dacad5SJay Sternberg { 1274f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1275f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 127657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 127757dacad5SJay Sternberg struct request *abort_req; 127857dacad5SJay Sternberg struct nvme_command cmd; 1279b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1280b2a0eb1aSKeith Busch 1281651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1282651438bbSWen Xiong * the recovery mechanism will surely fail. 1283651438bbSWen Xiong */ 1284651438bbSWen Xiong mb(); 1285651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1286651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1287651438bbSWen Xiong 1288b2a0eb1aSKeith Busch /* 1289b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1290b2a0eb1aSKeith Busch */ 1291b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1292b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1293b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1294d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1295db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1296b2a0eb1aSKeith Busch } 129757dacad5SJay Sternberg 129831c7c7d2SChristoph Hellwig /* 12997776db1cSKeith Busch * Did we miss an interrupt? 13007776db1cSKeith Busch */ 13010b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 13027776db1cSKeith Busch dev_warn(dev->ctrl.device, 13037776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13047776db1cSKeith Busch req->tag, nvmeq->qid); 1305db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13067776db1cSKeith Busch } 13077776db1cSKeith Busch 13087776db1cSKeith Busch /* 1309fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1310fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1311fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1312db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1313fd634f41SChristoph Hellwig */ 13144244140dSKeith Busch switch (dev->ctrl.state) { 13154244140dSKeith Busch case NVME_CTRL_CONNECTING: 13164244140dSKeith Busch case NVME_CTRL_RESETTING: 1317b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1318fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1319fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1320a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 132127fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1322db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13234244140dSKeith Busch default: 13244244140dSKeith Busch break; 1325fd634f41SChristoph Hellwig } 1326fd634f41SChristoph Hellwig 1327fd634f41SChristoph Hellwig /* 1328e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1329e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1330e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 133131c7c7d2SChristoph Hellwig */ 1332f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13331b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 133457dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 133557dacad5SJay Sternberg req->tag, nvmeq->qid); 1336a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1337d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1338e1569a16SKeith Busch 133927fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1340db8c48e4SChristoph Hellwig return BLK_EH_DONE; 134157dacad5SJay Sternberg } 134257dacad5SJay Sternberg 1343e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1344e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1345e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1346e7a2a87dSChristoph Hellwig } 13477bf7d778SKeith Busch iod->aborted = 1; 134857dacad5SJay Sternberg 134957dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 135057dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 135157dacad5SJay Sternberg cmd.abort.cid = req->tag; 135257dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 135357dacad5SJay Sternberg 13541b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13551b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 135657dacad5SJay Sternberg req->tag, nvmeq->qid); 1357e7a2a87dSChristoph Hellwig 1358e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1359eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13606bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13616bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 136231c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 136357dacad5SJay Sternberg } 136457dacad5SJay Sternberg 1365e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1366e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1367e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 136857dacad5SJay Sternberg 136957dacad5SJay Sternberg /* 137057dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 137157dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 137257dacad5SJay Sternberg * as the device then is in a faulty state. 137357dacad5SJay Sternberg */ 137457dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 137557dacad5SJay Sternberg } 137657dacad5SJay Sternberg 137757dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 137857dacad5SJay Sternberg { 137957dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 138057dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 138163223078SChristoph Hellwig if (!nvmeq->sq_cmds) 138263223078SChristoph Hellwig return; 13830f238ff5SLogan Gunthorpe 138463223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 13850f238ff5SLogan Gunthorpe pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev), 138663223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 138763223078SChristoph Hellwig } else { 138863223078SChristoph Hellwig dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 138963223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13900f238ff5SLogan Gunthorpe } 139157dacad5SJay Sternberg } 139257dacad5SJay Sternberg 139357dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 139457dacad5SJay Sternberg { 139557dacad5SJay Sternberg int i; 139657dacad5SJay Sternberg 1397d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1398d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1399147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 140057dacad5SJay Sternberg } 140157dacad5SJay Sternberg } 140257dacad5SJay Sternberg 140357dacad5SJay Sternberg /** 140457dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 140540581d1aSBart Van Assche * @nvmeq: queue to suspend 140657dacad5SJay Sternberg */ 140757dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 140857dacad5SJay Sternberg { 14094e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 141057dacad5SJay Sternberg return 1; 141157dacad5SJay Sternberg 14124e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1413d1f06f4aSJens Axboe mb(); 141457dacad5SJay Sternberg 14154e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14161c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1417c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 14184e224106SChristoph Hellwig if (nvmeq->cq_vector == -1) 14194e224106SChristoph Hellwig return 0; 14204e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 14214e224106SChristoph Hellwig nvmeq->cq_vector = -1; 142257dacad5SJay Sternberg return 0; 142357dacad5SJay Sternberg } 142457dacad5SJay Sternberg 1425a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 142657dacad5SJay Sternberg { 1427147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 142857dacad5SJay Sternberg 1429a5cdb68cSKeith Busch if (shutdown) 1430a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1431a5cdb68cSKeith Busch else 143220d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 143357dacad5SJay Sternberg 14340b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 143557dacad5SJay Sternberg } 143657dacad5SJay Sternberg 143757dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 143857dacad5SJay Sternberg int entry_size) 143957dacad5SJay Sternberg { 144057dacad5SJay Sternberg int q_depth = dev->q_depth; 14415fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14425fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 144357dacad5SJay Sternberg 144457dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 144557dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14465fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 144757dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 144857dacad5SJay Sternberg 144957dacad5SJay Sternberg /* 145057dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 145157dacad5SJay Sternberg * would be better to map queues in system memory with the 145257dacad5SJay Sternberg * original depth 145357dacad5SJay Sternberg */ 145457dacad5SJay Sternberg if (q_depth < 64) 145557dacad5SJay Sternberg return -ENOMEM; 145657dacad5SJay Sternberg } 145757dacad5SJay Sternberg 145857dacad5SJay Sternberg return q_depth; 145957dacad5SJay Sternberg } 146057dacad5SJay Sternberg 146157dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 146257dacad5SJay Sternberg int qid, int depth) 146357dacad5SJay Sternberg { 14640f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1465815c6704SKeith Busch 14660f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14670f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14680f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14690f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 147063223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 147163223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 147263223078SChristoph Hellwig return 0; 147363223078SChristoph Hellwig } 14740f238ff5SLogan Gunthorpe } 14750f238ff5SLogan Gunthorpe 147657dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 147757dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 147857dacad5SJay Sternberg if (!nvmeq->sq_cmds) 147957dacad5SJay Sternberg return -ENOMEM; 148057dacad5SJay Sternberg return 0; 148157dacad5SJay Sternberg } 148257dacad5SJay Sternberg 1483a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 148457dacad5SJay Sternberg { 1485147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 148657dacad5SJay Sternberg 148762314e40SKeith Busch if (dev->ctrl.queue_count > qid) 148862314e40SKeith Busch return 0; 148957dacad5SJay Sternberg 149057dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 149157dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 149257dacad5SJay Sternberg if (!nvmeq->cqes) 149357dacad5SJay Sternberg goto free_nvmeq; 149457dacad5SJay Sternberg 149557dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 149657dacad5SJay Sternberg goto free_cqdma; 149757dacad5SJay Sternberg 149857dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 149957dacad5SJay Sternberg nvmeq->dev = dev; 15001ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15013a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 150257dacad5SJay Sternberg nvmeq->cq_head = 0; 150357dacad5SJay Sternberg nvmeq->cq_phase = 1; 150457dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 150557dacad5SJay Sternberg nvmeq->q_depth = depth; 150657dacad5SJay Sternberg nvmeq->qid = qid; 150757dacad5SJay Sternberg nvmeq->cq_vector = -1; 1508d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 150957dacad5SJay Sternberg 1510147b27e4SSagi Grimberg return 0; 151157dacad5SJay Sternberg 151257dacad5SJay Sternberg free_cqdma: 151357dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 151457dacad5SJay Sternberg nvmeq->cq_dma_addr); 151557dacad5SJay Sternberg free_nvmeq: 1516147b27e4SSagi Grimberg return -ENOMEM; 151757dacad5SJay Sternberg } 151857dacad5SJay Sternberg 1519dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 152057dacad5SJay Sternberg { 15210ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15220ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15230ff199cbSChristoph Hellwig 15240ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15250ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15260ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15270ff199cbSChristoph Hellwig } else { 15280ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15290ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15300ff199cbSChristoph Hellwig } 153157dacad5SJay Sternberg } 153257dacad5SJay Sternberg 153357dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 153457dacad5SJay Sternberg { 153557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 153657dacad5SJay Sternberg 153757dacad5SJay Sternberg nvmeq->sq_tail = 0; 153804f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 153957dacad5SJay Sternberg nvmeq->cq_head = 0; 154057dacad5SJay Sternberg nvmeq->cq_phase = 1; 154157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 154257dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1543f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 154457dacad5SJay Sternberg dev->online_queues++; 15453a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 154657dacad5SJay Sternberg } 154757dacad5SJay Sternberg 15484b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 154957dacad5SJay Sternberg { 155057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 155157dacad5SJay Sternberg int result; 1552a8e3e0bbSJianchao Wang s16 vector; 155357dacad5SJay Sternberg 1554d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1555d1ed6aa1SChristoph Hellwig 155622b55601SKeith Busch /* 155722b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 155822b55601SKeith Busch * has only one vector available. 155922b55601SKeith Busch */ 15604b04cc6aSJens Axboe if (!polled) 1561a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15624b04cc6aSJens Axboe else 15634b04cc6aSJens Axboe vector = -1; 15644b04cc6aSJens Axboe 1565a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1566ded45505SKeith Busch if (result) 1567ded45505SKeith Busch return result; 156857dacad5SJay Sternberg 156957dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 157057dacad5SJay Sternberg if (result < 0) 1571ded45505SKeith Busch return result; 1572ded45505SKeith Busch else if (result) 157357dacad5SJay Sternberg goto release_cq; 157457dacad5SJay Sternberg 1575a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1576161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15774b04cc6aSJens Axboe 15784b04cc6aSJens Axboe if (vector != -1) { 1579dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 158057dacad5SJay Sternberg if (result < 0) 158157dacad5SJay Sternberg goto release_sq; 15824b04cc6aSJens Axboe } 158357dacad5SJay Sternberg 15844e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 158557dacad5SJay Sternberg return result; 158657dacad5SJay Sternberg 158757dacad5SJay Sternberg release_sq: 1588a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 1589f25a2dfcSJianchao Wang dev->online_queues--; 159057dacad5SJay Sternberg adapter_delete_sq(dev, qid); 159157dacad5SJay Sternberg release_cq: 159257dacad5SJay Sternberg adapter_delete_cq(dev, qid); 159357dacad5SJay Sternberg return result; 159457dacad5SJay Sternberg } 159557dacad5SJay Sternberg 1596f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 159757dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 159877f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 159957dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 160057dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 16010350815aSChristoph Hellwig .init_request = nvme_init_request, 160257dacad5SJay Sternberg .timeout = nvme_timeout, 160357dacad5SJay Sternberg }; 160457dacad5SJay Sternberg 1605f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1606*376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1607*376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1608*376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1609*376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1610*376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1611*376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1612*376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1613c6d962aeSChristoph Hellwig .poll = nvme_poll, 1614dabcefabSJens Axboe }; 1615dabcefabSJens Axboe 161657dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 161757dacad5SJay Sternberg { 16181c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 161969d9a99cSKeith Busch /* 162069d9a99cSKeith Busch * If the controller was reset during removal, it's possible 162169d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 162269d9a99cSKeith Busch * queue to flush these to completion. 162369d9a99cSKeith Busch */ 1624c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16251c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 162657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 162757dacad5SJay Sternberg } 162857dacad5SJay Sternberg } 162957dacad5SJay Sternberg 163057dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 163157dacad5SJay Sternberg { 16321c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 163357dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 163457dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1635e3e9d50cSKeith Busch 163638dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 163757dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 163857dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1639a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1640d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 164157dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 164257dacad5SJay Sternberg 164357dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 164457dacad5SJay Sternberg return -ENOMEM; 164534b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 164657dacad5SJay Sternberg 16471c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16481c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 164957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 165057dacad5SJay Sternberg return -ENOMEM; 165157dacad5SJay Sternberg } 16521c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 165357dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16541c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 165557dacad5SJay Sternberg return -ENODEV; 165657dacad5SJay Sternberg } 165757dacad5SJay Sternberg } else 1658c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 165957dacad5SJay Sternberg 166057dacad5SJay Sternberg return 0; 166157dacad5SJay Sternberg } 166257dacad5SJay Sternberg 166397f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 166497f6ef64SXu Yu { 166597f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 166697f6ef64SXu Yu } 166797f6ef64SXu Yu 166897f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 166997f6ef64SXu Yu { 167097f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 167197f6ef64SXu Yu 167297f6ef64SXu Yu if (size <= dev->bar_mapped_size) 167397f6ef64SXu Yu return 0; 167497f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 167597f6ef64SXu Yu return -ENOMEM; 167697f6ef64SXu Yu if (dev->bar) 167797f6ef64SXu Yu iounmap(dev->bar); 167897f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 167997f6ef64SXu Yu if (!dev->bar) { 168097f6ef64SXu Yu dev->bar_mapped_size = 0; 168197f6ef64SXu Yu return -ENOMEM; 168297f6ef64SXu Yu } 168397f6ef64SXu Yu dev->bar_mapped_size = size; 168497f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 168597f6ef64SXu Yu 168697f6ef64SXu Yu return 0; 168797f6ef64SXu Yu } 168897f6ef64SXu Yu 168901ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 169057dacad5SJay Sternberg { 169157dacad5SJay Sternberg int result; 169257dacad5SJay Sternberg u32 aqa; 169357dacad5SJay Sternberg struct nvme_queue *nvmeq; 169457dacad5SJay Sternberg 169597f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 169697f6ef64SXu Yu if (result < 0) 169797f6ef64SXu Yu return result; 169897f6ef64SXu Yu 16998ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 170020d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 170157dacad5SJay Sternberg 17027a67cbeaSChristoph Hellwig if (dev->subsystem && 17037a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17047a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 170557dacad5SJay Sternberg 170620d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 170757dacad5SJay Sternberg if (result < 0) 170857dacad5SJay Sternberg return result; 170957dacad5SJay Sternberg 1710a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1711147b27e4SSagi Grimberg if (result) 1712147b27e4SSagi Grimberg return result; 171357dacad5SJay Sternberg 1714147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 171557dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 171657dacad5SJay Sternberg aqa |= aqa << 16; 171757dacad5SJay Sternberg 17187a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17197a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17207a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 172157dacad5SJay Sternberg 172220d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 172357dacad5SJay Sternberg if (result) 1724d4875622SKeith Busch return result; 172557dacad5SJay Sternberg 172657dacad5SJay Sternberg nvmeq->cq_vector = 0; 1727161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1728dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 172957dacad5SJay Sternberg if (result) { 173057dacad5SJay Sternberg nvmeq->cq_vector = -1; 1731d4875622SKeith Busch return result; 173257dacad5SJay Sternberg } 173357dacad5SJay Sternberg 17344e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 173557dacad5SJay Sternberg return result; 173657dacad5SJay Sternberg } 173757dacad5SJay Sternberg 1738749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 173957dacad5SJay Sternberg { 17404b04cc6aSJens Axboe unsigned i, max, rw_queues; 1741749941f2SChristoph Hellwig int ret = 0; 174257dacad5SJay Sternberg 1743d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1744a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1745749941f2SChristoph Hellwig ret = -ENOMEM; 174657dacad5SJay Sternberg break; 1747749941f2SChristoph Hellwig } 1748749941f2SChristoph Hellwig } 174957dacad5SJay Sternberg 1750d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1751e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1752e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1753e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17544b04cc6aSJens Axboe } else { 17554b04cc6aSJens Axboe rw_queues = max; 17564b04cc6aSJens Axboe } 17574b04cc6aSJens Axboe 1758949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17594b04cc6aSJens Axboe bool polled = i > rw_queues; 17604b04cc6aSJens Axboe 17614b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1762d4875622SKeith Busch if (ret) 176357dacad5SJay Sternberg break; 176457dacad5SJay Sternberg } 176557dacad5SJay Sternberg 1766749941f2SChristoph Hellwig /* 1767749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17688adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17698adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1770749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1771749941f2SChristoph Hellwig */ 1772749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 177357dacad5SJay Sternberg } 177457dacad5SJay Sternberg 1775202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1776202021c1SStephen Bates struct device_attribute *attr, 1777202021c1SStephen Bates char *buf) 1778202021c1SStephen Bates { 1779202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1780202021c1SStephen Bates 1781c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1782202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1783202021c1SStephen Bates } 1784202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1785202021c1SStephen Bates 178688de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 178757dacad5SJay Sternberg { 178888de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 178988de4598SChristoph Hellwig 179088de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 179188de4598SChristoph Hellwig } 179288de4598SChristoph Hellwig 179388de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 179488de4598SChristoph Hellwig { 179588de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 179688de4598SChristoph Hellwig } 179788de4598SChristoph Hellwig 1798f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 179957dacad5SJay Sternberg { 180088de4598SChristoph Hellwig u64 size, offset; 180157dacad5SJay Sternberg resource_size_t bar_size; 180257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 18038969f1f8SChristoph Hellwig int bar; 180457dacad5SJay Sternberg 18059fe5c59fSKeith Busch if (dev->cmb_size) 18069fe5c59fSKeith Busch return; 18079fe5c59fSKeith Busch 18087a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1809f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1810f65efd6dSChristoph Hellwig return; 1811202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 181257dacad5SJay Sternberg 181388de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 181488de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18158969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18168969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 181757dacad5SJay Sternberg 181857dacad5SJay Sternberg if (offset > bar_size) 1819f65efd6dSChristoph Hellwig return; 182057dacad5SJay Sternberg 182157dacad5SJay Sternberg /* 182257dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 182357dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 182457dacad5SJay Sternberg * the reported size of the BAR 182557dacad5SJay Sternberg */ 182657dacad5SJay Sternberg if (size > bar_size - offset) 182757dacad5SJay Sternberg size = bar_size - offset; 182857dacad5SJay Sternberg 18290f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18300f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18310f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1832f65efd6dSChristoph Hellwig return; 18330f238ff5SLogan Gunthorpe } 18340f238ff5SLogan Gunthorpe 183557dacad5SJay Sternberg dev->cmb_size = size; 18360f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18370f238ff5SLogan Gunthorpe 18380f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18390f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18400f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1841f65efd6dSChristoph Hellwig 1842f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1843f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1844f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1845f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 184657dacad5SJay Sternberg } 184757dacad5SJay Sternberg 184857dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 184957dacad5SJay Sternberg { 18500f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1851f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1852f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18530f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1854f63572dfSJon Derrick } 185557dacad5SJay Sternberg } 185657dacad5SJay Sternberg 185787ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 185857dacad5SJay Sternberg { 18594033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 186087ad72a5SChristoph Hellwig struct nvme_command c; 186187ad72a5SChristoph Hellwig int ret; 186287ad72a5SChristoph Hellwig 186387ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 186487ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 186587ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 186687ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 186787ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 186887ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 186987ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 187087ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 187187ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 187287ad72a5SChristoph Hellwig 187387ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 187487ad72a5SChristoph Hellwig if (ret) { 187587ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 187687ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 187787ad72a5SChristoph Hellwig ret, bits); 187887ad72a5SChristoph Hellwig } 187987ad72a5SChristoph Hellwig return ret; 188087ad72a5SChristoph Hellwig } 188187ad72a5SChristoph Hellwig 188287ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 188387ad72a5SChristoph Hellwig { 188487ad72a5SChristoph Hellwig int i; 188587ad72a5SChristoph Hellwig 188687ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 188787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 188887ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 188987ad72a5SChristoph Hellwig 189087ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 189187ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 189287ad72a5SChristoph Hellwig } 189387ad72a5SChristoph Hellwig 189487ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 189587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18964033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18974033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18984033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 189987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 19007e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 190187ad72a5SChristoph Hellwig } 190287ad72a5SChristoph Hellwig 190392dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 190492dc6895SChristoph Hellwig u32 chunk_size) 190587ad72a5SChristoph Hellwig { 190687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 190792dc6895SChristoph Hellwig u32 max_entries, len; 19084033f35dSChristoph Hellwig dma_addr_t descs_dma; 19092ee0e4edSDan Carpenter int i = 0; 191087ad72a5SChristoph Hellwig void **bufs; 19116fbcde66SMinwoo Im u64 size, tmp; 191287ad72a5SChristoph Hellwig 191387ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 191487ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 191587ad72a5SChristoph Hellwig max_entries = tmp; 1916044a9df1SChristoph Hellwig 1917044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1918044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1919044a9df1SChristoph Hellwig 19204033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 19214033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 192287ad72a5SChristoph Hellwig if (!descs) 192387ad72a5SChristoph Hellwig goto out; 192487ad72a5SChristoph Hellwig 192587ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 192687ad72a5SChristoph Hellwig if (!bufs) 192787ad72a5SChristoph Hellwig goto out_free_descs; 192887ad72a5SChristoph Hellwig 1929244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 193087ad72a5SChristoph Hellwig dma_addr_t dma_addr; 193187ad72a5SChristoph Hellwig 193250cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 193387ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 193487ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 193587ad72a5SChristoph Hellwig if (!bufs[i]) 193687ad72a5SChristoph Hellwig break; 193787ad72a5SChristoph Hellwig 193887ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 193987ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 194087ad72a5SChristoph Hellwig i++; 194187ad72a5SChristoph Hellwig } 194287ad72a5SChristoph Hellwig 194392dc6895SChristoph Hellwig if (!size) 194487ad72a5SChristoph Hellwig goto out_free_bufs; 194587ad72a5SChristoph Hellwig 194687ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 194787ad72a5SChristoph Hellwig dev->host_mem_size = size; 194887ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19494033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 195087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 195187ad72a5SChristoph Hellwig return 0; 195287ad72a5SChristoph Hellwig 195387ad72a5SChristoph Hellwig out_free_bufs: 195487ad72a5SChristoph Hellwig while (--i >= 0) { 195587ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 195687ad72a5SChristoph Hellwig 195787ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 195887ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 195987ad72a5SChristoph Hellwig } 196087ad72a5SChristoph Hellwig 196187ad72a5SChristoph Hellwig kfree(bufs); 196287ad72a5SChristoph Hellwig out_free_descs: 19634033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19644033f35dSChristoph Hellwig descs_dma); 196587ad72a5SChristoph Hellwig out: 196687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 196787ad72a5SChristoph Hellwig return -ENOMEM; 196887ad72a5SChristoph Hellwig } 196987ad72a5SChristoph Hellwig 197092dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 197192dc6895SChristoph Hellwig { 197292dc6895SChristoph Hellwig u32 chunk_size; 197392dc6895SChristoph Hellwig 197492dc6895SChristoph Hellwig /* start big and work our way down */ 197530f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1976044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 197792dc6895SChristoph Hellwig chunk_size /= 2) { 197892dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 197992dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 198092dc6895SChristoph Hellwig return 0; 198192dc6895SChristoph Hellwig nvme_free_host_mem(dev); 198292dc6895SChristoph Hellwig } 198392dc6895SChristoph Hellwig } 198492dc6895SChristoph Hellwig 198592dc6895SChristoph Hellwig return -ENOMEM; 198692dc6895SChristoph Hellwig } 198792dc6895SChristoph Hellwig 19889620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 198987ad72a5SChristoph Hellwig { 199087ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 199187ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 199287ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 199387ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19946fbcde66SMinwoo Im int ret; 199587ad72a5SChristoph Hellwig 199687ad72a5SChristoph Hellwig preferred = min(preferred, max); 199787ad72a5SChristoph Hellwig if (min > max) { 199887ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 199987ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 200087ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 200187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20029620cfbaSChristoph Hellwig return 0; 200387ad72a5SChristoph Hellwig } 200487ad72a5SChristoph Hellwig 200587ad72a5SChristoph Hellwig /* 200687ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 200787ad72a5SChristoph Hellwig */ 200887ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 200987ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 201087ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 201187ad72a5SChristoph Hellwig else 201287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 201387ad72a5SChristoph Hellwig } 201487ad72a5SChristoph Hellwig 201587ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 201692dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 201792dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 201892dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20199620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 202087ad72a5SChristoph Hellwig } 202187ad72a5SChristoph Hellwig 202292dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 202392dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 202492dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 202592dc6895SChristoph Hellwig } 202692dc6895SChristoph Hellwig 20279620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20289620cfbaSChristoph Hellwig if (ret) 202987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20309620cfbaSChristoph Hellwig return ret; 203157dacad5SJay Sternberg } 203257dacad5SJay Sternberg 20333b6592f7SJens Axboe static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int nr_io_queues) 20343b6592f7SJens Axboe { 20353b6592f7SJens Axboe unsigned int this_w_queues = write_queues; 20364b04cc6aSJens Axboe unsigned int this_p_queues = poll_queues; 20373b6592f7SJens Axboe 20383b6592f7SJens Axboe /* 20393b6592f7SJens Axboe * Setup read/write queue split 20403b6592f7SJens Axboe */ 20413b6592f7SJens Axboe if (nr_io_queues == 1) { 2042e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2043e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = 0; 2044e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_POLL] = 0; 20453b6592f7SJens Axboe return; 20463b6592f7SJens Axboe } 20473b6592f7SJens Axboe 20483b6592f7SJens Axboe /* 20494b04cc6aSJens Axboe * Configure number of poll queues, if set 20504b04cc6aSJens Axboe */ 20514b04cc6aSJens Axboe if (this_p_queues) { 20524b04cc6aSJens Axboe /* 20534b04cc6aSJens Axboe * We need at least one queue left. With just one queue, we'll 20544b04cc6aSJens Axboe * have a single shared read/write set. 20554b04cc6aSJens Axboe */ 20564b04cc6aSJens Axboe if (this_p_queues >= nr_io_queues) { 20574b04cc6aSJens Axboe this_w_queues = 0; 20584b04cc6aSJens Axboe this_p_queues = nr_io_queues - 1; 20594b04cc6aSJens Axboe } 20604b04cc6aSJens Axboe 2061e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20624b04cc6aSJens Axboe nr_io_queues -= this_p_queues; 20634b04cc6aSJens Axboe } else 2064e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_POLL] = 0; 20654b04cc6aSJens Axboe 20664b04cc6aSJens Axboe /* 20673b6592f7SJens Axboe * If 'write_queues' is set, ensure it leaves room for at least 20683b6592f7SJens Axboe * one read queue 20693b6592f7SJens Axboe */ 20703b6592f7SJens Axboe if (this_w_queues >= nr_io_queues) 20713b6592f7SJens Axboe this_w_queues = nr_io_queues - 1; 20723b6592f7SJens Axboe 20733b6592f7SJens Axboe /* 20743b6592f7SJens Axboe * If 'write_queues' is set to zero, reads and writes will share 20753b6592f7SJens Axboe * a queue set. 20763b6592f7SJens Axboe */ 20773b6592f7SJens Axboe if (!this_w_queues) { 2078e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = nr_io_queues; 2079e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = 0; 20803b6592f7SJens Axboe } else { 2081e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues; 2082e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = nr_io_queues - this_w_queues; 20833b6592f7SJens Axboe } 20843b6592f7SJens Axboe } 20853b6592f7SJens Axboe 20863b6592f7SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, int nr_io_queues) 20873b6592f7SJens Axboe { 20883b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20893b6592f7SJens Axboe int irq_sets[2]; 20903b6592f7SJens Axboe struct irq_affinity affd = { 20913b6592f7SJens Axboe .pre_vectors = 1, 20923b6592f7SJens Axboe .nr_sets = ARRAY_SIZE(irq_sets), 20933b6592f7SJens Axboe .sets = irq_sets, 20943b6592f7SJens Axboe }; 209530e06628SJens Axboe int result = 0; 20963b6592f7SJens Axboe 20973b6592f7SJens Axboe /* 20983b6592f7SJens Axboe * For irq sets, we have to ask for minvec == maxvec. This passes 20993b6592f7SJens Axboe * any reduction back to us, so we can adjust our queue counts and 21003b6592f7SJens Axboe * IRQ vector needs. 21013b6592f7SJens Axboe */ 21023b6592f7SJens Axboe do { 21033b6592f7SJens Axboe nvme_calc_io_queues(dev, nr_io_queues); 2104e20ba6e1SChristoph Hellwig irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT]; 2105e20ba6e1SChristoph Hellwig irq_sets[1] = dev->io_queues[HCTX_TYPE_READ]; 21063b6592f7SJens Axboe if (!irq_sets[1]) 21073b6592f7SJens Axboe affd.nr_sets = 1; 21083b6592f7SJens Axboe 21093b6592f7SJens Axboe /* 2110db29eb05SJens Axboe * If we got a failure and we're down to asking for just 2111db29eb05SJens Axboe * 1 + 1 queues, just ask for a single vector. We'll share 2112db29eb05SJens Axboe * that between the single IO queue and the admin queue. 21133b6592f7SJens Axboe */ 2114db29eb05SJens Axboe if (!(result < 0 && nr_io_queues == 1)) 21153b6592f7SJens Axboe nr_io_queues = irq_sets[0] + irq_sets[1] + 1; 21163b6592f7SJens Axboe 21173b6592f7SJens Axboe result = pci_alloc_irq_vectors_affinity(pdev, nr_io_queues, 21183b6592f7SJens Axboe nr_io_queues, 21193b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 21203b6592f7SJens Axboe 21213b6592f7SJens Axboe /* 2122db29eb05SJens Axboe * Need to reduce our vec counts. If we get ENOSPC, the 2123db29eb05SJens Axboe * platform should support mulitple vecs, we just need 2124db29eb05SJens Axboe * to decrease our ask. If we get EINVAL, the platform 2125db29eb05SJens Axboe * likely does not. Back down to ask for just one vector. 21263b6592f7SJens Axboe */ 21273b6592f7SJens Axboe if (result == -ENOSPC) { 21283b6592f7SJens Axboe nr_io_queues--; 21293b6592f7SJens Axboe if (!nr_io_queues) 21303b6592f7SJens Axboe return result; 21313b6592f7SJens Axboe continue; 2132db29eb05SJens Axboe } else if (result == -EINVAL) { 2133db29eb05SJens Axboe nr_io_queues = 1; 2134db29eb05SJens Axboe continue; 21353b6592f7SJens Axboe } else if (result <= 0) 21363b6592f7SJens Axboe return -EIO; 21373b6592f7SJens Axboe break; 21383b6592f7SJens Axboe } while (1); 21393b6592f7SJens Axboe 21403b6592f7SJens Axboe return result; 21413b6592f7SJens Axboe } 21423b6592f7SJens Axboe 214357dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 214457dacad5SJay Sternberg { 2145147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 214657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 214797f6ef64SXu Yu int result, nr_io_queues; 214897f6ef64SXu Yu unsigned long size; 214957dacad5SJay Sternberg 21503b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21519a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21529a0be7abSChristoph Hellwig if (result < 0) 215357dacad5SJay Sternberg return result; 21549a0be7abSChristoph Hellwig 2155f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2156a5229050SKeith Busch return 0; 215757dacad5SJay Sternberg 21584e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21594e224106SChristoph Hellwig 21600f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 216157dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 216257dacad5SJay Sternberg sizeof(struct nvme_command)); 216357dacad5SJay Sternberg if (result > 0) 216457dacad5SJay Sternberg dev->q_depth = result; 216557dacad5SJay Sternberg else 21660f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 216757dacad5SJay Sternberg } 216857dacad5SJay Sternberg 216957dacad5SJay Sternberg do { 217097f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 217197f6ef64SXu Yu result = nvme_remap_bar(dev, size); 217297f6ef64SXu Yu if (!result) 217357dacad5SJay Sternberg break; 217457dacad5SJay Sternberg if (!--nr_io_queues) 217557dacad5SJay Sternberg return -ENOMEM; 217657dacad5SJay Sternberg } while (1); 217757dacad5SJay Sternberg adminq->q_db = dev->dbs; 217857dacad5SJay Sternberg 217957dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21800ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 218157dacad5SJay Sternberg 218257dacad5SJay Sternberg /* 218357dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 218457dacad5SJay Sternberg * setting up the full range we need. 218557dacad5SJay Sternberg */ 2186dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21873b6592f7SJens Axboe 21883b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 218922b55601SKeith Busch if (result <= 0) 2190dca51e78SChristoph Hellwig return -EIO; 21913b6592f7SJens Axboe 219222b55601SKeith Busch dev->num_vecs = result; 21934b04cc6aSJens Axboe result = max(result - 1, 1); 2194e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 219557dacad5SJay Sternberg 2196e20ba6e1SChristoph Hellwig dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2197e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT], 2198e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ], 2199e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_POLL]); 22003b6592f7SJens Axboe 220157dacad5SJay Sternberg /* 220257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 220357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 220457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 220557dacad5SJay Sternberg * number of interrupts. 220657dacad5SJay Sternberg */ 220757dacad5SJay Sternberg 2208dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 220957dacad5SJay Sternberg if (result) { 221057dacad5SJay Sternberg adminq->cq_vector = -1; 2211d4875622SKeith Busch return result; 221257dacad5SJay Sternberg } 22134e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2214749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 221557dacad5SJay Sternberg } 221657dacad5SJay Sternberg 22172a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2218db3cbfffSKeith Busch { 2219db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2220db3cbfffSKeith Busch 2221db3cbfffSKeith Busch blk_mq_free_request(req); 2222d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2223db3cbfffSKeith Busch } 2224db3cbfffSKeith Busch 22252a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2226db3cbfffSKeith Busch { 2227db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2228db3cbfffSKeith Busch 2229d1ed6aa1SChristoph Hellwig if (error) 2230d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2231db3cbfffSKeith Busch 2232db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2233db3cbfffSKeith Busch } 2234db3cbfffSKeith Busch 2235db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2236db3cbfffSKeith Busch { 2237db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2238db3cbfffSKeith Busch struct request *req; 2239db3cbfffSKeith Busch struct nvme_command cmd; 2240db3cbfffSKeith Busch 2241db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2242db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2243db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2244db3cbfffSKeith Busch 2245eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2246db3cbfffSKeith Busch if (IS_ERR(req)) 2247db3cbfffSKeith Busch return PTR_ERR(req); 2248db3cbfffSKeith Busch 2249db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2250db3cbfffSKeith Busch req->end_io_data = nvmeq; 2251db3cbfffSKeith Busch 2252d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2253db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2254db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2255db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2256db3cbfffSKeith Busch return 0; 2257db3cbfffSKeith Busch } 2258db3cbfffSKeith Busch 22595271edd4SChristoph Hellwig static bool nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2260db3cbfffSKeith Busch { 22615271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2262db3cbfffSKeith Busch unsigned long timeout; 2263db3cbfffSKeith Busch 2264db3cbfffSKeith Busch retry: 2265db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22665271edd4SChristoph Hellwig while (nr_queues > 0) { 22675271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2268db3cbfffSKeith Busch break; 22695271edd4SChristoph Hellwig nr_queues--; 22705271edd4SChristoph Hellwig sent++; 22715271edd4SChristoph Hellwig } 2272d1ed6aa1SChristoph Hellwig while (sent) { 2273d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2274d1ed6aa1SChristoph Hellwig 2275d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22765271edd4SChristoph Hellwig timeout); 2277db3cbfffSKeith Busch if (timeout == 0) 22785271edd4SChristoph Hellwig return false; 2279d1ed6aa1SChristoph Hellwig 2280d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2281d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2282d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2283d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2284d1ed6aa1SChristoph Hellwig 2285d1ed6aa1SChristoph Hellwig sent--; 22865271edd4SChristoph Hellwig if (nr_queues) 2287db3cbfffSKeith Busch goto retry; 2288db3cbfffSKeith Busch } 22895271edd4SChristoph Hellwig return true; 2290db3cbfffSKeith Busch } 2291db3cbfffSKeith Busch 229257dacad5SJay Sternberg /* 22932b1b7e78SJianchao Wang * return error value only when tagset allocation failed 229457dacad5SJay Sternberg */ 229557dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 229657dacad5SJay Sternberg { 22972b1b7e78SJianchao Wang int ret; 22982b1b7e78SJianchao Wang 22995bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2300c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 230157dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2302e20ba6e1SChristoph Hellwig dev->tagset.nr_maps = HCTX_MAX_TYPES; 230357dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 230457dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 230557dacad5SJay Sternberg dev->tagset.queue_depth = 230657dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2307a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2308a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2309a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2310a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2311a7a7cbe3SChaitanya Kulkarni } 231257dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 231357dacad5SJay Sternberg dev->tagset.driver_data = dev; 231457dacad5SJay Sternberg 23152b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 23162b1b7e78SJianchao Wang if (ret) { 23172b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23182b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 23192b1b7e78SJianchao Wang return ret; 23202b1b7e78SJianchao Wang } 23215bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2322f9f38e33SHelen Koike 2323f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2324949928c1SKeith Busch } else { 2325949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2326949928c1SKeith Busch 2327949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2328949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 232957dacad5SJay Sternberg } 2330949928c1SKeith Busch 233157dacad5SJay Sternberg return 0; 233257dacad5SJay Sternberg } 233357dacad5SJay Sternberg 2334b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 233557dacad5SJay Sternberg { 2336b00a726aSKeith Busch int result = -ENOMEM; 233757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 233857dacad5SJay Sternberg 233957dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 234057dacad5SJay Sternberg return result; 234157dacad5SJay Sternberg 234257dacad5SJay Sternberg pci_set_master(pdev); 234357dacad5SJay Sternberg 234457dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 234557dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 234657dacad5SJay Sternberg goto disable; 234757dacad5SJay Sternberg 23487a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 234957dacad5SJay Sternberg result = -ENODEV; 2350b00a726aSKeith Busch goto disable; 235157dacad5SJay Sternberg } 235257dacad5SJay Sternberg 235357dacad5SJay Sternberg /* 2354a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2355a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2356a5229050SKeith Busch * adjust this later. 235757dacad5SJay Sternberg */ 2358dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2359dca51e78SChristoph Hellwig if (result < 0) 2360dca51e78SChristoph Hellwig return result; 236157dacad5SJay Sternberg 236220d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23637a67cbeaSChristoph Hellwig 236420d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2365b27c1e68Sweiping zhang io_queue_depth); 236620d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23677a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23681f390c1fSStephan Günther 23691f390c1fSStephan Günther /* 23701f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23711f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23721f390c1fSStephan Günther */ 23731f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23741f390c1fSStephan Günther dev->q_depth = 2; 23759bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23769bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23771f390c1fSStephan Günther dev->q_depth); 2378d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2379d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 238020d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2381d554b5e1SMartin K. Petersen dev->q_depth = 64; 2382d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2383d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23841f390c1fSStephan Günther } 23851f390c1fSStephan Günther 2386f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2387202021c1SStephen Bates 2388a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2389a0a3408eSKeith Busch pci_save_state(pdev); 239057dacad5SJay Sternberg return 0; 239157dacad5SJay Sternberg 239257dacad5SJay Sternberg disable: 239357dacad5SJay Sternberg pci_disable_device(pdev); 239457dacad5SJay Sternberg return result; 239557dacad5SJay Sternberg } 239657dacad5SJay Sternberg 239757dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 239857dacad5SJay Sternberg { 2399b00a726aSKeith Busch if (dev->bar) 2400b00a726aSKeith Busch iounmap(dev->bar); 2401a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2402b00a726aSKeith Busch } 2403b00a726aSKeith Busch 2404b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2405b00a726aSKeith Busch { 240657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 240757dacad5SJay Sternberg 2408dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 240957dacad5SJay Sternberg 2410a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2411a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 241257dacad5SJay Sternberg pci_disable_device(pdev); 241357dacad5SJay Sternberg } 2414a0a3408eSKeith Busch } 241557dacad5SJay Sternberg 2416a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 241757dacad5SJay Sternberg { 2418ee9aebb2SKeith Busch int i; 2419302ad8ccSKeith Busch bool dead = true; 2420302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 242157dacad5SJay Sternberg 242277bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2423302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2424302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2425302ad8ccSKeith Busch 2426ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2427ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2428302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2429302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2430302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 243157dacad5SJay Sternberg } 2432c21377f8SGabriel Krisman Bertazi 2433302ad8ccSKeith Busch /* 2434302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2435302ad8ccSKeith Busch * doing a safe shutdown. 2436302ad8ccSKeith Busch */ 243787ad72a5SChristoph Hellwig if (!dead) { 243887ad72a5SChristoph Hellwig if (shutdown) 2439302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 24409a915a5bSJianchao Wang } 244187ad72a5SChristoph Hellwig 24429a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24439a915a5bSJianchao Wang 244464ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24455271edd4SChristoph Hellwig if (nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 24465271edd4SChristoph Hellwig nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2447a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 244857dacad5SJay Sternberg } 2449ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2450ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2451ee9aebb2SKeith Busch 2452b00a726aSKeith Busch nvme_pci_disable(dev); 245357dacad5SJay Sternberg 2454e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2455e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2456302ad8ccSKeith Busch 2457302ad8ccSKeith Busch /* 2458302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2459302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2460302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2461302ad8ccSKeith Busch */ 2462302ad8ccSKeith Busch if (shutdown) 2463302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 246477bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 246557dacad5SJay Sternberg } 246657dacad5SJay Sternberg 246757dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 246857dacad5SJay Sternberg { 246957dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 247057dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 247157dacad5SJay Sternberg if (!dev->prp_page_pool) 247257dacad5SJay Sternberg return -ENOMEM; 247357dacad5SJay Sternberg 247457dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 247557dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 247657dacad5SJay Sternberg 256, 256, 0); 247757dacad5SJay Sternberg if (!dev->prp_small_pool) { 247857dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 247957dacad5SJay Sternberg return -ENOMEM; 248057dacad5SJay Sternberg } 248157dacad5SJay Sternberg return 0; 248257dacad5SJay Sternberg } 248357dacad5SJay Sternberg 248457dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 248557dacad5SJay Sternberg { 248657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 248757dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 248857dacad5SJay Sternberg } 248957dacad5SJay Sternberg 24901673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 249157dacad5SJay Sternberg { 24921673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 249357dacad5SJay Sternberg 2494f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 249557dacad5SJay Sternberg put_device(dev->dev); 249657dacad5SJay Sternberg if (dev->tagset.tags) 249757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24981c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24991c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 250057dacad5SJay Sternberg kfree(dev->queues); 2501e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2502943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 250357dacad5SJay Sternberg kfree(dev); 250457dacad5SJay Sternberg } 250557dacad5SJay Sternberg 2506f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2507f58944e2SKeith Busch { 2508237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2509f58944e2SKeith Busch 2510d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 251169d9a99cSKeith Busch nvme_dev_disable(dev, false); 25129f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 251303e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2514f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2515f58944e2SKeith Busch } 2516f58944e2SKeith Busch 2517fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 251857dacad5SJay Sternberg { 2519d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2520d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2521a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2522f58944e2SKeith Busch int result = -ENODEV; 25232b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 252457dacad5SJay Sternberg 252582b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2526fd634f41SChristoph Hellwig goto out; 2527fd634f41SChristoph Hellwig 2528fd634f41SChristoph Hellwig /* 2529fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2530fd634f41SChristoph Hellwig * moving on. 2531fd634f41SChristoph Hellwig */ 2532b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2533a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2534fd634f41SChristoph Hellwig 2535ad70062cSJianchao Wang /* 2536ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2537ad70062cSJianchao Wang * initializing procedure here. 2538ad70062cSJianchao Wang */ 2539ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2540ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2541ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2542ad70062cSJianchao Wang goto out; 2543ad70062cSJianchao Wang } 2544ad70062cSJianchao Wang 2545b00a726aSKeith Busch result = nvme_pci_enable(dev); 254657dacad5SJay Sternberg if (result) 254757dacad5SJay Sternberg goto out; 254857dacad5SJay Sternberg 254901ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 255057dacad5SJay Sternberg if (result) 2551f58944e2SKeith Busch goto out; 255257dacad5SJay Sternberg 255357dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 255457dacad5SJay Sternberg if (result) 2555f58944e2SKeith Busch goto out; 255657dacad5SJay Sternberg 2557943e942eSJens Axboe /* 2558943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2559943e942eSJens Axboe * over a single page. 2560943e942eSJens Axboe */ 2561943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2562943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2563943e942eSJens Axboe 2564ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2565ce4541f4SChristoph Hellwig if (result) 2566f58944e2SKeith Busch goto out; 2567ce4541f4SChristoph Hellwig 2568e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2569e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25704f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25714f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2572e286bcfcSScott Bauer else if (was_suspend) 25734f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2574e286bcfcSScott Bauer } else { 2575e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2576e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2577e286bcfcSScott Bauer } 2578a98e58e5SScott Bauer 2579f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2580f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2581f9f38e33SHelen Koike if (result) 2582f9f38e33SHelen Koike dev_warn(dev->dev, 2583f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2584f9f38e33SHelen Koike } 2585f9f38e33SHelen Koike 25869620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25879620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25889620cfbaSChristoph Hellwig if (result < 0) 25899620cfbaSChristoph Hellwig goto out; 25909620cfbaSChristoph Hellwig } 259187ad72a5SChristoph Hellwig 259257dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 259357dacad5SJay Sternberg if (result) 2594f58944e2SKeith Busch goto out; 259557dacad5SJay Sternberg 259621f033f7SKeith Busch /* 259757dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 259857dacad5SJay Sternberg * any working I/O queue. 259957dacad5SJay Sternberg */ 260057dacad5SJay Sternberg if (dev->online_queues < 2) { 26011b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 26023b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 26035bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 26042b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 260557dacad5SJay Sternberg } else { 260625646264SKeith Busch nvme_start_queues(&dev->ctrl); 2607302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26082b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 26092b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 26102b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2611302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 261257dacad5SJay Sternberg } 261357dacad5SJay Sternberg 26142b1b7e78SJianchao Wang /* 26152b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26162b1b7e78SJianchao Wang * recovery. 26172b1b7e78SJianchao Wang */ 26182b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 26192b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26202b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2621bb8d261eSChristoph Hellwig goto out; 2622bb8d261eSChristoph Hellwig } 262392911a55SChristoph Hellwig 2624d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 262557dacad5SJay Sternberg return; 262657dacad5SJay Sternberg 262757dacad5SJay Sternberg out: 2628f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 262957dacad5SJay Sternberg } 263057dacad5SJay Sternberg 26315c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 263257dacad5SJay Sternberg { 26335c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 263457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 263557dacad5SJay Sternberg 263657dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2637921920abSKeith Busch device_release_driver(&pdev->dev); 26381673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 263957dacad5SJay Sternberg } 264057dacad5SJay Sternberg 26411c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 264257dacad5SJay Sternberg { 26431c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26441c63dc66SChristoph Hellwig return 0; 264557dacad5SJay Sternberg } 26461c63dc66SChristoph Hellwig 26475fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26485fd4ce1bSChristoph Hellwig { 26495fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26505fd4ce1bSChristoph Hellwig return 0; 26515fd4ce1bSChristoph Hellwig } 26525fd4ce1bSChristoph Hellwig 26537fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26547fd8930fSChristoph Hellwig { 26557fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26567fd8930fSChristoph Hellwig return 0; 26577fd8930fSChristoph Hellwig } 26587fd8930fSChristoph Hellwig 265997c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 266097c12223SKeith Busch { 266197c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 266297c12223SKeith Busch 266397c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 266497c12223SKeith Busch } 266597c12223SKeith Busch 26661c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26671a353d85SMing Lin .name = "pcie", 2668e439bb12SSagi Grimberg .module = THIS_MODULE, 2669e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2670e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26711c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26725fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26737fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26741673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2675f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 267697c12223SKeith Busch .get_address = nvme_pci_get_address, 26771c63dc66SChristoph Hellwig }; 267857dacad5SJay Sternberg 2679b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2680b00a726aSKeith Busch { 2681b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2682b00a726aSKeith Busch 2683a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2684b00a726aSKeith Busch return -ENODEV; 2685b00a726aSKeith Busch 268697f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2687b00a726aSKeith Busch goto release; 2688b00a726aSKeith Busch 2689b00a726aSKeith Busch return 0; 2690b00a726aSKeith Busch release: 2691a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2692b00a726aSKeith Busch return -ENODEV; 2693b00a726aSKeith Busch } 2694b00a726aSKeith Busch 26958427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2696ff5350a8SAndy Lutomirski { 2697ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2698ff5350a8SAndy Lutomirski /* 2699ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2700ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2701ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2702ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2703ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2704ff5350a8SAndy Lutomirski * laptops. 2705ff5350a8SAndy Lutomirski */ 2706ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2707ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2708ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2709ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27108427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27118427bbc2SKai-Heng Feng /* 27128427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2713467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2714467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2715467c77d4SJarosław Janik * ASUS PRIME Z370-A 27168427bbc2SKai-Heng Feng */ 27178427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2718467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2719467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27208427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2721ff5350a8SAndy Lutomirski } 2722ff5350a8SAndy Lutomirski 2723ff5350a8SAndy Lutomirski return 0; 2724ff5350a8SAndy Lutomirski } 2725ff5350a8SAndy Lutomirski 272618119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 272718119775SKeith Busch { 272818119775SKeith Busch struct nvme_dev *dev = data; 272980f513b5SKeith Busch 273018119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 273118119775SKeith Busch flush_work(&dev->ctrl.scan_work); 273280f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 273318119775SKeith Busch } 273418119775SKeith Busch 273557dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 273657dacad5SJay Sternberg { 273757dacad5SJay Sternberg int node, result = -ENOMEM; 273857dacad5SJay Sternberg struct nvme_dev *dev; 2739ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2740943e942eSJens Axboe size_t alloc_size; 274157dacad5SJay Sternberg 274257dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 274357dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27442fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 274557dacad5SJay Sternberg 274657dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 274757dacad5SJay Sternberg if (!dev) 274857dacad5SJay Sternberg return -ENOMEM; 2749147b27e4SSagi Grimberg 27503b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27513b6592f7SJens Axboe GFP_KERNEL, node); 275257dacad5SJay Sternberg if (!dev->queues) 275357dacad5SJay Sternberg goto free; 275457dacad5SJay Sternberg 275557dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 275657dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 275757dacad5SJay Sternberg 2758b00a726aSKeith Busch result = nvme_dev_map(dev); 2759b00a726aSKeith Busch if (result) 2760b00c9b7aSChristophe JAILLET goto put_pci; 2761b00a726aSKeith Busch 2762d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27635c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 276477bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2765f3ca80fcSChristoph Hellwig 2766f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2767f3ca80fcSChristoph Hellwig if (result) 2768b00c9b7aSChristophe JAILLET goto unmap; 2769f3ca80fcSChristoph Hellwig 27708427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2771ff5350a8SAndy Lutomirski 2772943e942eSJens Axboe /* 2773943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2774943e942eSJens Axboe * command we support. 2775943e942eSJens Axboe */ 2776943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2777943e942eSJens Axboe NVME_MAX_SEGS, true); 2778943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2779943e942eSJens Axboe 2780943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2781943e942eSJens Axboe mempool_kfree, 2782943e942eSJens Axboe (void *) alloc_size, 2783943e942eSJens Axboe GFP_KERNEL, node); 2784943e942eSJens Axboe if (!dev->iod_mempool) { 2785943e942eSJens Axboe result = -ENOMEM; 2786943e942eSJens Axboe goto release_pools; 2787943e942eSJens Axboe } 2788943e942eSJens Axboe 2789b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2790b6e44b4cSKeith Busch quirks); 2791b6e44b4cSKeith Busch if (result) 2792b6e44b4cSKeith Busch goto release_mempool; 2793b6e44b4cSKeith Busch 27941b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27951b3c47c1SSagi Grimberg 279680f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 279718119775SKeith Busch async_schedule(nvme_async_probe, dev); 27984caff8fcSSagi Grimberg 279957dacad5SJay Sternberg return 0; 280057dacad5SJay Sternberg 2801b6e44b4cSKeith Busch release_mempool: 2802b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 280357dacad5SJay Sternberg release_pools: 280457dacad5SJay Sternberg nvme_release_prp_pools(dev); 2805b00c9b7aSChristophe JAILLET unmap: 2806b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 280757dacad5SJay Sternberg put_pci: 280857dacad5SJay Sternberg put_device(dev->dev); 280957dacad5SJay Sternberg free: 281057dacad5SJay Sternberg kfree(dev->queues); 281157dacad5SJay Sternberg kfree(dev); 281257dacad5SJay Sternberg return result; 281357dacad5SJay Sternberg } 281457dacad5SJay Sternberg 2815775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 281657dacad5SJay Sternberg { 281757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2818a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2819775755edSChristoph Hellwig } 282057dacad5SJay Sternberg 2821775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2822775755edSChristoph Hellwig { 2823f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 282479c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 282557dacad5SJay Sternberg } 282657dacad5SJay Sternberg 282757dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 282857dacad5SJay Sternberg { 282957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2830a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 283157dacad5SJay Sternberg } 283257dacad5SJay Sternberg 2833f58944e2SKeith Busch /* 2834f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2835f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2836f58944e2SKeith Busch * order to proceed. 2837f58944e2SKeith Busch */ 283857dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 283957dacad5SJay Sternberg { 284057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 284157dacad5SJay Sternberg 2842bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 284357dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28440ff9d4e1SKeith Busch 28456db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28460ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28471d39e692SKeith Busch nvme_dev_disable(dev, true); 2848cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28496db28edaSKeith Busch } 28500ff9d4e1SKeith Busch 2851d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2852d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2853d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2854a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28559fe5c59fSKeith Busch nvme_release_cmb(dev); 285687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 285757dacad5SJay Sternberg nvme_dev_remove_admin(dev); 285857dacad5SJay Sternberg nvme_free_queues(dev, 0); 2859d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 286057dacad5SJay Sternberg nvme_release_prp_pools(dev); 2861b00a726aSKeith Busch nvme_dev_unmap(dev); 28621673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 286357dacad5SJay Sternberg } 286457dacad5SJay Sternberg 286557dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 286657dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 286757dacad5SJay Sternberg { 286857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 286957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 287057dacad5SJay Sternberg 2871a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 287257dacad5SJay Sternberg return 0; 287357dacad5SJay Sternberg } 287457dacad5SJay Sternberg 287557dacad5SJay Sternberg static int nvme_resume(struct device *dev) 287657dacad5SJay Sternberg { 287757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 287857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 287957dacad5SJay Sternberg 2880d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 288157dacad5SJay Sternberg return 0; 288257dacad5SJay Sternberg } 288357dacad5SJay Sternberg #endif 288457dacad5SJay Sternberg 288557dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 288657dacad5SJay Sternberg 2887a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2888a0a3408eSKeith Busch pci_channel_state_t state) 2889a0a3408eSKeith Busch { 2890a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2891a0a3408eSKeith Busch 2892a0a3408eSKeith Busch /* 2893a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2894a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2895a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2896a0a3408eSKeith Busch */ 2897a0a3408eSKeith Busch switch (state) { 2898a0a3408eSKeith Busch case pci_channel_io_normal: 2899a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2900a0a3408eSKeith Busch case pci_channel_io_frozen: 2901d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2902d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2903a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2904a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2905a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2906d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2907d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2908a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2909a0a3408eSKeith Busch } 2910a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2911a0a3408eSKeith Busch } 2912a0a3408eSKeith Busch 2913a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2914a0a3408eSKeith Busch { 2915a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2916a0a3408eSKeith Busch 29171b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2918a0a3408eSKeith Busch pci_restore_state(pdev); 2919d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2920a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2921a0a3408eSKeith Busch } 2922a0a3408eSKeith Busch 2923a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2924a0a3408eSKeith Busch { 292572cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 292672cd4cc2SKeith Busch 292772cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2928a0a3408eSKeith Busch } 2929a0a3408eSKeith Busch 293057dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 293157dacad5SJay Sternberg .error_detected = nvme_error_detected, 293257dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 293357dacad5SJay Sternberg .resume = nvme_error_resume, 2934775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2935775755edSChristoph Hellwig .reset_done = nvme_reset_done, 293657dacad5SJay Sternberg }; 293757dacad5SJay Sternberg 293857dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2939106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 294008095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2941e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 294299466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 294399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2944e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 294599466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 294699466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2947e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2948f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2949f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2950f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 295150af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 29529abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 29539abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 2954540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2955540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 29560302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 29570302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 295854adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 295954adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 29608c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 29618c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2962015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2963015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2964d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2965d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2966d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2967d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2968608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2969608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2970608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2971608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2972ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2973ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 297457dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2975c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2976124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 297757dacad5SJay Sternberg { 0, } 297857dacad5SJay Sternberg }; 297957dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 298057dacad5SJay Sternberg 298157dacad5SJay Sternberg static struct pci_driver nvme_driver = { 298257dacad5SJay Sternberg .name = "nvme", 298357dacad5SJay Sternberg .id_table = nvme_id_table, 298457dacad5SJay Sternberg .probe = nvme_probe, 298557dacad5SJay Sternberg .remove = nvme_remove, 298657dacad5SJay Sternberg .shutdown = nvme_shutdown, 298757dacad5SJay Sternberg .driver = { 298857dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 298957dacad5SJay Sternberg }, 299074d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 299157dacad5SJay Sternberg .err_handler = &nvme_err_handler, 299257dacad5SJay Sternberg }; 299357dacad5SJay Sternberg 299457dacad5SJay Sternberg static int __init nvme_init(void) 299557dacad5SJay Sternberg { 29969a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 299757dacad5SJay Sternberg } 299857dacad5SJay Sternberg 299957dacad5SJay Sternberg static void __exit nvme_exit(void) 300057dacad5SJay Sternberg { 300157dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 300203e0f3a6SMing Lei flush_workqueue(nvme_wq); 300357dacad5SJay Sternberg _nvme_check_size(); 300457dacad5SJay Sternberg } 300557dacad5SJay Sternberg 300657dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 300757dacad5SJay Sternberg MODULE_LICENSE("GPL"); 300857dacad5SJay Sternberg MODULE_VERSION("1.0"); 300957dacad5SJay Sternberg module_init(nvme_init); 301057dacad5SJay Sternberg module_exit(nvme_exit); 3011