15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 1857dacad5SJay Sternberg #include <linux/mm.h> 1957dacad5SJay Sternberg #include <linux/module.h> 2077bf25eaSKeith Busch #include <linux/mutex.h> 21d0877473SKeith Busch #include <linux/once.h> 2257dacad5SJay Sternberg #include <linux/pci.h> 23d916b1beSKeith Busch #include <linux/suspend.h> 2457dacad5SJay Sternberg #include <linux/t10-pi.h> 2557dacad5SJay Sternberg #include <linux/types.h> 269cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2720d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 28a98e58e5SScott Bauer #include <linux/sed-opal.h> 290f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3057dacad5SJay Sternberg 31604c01d5Syupeng #include "trace.h" 3257dacad5SJay Sternberg #include "nvme.h" 3357dacad5SJay Sternberg 34c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 358a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3657dacad5SJay Sternberg 37a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 38adf68f21SChristoph Hellwig 39943e942eSJens Axboe /* 40943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 41943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 42943e942eSJens Axboe */ 43943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 44943e942eSJens Axboe #define NVME_MAX_SEGS 127 45943e942eSJens Axboe 4657dacad5SJay Sternberg static int use_threaded_interrupts; 4757dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4857dacad5SJay Sternberg 4957dacad5SJay Sternberg static bool use_cmb_sqes = true; 5069f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5157dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5257dacad5SJay Sternberg 5387ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5487ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5587ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5687ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5757dacad5SJay Sternberg 58a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 59a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 60a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 61a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 62a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 63a7a7cbe3SChaitanya Kulkarni 6427453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6527453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 66b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 67b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 68b27c1e68Sweiping zhang .set = io_queue_depth_set, 6961f3b896SChaitanya Kulkarni .get = param_get_uint, 70b27c1e68Sweiping zhang }; 71b27c1e68Sweiping zhang 7261f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 73b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7427453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 75b27c1e68Sweiping zhang 769c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 779c9e76d5SWeiping Zhang { 789c9e76d5SWeiping Zhang unsigned int n; 799c9e76d5SWeiping Zhang int ret; 809c9e76d5SWeiping Zhang 819c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 829c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 839c9e76d5SWeiping Zhang return -EINVAL; 849c9e76d5SWeiping Zhang return param_set_uint(val, kp); 859c9e76d5SWeiping Zhang } 869c9e76d5SWeiping Zhang 879c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 889c9e76d5SWeiping Zhang .set = io_queue_count_set, 899c9e76d5SWeiping Zhang .get = param_get_uint, 909c9e76d5SWeiping Zhang }; 919c9e76d5SWeiping Zhang 923f68baf7SKeith Busch static unsigned int write_queues; 939c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 943b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 953b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 963b6592f7SJens Axboe "will share a queue set."); 973b6592f7SJens Axboe 983f68baf7SKeith Busch static unsigned int poll_queues; 999c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1004b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1014b04cc6aSJens Axboe 102df4f9bc4SDavid E. Box static bool noacpi; 103df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 104df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 105df4f9bc4SDavid E. Box 1061c63dc66SChristoph Hellwig struct nvme_dev; 1071c63dc66SChristoph Hellwig struct nvme_queue; 10857dacad5SJay Sternberg 109a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1108fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11157dacad5SJay Sternberg 11257dacad5SJay Sternberg /* 1131c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1141c63dc66SChristoph Hellwig */ 1151c63dc66SChristoph Hellwig struct nvme_dev { 116147b27e4SSagi Grimberg struct nvme_queue *queues; 1171c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1181c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1191c63dc66SChristoph Hellwig u32 __iomem *dbs; 1201c63dc66SChristoph Hellwig struct device *dev; 1211c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1221c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1231c63dc66SChristoph Hellwig unsigned online_queues; 1241c63dc66SChristoph Hellwig unsigned max_qid; 125e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12622b55601SKeith Busch unsigned int num_vecs; 1277442ddceSJohn Garry u32 q_depth; 128c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1291c63dc66SChristoph Hellwig u32 db_stride; 1301c63dc66SChristoph Hellwig void __iomem *bar; 13197f6ef64SXu Yu unsigned long bar_mapped_size; 1325c8809e6SChristoph Hellwig struct work_struct remove_work; 13377bf25eaSKeith Busch struct mutex shutdown_lock; 1341c63dc66SChristoph Hellwig bool subsystem; 1351c63dc66SChristoph Hellwig u64 cmb_size; 1360f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1371c63dc66SChristoph Hellwig u32 cmbsz; 138202021c1SStephen Bates u32 cmbloc; 1391c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 140d916b1beSKeith Busch u32 last_ps; 141a5df5e79SKeith Busch bool hmb; 14287ad72a5SChristoph Hellwig 143943e942eSJens Axboe mempool_t *iod_mempool; 144943e942eSJens Axboe 14587ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 146f9f38e33SHelen Koike u32 *dbbuf_dbs; 147f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 148f9f38e33SHelen Koike u32 *dbbuf_eis; 149f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15087ad72a5SChristoph Hellwig 15187ad72a5SChristoph Hellwig /* host memory buffer support: */ 15287ad72a5SChristoph Hellwig u64 host_mem_size; 15387ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1544033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15687ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1572a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1582a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1592a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 1600521905eSKeith Busch 1610521905eSKeith Busch bool attrs_added; 16257dacad5SJay Sternberg }; 16357dacad5SJay Sternberg 164b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 165b27c1e68Sweiping zhang { 16627453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16727453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 168b27c1e68Sweiping zhang } 169b27c1e68Sweiping zhang 170f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 171f9f38e33SHelen Koike { 172f9f38e33SHelen Koike return qid * 2 * stride; 173f9f38e33SHelen Koike } 174f9f38e33SHelen Koike 175f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 176f9f38e33SHelen Koike { 177f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 178f9f38e33SHelen Koike } 179f9f38e33SHelen Koike 1801c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1811c63dc66SChristoph Hellwig { 1821c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1831c63dc66SChristoph Hellwig } 1841c63dc66SChristoph Hellwig 18557dacad5SJay Sternberg /* 18657dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18757dacad5SJay Sternberg * commands and one for I/O commands). 18857dacad5SJay Sternberg */ 18957dacad5SJay Sternberg struct nvme_queue { 19057dacad5SJay Sternberg struct nvme_dev *dev; 1911ab0cd69SJens Axboe spinlock_t sq_lock; 192c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1933a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1943a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19574943d45SKeith Busch struct nvme_completion *cqes; 19657dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19757dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19857dacad5SJay Sternberg u32 __iomem *q_db; 1997442ddceSJohn Garry u32 q_depth; 2007c349ddeSKeith Busch u16 cq_vector; 20157dacad5SJay Sternberg u16 sq_tail; 20238210800SKeith Busch u16 last_sq_tail; 20357dacad5SJay Sternberg u16 cq_head; 20457dacad5SJay Sternberg u16 qid; 20557dacad5SJay Sternberg u8 cq_phase; 206c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2074e224106SChristoph Hellwig unsigned long flags; 2084e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20963223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 210d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2117c349ddeSKeith Busch #define NVMEQ_POLLED 3 212f9f38e33SHelen Koike u32 *dbbuf_sq_db; 213f9f38e33SHelen Koike u32 *dbbuf_cq_db; 214f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 215f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 216d1ed6aa1SChristoph Hellwig struct completion delete_done; 21757dacad5SJay Sternberg }; 21857dacad5SJay Sternberg 21957dacad5SJay Sternberg /* 2209b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2219b048119SChristoph Hellwig * 2229b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2239b048119SChristoph Hellwig * to the actual struct scatterlist. 22471bd150cSChristoph Hellwig */ 22571bd150cSChristoph Hellwig struct nvme_iod { 226d49187e9SChristoph Hellwig struct nvme_request req; 227af7fae85SKeith Busch struct nvme_command cmd; 228f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 229a7a7cbe3SChaitanya Kulkarni bool use_sgl; 230f4800d6dSChristoph Hellwig int aborted; 23171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 23271bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 23371bd150cSChristoph Hellwig dma_addr_t first_dma; 234dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 235783b94bdSChristoph Hellwig dma_addr_t meta_dma; 236f4800d6dSChristoph Hellwig struct scatterlist *sg; 23757dacad5SJay Sternberg }; 23857dacad5SJay Sternberg 2392a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2403b6592f7SJens Axboe { 2412a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 242f9f38e33SHelen Koike } 243f9f38e33SHelen Koike 244f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 245f9f38e33SHelen Koike { 2462a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 247f9f38e33SHelen Koike 24858847f12SKeith Busch if (dev->dbbuf_dbs) { 24958847f12SKeith Busch /* 25058847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25158847f12SKeith Busch * values from the previous instantiation. 25258847f12SKeith Busch */ 25358847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 25458847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 255f9f38e33SHelen Koike return 0; 25658847f12SKeith Busch } 257f9f38e33SHelen Koike 258f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 259f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 260f9f38e33SHelen Koike GFP_KERNEL); 261f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 262f9f38e33SHelen Koike return -ENOMEM; 263f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 264f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 265f9f38e33SHelen Koike GFP_KERNEL); 266f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 267f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 268f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 269f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 270f9f38e33SHelen Koike return -ENOMEM; 271f9f38e33SHelen Koike } 272f9f38e33SHelen Koike 273f9f38e33SHelen Koike return 0; 274f9f38e33SHelen Koike } 275f9f38e33SHelen Koike 276f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 277f9f38e33SHelen Koike { 2782a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 279f9f38e33SHelen Koike 280f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 281f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 282f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 283f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 284f9f38e33SHelen Koike } 285f9f38e33SHelen Koike if (dev->dbbuf_eis) { 286f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 287f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 288f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 289f9f38e33SHelen Koike } 290f9f38e33SHelen Koike } 291f9f38e33SHelen Koike 292f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 293f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 294f9f38e33SHelen Koike { 295f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 296f9f38e33SHelen Koike return; 297f9f38e33SHelen Koike 298f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 299f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 300f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 301f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 302f9f38e33SHelen Koike } 303f9f38e33SHelen Koike 3040f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3050f0d2c87SMinwoo Im { 3060f0d2c87SMinwoo Im if (!nvmeq->qid) 3070f0d2c87SMinwoo Im return; 3080f0d2c87SMinwoo Im 3090f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3100f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3110f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3120f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3130f0d2c87SMinwoo Im } 3140f0d2c87SMinwoo Im 315f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 316f9f38e33SHelen Koike { 317f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3180f0d2c87SMinwoo Im unsigned int i; 319f9f38e33SHelen Koike 320f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 321f9f38e33SHelen Koike return; 322f9f38e33SHelen Koike 323f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 324f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 325f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 326f9f38e33SHelen Koike 327f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3289bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 329f9f38e33SHelen Koike /* Free memory and continue on */ 330f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3310f0d2c87SMinwoo Im 3320f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3330f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 334f9f38e33SHelen Koike } 335f9f38e33SHelen Koike } 336f9f38e33SHelen Koike 337f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 338f9f38e33SHelen Koike { 339f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 340f9f38e33SHelen Koike } 341f9f38e33SHelen Koike 342f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 343f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 344f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 345f9f38e33SHelen Koike { 346f9f38e33SHelen Koike if (dbbuf_db) { 347f9f38e33SHelen Koike u16 old_value; 348f9f38e33SHelen Koike 349f9f38e33SHelen Koike /* 350f9f38e33SHelen Koike * Ensure that the queue is written before updating 351f9f38e33SHelen Koike * the doorbell in memory 352f9f38e33SHelen Koike */ 353f9f38e33SHelen Koike wmb(); 354f9f38e33SHelen Koike 355f9f38e33SHelen Koike old_value = *dbbuf_db; 356f9f38e33SHelen Koike *dbbuf_db = value; 357f9f38e33SHelen Koike 358f1ed3df2SMichal Wnukowski /* 359f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 360f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 361f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 362f1ed3df2SMichal Wnukowski * the doorbell. 363f1ed3df2SMichal Wnukowski */ 364f1ed3df2SMichal Wnukowski mb(); 365f1ed3df2SMichal Wnukowski 366f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 367f9f38e33SHelen Koike return false; 368f9f38e33SHelen Koike } 369f9f38e33SHelen Koike 370f9f38e33SHelen Koike return true; 37157dacad5SJay Sternberg } 37257dacad5SJay Sternberg 37357dacad5SJay Sternberg /* 37457dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37557dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37657dacad5SJay Sternberg * the I/O. 37757dacad5SJay Sternberg */ 378b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 37957dacad5SJay Sternberg { 380b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3816c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 38257dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38357dacad5SJay Sternberg } 38457dacad5SJay Sternberg 385a7a7cbe3SChaitanya Kulkarni /* 386a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 387a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 388a7a7cbe3SChaitanya Kulkarni */ 389b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 390f4800d6dSChristoph Hellwig { 391b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 392b13c6393SChaitanya Kulkarni PAGE_SIZE); 393f4800d6dSChristoph Hellwig } 394f4800d6dSChristoph Hellwig 395b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 39657dacad5SJay Sternberg { 397b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 398a7a7cbe3SChaitanya Kulkarni 399b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 400b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 401a7a7cbe3SChaitanya Kulkarni } 402a7a7cbe3SChaitanya Kulkarni 40357dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40457dacad5SJay Sternberg unsigned int hctx_idx) 40557dacad5SJay Sternberg { 40657dacad5SJay Sternberg struct nvme_dev *dev = data; 407147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40857dacad5SJay Sternberg 40957dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 41057dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 41157dacad5SJay Sternberg 41257dacad5SJay Sternberg hctx->driver_data = nvmeq; 41357dacad5SJay Sternberg return 0; 41457dacad5SJay Sternberg } 41557dacad5SJay Sternberg 41657dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41757dacad5SJay Sternberg unsigned int hctx_idx) 41857dacad5SJay Sternberg { 41957dacad5SJay Sternberg struct nvme_dev *dev = data; 420147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 42157dacad5SJay Sternberg 42257dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 42357dacad5SJay Sternberg hctx->driver_data = nvmeq; 42457dacad5SJay Sternberg return 0; 42557dacad5SJay Sternberg } 42657dacad5SJay Sternberg 427d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 428d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 42957dacad5SJay Sternberg { 430d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 431f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4320350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 433147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 43457dacad5SJay Sternberg 43557dacad5SJay Sternberg BUG_ON(!nvmeq); 436f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 43759e29ce6SSagi Grimberg 43859e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 439f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 44057dacad5SJay Sternberg return 0; 44157dacad5SJay Sternberg } 44257dacad5SJay Sternberg 4433b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4443b6592f7SJens Axboe { 4453b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4463b6592f7SJens Axboe if (dev->num_vecs > 1) 4473b6592f7SJens Axboe return 1; 4483b6592f7SJens Axboe 4493b6592f7SJens Axboe return 0; 4503b6592f7SJens Axboe } 4513b6592f7SJens Axboe 452dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 453dca51e78SChristoph Hellwig { 454dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4553b6592f7SJens Axboe int i, qoff, offset; 456dca51e78SChristoph Hellwig 4573b6592f7SJens Axboe offset = queue_irq_offset(dev); 4583b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4593b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4603b6592f7SJens Axboe 4613b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4623b6592f7SJens Axboe if (!map->nr_queues) { 463e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4647e849dd9SChristoph Hellwig continue; 4653b6592f7SJens Axboe } 4663b6592f7SJens Axboe 4674b04cc6aSJens Axboe /* 4684b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4694b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4704b04cc6aSJens Axboe */ 4713b6592f7SJens Axboe map->queue_offset = qoff; 472cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4733b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4744b04cc6aSJens Axboe else 4754b04cc6aSJens Axboe blk_mq_map_queues(map); 4763b6592f7SJens Axboe qoff += map->nr_queues; 4773b6592f7SJens Axboe offset += map->nr_queues; 4783b6592f7SJens Axboe } 4793b6592f7SJens Axboe 4803b6592f7SJens Axboe return 0; 481dca51e78SChristoph Hellwig } 482dca51e78SChristoph Hellwig 48338210800SKeith Busch /* 48438210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 48538210800SKeith Busch */ 48638210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 48704f3eafdSJens Axboe { 48838210800SKeith Busch if (!write_sq) { 48938210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 49038210800SKeith Busch 49138210800SKeith Busch if (next_tail == nvmeq->q_depth) 49238210800SKeith Busch next_tail = 0; 49338210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 49438210800SKeith Busch return; 49538210800SKeith Busch } 49638210800SKeith Busch 49704f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 49804f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 49904f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 50038210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 50104f3eafdSJens Axboe } 50204f3eafdSJens Axboe 503*3233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 504*3233b94cSJens Axboe struct nvme_command *cmd) 50557dacad5SJay Sternberg { 506c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 507*3233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 50890ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 50990ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 51004f3eafdSJens Axboe } 51104f3eafdSJens Axboe 51204f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 51304f3eafdSJens Axboe { 51404f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 51504f3eafdSJens Axboe 51604f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 51738210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 51838210800SKeith Busch nvme_write_sq_db(nvmeq, true); 51990ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 52057dacad5SJay Sternberg } 52157dacad5SJay Sternberg 522a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 52357dacad5SJay Sternberg { 524f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 525a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 52657dacad5SJay Sternberg } 52757dacad5SJay Sternberg 528955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 529955b1b5aSMinwoo Im { 530955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 53120469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 532955b1b5aSMinwoo Im unsigned int avg_seg_size; 533955b1b5aSMinwoo Im 53420469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 535955b1b5aSMinwoo Im 536253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 537955b1b5aSMinwoo Im return false; 538955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 539955b1b5aSMinwoo Im return false; 540955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 541955b1b5aSMinwoo Im return false; 542955b1b5aSMinwoo Im return true; 543955b1b5aSMinwoo Im } 544955b1b5aSMinwoo Im 5459275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 54657dacad5SJay Sternberg { 5476c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5489275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5499275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 55057dacad5SJay Sternberg int i; 55157dacad5SJay Sternberg 5529275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5539275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5549275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5559275c206SChristoph Hellwig 5569275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5579275c206SChristoph Hellwig dma_addr = next_dma_addr; 558dff824b2SChristoph Hellwig } 5599275c206SChristoph Hellwig } 5609275c206SChristoph Hellwig 5619275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5629275c206SChristoph Hellwig { 5639275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5649275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5659275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5669275c206SChristoph Hellwig int i; 5679275c206SChristoph Hellwig 5689275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5699275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5709275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5719275c206SChristoph Hellwig 5729275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5739275c206SChristoph Hellwig dma_addr = next_dma_addr; 5749275c206SChristoph Hellwig } 5759275c206SChristoph Hellwig } 5769275c206SChristoph Hellwig 5779275c206SChristoph Hellwig static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 5789275c206SChristoph Hellwig { 5799275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 580dff824b2SChristoph Hellwig 5817f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5827f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5837f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5847f73eac3SLogan Gunthorpe else 585dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5869275c206SChristoph Hellwig } 5877fe07d14SChristoph Hellwig 5889275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5899275c206SChristoph Hellwig { 5909275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5917fe07d14SChristoph Hellwig 5929275c206SChristoph Hellwig if (iod->dma_len) { 5939275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5949275c206SChristoph Hellwig rq_dma_dir(req)); 5959275c206SChristoph Hellwig return; 5969275c206SChristoph Hellwig } 5979275c206SChristoph Hellwig 5989275c206SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 5999275c206SChristoph Hellwig 6009275c206SChristoph Hellwig nvme_unmap_sg(dev, req); 60157dacad5SJay Sternberg if (iod->npages == 0) 602a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 6039275c206SChristoph Hellwig iod->first_dma); 6049275c206SChristoph Hellwig else if (iod->use_sgl) 6059275c206SChristoph Hellwig nvme_free_sgls(dev, req); 6069275c206SChristoph Hellwig else 6079275c206SChristoph Hellwig nvme_free_prps(dev, req); 608943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 60957dacad5SJay Sternberg } 61057dacad5SJay Sternberg 611d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 612d0877473SKeith Busch { 613d0877473SKeith Busch int i; 614d0877473SKeith Busch struct scatterlist *sg; 615d0877473SKeith Busch 616d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 617d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 618d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 619d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 620d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 621d0877473SKeith Busch sg_dma_len(sg)); 622d0877473SKeith Busch } 623d0877473SKeith Busch } 624d0877473SKeith Busch 625a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 626a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 62757dacad5SJay Sternberg { 628f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 62957dacad5SJay Sternberg struct dma_pool *pool; 630b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 63157dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 63257dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 63357dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6346c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 63557dacad5SJay Sternberg __le64 *prp_list; 636a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 63757dacad5SJay Sternberg dma_addr_t prp_dma; 63857dacad5SJay Sternberg int nprps, i; 63957dacad5SJay Sternberg 6406c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6415228b328SJan H. Schönherr if (length <= 0) { 6425228b328SJan H. Schönherr iod->first_dma = 0; 643a7a7cbe3SChaitanya Kulkarni goto done; 6445228b328SJan H. Schönherr } 64557dacad5SJay Sternberg 6466c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 64757dacad5SJay Sternberg if (dma_len) { 6486c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 64957dacad5SJay Sternberg } else { 65057dacad5SJay Sternberg sg = sg_next(sg); 65157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65357dacad5SJay Sternberg } 65457dacad5SJay Sternberg 6556c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 65657dacad5SJay Sternberg iod->first_dma = dma_addr; 657a7a7cbe3SChaitanya Kulkarni goto done; 65857dacad5SJay Sternberg } 65957dacad5SJay Sternberg 6606c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 66157dacad5SJay Sternberg if (nprps <= (256 / 8)) { 66257dacad5SJay Sternberg pool = dev->prp_small_pool; 66357dacad5SJay Sternberg iod->npages = 0; 66457dacad5SJay Sternberg } else { 66557dacad5SJay Sternberg pool = dev->prp_page_pool; 66657dacad5SJay Sternberg iod->npages = 1; 66757dacad5SJay Sternberg } 66857dacad5SJay Sternberg 66969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67057dacad5SJay Sternberg if (!prp_list) { 67157dacad5SJay Sternberg iod->first_dma = dma_addr; 67257dacad5SJay Sternberg iod->npages = -1; 67386eea289SKeith Busch return BLK_STS_RESOURCE; 67457dacad5SJay Sternberg } 67557dacad5SJay Sternberg list[0] = prp_list; 67657dacad5SJay Sternberg iod->first_dma = prp_dma; 67757dacad5SJay Sternberg i = 0; 67857dacad5SJay Sternberg for (;;) { 6796c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 68057dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 68169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68257dacad5SJay Sternberg if (!prp_list) 683fa073216SChristoph Hellwig goto free_prps; 68457dacad5SJay Sternberg list[iod->npages++] = prp_list; 68557dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 68657dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 68757dacad5SJay Sternberg i = 1; 68857dacad5SJay Sternberg } 68957dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6906c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6916c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6926c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 69357dacad5SJay Sternberg if (length <= 0) 69457dacad5SJay Sternberg break; 69557dacad5SJay Sternberg if (dma_len > 0) 69657dacad5SJay Sternberg continue; 69786eea289SKeith Busch if (unlikely(dma_len < 0)) 69886eea289SKeith Busch goto bad_sgl; 69957dacad5SJay Sternberg sg = sg_next(sg); 70057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 70157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 70257dacad5SJay Sternberg } 703a7a7cbe3SChaitanya Kulkarni done: 704a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 705a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 70686eea289SKeith Busch return BLK_STS_OK; 707fa073216SChristoph Hellwig free_prps: 708fa073216SChristoph Hellwig nvme_free_prps(dev, req); 709fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 71086eea289SKeith Busch bad_sgl: 711d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 712d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 713d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 71486eea289SKeith Busch return BLK_STS_IOERR; 71557dacad5SJay Sternberg } 71657dacad5SJay Sternberg 717a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 718a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 719a7a7cbe3SChaitanya Kulkarni { 720a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 721a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 722a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 723a7a7cbe3SChaitanya Kulkarni } 724a7a7cbe3SChaitanya Kulkarni 725a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 726a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 727a7a7cbe3SChaitanya Kulkarni { 728a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 729a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 730a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 731a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 732a7a7cbe3SChaitanya Kulkarni } else { 733a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 734a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 735a7a7cbe3SChaitanya Kulkarni } 736a7a7cbe3SChaitanya Kulkarni } 737a7a7cbe3SChaitanya Kulkarni 738a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 739b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 740a7a7cbe3SChaitanya Kulkarni { 741a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 742a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 743a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 744a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 745a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 746b0f2853bSChristoph Hellwig int i = 0; 747a7a7cbe3SChaitanya Kulkarni 748a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 749a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 750a7a7cbe3SChaitanya Kulkarni 751b0f2853bSChristoph Hellwig if (entries == 1) { 752a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 753a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 754a7a7cbe3SChaitanya Kulkarni } 755a7a7cbe3SChaitanya Kulkarni 756a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 757a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 758a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 759a7a7cbe3SChaitanya Kulkarni } else { 760a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 761a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 762a7a7cbe3SChaitanya Kulkarni } 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 765a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 766a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 767a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 768a7a7cbe3SChaitanya Kulkarni } 769a7a7cbe3SChaitanya Kulkarni 770a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 771a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 774a7a7cbe3SChaitanya Kulkarni 775a7a7cbe3SChaitanya Kulkarni do { 776a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 777a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 778a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 779a7a7cbe3SChaitanya Kulkarni 780a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 781a7a7cbe3SChaitanya Kulkarni if (!sg_list) 782fa073216SChristoph Hellwig goto free_sgls; 783a7a7cbe3SChaitanya Kulkarni 784a7a7cbe3SChaitanya Kulkarni i = 0; 785a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 786a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 787a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 788a7a7cbe3SChaitanya Kulkarni } 789a7a7cbe3SChaitanya Kulkarni 790a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 791a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 792b0f2853bSChristoph Hellwig } while (--entries > 0); 793a7a7cbe3SChaitanya Kulkarni 794a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 795fa073216SChristoph Hellwig free_sgls: 796fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 797fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 798a7a7cbe3SChaitanya Kulkarni } 799a7a7cbe3SChaitanya Kulkarni 800dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 801dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 802dff824b2SChristoph Hellwig struct bio_vec *bv) 803dff824b2SChristoph Hellwig { 804dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8056c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 8066c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 807dff824b2SChristoph Hellwig 808dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 809dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 810dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 811dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 812dff824b2SChristoph Hellwig 813dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 814dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 815dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 816359c1f88SBaolin Wang return BLK_STS_OK; 817dff824b2SChristoph Hellwig } 818dff824b2SChristoph Hellwig 81929791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 82029791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 82129791057SChristoph Hellwig struct bio_vec *bv) 82229791057SChristoph Hellwig { 82329791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82429791057SChristoph Hellwig 82529791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 82629791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 82729791057SChristoph Hellwig return BLK_STS_RESOURCE; 82829791057SChristoph Hellwig iod->dma_len = bv->bv_len; 82929791057SChristoph Hellwig 830049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 83129791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 83229791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 83329791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 834359c1f88SBaolin Wang return BLK_STS_OK; 83529791057SChristoph Hellwig } 83629791057SChristoph Hellwig 837fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 838b131c61dSChristoph Hellwig struct nvme_command *cmnd) 83957dacad5SJay Sternberg { 840f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 84170479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 842b0f2853bSChristoph Hellwig int nr_mapped; 84357dacad5SJay Sternberg 844dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 845dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 846dff824b2SChristoph Hellwig 847dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8486c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 849dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 850dff824b2SChristoph Hellwig &cmnd->rw, &bv); 85129791057SChristoph Hellwig 852e51183beSNiklas Cassel if (iod->nvmeq->qid && sgl_threshold && 853253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 85429791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 85529791057SChristoph Hellwig &cmnd->rw, &bv); 856dff824b2SChristoph Hellwig } 857dff824b2SChristoph Hellwig } 858dff824b2SChristoph Hellwig 859dff824b2SChristoph Hellwig iod->dma_len = 0; 8609b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8619b048119SChristoph Hellwig if (!iod->sg) 8629b048119SChristoph Hellwig return BLK_STS_RESOURCE; 863f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 86470479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 865ba1ca37eSChristoph Hellwig if (!iod->nents) 866fa073216SChristoph Hellwig goto out_free_sg; 867ba1ca37eSChristoph Hellwig 868e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8692b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8702b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 871e0596ab2SLogan Gunthorpe else 872e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 87370479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 874b0f2853bSChristoph Hellwig if (!nr_mapped) 875fa073216SChristoph Hellwig goto out_free_sg; 876ba1ca37eSChristoph Hellwig 87770479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 878955b1b5aSMinwoo Im if (iod->use_sgl) 879b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 880a7a7cbe3SChaitanya Kulkarni else 881a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8824aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 883fa073216SChristoph Hellwig goto out_unmap_sg; 884fa073216SChristoph Hellwig return BLK_STS_OK; 885fa073216SChristoph Hellwig 886fa073216SChristoph Hellwig out_unmap_sg: 887fa073216SChristoph Hellwig nvme_unmap_sg(dev, req); 888fa073216SChristoph Hellwig out_free_sg: 889fa073216SChristoph Hellwig mempool_free(iod->sg, dev->iod_mempool); 890ba1ca37eSChristoph Hellwig return ret; 89157dacad5SJay Sternberg } 89257dacad5SJay Sternberg 8934aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8944aedb705SChristoph Hellwig struct nvme_command *cmnd) 8954aedb705SChristoph Hellwig { 8964aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8974aedb705SChristoph Hellwig 8984aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8994aedb705SChristoph Hellwig rq_dma_dir(req), 0); 9004aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 9014aedb705SChristoph Hellwig return BLK_STS_IOERR; 9024aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 903359c1f88SBaolin Wang return BLK_STS_OK; 9044aedb705SChristoph Hellwig } 9054aedb705SChristoph Hellwig 90657dacad5SJay Sternberg /* 90757dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 90857dacad5SJay Sternberg */ 909fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 91057dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 91157dacad5SJay Sternberg { 91257dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 91357dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 91457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 91557dacad5SJay Sternberg struct request *req = bd->rq; 9169b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 917af7fae85SKeith Busch struct nvme_command *cmnd = &iod->cmd; 918ebe6d874SChristoph Hellwig blk_status_t ret; 91957dacad5SJay Sternberg 9209b048119SChristoph Hellwig iod->aborted = 0; 9219b048119SChristoph Hellwig iod->npages = -1; 9229b048119SChristoph Hellwig iod->nents = 0; 9239b048119SChristoph Hellwig 924d1f06f4aSJens Axboe /* 925d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 926d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 927d1f06f4aSJens Axboe */ 9284e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 929d1f06f4aSJens Axboe return BLK_STS_IOERR; 930d1f06f4aSJens Axboe 931d4060d2bSTao Chiu if (!nvme_check_ready(&dev->ctrl, req, true)) 932d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 933d4060d2bSTao Chiu 934f4b9e6c9SKeith Busch ret = nvme_setup_cmd(ns, req); 935fc17b653SChristoph Hellwig if (ret) 936f4800d6dSChristoph Hellwig return ret; 93757dacad5SJay Sternberg 938fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 939af7fae85SKeith Busch ret = nvme_map_data(dev, req, cmnd); 940fc17b653SChristoph Hellwig if (ret) 9419b048119SChristoph Hellwig goto out_free_cmd; 942fc17b653SChristoph Hellwig } 943ba1ca37eSChristoph Hellwig 9444aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 945af7fae85SKeith Busch ret = nvme_map_metadata(dev, req, cmnd); 9464aedb705SChristoph Hellwig if (ret) 9474aedb705SChristoph Hellwig goto out_unmap_data; 9484aedb705SChristoph Hellwig } 9494aedb705SChristoph Hellwig 950aae239e1SChristoph Hellwig blk_mq_start_request(req); 951*3233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 952*3233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 953*3233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 954*3233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 955fc17b653SChristoph Hellwig return BLK_STS_OK; 9564aedb705SChristoph Hellwig out_unmap_data: 9574aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 958f9d03f96SChristoph Hellwig out_free_cmd: 959f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 960ba1ca37eSChristoph Hellwig return ret; 96157dacad5SJay Sternberg } 96257dacad5SJay Sternberg 963c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 964eee417b0SChristoph Hellwig { 965f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9664aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 967eee417b0SChristoph Hellwig 9684aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9694aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9704aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 971b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9724aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 973c234a653SJens Axboe } 974c234a653SJens Axboe 975c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 976c234a653SJens Axboe { 977c234a653SJens Axboe nvme_pci_unmap_rq(req); 97877f02a7aSChristoph Hellwig nvme_complete_rq(req); 97957dacad5SJay Sternberg } 98057dacad5SJay Sternberg 981c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 982c234a653SJens Axboe { 983c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 984c234a653SJens Axboe } 985c234a653SJens Axboe 986d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 987750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 988d783e0bdSMarta Rybczynska { 98974943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 99074943d45SKeith Busch 99174943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 992d783e0bdSMarta Rybczynska } 993d783e0bdSMarta Rybczynska 994eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 99557dacad5SJay Sternberg { 996eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 99757dacad5SJay Sternberg 998eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 999eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1000eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1001eb281c82SSagi Grimberg } 1002adf68f21SChristoph Hellwig 1003cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1004cfa27356SChristoph Hellwig { 1005cfa27356SChristoph Hellwig if (!nvmeq->qid) 1006cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1007cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1008cfa27356SChristoph Hellwig } 1009cfa27356SChristoph Hellwig 1010c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1011c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 101257dacad5SJay Sternberg { 101374943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 101462df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 101557dacad5SJay Sternberg struct request *req; 1016adf68f21SChristoph Hellwig 1017adf68f21SChristoph Hellwig /* 1018adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1019adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1020adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1021adf68f21SChristoph Hellwig * for them but rather special case them here. 1022adf68f21SChristoph Hellwig */ 102362df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10247bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 102583a12fb7SSagi Grimberg cqe->status, &cqe->result); 1026a0fa9647SJens Axboe return; 102757dacad5SJay Sternberg } 102857dacad5SJay Sternberg 1029e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 103050b7c243SXianting Tian if (unlikely(!req)) { 103150b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 103250b7c243SXianting Tian "invalid id %d completed on queue %d\n", 103362df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 103450b7c243SXianting Tian return; 103550b7c243SXianting Tian } 103650b7c243SXianting Tian 1037604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1038c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1039c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1040c234a653SJens Axboe nvme_pci_complete_batch)) 1041ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 104283a12fb7SSagi Grimberg } 104357dacad5SJay Sternberg 10445cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10455cb525c8SJens Axboe { 1046a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1047a8de6639SAlexey Dobriyan 1048a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1049920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1050e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1051a8de6639SAlexey Dobriyan } else { 1052a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1053920d13a8SSagi Grimberg } 1054a0fa9647SJens Axboe } 1055a0fa9647SJens Axboe 1056c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1057c234a653SJens Axboe struct io_comp_batch *iob) 1058a0fa9647SJens Axboe { 10591052b8acSJens Axboe int found = 0; 106083a12fb7SSagi Grimberg 10611052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10621052b8acSJens Axboe found++; 1063b69e2ef2SKeith Busch /* 1064b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1065b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1066b69e2ef2SKeith Busch */ 1067b69e2ef2SKeith Busch dma_rmb(); 1068c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 10695cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 107057dacad5SJay Sternberg } 107157dacad5SJay Sternberg 1072324b494cSKeith Busch if (found) 1073eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10745cb525c8SJens Axboe return found; 107557dacad5SJay Sternberg } 107657dacad5SJay Sternberg 107757dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 107857dacad5SJay Sternberg { 107957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10804f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 10815cb525c8SJens Axboe 10824f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 10834f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 10844f502245SJens Axboe nvme_pci_complete_batch(&iob); 108505fae499SChaitanya Kulkarni return IRQ_HANDLED; 10864f502245SJens Axboe } 108705fae499SChaitanya Kulkarni return IRQ_NONE; 108857dacad5SJay Sternberg } 108957dacad5SJay Sternberg 109057dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 109157dacad5SJay Sternberg { 109257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10934e523547SBaolin Wang 1094750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 109557dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1096d783e0bdSMarta Rybczynska return IRQ_NONE; 109757dacad5SJay Sternberg } 109857dacad5SJay Sternberg 10990b2a8a9fSChristoph Hellwig /* 1100fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11010b2a8a9fSChristoph Hellwig * Can be called from any context. 11020b2a8a9fSChristoph Hellwig */ 1103fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1104a0fa9647SJens Axboe { 11053a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1106a0fa9647SJens Axboe 1107fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1108fa059b85SKeith Busch 11093a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1110c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11113a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 111291a509f8SChristoph Hellwig } 1113442e19b7SSagi Grimberg 11145a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11157776db1cSKeith Busch { 11167776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1117dabcefabSJens Axboe bool found; 1118dabcefabSJens Axboe 1119dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1120dabcefabSJens Axboe return 0; 1121dabcefabSJens Axboe 11223a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1123c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11243a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1125dabcefabSJens Axboe 1126dabcefabSJens Axboe return found; 1127dabcefabSJens Axboe } 1128dabcefabSJens Axboe 1129ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 113057dacad5SJay Sternberg { 1131f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1132147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1133f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 113457dacad5SJay Sternberg 113557dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1136ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1137*3233b94cSJens Axboe 1138*3233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 1139*3233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 1140*3233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 1141*3233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 114257dacad5SJay Sternberg } 114357dacad5SJay Sternberg 114457dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 114557dacad5SJay Sternberg { 1146f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 114757dacad5SJay Sternberg 114857dacad5SJay Sternberg c.delete_queue.opcode = opcode; 114957dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 115057dacad5SJay Sternberg 11511c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 115257dacad5SJay Sternberg } 115357dacad5SJay Sternberg 115457dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1155a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 115657dacad5SJay Sternberg { 1157f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 11584b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11594b04cc6aSJens Axboe 11607c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11614b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 116257dacad5SJay Sternberg 116357dacad5SJay Sternberg /* 116416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 116557dacad5SJay Sternberg * is attached to the request. 116657dacad5SJay Sternberg */ 116757dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 116857dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 116957dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 117057dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 117157dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1172a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 117357dacad5SJay Sternberg 11741c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 117557dacad5SJay Sternberg } 117657dacad5SJay Sternberg 117757dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 117857dacad5SJay Sternberg struct nvme_queue *nvmeq) 117957dacad5SJay Sternberg { 11809abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1181f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 118281c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 118357dacad5SJay Sternberg 118457dacad5SJay Sternberg /* 11859abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11869abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11879abd68efSJens Axboe * URGENT. 11889abd68efSJens Axboe */ 11899abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11909abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11919abd68efSJens Axboe 11929abd68efSJens Axboe /* 119316772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 119457dacad5SJay Sternberg * is attached to the request. 119557dacad5SJay Sternberg */ 119657dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 119757dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 119857dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 119957dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 120057dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 120157dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 120257dacad5SJay Sternberg 12031c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120457dacad5SJay Sternberg } 120557dacad5SJay Sternberg 120657dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 120757dacad5SJay Sternberg { 120857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 120957dacad5SJay Sternberg } 121057dacad5SJay Sternberg 121157dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 121257dacad5SJay Sternberg { 121357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 121457dacad5SJay Sternberg } 121557dacad5SJay Sternberg 12162a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 121757dacad5SJay Sternberg { 1218f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1219f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 122057dacad5SJay Sternberg 122127fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 122227fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1223e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1224e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 122557dacad5SJay Sternberg } 122657dacad5SJay Sternberg 1227b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1228b2a0eb1aSKeith Busch { 1229b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1230b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1231b2a0eb1aSKeith Busch */ 1232b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1233b2a0eb1aSKeith Busch 1234ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1235ad70062cSJianchao Wang switch (dev->ctrl.state) { 1236ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1237ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1238b2a0eb1aSKeith Busch return false; 1239ad70062cSJianchao Wang default: 1240ad70062cSJianchao Wang break; 1241ad70062cSJianchao Wang } 1242b2a0eb1aSKeith Busch 1243b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1244b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1245b2a0eb1aSKeith Busch */ 1246b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1247b2a0eb1aSKeith Busch return false; 1248b2a0eb1aSKeith Busch 1249b2a0eb1aSKeith Busch return true; 1250b2a0eb1aSKeith Busch } 1251b2a0eb1aSKeith Busch 1252b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1253b2a0eb1aSKeith Busch { 1254b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1255b2a0eb1aSKeith Busch u16 pci_status; 1256b2a0eb1aSKeith Busch int result; 1257b2a0eb1aSKeith Busch 1258b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1259b2a0eb1aSKeith Busch &pci_status); 1260b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1261b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1262b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1263b2a0eb1aSKeith Busch csts, pci_status); 1264b2a0eb1aSKeith Busch else 1265b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1266b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1267b2a0eb1aSKeith Busch csts, result); 1268b2a0eb1aSKeith Busch } 1269b2a0eb1aSKeith Busch 127031c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 127157dacad5SJay Sternberg { 1272f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1273f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 127457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 127557dacad5SJay Sternberg struct request *abort_req; 1276f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1277b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1278b2a0eb1aSKeith Busch 1279651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1280651438bbSWen Xiong * the recovery mechanism will surely fail. 1281651438bbSWen Xiong */ 1282651438bbSWen Xiong mb(); 1283651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1284651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1285651438bbSWen Xiong 1286b2a0eb1aSKeith Busch /* 1287b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1288b2a0eb1aSKeith Busch */ 1289b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1290b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1291b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1292d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1293db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1294b2a0eb1aSKeith Busch } 129557dacad5SJay Sternberg 129631c7c7d2SChristoph Hellwig /* 12977776db1cSKeith Busch * Did we miss an interrupt? 12987776db1cSKeith Busch */ 1299fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13005a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1301fa059b85SKeith Busch else 1302bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1303fa059b85SKeith Busch 1304bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 13057776db1cSKeith Busch dev_warn(dev->ctrl.device, 13067776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13077776db1cSKeith Busch req->tag, nvmeq->qid); 1308db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13097776db1cSKeith Busch } 13107776db1cSKeith Busch 13117776db1cSKeith Busch /* 1312fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1313fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1314fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1315db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1316fd634f41SChristoph Hellwig */ 13174244140dSKeith Busch switch (dev->ctrl.state) { 13184244140dSKeith Busch case NVME_CTRL_CONNECTING: 13192036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1320df561f66SGustavo A. R. Silva fallthrough; 13212036f726SKeith Busch case NVME_CTRL_DELETING: 1322b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1323fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1324fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 132527fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13267ad92f65STong Zhang nvme_dev_disable(dev, true); 1327db8c48e4SChristoph Hellwig return BLK_EH_DONE; 132839a9dd81SKeith Busch case NVME_CTRL_RESETTING: 132939a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13304244140dSKeith Busch default: 13314244140dSKeith Busch break; 1332fd634f41SChristoph Hellwig } 1333fd634f41SChristoph Hellwig 1334fd634f41SChristoph Hellwig /* 1335e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1336e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1337e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 133831c7c7d2SChristoph Hellwig */ 1339f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13401b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 134157dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 134257dacad5SJay Sternberg req->tag, nvmeq->qid); 13437ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1344a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1345d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1346e1569a16SKeith Busch 1347db8c48e4SChristoph Hellwig return BLK_EH_DONE; 134857dacad5SJay Sternberg } 134957dacad5SJay Sternberg 1350e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1351e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1352e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1353e7a2a87dSChristoph Hellwig } 13547bf7d778SKeith Busch iod->aborted = 1; 135557dacad5SJay Sternberg 135657dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 135785f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 135857dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 135957dacad5SJay Sternberg 13601b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13611b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 136257dacad5SJay Sternberg req->tag, nvmeq->qid); 1363e7a2a87dSChristoph Hellwig 1364e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 136539dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 13666bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13676bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 136831c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 136957dacad5SJay Sternberg } 137057dacad5SJay Sternberg 1371e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1372b84ba30bSChristoph Hellwig blk_execute_rq_nowait(abort_req, false, abort_endio); 137357dacad5SJay Sternberg 137457dacad5SJay Sternberg /* 137557dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 137657dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 137757dacad5SJay Sternberg * as the device then is in a faulty state. 137857dacad5SJay Sternberg */ 137957dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 138057dacad5SJay Sternberg } 138157dacad5SJay Sternberg 138257dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 138357dacad5SJay Sternberg { 13848a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 138557dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 138663223078SChristoph Hellwig if (!nvmeq->sq_cmds) 138763223078SChristoph Hellwig return; 13880f238ff5SLogan Gunthorpe 138963223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 139088a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13918a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 139263223078SChristoph Hellwig } else { 13938a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 139463223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13950f238ff5SLogan Gunthorpe } 139657dacad5SJay Sternberg } 139757dacad5SJay Sternberg 139857dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 139957dacad5SJay Sternberg { 140057dacad5SJay Sternberg int i; 140157dacad5SJay Sternberg 1402d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1403d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1404147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 140557dacad5SJay Sternberg } 140657dacad5SJay Sternberg } 140757dacad5SJay Sternberg 140857dacad5SJay Sternberg /** 140957dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 141040581d1aSBart Van Assche * @nvmeq: queue to suspend 141157dacad5SJay Sternberg */ 141257dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 141357dacad5SJay Sternberg { 14144e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 141557dacad5SJay Sternberg return 1; 141657dacad5SJay Sternberg 14174e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1418d1f06f4aSJens Axboe mb(); 141957dacad5SJay Sternberg 14204e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14211c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 14226ca1d902SMing Lei nvme_stop_admin_queue(&nvmeq->dev->ctrl); 14237c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14244e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 142557dacad5SJay Sternberg return 0; 142657dacad5SJay Sternberg } 142757dacad5SJay Sternberg 14288fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14298fae268bSKeith Busch { 14308fae268bSKeith Busch int i; 14318fae268bSKeith Busch 14328fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14338fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14348fae268bSKeith Busch } 14358fae268bSKeith Busch 1436a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 143757dacad5SJay Sternberg { 1438147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 143957dacad5SJay Sternberg 1440a5cdb68cSKeith Busch if (shutdown) 1441a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1442a5cdb68cSKeith Busch else 1443b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 144457dacad5SJay Sternberg 1445bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 144657dacad5SJay Sternberg } 144757dacad5SJay Sternberg 1448fa46c6fbSKeith Busch /* 1449fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 14509210c075SDongli Zhang * that can check this device's completion queues have synced, except 14519210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 14529210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1453fa46c6fbSKeith Busch */ 1454fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1455fa46c6fbSKeith Busch { 1456fa46c6fbSKeith Busch int i; 1457fa46c6fbSKeith Busch 14589210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 14599210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1460c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 14619210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 14629210c075SDongli Zhang } 1463fa46c6fbSKeith Busch } 1464fa46c6fbSKeith Busch 146557dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 146657dacad5SJay Sternberg int entry_size) 146757dacad5SJay Sternberg { 146857dacad5SJay Sternberg int q_depth = dev->q_depth; 14695fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14706c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 147157dacad5SJay Sternberg 147257dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 147357dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14744e523547SBaolin Wang 14756c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 147657dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 147757dacad5SJay Sternberg 147857dacad5SJay Sternberg /* 147957dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 148057dacad5SJay Sternberg * would be better to map queues in system memory with the 148157dacad5SJay Sternberg * original depth 148257dacad5SJay Sternberg */ 148357dacad5SJay Sternberg if (q_depth < 64) 148457dacad5SJay Sternberg return -ENOMEM; 148557dacad5SJay Sternberg } 148657dacad5SJay Sternberg 148757dacad5SJay Sternberg return q_depth; 148857dacad5SJay Sternberg } 148957dacad5SJay Sternberg 149057dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14918a1d09a6SBenjamin Herrenschmidt int qid) 149257dacad5SJay Sternberg { 14930f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1494815c6704SKeith Busch 14950f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14968a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1497bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14980f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14990f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 150063223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 150163223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 150263223078SChristoph Hellwig return 0; 150363223078SChristoph Hellwig } 1504bfac8e9fSAlan Mikhak 15058a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1506bfac8e9fSAlan Mikhak } 15070f238ff5SLogan Gunthorpe } 15080f238ff5SLogan Gunthorpe 15098a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 151057dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 151157dacad5SJay Sternberg if (!nvmeq->sq_cmds) 151257dacad5SJay Sternberg return -ENOMEM; 151357dacad5SJay Sternberg return 0; 151457dacad5SJay Sternberg } 151557dacad5SJay Sternberg 1516a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 151757dacad5SJay Sternberg { 1518147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 151957dacad5SJay Sternberg 152062314e40SKeith Busch if (dev->ctrl.queue_count > qid) 152162314e40SKeith Busch return 0; 152257dacad5SJay Sternberg 1523c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15248a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15258a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 152657dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 152757dacad5SJay Sternberg if (!nvmeq->cqes) 152857dacad5SJay Sternberg goto free_nvmeq; 152957dacad5SJay Sternberg 15308a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 153157dacad5SJay Sternberg goto free_cqdma; 153257dacad5SJay Sternberg 153357dacad5SJay Sternberg nvmeq->dev = dev; 15341ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15353a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 153657dacad5SJay Sternberg nvmeq->cq_head = 0; 153757dacad5SJay Sternberg nvmeq->cq_phase = 1; 153857dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 153957dacad5SJay Sternberg nvmeq->qid = qid; 1540d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 154157dacad5SJay Sternberg 1542147b27e4SSagi Grimberg return 0; 154357dacad5SJay Sternberg 154457dacad5SJay Sternberg free_cqdma: 15458a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 154657dacad5SJay Sternberg nvmeq->cq_dma_addr); 154757dacad5SJay Sternberg free_nvmeq: 1548147b27e4SSagi Grimberg return -ENOMEM; 154957dacad5SJay Sternberg } 155057dacad5SJay Sternberg 1551dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 155257dacad5SJay Sternberg { 15530ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15540ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15550ff199cbSChristoph Hellwig 15560ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15570ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15580ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15590ff199cbSChristoph Hellwig } else { 15600ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15610ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15620ff199cbSChristoph Hellwig } 156357dacad5SJay Sternberg } 156457dacad5SJay Sternberg 156557dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 156657dacad5SJay Sternberg { 156757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 156857dacad5SJay Sternberg 156957dacad5SJay Sternberg nvmeq->sq_tail = 0; 157038210800SKeith Busch nvmeq->last_sq_tail = 0; 157157dacad5SJay Sternberg nvmeq->cq_head = 0; 157257dacad5SJay Sternberg nvmeq->cq_phase = 1; 157357dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15748a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1575f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 157657dacad5SJay Sternberg dev->online_queues++; 15773a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 157857dacad5SJay Sternberg } 157957dacad5SJay Sternberg 1580e4b9852aSCasey Chen /* 1581e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1582e4b9852aSCasey Chen */ 1583e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1584e4b9852aSCasey Chen { 1585e4b9852aSCasey Chen /* 1586e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1587e4b9852aSCasey Chen */ 1588e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1589e4b9852aSCasey Chen return -ENODEV; 1590e4b9852aSCasey Chen 1591e4b9852aSCasey Chen /* 1592e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1593e4b9852aSCasey Chen */ 1594e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1595e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1596e4b9852aSCasey Chen return -ENODEV; 1597e4b9852aSCasey Chen } 1598e4b9852aSCasey Chen 1599e4b9852aSCasey Chen return 0; 1600e4b9852aSCasey Chen } 1601e4b9852aSCasey Chen 16024b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 160357dacad5SJay Sternberg { 160457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 160557dacad5SJay Sternberg int result; 16067c349ddeSKeith Busch u16 vector = 0; 160757dacad5SJay Sternberg 1608d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1609d1ed6aa1SChristoph Hellwig 161022b55601SKeith Busch /* 161122b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 161222b55601SKeith Busch * has only one vector available. 161322b55601SKeith Busch */ 16144b04cc6aSJens Axboe if (!polled) 1615a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16164b04cc6aSJens Axboe else 16177c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16184b04cc6aSJens Axboe 1619a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1620ded45505SKeith Busch if (result) 1621ded45505SKeith Busch return result; 162257dacad5SJay Sternberg 162357dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 162457dacad5SJay Sternberg if (result < 0) 1625ded45505SKeith Busch return result; 1626c80b36cdSEdmund Nadolski if (result) 162757dacad5SJay Sternberg goto release_cq; 162857dacad5SJay Sternberg 1629a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16304b04cc6aSJens Axboe 1631e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1632e4b9852aSCasey Chen if (result) 1633e4b9852aSCasey Chen return result; 1634e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 16357c349ddeSKeith Busch if (!polled) { 1636dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 163757dacad5SJay Sternberg if (result < 0) 163857dacad5SJay Sternberg goto release_sq; 16394b04cc6aSJens Axboe } 164057dacad5SJay Sternberg 16414e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1642e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 164357dacad5SJay Sternberg return result; 164457dacad5SJay Sternberg 164557dacad5SJay Sternberg release_sq: 1646f25a2dfcSJianchao Wang dev->online_queues--; 1647e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 164857dacad5SJay Sternberg adapter_delete_sq(dev, qid); 164957dacad5SJay Sternberg release_cq: 165057dacad5SJay Sternberg adapter_delete_cq(dev, qid); 165157dacad5SJay Sternberg return result; 165257dacad5SJay Sternberg } 165357dacad5SJay Sternberg 1654f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 165557dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 165677f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 165757dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 16580350815aSChristoph Hellwig .init_request = nvme_init_request, 165957dacad5SJay Sternberg .timeout = nvme_timeout, 166057dacad5SJay Sternberg }; 166157dacad5SJay Sternberg 1662f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1663376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1664376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1665376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1666376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1667376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1668376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1669376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1670c6d962aeSChristoph Hellwig .poll = nvme_poll, 1671dabcefabSJens Axboe }; 1672dabcefabSJens Axboe 167357dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 167457dacad5SJay Sternberg { 16751c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 167669d9a99cSKeith Busch /* 167769d9a99cSKeith Busch * If the controller was reset during removal, it's possible 167869d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 167969d9a99cSKeith Busch * queue to flush these to completion. 168069d9a99cSKeith Busch */ 16816ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 16821c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 168357dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 168457dacad5SJay Sternberg } 168557dacad5SJay Sternberg } 168657dacad5SJay Sternberg 168757dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 168857dacad5SJay Sternberg { 16891c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 169057dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 169157dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1692e3e9d50cSKeith Busch 169338dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1694dc96f938SChaitanya Kulkarni dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; 1695d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1696d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1697d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 169857dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 169957dacad5SJay Sternberg 170057dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 170157dacad5SJay Sternberg return -ENOMEM; 170234b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 170357dacad5SJay Sternberg 17041c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 17051c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 170657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 170757dacad5SJay Sternberg return -ENOMEM; 170857dacad5SJay Sternberg } 17091c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 171057dacad5SJay Sternberg nvme_dev_remove_admin(dev); 17111c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 171257dacad5SJay Sternberg return -ENODEV; 171357dacad5SJay Sternberg } 171457dacad5SJay Sternberg } else 17156ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 171657dacad5SJay Sternberg 171757dacad5SJay Sternberg return 0; 171857dacad5SJay Sternberg } 171957dacad5SJay Sternberg 172097f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 172197f6ef64SXu Yu { 172297f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 172397f6ef64SXu Yu } 172497f6ef64SXu Yu 172597f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 172697f6ef64SXu Yu { 172797f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 172897f6ef64SXu Yu 172997f6ef64SXu Yu if (size <= dev->bar_mapped_size) 173097f6ef64SXu Yu return 0; 173197f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 173297f6ef64SXu Yu return -ENOMEM; 173397f6ef64SXu Yu if (dev->bar) 173497f6ef64SXu Yu iounmap(dev->bar); 173597f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 173697f6ef64SXu Yu if (!dev->bar) { 173797f6ef64SXu Yu dev->bar_mapped_size = 0; 173897f6ef64SXu Yu return -ENOMEM; 173997f6ef64SXu Yu } 174097f6ef64SXu Yu dev->bar_mapped_size = size; 174197f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 174297f6ef64SXu Yu 174397f6ef64SXu Yu return 0; 174497f6ef64SXu Yu } 174597f6ef64SXu Yu 174601ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 174757dacad5SJay Sternberg { 174857dacad5SJay Sternberg int result; 174957dacad5SJay Sternberg u32 aqa; 175057dacad5SJay Sternberg struct nvme_queue *nvmeq; 175157dacad5SJay Sternberg 175297f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 175397f6ef64SXu Yu if (result < 0) 175497f6ef64SXu Yu return result; 175597f6ef64SXu Yu 17568ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 175720d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 175857dacad5SJay Sternberg 17597a67cbeaSChristoph Hellwig if (dev->subsystem && 17607a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17617a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 176257dacad5SJay Sternberg 1763b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 176457dacad5SJay Sternberg if (result < 0) 176557dacad5SJay Sternberg return result; 176657dacad5SJay Sternberg 1767a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1768147b27e4SSagi Grimberg if (result) 1769147b27e4SSagi Grimberg return result; 177057dacad5SJay Sternberg 1771635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1772635333e4SMax Gurtovoy 1773147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 177457dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 177557dacad5SJay Sternberg aqa |= aqa << 16; 177657dacad5SJay Sternberg 17777a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17787a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17797a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 178057dacad5SJay Sternberg 1781c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 178257dacad5SJay Sternberg if (result) 1783d4875622SKeith Busch return result; 178457dacad5SJay Sternberg 178557dacad5SJay Sternberg nvmeq->cq_vector = 0; 1786161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1787dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 178857dacad5SJay Sternberg if (result) { 17897c349ddeSKeith Busch dev->online_queues--; 1790d4875622SKeith Busch return result; 179157dacad5SJay Sternberg } 179257dacad5SJay Sternberg 17934e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 179457dacad5SJay Sternberg return result; 179557dacad5SJay Sternberg } 179657dacad5SJay Sternberg 1797749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 179857dacad5SJay Sternberg { 17994b04cc6aSJens Axboe unsigned i, max, rw_queues; 1800749941f2SChristoph Hellwig int ret = 0; 180157dacad5SJay Sternberg 1802d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1803a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1804749941f2SChristoph Hellwig ret = -ENOMEM; 180557dacad5SJay Sternberg break; 1806749941f2SChristoph Hellwig } 1807749941f2SChristoph Hellwig } 180857dacad5SJay Sternberg 1809d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1810e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1811e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1812e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 18134b04cc6aSJens Axboe } else { 18144b04cc6aSJens Axboe rw_queues = max; 18154b04cc6aSJens Axboe } 18164b04cc6aSJens Axboe 1817949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 18184b04cc6aSJens Axboe bool polled = i > rw_queues; 18194b04cc6aSJens Axboe 18204b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1821d4875622SKeith Busch if (ret) 182257dacad5SJay Sternberg break; 182357dacad5SJay Sternberg } 182457dacad5SJay Sternberg 1825749941f2SChristoph Hellwig /* 1826749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18278adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18288adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1829749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1830749941f2SChristoph Hellwig */ 1831749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 183257dacad5SJay Sternberg } 183357dacad5SJay Sternberg 183488de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 183557dacad5SJay Sternberg { 183688de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 183788de4598SChristoph Hellwig 183888de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 183988de4598SChristoph Hellwig } 184088de4598SChristoph Hellwig 184188de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 184288de4598SChristoph Hellwig { 184388de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 184488de4598SChristoph Hellwig } 184588de4598SChristoph Hellwig 1846f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 184757dacad5SJay Sternberg { 184888de4598SChristoph Hellwig u64 size, offset; 184957dacad5SJay Sternberg resource_size_t bar_size; 185057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 18518969f1f8SChristoph Hellwig int bar; 185257dacad5SJay Sternberg 18539fe5c59fSKeith Busch if (dev->cmb_size) 18549fe5c59fSKeith Busch return; 18559fe5c59fSKeith Busch 185620d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 185720d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 185820d3bb92SKlaus Jensen 18597a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1860f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1861f65efd6dSChristoph Hellwig return; 1862202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 186357dacad5SJay Sternberg 186488de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 186588de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18668969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18678969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 186857dacad5SJay Sternberg 186957dacad5SJay Sternberg if (offset > bar_size) 1870f65efd6dSChristoph Hellwig return; 187157dacad5SJay Sternberg 187257dacad5SJay Sternberg /* 187320d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 187420d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 187520d3bb92SKlaus Jensen */ 187620d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 187720d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 187820d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 187920d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 188020d3bb92SKlaus Jensen } 188120d3bb92SKlaus Jensen 188220d3bb92SKlaus Jensen /* 188357dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 188457dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 188557dacad5SJay Sternberg * the reported size of the BAR 188657dacad5SJay Sternberg */ 188757dacad5SJay Sternberg if (size > bar_size - offset) 188857dacad5SJay Sternberg size = bar_size - offset; 188957dacad5SJay Sternberg 18900f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18910f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18920f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1893f65efd6dSChristoph Hellwig return; 18940f238ff5SLogan Gunthorpe } 18950f238ff5SLogan Gunthorpe 189657dacad5SJay Sternberg dev->cmb_size = size; 18970f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18980f238ff5SLogan Gunthorpe 18990f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 19000f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 19010f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 190257dacad5SJay Sternberg } 190357dacad5SJay Sternberg 190487ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 190557dacad5SJay Sternberg { 19066c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19074033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1908f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 190987ad72a5SChristoph Hellwig int ret; 191087ad72a5SChristoph Hellwig 191187ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 191287ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 191387ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19146c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 191587ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 191687ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 191787ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 191887ad72a5SChristoph Hellwig 191987ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 192087ad72a5SChristoph Hellwig if (ret) { 192187ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 192287ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 192387ad72a5SChristoph Hellwig ret, bits); 1924a5df5e79SKeith Busch } else 1925a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1926a5df5e79SKeith Busch 192787ad72a5SChristoph Hellwig return ret; 192887ad72a5SChristoph Hellwig } 192987ad72a5SChristoph Hellwig 193087ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 193187ad72a5SChristoph Hellwig { 193287ad72a5SChristoph Hellwig int i; 193387ad72a5SChristoph Hellwig 193487ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 193587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19366c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 193787ad72a5SChristoph Hellwig 1938cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1939cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1940cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 194187ad72a5SChristoph Hellwig } 194287ad72a5SChristoph Hellwig 194387ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 194487ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19454033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 19464033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 19474033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 194887ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 19497e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 195087ad72a5SChristoph Hellwig } 195187ad72a5SChristoph Hellwig 195292dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 195392dc6895SChristoph Hellwig u32 chunk_size) 195487ad72a5SChristoph Hellwig { 195587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 195692dc6895SChristoph Hellwig u32 max_entries, len; 19574033f35dSChristoph Hellwig dma_addr_t descs_dma; 19582ee0e4edSDan Carpenter int i = 0; 195987ad72a5SChristoph Hellwig void **bufs; 19606fbcde66SMinwoo Im u64 size, tmp; 196187ad72a5SChristoph Hellwig 196287ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 196387ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 196487ad72a5SChristoph Hellwig max_entries = tmp; 1965044a9df1SChristoph Hellwig 1966044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1967044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1968044a9df1SChristoph Hellwig 1969750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19704033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 197187ad72a5SChristoph Hellwig if (!descs) 197287ad72a5SChristoph Hellwig goto out; 197387ad72a5SChristoph Hellwig 197487ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 197587ad72a5SChristoph Hellwig if (!bufs) 197687ad72a5SChristoph Hellwig goto out_free_descs; 197787ad72a5SChristoph Hellwig 1978244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 197987ad72a5SChristoph Hellwig dma_addr_t dma_addr; 198087ad72a5SChristoph Hellwig 198150cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 198287ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 198387ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 198487ad72a5SChristoph Hellwig if (!bufs[i]) 198587ad72a5SChristoph Hellwig break; 198687ad72a5SChristoph Hellwig 198787ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 19886c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 198987ad72a5SChristoph Hellwig i++; 199087ad72a5SChristoph Hellwig } 199187ad72a5SChristoph Hellwig 199292dc6895SChristoph Hellwig if (!size) 199387ad72a5SChristoph Hellwig goto out_free_bufs; 199487ad72a5SChristoph Hellwig 199587ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 199687ad72a5SChristoph Hellwig dev->host_mem_size = size; 199787ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19984033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 199987ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 200087ad72a5SChristoph Hellwig return 0; 200187ad72a5SChristoph Hellwig 200287ad72a5SChristoph Hellwig out_free_bufs: 200387ad72a5SChristoph Hellwig while (--i >= 0) { 20046c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 200587ad72a5SChristoph Hellwig 2006cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2007cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2008cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 200987ad72a5SChristoph Hellwig } 201087ad72a5SChristoph Hellwig 201187ad72a5SChristoph Hellwig kfree(bufs); 201287ad72a5SChristoph Hellwig out_free_descs: 20134033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20144033f35dSChristoph Hellwig descs_dma); 201587ad72a5SChristoph Hellwig out: 201687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 201787ad72a5SChristoph Hellwig return -ENOMEM; 201887ad72a5SChristoph Hellwig } 201987ad72a5SChristoph Hellwig 202092dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 202192dc6895SChristoph Hellwig { 20229dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20239dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20249dc54a0dSChaitanya Kulkarni u64 chunk_size; 202592dc6895SChristoph Hellwig 202692dc6895SChristoph Hellwig /* start big and work our way down */ 20279dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 202892dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 202992dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 203092dc6895SChristoph Hellwig return 0; 203192dc6895SChristoph Hellwig nvme_free_host_mem(dev); 203292dc6895SChristoph Hellwig } 203392dc6895SChristoph Hellwig } 203492dc6895SChristoph Hellwig 203592dc6895SChristoph Hellwig return -ENOMEM; 203692dc6895SChristoph Hellwig } 203792dc6895SChristoph Hellwig 20389620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 203987ad72a5SChristoph Hellwig { 204087ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 204187ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 204287ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 204387ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20446fbcde66SMinwoo Im int ret; 204587ad72a5SChristoph Hellwig 204687ad72a5SChristoph Hellwig preferred = min(preferred, max); 204787ad72a5SChristoph Hellwig if (min > max) { 204887ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 204987ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 205087ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 205187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20529620cfbaSChristoph Hellwig return 0; 205387ad72a5SChristoph Hellwig } 205487ad72a5SChristoph Hellwig 205587ad72a5SChristoph Hellwig /* 205687ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 205787ad72a5SChristoph Hellwig */ 205887ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 205987ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 206087ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 206187ad72a5SChristoph Hellwig else 206287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 206387ad72a5SChristoph Hellwig } 206487ad72a5SChristoph Hellwig 206587ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 206692dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 206792dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 206892dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20699620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 207087ad72a5SChristoph Hellwig } 207187ad72a5SChristoph Hellwig 207292dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 207392dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 207492dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 207592dc6895SChristoph Hellwig } 207692dc6895SChristoph Hellwig 20779620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20789620cfbaSChristoph Hellwig if (ret) 207987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20809620cfbaSChristoph Hellwig return ret; 208157dacad5SJay Sternberg } 208257dacad5SJay Sternberg 20830521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 20840521905eSKeith Busch char *buf) 20850521905eSKeith Busch { 20860521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20870521905eSKeith Busch 20880521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 20890521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 20900521905eSKeith Busch } 20910521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 20920521905eSKeith Busch 20931751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 20941751e97aSKeith Busch char *buf) 20951751e97aSKeith Busch { 20961751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20971751e97aSKeith Busch 20981751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 20991751e97aSKeith Busch } 21001751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 21011751e97aSKeith Busch 21021751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 21031751e97aSKeith Busch char *buf) 21041751e97aSKeith Busch { 21051751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21061751e97aSKeith Busch 21071751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 21081751e97aSKeith Busch } 21091751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 21101751e97aSKeith Busch 2111a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2112a5df5e79SKeith Busch char *buf) 2113a5df5e79SKeith Busch { 2114a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2115a5df5e79SKeith Busch 2116a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2117a5df5e79SKeith Busch } 2118a5df5e79SKeith Busch 2119a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2120a5df5e79SKeith Busch const char *buf, size_t count) 2121a5df5e79SKeith Busch { 2122a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2123a5df5e79SKeith Busch bool new; 2124a5df5e79SKeith Busch int ret; 2125a5df5e79SKeith Busch 2126a5df5e79SKeith Busch if (strtobool(buf, &new) < 0) 2127a5df5e79SKeith Busch return -EINVAL; 2128a5df5e79SKeith Busch 2129a5df5e79SKeith Busch if (new == ndev->hmb) 2130a5df5e79SKeith Busch return count; 2131a5df5e79SKeith Busch 2132a5df5e79SKeith Busch if (new) { 2133a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2134a5df5e79SKeith Busch } else { 2135a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2136a5df5e79SKeith Busch if (!ret) 2137a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2138a5df5e79SKeith Busch } 2139a5df5e79SKeith Busch 2140a5df5e79SKeith Busch if (ret < 0) 2141a5df5e79SKeith Busch return ret; 2142a5df5e79SKeith Busch 2143a5df5e79SKeith Busch return count; 2144a5df5e79SKeith Busch } 2145a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2146a5df5e79SKeith Busch 21470521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 21480521905eSKeith Busch struct attribute *a, int n) 21490521905eSKeith Busch { 21500521905eSKeith Busch struct nvme_ctrl *ctrl = 21510521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 21520521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 21530521905eSKeith Busch 21541751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 21551751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 21561751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 21571751e97aSKeith Busch if (!dev->cmbsz) 21580521905eSKeith Busch return 0; 21591751e97aSKeith Busch } 2160a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2161a5df5e79SKeith Busch return 0; 2162a5df5e79SKeith Busch 21630521905eSKeith Busch return a->mode; 21640521905eSKeith Busch } 21650521905eSKeith Busch 21660521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 21670521905eSKeith Busch &dev_attr_cmb.attr, 21681751e97aSKeith Busch &dev_attr_cmbloc.attr, 21691751e97aSKeith Busch &dev_attr_cmbsz.attr, 2170a5df5e79SKeith Busch &dev_attr_hmb.attr, 21710521905eSKeith Busch NULL, 21720521905eSKeith Busch }; 21730521905eSKeith Busch 21740521905eSKeith Busch static const struct attribute_group nvme_pci_attr_group = { 21750521905eSKeith Busch .attrs = nvme_pci_attrs, 21760521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 21770521905eSKeith Busch }; 21780521905eSKeith Busch 2179612b7286SMing Lei /* 2180612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2181612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2182612b7286SMing Lei */ 2183612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 21843b6592f7SJens Axboe { 2185612b7286SMing Lei struct nvme_dev *dev = affd->priv; 21862a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2187c45b1fa2SMing Lei 21883b6592f7SJens Axboe /* 2189ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2190612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2191612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2192612b7286SMing Lei * 2193612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2194612b7286SMing Lei * write and read queues. 2195612b7286SMing Lei * 2196612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2197612b7286SMing Lei * queue. 21983b6592f7SJens Axboe */ 2199612b7286SMing Lei if (!nrirqs) { 2200612b7286SMing Lei nrirqs = 1; 2201612b7286SMing Lei nr_read_queues = 0; 22022a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2203612b7286SMing Lei nr_read_queues = 0; 22042a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2205612b7286SMing Lei nr_read_queues = 1; 22063b6592f7SJens Axboe } else { 22072a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22083b6592f7SJens Axboe } 2209612b7286SMing Lei 2210612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2211612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2212612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2213612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2214612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22153b6592f7SJens Axboe } 22163b6592f7SJens Axboe 22176451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22183b6592f7SJens Axboe { 22193b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22203b6592f7SJens Axboe struct irq_affinity affd = { 22213b6592f7SJens Axboe .pre_vectors = 1, 2222612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2223612b7286SMing Lei .priv = dev, 22243b6592f7SJens Axboe }; 222521cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22266451fe73SJens Axboe 22276451fe73SJens Axboe /* 222821cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 222921cc2f3fSJeffle Xu * left over for non-polled I/O. 22306451fe73SJens Axboe */ 223121cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 223221cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 22333b6592f7SJens Axboe 223421cc2f3fSJeffle Xu /* 223521cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 223621cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 223721cc2f3fSJeffle Xu */ 2238612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2239612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 22403b6592f7SJens Axboe 224166341331SBenjamin Herrenschmidt /* 224221cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 224321cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 224421cc2f3fSJeffle Xu * vector. 224566341331SBenjamin Herrenschmidt */ 224666341331SBenjamin Herrenschmidt irq_queues = 1; 224721cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 224821cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2249612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 22503b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 22513b6592f7SJens Axboe } 22523b6592f7SJens Axboe 22538fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 22548fae268bSKeith Busch { 22558fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 22568fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 22578fae268bSKeith Busch } 22588fae268bSKeith Busch 22592a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 22602a5bcfddSWeiping Zhang { 2261e3aef095SNiklas Schnelle /* 2262e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2263e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2264e3aef095SNiklas Schnelle */ 2265e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2266e3aef095SNiklas Schnelle return 1; 22672a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 22682a5bcfddSWeiping Zhang } 22692a5bcfddSWeiping Zhang 227057dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 227157dacad5SJay Sternberg { 2272147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 227357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 22742a5bcfddSWeiping Zhang unsigned int nr_io_queues; 227597f6ef64SXu Yu unsigned long size; 22762a5bcfddSWeiping Zhang int result; 227757dacad5SJay Sternberg 22782a5bcfddSWeiping Zhang /* 22792a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 22802a5bcfddSWeiping Zhang * stable values to work with. 22812a5bcfddSWeiping Zhang */ 22822a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 22832a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2284d38e9f04SBenjamin Herrenschmidt 2285ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 22869a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 22879a0be7abSChristoph Hellwig if (result < 0) 228857dacad5SJay Sternberg return result; 22899a0be7abSChristoph Hellwig 2290f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2291a5229050SKeith Busch return 0; 229257dacad5SJay Sternberg 2293e4b9852aSCasey Chen /* 2294e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2295e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2296e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2297e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2298e4b9852aSCasey Chen * nvme_dev_disable() path. 2299e4b9852aSCasey Chen */ 2300e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2301e4b9852aSCasey Chen if (result) 2302e4b9852aSCasey Chen return result; 2303e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2304e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 23054e224106SChristoph Hellwig 23060f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 230757dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 230857dacad5SJay Sternberg sizeof(struct nvme_command)); 230957dacad5SJay Sternberg if (result > 0) 231057dacad5SJay Sternberg dev->q_depth = result; 231157dacad5SJay Sternberg else 23120f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 231357dacad5SJay Sternberg } 231457dacad5SJay Sternberg 231557dacad5SJay Sternberg do { 231697f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 231797f6ef64SXu Yu result = nvme_remap_bar(dev, size); 231897f6ef64SXu Yu if (!result) 231957dacad5SJay Sternberg break; 2320e4b9852aSCasey Chen if (!--nr_io_queues) { 2321e4b9852aSCasey Chen result = -ENOMEM; 2322e4b9852aSCasey Chen goto out_unlock; 2323e4b9852aSCasey Chen } 232457dacad5SJay Sternberg } while (1); 232557dacad5SJay Sternberg adminq->q_db = dev->dbs; 232657dacad5SJay Sternberg 23278fae268bSKeith Busch retry: 232857dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2329e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23300ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 233157dacad5SJay Sternberg 233257dacad5SJay Sternberg /* 233357dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 233457dacad5SJay Sternberg * setting up the full range we need. 233557dacad5SJay Sternberg */ 2336dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 23373b6592f7SJens Axboe 23383b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2339e4b9852aSCasey Chen if (result <= 0) { 2340e4b9852aSCasey Chen result = -EIO; 2341e4b9852aSCasey Chen goto out_unlock; 2342e4b9852aSCasey Chen } 23433b6592f7SJens Axboe 234422b55601SKeith Busch dev->num_vecs = result; 23454b04cc6aSJens Axboe result = max(result - 1, 1); 2346e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 234757dacad5SJay Sternberg 234857dacad5SJay Sternberg /* 234957dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 235057dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 235157dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 235257dacad5SJay Sternberg * number of interrupts. 235357dacad5SJay Sternberg */ 2354dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 23557c349ddeSKeith Busch if (result) 2356e4b9852aSCasey Chen goto out_unlock; 23574e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2358e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 23598fae268bSKeith Busch 23608fae268bSKeith Busch result = nvme_create_io_queues(dev); 23618fae268bSKeith Busch if (result || dev->online_queues < 2) 23628fae268bSKeith Busch return result; 23638fae268bSKeith Busch 23648fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 23658fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 23668fae268bSKeith Busch nvme_disable_io_queues(dev); 2367e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2368e4b9852aSCasey Chen if (result) 2369e4b9852aSCasey Chen return result; 23708fae268bSKeith Busch nvme_suspend_io_queues(dev); 23718fae268bSKeith Busch goto retry; 23728fae268bSKeith Busch } 23738fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 23748fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 23758fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 23768fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 23778fae268bSKeith Busch return 0; 2378e4b9852aSCasey Chen out_unlock: 2379e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2380e4b9852aSCasey Chen return result; 238157dacad5SJay Sternberg } 238257dacad5SJay Sternberg 23832a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2384db3cbfffSKeith Busch { 2385db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2386db3cbfffSKeith Busch 2387db3cbfffSKeith Busch blk_mq_free_request(req); 2388d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2389db3cbfffSKeith Busch } 2390db3cbfffSKeith Busch 23912a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2392db3cbfffSKeith Busch { 2393db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2394db3cbfffSKeith Busch 2395d1ed6aa1SChristoph Hellwig if (error) 2396d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2397db3cbfffSKeith Busch 2398db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2399db3cbfffSKeith Busch } 2400db3cbfffSKeith Busch 2401db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2402db3cbfffSKeith Busch { 2403db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2404db3cbfffSKeith Busch struct request *req; 2405f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2406db3cbfffSKeith Busch 2407db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2408db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2409db3cbfffSKeith Busch 241039dfe844SChaitanya Kulkarni req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); 2411db3cbfffSKeith Busch if (IS_ERR(req)) 2412db3cbfffSKeith Busch return PTR_ERR(req); 2413db3cbfffSKeith Busch 2414db3cbfffSKeith Busch req->end_io_data = nvmeq; 2415db3cbfffSKeith Busch 2416d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2417b84ba30bSChristoph Hellwig blk_execute_rq_nowait(req, false, opcode == nvme_admin_delete_cq ? 2418db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2419db3cbfffSKeith Busch return 0; 2420db3cbfffSKeith Busch } 2421db3cbfffSKeith Busch 24228fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2423db3cbfffSKeith Busch { 24245271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2425db3cbfffSKeith Busch unsigned long timeout; 2426db3cbfffSKeith Busch 2427db3cbfffSKeith Busch retry: 2428dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 24295271edd4SChristoph Hellwig while (nr_queues > 0) { 24305271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2431db3cbfffSKeith Busch break; 24325271edd4SChristoph Hellwig nr_queues--; 24335271edd4SChristoph Hellwig sent++; 24345271edd4SChristoph Hellwig } 2435d1ed6aa1SChristoph Hellwig while (sent) { 2436d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2437d1ed6aa1SChristoph Hellwig 2438d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 24395271edd4SChristoph Hellwig timeout); 2440db3cbfffSKeith Busch if (timeout == 0) 24415271edd4SChristoph Hellwig return false; 2442d1ed6aa1SChristoph Hellwig 2443d1ed6aa1SChristoph Hellwig sent--; 24445271edd4SChristoph Hellwig if (nr_queues) 2445db3cbfffSKeith Busch goto retry; 2446db3cbfffSKeith Busch } 24475271edd4SChristoph Hellwig return true; 2448db3cbfffSKeith Busch } 2449db3cbfffSKeith Busch 24505d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 245157dacad5SJay Sternberg { 24522b1b7e78SJianchao Wang int ret; 24532b1b7e78SJianchao Wang 24545bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2455c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 245657dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 24578fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2458ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2459ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 246057dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2461d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 246261f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 246361f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2464d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 246557dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 246657dacad5SJay Sternberg dev->tagset.driver_data = dev; 246757dacad5SJay Sternberg 2468d38e9f04SBenjamin Herrenschmidt /* 2469d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2470d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2471d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2472d38e9f04SBenjamin Herrenschmidt */ 2473d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2474d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2475d38e9f04SBenjamin Herrenschmidt 24762b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 24772b1b7e78SJianchao Wang if (ret) { 24782b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 24792b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 24805d02a5c1SKeith Busch return; 24812b1b7e78SJianchao Wang } 24825bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2483949928c1SKeith Busch } else { 2484949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2485949928c1SKeith Busch 2486949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2487949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 248857dacad5SJay Sternberg } 2489949928c1SKeith Busch 2490e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 249157dacad5SJay Sternberg } 249257dacad5SJay Sternberg 2493b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 249457dacad5SJay Sternberg { 2495b00a726aSKeith Busch int result = -ENOMEM; 249657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 24974bdf2603SFilippo Sironi int dma_address_bits = 64; 249857dacad5SJay Sternberg 249957dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 250057dacad5SJay Sternberg return result; 250157dacad5SJay Sternberg 250257dacad5SJay Sternberg pci_set_master(pdev); 250357dacad5SJay Sternberg 25044bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 25054bdf2603SFilippo Sironi dma_address_bits = 48; 25064bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 250757dacad5SJay Sternberg goto disable; 250857dacad5SJay Sternberg 25097a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 251057dacad5SJay Sternberg result = -ENODEV; 2511b00a726aSKeith Busch goto disable; 251257dacad5SJay Sternberg } 251357dacad5SJay Sternberg 251457dacad5SJay Sternberg /* 2515a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2516a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2517a5229050SKeith Busch * adjust this later. 251857dacad5SJay Sternberg */ 2519dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2520dca51e78SChristoph Hellwig if (result < 0) 2521dca51e78SChristoph Hellwig return result; 252257dacad5SJay Sternberg 252320d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 25247a67cbeaSChristoph Hellwig 25257442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2526b27c1e68Sweiping zhang io_queue_depth); 2527aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 252820d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 25297a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 25301f390c1fSStephan Günther 25311f390c1fSStephan Günther /* 253266341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 253366341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 253466341331SBenjamin Herrenschmidt * so we don't bother updating it here. 253566341331SBenjamin Herrenschmidt */ 253666341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 253766341331SBenjamin Herrenschmidt dev->io_sqes = 7; 253866341331SBenjamin Herrenschmidt else 2539c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 25401f390c1fSStephan Günther 25411f390c1fSStephan Günther /* 25421f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 25431f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 25441f390c1fSStephan Günther */ 25451f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 25461f390c1fSStephan Günther dev->q_depth = 2; 25479bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 25489bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 25491f390c1fSStephan Günther dev->q_depth); 2550d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2551d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 255220d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2553d554b5e1SMartin K. Petersen dev->q_depth = 64; 2554d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2555d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 25561f390c1fSStephan Günther } 25571f390c1fSStephan Günther 2558d38e9f04SBenjamin Herrenschmidt /* 2559d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2560d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2561d38e9f04SBenjamin Herrenschmidt */ 2562d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2563d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2564d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2565d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2566d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2567d38e9f04SBenjamin Herrenschmidt } 2568d38e9f04SBenjamin Herrenschmidt 2569d38e9f04SBenjamin Herrenschmidt 2570f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2571202021c1SStephen Bates 2572a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2573a0a3408eSKeith Busch pci_save_state(pdev); 257457dacad5SJay Sternberg return 0; 257557dacad5SJay Sternberg 257657dacad5SJay Sternberg disable: 257757dacad5SJay Sternberg pci_disable_device(pdev); 257857dacad5SJay Sternberg return result; 257957dacad5SJay Sternberg } 258057dacad5SJay Sternberg 258157dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 258257dacad5SJay Sternberg { 2583b00a726aSKeith Busch if (dev->bar) 2584b00a726aSKeith Busch iounmap(dev->bar); 2585a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2586b00a726aSKeith Busch } 2587b00a726aSKeith Busch 2588b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2589b00a726aSKeith Busch { 259057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 259157dacad5SJay Sternberg 2592dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 259357dacad5SJay Sternberg 2594a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2595a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 259657dacad5SJay Sternberg pci_disable_device(pdev); 259757dacad5SJay Sternberg } 2598a0a3408eSKeith Busch } 259957dacad5SJay Sternberg 2600a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 260157dacad5SJay Sternberg { 2602e43269e6SKeith Busch bool dead = true, freeze = false; 2603302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 260457dacad5SJay Sternberg 260577bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2606302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2607302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2608302ad8ccSKeith Busch 2609ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2610e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2611e43269e6SKeith Busch freeze = true; 2612302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2613e43269e6SKeith Busch } 2614302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2615302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 261657dacad5SJay Sternberg } 2617c21377f8SGabriel Krisman Bertazi 2618302ad8ccSKeith Busch /* 2619302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2620302ad8ccSKeith Busch * doing a safe shutdown. 2621302ad8ccSKeith Busch */ 2622e43269e6SKeith Busch if (!dead && shutdown && freeze) 2623302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 262487ad72a5SChristoph Hellwig 26259a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 26269a915a5bSJianchao Wang 262764ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 26288fae268bSKeith Busch nvme_disable_io_queues(dev); 2629a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 263057dacad5SJay Sternberg } 26318fae268bSKeith Busch nvme_suspend_io_queues(dev); 26328fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2633b00a726aSKeith Busch nvme_pci_disable(dev); 2634fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 263557dacad5SJay Sternberg 2636e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2637e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2638622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2639622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2640302ad8ccSKeith Busch 2641302ad8ccSKeith Busch /* 2642302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2643302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2644302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2645302ad8ccSKeith Busch */ 2646c8e9e9b7SKeith Busch if (shutdown) { 2647302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2648c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 26496ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 2650c8e9e9b7SKeith Busch } 265177bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 265257dacad5SJay Sternberg } 265357dacad5SJay Sternberg 2654c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2655c1ac9a4bSKeith Busch { 2656c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2657c1ac9a4bSKeith Busch return -EBUSY; 2658c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2659c1ac9a4bSKeith Busch return 0; 2660c1ac9a4bSKeith Busch } 2661c1ac9a4bSKeith Busch 266257dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 266357dacad5SJay Sternberg { 266457dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2665c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2666c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 266757dacad5SJay Sternberg if (!dev->prp_page_pool) 266857dacad5SJay Sternberg return -ENOMEM; 266957dacad5SJay Sternberg 267057dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 267157dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 267257dacad5SJay Sternberg 256, 256, 0); 267357dacad5SJay Sternberg if (!dev->prp_small_pool) { 267457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 267557dacad5SJay Sternberg return -ENOMEM; 267657dacad5SJay Sternberg } 267757dacad5SJay Sternberg return 0; 267857dacad5SJay Sternberg } 267957dacad5SJay Sternberg 268057dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 268157dacad5SJay Sternberg { 268257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 268357dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 268457dacad5SJay Sternberg } 268557dacad5SJay Sternberg 2686770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2687770597ecSKeith Busch { 2688770597ecSKeith Busch if (dev->tagset.tags) 2689770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2690770597ecSKeith Busch dev->ctrl.tagset = NULL; 2691770597ecSKeith Busch } 2692770597ecSKeith Busch 26931673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 269457dacad5SJay Sternberg { 26951673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 269657dacad5SJay Sternberg 2697f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2698770597ecSKeith Busch nvme_free_tagset(dev); 26991c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 27001c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2701e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2702943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2703253fd4acSIsrael Rukshin put_device(dev->dev); 2704253fd4acSIsrael Rukshin kfree(dev->queues); 270557dacad5SJay Sternberg kfree(dev); 270657dacad5SJay Sternberg } 270757dacad5SJay Sternberg 27087c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2709f58944e2SKeith Busch { 2710c1ac9a4bSKeith Busch /* 2711c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2712c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2713c1ac9a4bSKeith Busch */ 2714c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2715d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 271669d9a99cSKeith Busch nvme_dev_disable(dev, false); 27179f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 271803e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2719f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2720f58944e2SKeith Busch } 2721f58944e2SKeith Busch 2722fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 272357dacad5SJay Sternberg { 2724d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2725d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2726a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2727e71afda4SChaitanya Kulkarni int result; 272857dacad5SJay Sternberg 27297764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 27307764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 27317764656bSZhihao Cheng dev->ctrl.state); 2732e71afda4SChaitanya Kulkarni result = -ENODEV; 2733fd634f41SChristoph Hellwig goto out; 2734e71afda4SChaitanya Kulkarni } 2735fd634f41SChristoph Hellwig 2736fd634f41SChristoph Hellwig /* 2737fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2738fd634f41SChristoph Hellwig * moving on. 2739fd634f41SChristoph Hellwig */ 2740b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2741a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2742d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2743fd634f41SChristoph Hellwig 27445c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2745b00a726aSKeith Busch result = nvme_pci_enable(dev); 274657dacad5SJay Sternberg if (result) 27474726bcf3SKeith Busch goto out_unlock; 274857dacad5SJay Sternberg 274901ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 275057dacad5SJay Sternberg if (result) 27514726bcf3SKeith Busch goto out_unlock; 275257dacad5SJay Sternberg 275357dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 275457dacad5SJay Sternberg if (result) 27554726bcf3SKeith Busch goto out_unlock; 275657dacad5SJay Sternberg 2757943e942eSJens Axboe /* 2758943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2759943e942eSJens Axboe * over a single page. 2760943e942eSJens Axboe */ 27617637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 27627637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2763943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2764a48bc520SChristoph Hellwig 2765a48bc520SChristoph Hellwig /* 2766a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2767a48bc520SChristoph Hellwig */ 2768a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 27693d2d861eSJianxiong Gao dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2770a48bc520SChristoph Hellwig 27715c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 27725c959d73SKeith Busch 27735c959d73SKeith Busch /* 27745c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 27755c959d73SKeith Busch * initializing procedure here. 27765c959d73SKeith Busch */ 27775c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 27785c959d73SKeith Busch dev_warn(dev->ctrl.device, 27795c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2780cee6c269SMinwoo Im result = -EBUSY; 27815c959d73SKeith Busch goto out; 27825c959d73SKeith Busch } 2783943e942eSJens Axboe 278495093350SMax Gurtovoy /* 278595093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 278695093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 278795093350SMax Gurtovoy */ 278895093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 278995093350SMax Gurtovoy 2790f21c4769SChaitanya Kulkarni result = nvme_init_ctrl_finish(&dev->ctrl); 2791ce4541f4SChristoph Hellwig if (result) 2792f58944e2SKeith Busch goto out; 2793ce4541f4SChristoph Hellwig 2794e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2795e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 27964f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 27974f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2798e286bcfcSScott Bauer else if (was_suspend) 27994f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2800e286bcfcSScott Bauer } else { 2801e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2802e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2803e286bcfcSScott Bauer } 2804a98e58e5SScott Bauer 2805f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2806f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2807f9f38e33SHelen Koike if (result) 2808f9f38e33SHelen Koike dev_warn(dev->dev, 2809f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2810f9f38e33SHelen Koike } 2811f9f38e33SHelen Koike 28129620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 28139620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 28149620cfbaSChristoph Hellwig if (result < 0) 28159620cfbaSChristoph Hellwig goto out; 28169620cfbaSChristoph Hellwig } 281787ad72a5SChristoph Hellwig 281857dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 281957dacad5SJay Sternberg if (result) 2820f58944e2SKeith Busch goto out; 282157dacad5SJay Sternberg 282221f033f7SKeith Busch /* 282357dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 282457dacad5SJay Sternberg * any working I/O queue. 282557dacad5SJay Sternberg */ 282657dacad5SJay Sternberg if (dev->online_queues < 2) { 28271b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 28283b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 28295bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2830770597ecSKeith Busch nvme_free_tagset(dev); 283157dacad5SJay Sternberg } else { 283225646264SKeith Busch nvme_start_queues(&dev->ctrl); 2833302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 28345d02a5c1SKeith Busch nvme_dev_add(dev); 2835302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 283657dacad5SJay Sternberg } 283757dacad5SJay Sternberg 28382b1b7e78SJianchao Wang /* 28392b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 28402b1b7e78SJianchao Wang * recovery. 28412b1b7e78SJianchao Wang */ 28425d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 28432b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 28445d02a5c1SKeith Busch "failed to mark controller live state\n"); 2845e71afda4SChaitanya Kulkarni result = -ENODEV; 2846bb8d261eSChristoph Hellwig goto out; 2847bb8d261eSChristoph Hellwig } 284892911a55SChristoph Hellwig 28490521905eSKeith Busch if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, 28500521905eSKeith Busch &nvme_pci_attr_group)) 28510521905eSKeith Busch dev->attrs_added = true; 28520521905eSKeith Busch 2853d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 285457dacad5SJay Sternberg return; 285557dacad5SJay Sternberg 28564726bcf3SKeith Busch out_unlock: 28574726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 285857dacad5SJay Sternberg out: 28597c1ce408SChaitanya Kulkarni if (result) 28607c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 28617c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 28627c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 286357dacad5SJay Sternberg } 286457dacad5SJay Sternberg 28655c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 286657dacad5SJay Sternberg { 28675c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 286857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 286957dacad5SJay Sternberg 287057dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2871921920abSKeith Busch device_release_driver(&pdev->dev); 28721673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 287357dacad5SJay Sternberg } 287457dacad5SJay Sternberg 28751c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 287657dacad5SJay Sternberg { 28771c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 28781c63dc66SChristoph Hellwig return 0; 287957dacad5SJay Sternberg } 28801c63dc66SChristoph Hellwig 28815fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 28825fd4ce1bSChristoph Hellwig { 28835fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 28845fd4ce1bSChristoph Hellwig return 0; 28855fd4ce1bSChristoph Hellwig } 28865fd4ce1bSChristoph Hellwig 28877fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 28887fd8930fSChristoph Hellwig { 28893a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 28907fd8930fSChristoph Hellwig return 0; 28917fd8930fSChristoph Hellwig } 28927fd8930fSChristoph Hellwig 289397c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 289497c12223SKeith Busch { 289597c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 289697c12223SKeith Busch 28972db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 289897c12223SKeith Busch } 289997c12223SKeith Busch 29001c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 29011a353d85SMing Lin .name = "pcie", 2902e439bb12SSagi Grimberg .module = THIS_MODULE, 2903e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2904e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 29051c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 29065fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 29077fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 29081673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2909f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 291097c12223SKeith Busch .get_address = nvme_pci_get_address, 29111c63dc66SChristoph Hellwig }; 291257dacad5SJay Sternberg 2913b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2914b00a726aSKeith Busch { 2915b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2916b00a726aSKeith Busch 2917a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2918b00a726aSKeith Busch return -ENODEV; 2919b00a726aSKeith Busch 292097f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2921b00a726aSKeith Busch goto release; 2922b00a726aSKeith Busch 2923b00a726aSKeith Busch return 0; 2924b00a726aSKeith Busch release: 2925a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2926b00a726aSKeith Busch return -ENODEV; 2927b00a726aSKeith Busch } 2928b00a726aSKeith Busch 29298427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2930ff5350a8SAndy Lutomirski { 2931ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2932ff5350a8SAndy Lutomirski /* 2933ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2934ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2935ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2936ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2937ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2938ff5350a8SAndy Lutomirski * laptops. 2939ff5350a8SAndy Lutomirski */ 2940ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2941ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2942ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2943ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 29448427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 29458427bbc2SKai-Heng Feng /* 29468427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2947467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2948467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2949467c77d4SJarosław Janik * ASUS PRIME Z370-A 29508427bbc2SKai-Heng Feng */ 29518427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2952467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2953467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 29548427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 29551fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 29561fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 29571fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 29581fae37acSShyjumon N /* 29591fae37acSShyjumon N * Forcing to use host managed nvme power settings for 29601fae37acSShyjumon N * lowest idle power with quick resume latency on 29611fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 29621fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 29631fae37acSShyjumon N */ 29641fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 29651fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 29661fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2967ff5350a8SAndy Lutomirski } 2968ff5350a8SAndy Lutomirski 2969ff5350a8SAndy Lutomirski return 0; 2970ff5350a8SAndy Lutomirski } 2971ff5350a8SAndy Lutomirski 297218119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 297318119775SKeith Busch { 297418119775SKeith Busch struct nvme_dev *dev = data; 297580f513b5SKeith Busch 2976bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 297718119775SKeith Busch flush_work(&dev->ctrl.scan_work); 297880f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 297918119775SKeith Busch } 298018119775SKeith Busch 298157dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 298257dacad5SJay Sternberg { 298357dacad5SJay Sternberg int node, result = -ENOMEM; 298457dacad5SJay Sternberg struct nvme_dev *dev; 2985ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2986943e942eSJens Axboe size_t alloc_size; 298757dacad5SJay Sternberg 298857dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 298957dacad5SJay Sternberg if (node == NUMA_NO_NODE) 29902fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 299157dacad5SJay Sternberg 299257dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 299357dacad5SJay Sternberg if (!dev) 299457dacad5SJay Sternberg return -ENOMEM; 2995147b27e4SSagi Grimberg 29962a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 29972a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 29982a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 29992a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 30002a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 300157dacad5SJay Sternberg if (!dev->queues) 300257dacad5SJay Sternberg goto free; 300357dacad5SJay Sternberg 300457dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 300557dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 300657dacad5SJay Sternberg 3007b00a726aSKeith Busch result = nvme_dev_map(dev); 3008b00a726aSKeith Busch if (result) 3009b00c9b7aSChristophe JAILLET goto put_pci; 3010b00a726aSKeith Busch 3011d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 30125c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 301377bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 3014f3ca80fcSChristoph Hellwig 3015f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 3016f3ca80fcSChristoph Hellwig if (result) 3017b00c9b7aSChristophe JAILLET goto unmap; 3018f3ca80fcSChristoph Hellwig 30198427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 3020ff5350a8SAndy Lutomirski 30212744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3022df4f9bc4SDavid E. Box /* 3023df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3024df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3025df4f9bc4SDavid E. Box */ 3026df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3027df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3028df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3029df4f9bc4SDavid E. Box } 3030df4f9bc4SDavid E. Box 3031943e942eSJens Axboe /* 3032943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 3033943e942eSJens Axboe * command we support. 3034943e942eSJens Axboe */ 3035b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 3036943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 3037943e942eSJens Axboe 3038943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 3039943e942eSJens Axboe mempool_kfree, 3040943e942eSJens Axboe (void *) alloc_size, 3041943e942eSJens Axboe GFP_KERNEL, node); 3042943e942eSJens Axboe if (!dev->iod_mempool) { 3043943e942eSJens Axboe result = -ENOMEM; 3044943e942eSJens Axboe goto release_pools; 3045943e942eSJens Axboe } 3046943e942eSJens Axboe 3047b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3048b6e44b4cSKeith Busch quirks); 3049b6e44b4cSKeith Busch if (result) 3050b6e44b4cSKeith Busch goto release_mempool; 3051b6e44b4cSKeith Busch 30521b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 30531b3c47c1SSagi Grimberg 3054bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 305518119775SKeith Busch async_schedule(nvme_async_probe, dev); 30564caff8fcSSagi Grimberg 305757dacad5SJay Sternberg return 0; 305857dacad5SJay Sternberg 3059b6e44b4cSKeith Busch release_mempool: 3060b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 306157dacad5SJay Sternberg release_pools: 306257dacad5SJay Sternberg nvme_release_prp_pools(dev); 3063b00c9b7aSChristophe JAILLET unmap: 3064b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 306557dacad5SJay Sternberg put_pci: 306657dacad5SJay Sternberg put_device(dev->dev); 306757dacad5SJay Sternberg free: 306857dacad5SJay Sternberg kfree(dev->queues); 306957dacad5SJay Sternberg kfree(dev); 307057dacad5SJay Sternberg return result; 307157dacad5SJay Sternberg } 307257dacad5SJay Sternberg 3073775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 307457dacad5SJay Sternberg { 307557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3076c1ac9a4bSKeith Busch 3077c1ac9a4bSKeith Busch /* 3078c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3079c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3080c1ac9a4bSKeith Busch * with ->remove(). 3081c1ac9a4bSKeith Busch */ 3082c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3083c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3084775755edSChristoph Hellwig } 308557dacad5SJay Sternberg 3086775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3087775755edSChristoph Hellwig { 3088f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3089c1ac9a4bSKeith Busch 3090c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3091c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 309257dacad5SJay Sternberg } 309357dacad5SJay Sternberg 309457dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 309557dacad5SJay Sternberg { 309657dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 30974e523547SBaolin Wang 3098c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 309957dacad5SJay Sternberg } 310057dacad5SJay Sternberg 31010521905eSKeith Busch static void nvme_remove_attrs(struct nvme_dev *dev) 31020521905eSKeith Busch { 31030521905eSKeith Busch if (dev->attrs_added) 31040521905eSKeith Busch sysfs_remove_group(&dev->ctrl.device->kobj, 31050521905eSKeith Busch &nvme_pci_attr_group); 31060521905eSKeith Busch } 31070521905eSKeith Busch 3108f58944e2SKeith Busch /* 3109f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3110f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3111f58944e2SKeith Busch * order to proceed. 3112f58944e2SKeith Busch */ 311357dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 311457dacad5SJay Sternberg { 311557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 311657dacad5SJay Sternberg 3117bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 311857dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 31190ff9d4e1SKeith Busch 31206db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 31210ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 31221d39e692SKeith Busch nvme_dev_disable(dev, true); 31236db28edaSKeith Busch } 31240ff9d4e1SKeith Busch 3125d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3126d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3127d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3128a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 31290521905eSKeith Busch nvme_remove_attrs(dev); 313087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 313157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 313257dacad5SJay Sternberg nvme_free_queues(dev, 0); 313357dacad5SJay Sternberg nvme_release_prp_pools(dev); 3134b00a726aSKeith Busch nvme_dev_unmap(dev); 3135726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 313657dacad5SJay Sternberg } 313757dacad5SJay Sternberg 313857dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3139d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3140d916b1beSKeith Busch { 3141d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3142d916b1beSKeith Busch } 3143d916b1beSKeith Busch 3144d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3145d916b1beSKeith Busch { 3146d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3147d916b1beSKeith Busch } 3148d916b1beSKeith Busch 3149d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3150d916b1beSKeith Busch { 3151d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3152d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3153d916b1beSKeith Busch 31544eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3155d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3156e5ad96f3SKeith Busch goto reset; 3157e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3158e5ad96f3SKeith Busch goto reset; 3159e5ad96f3SKeith Busch 3160d916b1beSKeith Busch return 0; 3161e5ad96f3SKeith Busch reset: 3162e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3163d916b1beSKeith Busch } 3164d916b1beSKeith Busch 316557dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 316657dacad5SJay Sternberg { 316757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 316857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3169d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3170d916b1beSKeith Busch int ret = -EBUSY; 3171d916b1beSKeith Busch 31724eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 31734eaefe8cSRafael J. Wysocki 3174d916b1beSKeith Busch /* 3175d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3176d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3177d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3178d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3179d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3180d916b1beSKeith Busch * device fully. 31814eaefe8cSRafael J. Wysocki * 31824eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 31834eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 31844eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 31854eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3186d916b1beSKeith Busch */ 31874eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3188cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3189c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3190c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3191d916b1beSKeith Busch 3192d916b1beSKeith Busch nvme_start_freeze(ctrl); 3193d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3194d916b1beSKeith Busch nvme_sync_queues(ctrl); 3195d916b1beSKeith Busch 31965d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3197d916b1beSKeith Busch goto unfreeze; 3198d916b1beSKeith Busch 3199e5ad96f3SKeith Busch /* 3200e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3201e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3202e5ad96f3SKeith Busch * non-operational power state. 3203e5ad96f3SKeith Busch */ 3204e5ad96f3SKeith Busch if (ndev->hmb) { 3205e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3206e5ad96f3SKeith Busch if (ret < 0) 3207e5ad96f3SKeith Busch goto unfreeze; 3208e5ad96f3SKeith Busch } 3209e5ad96f3SKeith Busch 3210d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3211d916b1beSKeith Busch if (ret < 0) 3212d916b1beSKeith Busch goto unfreeze; 3213d916b1beSKeith Busch 32147cbb5c6fSMario Limonciello /* 32157cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 32167cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 32177cbb5c6fSMario Limonciello * want pci interfering. 32187cbb5c6fSMario Limonciello */ 32197cbb5c6fSMario Limonciello pci_save_state(pdev); 32207cbb5c6fSMario Limonciello 3221d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3222d916b1beSKeith Busch if (ret < 0) 3223d916b1beSKeith Busch goto unfreeze; 3224d916b1beSKeith Busch 3225d916b1beSKeith Busch if (ret) { 32267cbb5c6fSMario Limonciello /* discard the saved state */ 32277cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 32287cbb5c6fSMario Limonciello 3229d916b1beSKeith Busch /* 3230d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 323105d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3232d916b1beSKeith Busch */ 3233c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3234d916b1beSKeith Busch ctrl->npss = 0; 3235d916b1beSKeith Busch } 3236d916b1beSKeith Busch unfreeze: 3237d916b1beSKeith Busch nvme_unfreeze(ctrl); 3238d916b1beSKeith Busch return ret; 3239d916b1beSKeith Busch } 3240d916b1beSKeith Busch 3241d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3242d916b1beSKeith Busch { 3243d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 32444e523547SBaolin Wang 3245c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 324657dacad5SJay Sternberg } 324757dacad5SJay Sternberg 3248d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 324957dacad5SJay Sternberg { 325057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 325157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 325257dacad5SJay Sternberg 3253c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 325457dacad5SJay Sternberg } 325557dacad5SJay Sternberg 325621774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3257d916b1beSKeith Busch .suspend = nvme_suspend, 3258d916b1beSKeith Busch .resume = nvme_resume, 3259d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3260d916b1beSKeith Busch .thaw = nvme_simple_resume, 3261d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3262d916b1beSKeith Busch .restore = nvme_simple_resume, 3263d916b1beSKeith Busch }; 3264d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 326557dacad5SJay Sternberg 3266a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3267a0a3408eSKeith Busch pci_channel_state_t state) 3268a0a3408eSKeith Busch { 3269a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3270a0a3408eSKeith Busch 3271a0a3408eSKeith Busch /* 3272a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3273a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3274a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3275a0a3408eSKeith Busch */ 3276a0a3408eSKeith Busch switch (state) { 3277a0a3408eSKeith Busch case pci_channel_io_normal: 3278a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3279a0a3408eSKeith Busch case pci_channel_io_frozen: 3280d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3281d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3282a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3283a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3284a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3285d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3286d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3287a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3288a0a3408eSKeith Busch } 3289a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3290a0a3408eSKeith Busch } 3291a0a3408eSKeith Busch 3292a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3293a0a3408eSKeith Busch { 3294a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3295a0a3408eSKeith Busch 32961b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3297a0a3408eSKeith Busch pci_restore_state(pdev); 3298d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3299a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3300a0a3408eSKeith Busch } 3301a0a3408eSKeith Busch 3302a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3303a0a3408eSKeith Busch { 330472cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 330572cd4cc2SKeith Busch 330672cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3307a0a3408eSKeith Busch } 3308a0a3408eSKeith Busch 330957dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 331057dacad5SJay Sternberg .error_detected = nvme_error_detected, 331157dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 331257dacad5SJay Sternberg .resume = nvme_error_resume, 3313775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3314775755edSChristoph Hellwig .reset_done = nvme_reset_done, 331557dacad5SJay Sternberg }; 331657dacad5SJay Sternberg 331757dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3318972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 331908095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3320e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3321972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 332299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3323e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3324972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 332599466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3326e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3327972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3328f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3329f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 333050af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 33319abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 33326c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3333ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3334ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 33356299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 33366299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3337540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 33387b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 33397b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 33405bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 33415bedd3afSChristoph Hellwig .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 33420302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 33435e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 33445e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 334554adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 334654adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 33478c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 33488c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3349015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3350015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3351d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3352d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3353d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 33547ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3355abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 33567ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3357c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3358c9e95c39SClaus Stovgaard .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 33596e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 33606e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 33616e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 336208b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 336308b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3364f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3365f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3366f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 33675611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 33685611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 336902ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 337002ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 337189919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 337289919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3373dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3374dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3375538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3376538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 33774bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 33784bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33794bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 33804bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33814bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 33824bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33834bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 33844bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33854bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 33864bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33874bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 33884bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 338998f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 339098f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3391124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 339266341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 339366341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3394d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3395a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3396a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 33970b85f59dSAndy Shevchenko 33980b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 339957dacad5SJay Sternberg { 0, } 340057dacad5SJay Sternberg }; 340157dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 340257dacad5SJay Sternberg 340357dacad5SJay Sternberg static struct pci_driver nvme_driver = { 340457dacad5SJay Sternberg .name = "nvme", 340557dacad5SJay Sternberg .id_table = nvme_id_table, 340657dacad5SJay Sternberg .probe = nvme_probe, 340757dacad5SJay Sternberg .remove = nvme_remove, 340857dacad5SJay Sternberg .shutdown = nvme_shutdown, 3409d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 341057dacad5SJay Sternberg .driver = { 341157dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 341257dacad5SJay Sternberg }, 3413d916b1beSKeith Busch #endif 341474d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 341557dacad5SJay Sternberg .err_handler = &nvme_err_handler, 341657dacad5SJay Sternberg }; 341757dacad5SJay Sternberg 341857dacad5SJay Sternberg static int __init nvme_init(void) 341957dacad5SJay Sternberg { 342081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 342181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 342281101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3423612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 342417c33167SKeith Busch 34259a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 342657dacad5SJay Sternberg } 342757dacad5SJay Sternberg 342857dacad5SJay Sternberg static void __exit nvme_exit(void) 342957dacad5SJay Sternberg { 343057dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 343103e0f3a6SMing Lei flush_workqueue(nvme_wq); 343257dacad5SJay Sternberg } 343357dacad5SJay Sternberg 343457dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 343557dacad5SJay Sternberg MODULE_LICENSE("GPL"); 343657dacad5SJay Sternberg MODULE_VERSION("1.0"); 343757dacad5SJay Sternberg module_init(nvme_init); 343857dacad5SJay Sternberg module_exit(nvme_exit); 3439