15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 21d916b1beSKeith Busch #include <linux/suspend.h> 2257dacad5SJay Sternberg #include <linux/t10-pi.h> 2357dacad5SJay Sternberg #include <linux/types.h> 249cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 25a98e58e5SScott Bauer #include <linux/sed-opal.h> 260f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2757dacad5SJay Sternberg 28604c01d5Syupeng #include "trace.h" 2957dacad5SJay Sternberg #include "nvme.h" 3057dacad5SJay Sternberg 31c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 328a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3357dacad5SJay Sternberg 34a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35adf68f21SChristoph Hellwig 36943e942eSJens Axboe /* 37943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 38943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 39943e942eSJens Axboe */ 40943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 41943e942eSJens Axboe #define NVME_MAX_SEGS 127 42943e942eSJens Axboe 4357dacad5SJay Sternberg static int use_threaded_interrupts; 4457dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4557dacad5SJay Sternberg 4657dacad5SJay Sternberg static bool use_cmb_sqes = true; 4769f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4857dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4957dacad5SJay Sternberg 5087ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5187ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5287ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5387ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5457dacad5SJay Sternberg 55a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 56a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 57a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 58a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 59a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 60a7a7cbe3SChaitanya Kulkarni 61b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 63b27c1e68Sweiping zhang .set = io_queue_depth_set, 64b27c1e68Sweiping zhang .get = param_get_int, 65b27c1e68Sweiping zhang }; 66b27c1e68Sweiping zhang 67b27c1e68Sweiping zhang static int io_queue_depth = 1024; 68b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70b27c1e68Sweiping zhang 713f68baf7SKeith Busch static unsigned int write_queues; 723f68baf7SKeith Busch module_param(write_queues, uint, 0644); 733b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 743b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 753b6592f7SJens Axboe "will share a queue set."); 763b6592f7SJens Axboe 773f68baf7SKeith Busch static unsigned int poll_queues; 783f68baf7SKeith Busch module_param(poll_queues, uint, 0644); 794b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 804b04cc6aSJens Axboe 811c63dc66SChristoph Hellwig struct nvme_dev; 821c63dc66SChristoph Hellwig struct nvme_queue; 8357dacad5SJay Sternberg 84a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 858fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 8657dacad5SJay Sternberg 8757dacad5SJay Sternberg /* 881c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 891c63dc66SChristoph Hellwig */ 901c63dc66SChristoph Hellwig struct nvme_dev { 91147b27e4SSagi Grimberg struct nvme_queue *queues; 921c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 931c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 941c63dc66SChristoph Hellwig u32 __iomem *dbs; 951c63dc66SChristoph Hellwig struct device *dev; 961c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 971c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 981c63dc66SChristoph Hellwig unsigned online_queues; 991c63dc66SChristoph Hellwig unsigned max_qid; 100e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 10122b55601SKeith Busch unsigned int num_vecs; 1021c63dc66SChristoph Hellwig int q_depth; 103c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1041c63dc66SChristoph Hellwig u32 db_stride; 1051c63dc66SChristoph Hellwig void __iomem *bar; 10697f6ef64SXu Yu unsigned long bar_mapped_size; 1075c8809e6SChristoph Hellwig struct work_struct remove_work; 10877bf25eaSKeith Busch struct mutex shutdown_lock; 1091c63dc66SChristoph Hellwig bool subsystem; 1101c63dc66SChristoph Hellwig u64 cmb_size; 1110f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1121c63dc66SChristoph Hellwig u32 cmbsz; 113202021c1SStephen Bates u32 cmbloc; 1141c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 115d916b1beSKeith Busch u32 last_ps; 11687ad72a5SChristoph Hellwig 117943e942eSJens Axboe mempool_t *iod_mempool; 118943e942eSJens Axboe 11987ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 120f9f38e33SHelen Koike u32 *dbbuf_dbs; 121f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 122f9f38e33SHelen Koike u32 *dbbuf_eis; 123f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 12487ad72a5SChristoph Hellwig 12587ad72a5SChristoph Hellwig /* host memory buffer support: */ 12687ad72a5SChristoph Hellwig u64 host_mem_size; 12787ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1284033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 12987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13087ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 13157dacad5SJay Sternberg }; 13257dacad5SJay Sternberg 133b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 134b27c1e68Sweiping zhang { 135b27c1e68Sweiping zhang int n = 0, ret; 136b27c1e68Sweiping zhang 137b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 138b27c1e68Sweiping zhang if (ret != 0 || n < 2) 139b27c1e68Sweiping zhang return -EINVAL; 140b27c1e68Sweiping zhang 141b27c1e68Sweiping zhang return param_set_int(val, kp); 142b27c1e68Sweiping zhang } 143b27c1e68Sweiping zhang 144f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 145f9f38e33SHelen Koike { 146f9f38e33SHelen Koike return qid * 2 * stride; 147f9f38e33SHelen Koike } 148f9f38e33SHelen Koike 149f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 150f9f38e33SHelen Koike { 151f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 152f9f38e33SHelen Koike } 153f9f38e33SHelen Koike 1541c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1551c63dc66SChristoph Hellwig { 1561c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1571c63dc66SChristoph Hellwig } 1581c63dc66SChristoph Hellwig 15957dacad5SJay Sternberg /* 16057dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 16157dacad5SJay Sternberg * commands and one for I/O commands). 16257dacad5SJay Sternberg */ 16357dacad5SJay Sternberg struct nvme_queue { 16457dacad5SJay Sternberg struct nvme_dev *dev; 1651ab0cd69SJens Axboe spinlock_t sq_lock; 166c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1673a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1683a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 16957dacad5SJay Sternberg volatile struct nvme_completion *cqes; 17057dacad5SJay Sternberg dma_addr_t sq_dma_addr; 17157dacad5SJay Sternberg dma_addr_t cq_dma_addr; 17257dacad5SJay Sternberg u32 __iomem *q_db; 17357dacad5SJay Sternberg u16 q_depth; 1747c349ddeSKeith Busch u16 cq_vector; 17557dacad5SJay Sternberg u16 sq_tail; 17604f3eafdSJens Axboe u16 last_sq_tail; 17757dacad5SJay Sternberg u16 cq_head; 17857dacad5SJay Sternberg u16 qid; 17957dacad5SJay Sternberg u8 cq_phase; 180c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 1814e224106SChristoph Hellwig unsigned long flags; 1824e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 18363223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 184d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 1857c349ddeSKeith Busch #define NVMEQ_POLLED 3 186f9f38e33SHelen Koike u32 *dbbuf_sq_db; 187f9f38e33SHelen Koike u32 *dbbuf_cq_db; 188f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 189f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 190d1ed6aa1SChristoph Hellwig struct completion delete_done; 19157dacad5SJay Sternberg }; 19257dacad5SJay Sternberg 19357dacad5SJay Sternberg /* 1949b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 1959b048119SChristoph Hellwig * 1969b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 1979b048119SChristoph Hellwig * to the actual struct scatterlist. 19871bd150cSChristoph Hellwig */ 19971bd150cSChristoph Hellwig struct nvme_iod { 200d49187e9SChristoph Hellwig struct nvme_request req; 201f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 202a7a7cbe3SChaitanya Kulkarni bool use_sgl; 203f4800d6dSChristoph Hellwig int aborted; 20471bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 20571bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 20671bd150cSChristoph Hellwig dma_addr_t first_dma; 207dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 208783b94bdSChristoph Hellwig dma_addr_t meta_dma; 209f4800d6dSChristoph Hellwig struct scatterlist *sg; 21057dacad5SJay Sternberg }; 21157dacad5SJay Sternberg 2123b6592f7SJens Axboe static unsigned int max_io_queues(void) 2133b6592f7SJens Axboe { 2144b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2153b6592f7SJens Axboe } 2163b6592f7SJens Axboe 2173b6592f7SJens Axboe static unsigned int max_queue_count(void) 2183b6592f7SJens Axboe { 2193b6592f7SJens Axboe /* IO queues + admin queue */ 2203b6592f7SJens Axboe return 1 + max_io_queues(); 2213b6592f7SJens Axboe } 2223b6592f7SJens Axboe 223f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 224f9f38e33SHelen Koike { 2253b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 226f9f38e33SHelen Koike } 227f9f38e33SHelen Koike 228f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 229f9f38e33SHelen Koike { 230f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 231f9f38e33SHelen Koike 232f9f38e33SHelen Koike if (dev->dbbuf_dbs) 233f9f38e33SHelen Koike return 0; 234f9f38e33SHelen Koike 235f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 236f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 237f9f38e33SHelen Koike GFP_KERNEL); 238f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 239f9f38e33SHelen Koike return -ENOMEM; 240f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 241f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 242f9f38e33SHelen Koike GFP_KERNEL); 243f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 244f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 245f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 246f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 247f9f38e33SHelen Koike return -ENOMEM; 248f9f38e33SHelen Koike } 249f9f38e33SHelen Koike 250f9f38e33SHelen Koike return 0; 251f9f38e33SHelen Koike } 252f9f38e33SHelen Koike 253f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 254f9f38e33SHelen Koike { 255f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 256f9f38e33SHelen Koike 257f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 258f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 259f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 260f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 261f9f38e33SHelen Koike } 262f9f38e33SHelen Koike if (dev->dbbuf_eis) { 263f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 264f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 265f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 266f9f38e33SHelen Koike } 267f9f38e33SHelen Koike } 268f9f38e33SHelen Koike 269f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 270f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 271f9f38e33SHelen Koike { 272f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 273f9f38e33SHelen Koike return; 274f9f38e33SHelen Koike 275f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 276f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 277f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 278f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 279f9f38e33SHelen Koike } 280f9f38e33SHelen Koike 281f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 282f9f38e33SHelen Koike { 283f9f38e33SHelen Koike struct nvme_command c; 284f9f38e33SHelen Koike 285f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 286f9f38e33SHelen Koike return; 287f9f38e33SHelen Koike 288f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 289f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 290f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 291f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 292f9f38e33SHelen Koike 293f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2949bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 295f9f38e33SHelen Koike /* Free memory and continue on */ 296f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 297f9f38e33SHelen Koike } 298f9f38e33SHelen Koike } 299f9f38e33SHelen Koike 300f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 301f9f38e33SHelen Koike { 302f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike 305f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 306f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 307f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 308f9f38e33SHelen Koike { 309f9f38e33SHelen Koike if (dbbuf_db) { 310f9f38e33SHelen Koike u16 old_value; 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike /* 313f9f38e33SHelen Koike * Ensure that the queue is written before updating 314f9f38e33SHelen Koike * the doorbell in memory 315f9f38e33SHelen Koike */ 316f9f38e33SHelen Koike wmb(); 317f9f38e33SHelen Koike 318f9f38e33SHelen Koike old_value = *dbbuf_db; 319f9f38e33SHelen Koike *dbbuf_db = value; 320f9f38e33SHelen Koike 321f1ed3df2SMichal Wnukowski /* 322f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 323f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 324f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 325f1ed3df2SMichal Wnukowski * the doorbell. 326f1ed3df2SMichal Wnukowski */ 327f1ed3df2SMichal Wnukowski mb(); 328f1ed3df2SMichal Wnukowski 329f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 330f9f38e33SHelen Koike return false; 331f9f38e33SHelen Koike } 332f9f38e33SHelen Koike 333f9f38e33SHelen Koike return true; 33457dacad5SJay Sternberg } 33557dacad5SJay Sternberg 33657dacad5SJay Sternberg /* 33757dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 33857dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 33957dacad5SJay Sternberg * the I/O. 34057dacad5SJay Sternberg */ 34157dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 34257dacad5SJay Sternberg { 3435fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3445fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 34557dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 34657dacad5SJay Sternberg } 34757dacad5SJay Sternberg 348a7a7cbe3SChaitanya Kulkarni /* 349a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 350a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 351a7a7cbe3SChaitanya Kulkarni */ 352a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 353f4800d6dSChristoph Hellwig { 354a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 355f4800d6dSChristoph Hellwig } 356f4800d6dSChristoph Hellwig 357a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 358a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 35957dacad5SJay Sternberg { 360a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 361a7a7cbe3SChaitanya Kulkarni 362a7a7cbe3SChaitanya Kulkarni if (use_sgl) 363a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 364a7a7cbe3SChaitanya Kulkarni else 365a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 366a7a7cbe3SChaitanya Kulkarni 367a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 368a7a7cbe3SChaitanya Kulkarni } 369a7a7cbe3SChaitanya Kulkarni 37057dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 37157dacad5SJay Sternberg unsigned int hctx_idx) 37257dacad5SJay Sternberg { 37357dacad5SJay Sternberg struct nvme_dev *dev = data; 374147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 37757dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 37857dacad5SJay Sternberg 37957dacad5SJay Sternberg hctx->driver_data = nvmeq; 38057dacad5SJay Sternberg return 0; 38157dacad5SJay Sternberg } 38257dacad5SJay Sternberg 38357dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38457dacad5SJay Sternberg unsigned int hctx_idx) 38557dacad5SJay Sternberg { 38657dacad5SJay Sternberg struct nvme_dev *dev = data; 387147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 38857dacad5SJay Sternberg 38957dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 39057dacad5SJay Sternberg hctx->driver_data = nvmeq; 39157dacad5SJay Sternberg return 0; 39257dacad5SJay Sternberg } 39357dacad5SJay Sternberg 394d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 395d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 39657dacad5SJay Sternberg { 397d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 398f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 3990350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 400147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 40157dacad5SJay Sternberg 40257dacad5SJay Sternberg BUG_ON(!nvmeq); 403f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 40459e29ce6SSagi Grimberg 40559e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 40657dacad5SJay Sternberg return 0; 40757dacad5SJay Sternberg } 40857dacad5SJay Sternberg 4093b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4103b6592f7SJens Axboe { 4113b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4123b6592f7SJens Axboe if (dev->num_vecs > 1) 4133b6592f7SJens Axboe return 1; 4143b6592f7SJens Axboe 4153b6592f7SJens Axboe return 0; 4163b6592f7SJens Axboe } 4173b6592f7SJens Axboe 418dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 419dca51e78SChristoph Hellwig { 420dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4213b6592f7SJens Axboe int i, qoff, offset; 422dca51e78SChristoph Hellwig 4233b6592f7SJens Axboe offset = queue_irq_offset(dev); 4243b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4253b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4263b6592f7SJens Axboe 4273b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4283b6592f7SJens Axboe if (!map->nr_queues) { 429e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4307e849dd9SChristoph Hellwig continue; 4313b6592f7SJens Axboe } 4323b6592f7SJens Axboe 4334b04cc6aSJens Axboe /* 4344b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4354b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4364b04cc6aSJens Axboe */ 4373b6592f7SJens Axboe map->queue_offset = qoff; 438cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4393b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4404b04cc6aSJens Axboe else 4414b04cc6aSJens Axboe blk_mq_map_queues(map); 4423b6592f7SJens Axboe qoff += map->nr_queues; 4433b6592f7SJens Axboe offset += map->nr_queues; 4443b6592f7SJens Axboe } 4453b6592f7SJens Axboe 4463b6592f7SJens Axboe return 0; 447dca51e78SChristoph Hellwig } 448dca51e78SChristoph Hellwig 44904f3eafdSJens Axboe /* 45004f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 45104f3eafdSJens Axboe */ 45204f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 45304f3eafdSJens Axboe { 45404f3eafdSJens Axboe if (!write_sq) { 45504f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 45604f3eafdSJens Axboe 45704f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 45804f3eafdSJens Axboe next_tail = 0; 45904f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 46004f3eafdSJens Axboe return; 46104f3eafdSJens Axboe } 46204f3eafdSJens Axboe 46304f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 46404f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 46504f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 46604f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 46704f3eafdSJens Axboe } 46804f3eafdSJens Axboe 46957dacad5SJay Sternberg /** 47090ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 47157dacad5SJay Sternberg * @nvmeq: The queue to use 47257dacad5SJay Sternberg * @cmd: The command to send 47304f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 47457dacad5SJay Sternberg */ 47504f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 47604f3eafdSJens Axboe bool write_sq) 47757dacad5SJay Sternberg { 47890ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 479c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 480c1e0cc7eSBenjamin Herrenschmidt cmd, sizeof(*cmd)); 48190ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 48290ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 48304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 48404f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 48504f3eafdSJens Axboe } 48604f3eafdSJens Axboe 48704f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 48804f3eafdSJens Axboe { 48904f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 49004f3eafdSJens Axboe 49104f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 49204f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 49304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 49490ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 49557dacad5SJay Sternberg } 49657dacad5SJay Sternberg 497a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 49857dacad5SJay Sternberg { 499f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 500a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 50157dacad5SJay Sternberg } 50257dacad5SJay Sternberg 503955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 504955b1b5aSMinwoo Im { 505955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 50620469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 507955b1b5aSMinwoo Im unsigned int avg_seg_size; 508955b1b5aSMinwoo Im 50920469a37SKeith Busch if (nseg == 0) 51020469a37SKeith Busch return false; 51120469a37SKeith Busch 51220469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 513955b1b5aSMinwoo Im 514955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 515955b1b5aSMinwoo Im return false; 516955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 517955b1b5aSMinwoo Im return false; 518955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 519955b1b5aSMinwoo Im return false; 520955b1b5aSMinwoo Im return true; 521955b1b5aSMinwoo Im } 522955b1b5aSMinwoo Im 5237fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 52457dacad5SJay Sternberg { 525f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 526a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 527a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 52857dacad5SJay Sternberg int i; 52957dacad5SJay Sternberg 530dff824b2SChristoph Hellwig if (iod->dma_len) { 531f2fa006fSIsrael Rukshin dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 532f2fa006fSIsrael Rukshin rq_dma_dir(req)); 533dff824b2SChristoph Hellwig return; 534dff824b2SChristoph Hellwig } 535dff824b2SChristoph Hellwig 536dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 537dff824b2SChristoph Hellwig 5387f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5397f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5407f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5417f73eac3SLogan Gunthorpe else 542dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5437fe07d14SChristoph Hellwig 5447fe07d14SChristoph Hellwig 54557dacad5SJay Sternberg if (iod->npages == 0) 546a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 547a7a7cbe3SChaitanya Kulkarni dma_addr); 548a7a7cbe3SChaitanya Kulkarni 54957dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 550a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 551a7a7cbe3SChaitanya Kulkarni 552a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 553a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 554a7a7cbe3SChaitanya Kulkarni 555a7a7cbe3SChaitanya Kulkarni next_dma_addr = 556a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 557a7a7cbe3SChaitanya Kulkarni } else { 558a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 559a7a7cbe3SChaitanya Kulkarni 560a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 561a7a7cbe3SChaitanya Kulkarni } 562a7a7cbe3SChaitanya Kulkarni 563a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 564a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 56557dacad5SJay Sternberg } 56657dacad5SJay Sternberg 567943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 56857dacad5SJay Sternberg } 56957dacad5SJay Sternberg 570d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 571d0877473SKeith Busch { 572d0877473SKeith Busch int i; 573d0877473SKeith Busch struct scatterlist *sg; 574d0877473SKeith Busch 575d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 576d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 577d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 578d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 579d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 580d0877473SKeith Busch sg_dma_len(sg)); 581d0877473SKeith Busch } 582d0877473SKeith Busch } 583d0877473SKeith Busch 584a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 585a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 58657dacad5SJay Sternberg { 587f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 58857dacad5SJay Sternberg struct dma_pool *pool; 589b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 59057dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 59157dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 59257dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5935fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 59457dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 59557dacad5SJay Sternberg __le64 *prp_list; 596a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 59757dacad5SJay Sternberg dma_addr_t prp_dma; 59857dacad5SJay Sternberg int nprps, i; 59957dacad5SJay Sternberg 60057dacad5SJay Sternberg length -= (page_size - offset); 6015228b328SJan H. Schönherr if (length <= 0) { 6025228b328SJan H. Schönherr iod->first_dma = 0; 603a7a7cbe3SChaitanya Kulkarni goto done; 6045228b328SJan H. Schönherr } 60557dacad5SJay Sternberg 60657dacad5SJay Sternberg dma_len -= (page_size - offset); 60757dacad5SJay Sternberg if (dma_len) { 60857dacad5SJay Sternberg dma_addr += (page_size - offset); 60957dacad5SJay Sternberg } else { 61057dacad5SJay Sternberg sg = sg_next(sg); 61157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 61257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 61357dacad5SJay Sternberg } 61457dacad5SJay Sternberg 61557dacad5SJay Sternberg if (length <= page_size) { 61657dacad5SJay Sternberg iod->first_dma = dma_addr; 617a7a7cbe3SChaitanya Kulkarni goto done; 61857dacad5SJay Sternberg } 61957dacad5SJay Sternberg 62057dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 62157dacad5SJay Sternberg if (nprps <= (256 / 8)) { 62257dacad5SJay Sternberg pool = dev->prp_small_pool; 62357dacad5SJay Sternberg iod->npages = 0; 62457dacad5SJay Sternberg } else { 62557dacad5SJay Sternberg pool = dev->prp_page_pool; 62657dacad5SJay Sternberg iod->npages = 1; 62757dacad5SJay Sternberg } 62857dacad5SJay Sternberg 62969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 63057dacad5SJay Sternberg if (!prp_list) { 63157dacad5SJay Sternberg iod->first_dma = dma_addr; 63257dacad5SJay Sternberg iod->npages = -1; 63386eea289SKeith Busch return BLK_STS_RESOURCE; 63457dacad5SJay Sternberg } 63557dacad5SJay Sternberg list[0] = prp_list; 63657dacad5SJay Sternberg iod->first_dma = prp_dma; 63757dacad5SJay Sternberg i = 0; 63857dacad5SJay Sternberg for (;;) { 63957dacad5SJay Sternberg if (i == page_size >> 3) { 64057dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 64169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 64257dacad5SJay Sternberg if (!prp_list) 64386eea289SKeith Busch return BLK_STS_RESOURCE; 64457dacad5SJay Sternberg list[iod->npages++] = prp_list; 64557dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 64657dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 64757dacad5SJay Sternberg i = 1; 64857dacad5SJay Sternberg } 64957dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 65057dacad5SJay Sternberg dma_len -= page_size; 65157dacad5SJay Sternberg dma_addr += page_size; 65257dacad5SJay Sternberg length -= page_size; 65357dacad5SJay Sternberg if (length <= 0) 65457dacad5SJay Sternberg break; 65557dacad5SJay Sternberg if (dma_len > 0) 65657dacad5SJay Sternberg continue; 65786eea289SKeith Busch if (unlikely(dma_len < 0)) 65886eea289SKeith Busch goto bad_sgl; 65957dacad5SJay Sternberg sg = sg_next(sg); 66057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 66157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 66257dacad5SJay Sternberg } 66357dacad5SJay Sternberg 664a7a7cbe3SChaitanya Kulkarni done: 665a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 666a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 667a7a7cbe3SChaitanya Kulkarni 66886eea289SKeith Busch return BLK_STS_OK; 66986eea289SKeith Busch 67086eea289SKeith Busch bad_sgl: 671d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 672d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 673d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 67486eea289SKeith Busch return BLK_STS_IOERR; 67557dacad5SJay Sternberg } 67657dacad5SJay Sternberg 677a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 678a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 679a7a7cbe3SChaitanya Kulkarni { 680a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 681a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 682a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 683a7a7cbe3SChaitanya Kulkarni } 684a7a7cbe3SChaitanya Kulkarni 685a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 686a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 687a7a7cbe3SChaitanya Kulkarni { 688a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 689a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 690a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 691a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 692a7a7cbe3SChaitanya Kulkarni } else { 693a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 694a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 695a7a7cbe3SChaitanya Kulkarni } 696a7a7cbe3SChaitanya Kulkarni } 697a7a7cbe3SChaitanya Kulkarni 698a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 699b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 700a7a7cbe3SChaitanya Kulkarni { 701a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 702a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 703a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 704a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 705a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 706b0f2853bSChristoph Hellwig int i = 0; 707a7a7cbe3SChaitanya Kulkarni 708a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 709a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 710a7a7cbe3SChaitanya Kulkarni 711b0f2853bSChristoph Hellwig if (entries == 1) { 712a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 713a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 714a7a7cbe3SChaitanya Kulkarni } 715a7a7cbe3SChaitanya Kulkarni 716a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 717a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 718a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 719a7a7cbe3SChaitanya Kulkarni } else { 720a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 721a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 722a7a7cbe3SChaitanya Kulkarni } 723a7a7cbe3SChaitanya Kulkarni 724a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 725a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 726a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 727a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 728a7a7cbe3SChaitanya Kulkarni } 729a7a7cbe3SChaitanya Kulkarni 730a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 731a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 732a7a7cbe3SChaitanya Kulkarni 733a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 734a7a7cbe3SChaitanya Kulkarni 735a7a7cbe3SChaitanya Kulkarni do { 736a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 737a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 738a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 739a7a7cbe3SChaitanya Kulkarni 740a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 741a7a7cbe3SChaitanya Kulkarni if (!sg_list) 742a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 743a7a7cbe3SChaitanya Kulkarni 744a7a7cbe3SChaitanya Kulkarni i = 0; 745a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 746a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 747a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 748a7a7cbe3SChaitanya Kulkarni } 749a7a7cbe3SChaitanya Kulkarni 750a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 751a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 752b0f2853bSChristoph Hellwig } while (--entries > 0); 753a7a7cbe3SChaitanya Kulkarni 754a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 755a7a7cbe3SChaitanya Kulkarni } 756a7a7cbe3SChaitanya Kulkarni 757dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 758dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 759dff824b2SChristoph Hellwig struct bio_vec *bv) 760dff824b2SChristoph Hellwig { 761dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 762a4f40484SKevin Hao unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1); 763a4f40484SKevin Hao unsigned int first_prp_len = dev->ctrl.page_size - offset; 764dff824b2SChristoph Hellwig 765dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 766dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 767dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 768dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 769dff824b2SChristoph Hellwig 770dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 771dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 772dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 773dff824b2SChristoph Hellwig return 0; 774dff824b2SChristoph Hellwig } 775dff824b2SChristoph Hellwig 77629791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 77729791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 77829791057SChristoph Hellwig struct bio_vec *bv) 77929791057SChristoph Hellwig { 78029791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 78129791057SChristoph Hellwig 78229791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 78329791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 78429791057SChristoph Hellwig return BLK_STS_RESOURCE; 78529791057SChristoph Hellwig iod->dma_len = bv->bv_len; 78629791057SChristoph Hellwig 787049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 78829791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 78929791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 79029791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 79129791057SChristoph Hellwig return 0; 79229791057SChristoph Hellwig } 79329791057SChristoph Hellwig 794fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 795b131c61dSChristoph Hellwig struct nvme_command *cmnd) 79657dacad5SJay Sternberg { 797f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 79870479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 799b0f2853bSChristoph Hellwig int nr_mapped; 80057dacad5SJay Sternberg 801dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 802dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 803dff824b2SChristoph Hellwig 804dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 805dff824b2SChristoph Hellwig if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 806dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 807dff824b2SChristoph Hellwig &cmnd->rw, &bv); 80829791057SChristoph Hellwig 80929791057SChristoph Hellwig if (iod->nvmeq->qid && 81029791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 81129791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 81229791057SChristoph Hellwig &cmnd->rw, &bv); 813dff824b2SChristoph Hellwig } 814dff824b2SChristoph Hellwig } 815dff824b2SChristoph Hellwig 816dff824b2SChristoph Hellwig iod->dma_len = 0; 8179b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8189b048119SChristoph Hellwig if (!iod->sg) 8199b048119SChristoph Hellwig return BLK_STS_RESOURCE; 820f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 82170479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 822ba1ca37eSChristoph Hellwig if (!iod->nents) 823ba1ca37eSChristoph Hellwig goto out; 824ba1ca37eSChristoph Hellwig 825e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8262b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8272b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 828e0596ab2SLogan Gunthorpe else 829e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 83070479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 831b0f2853bSChristoph Hellwig if (!nr_mapped) 832ba1ca37eSChristoph Hellwig goto out; 833ba1ca37eSChristoph Hellwig 83470479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 835955b1b5aSMinwoo Im if (iod->use_sgl) 836b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 837a7a7cbe3SChaitanya Kulkarni else 838a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 839ba1ca37eSChristoph Hellwig out: 8404aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8417fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 842ba1ca37eSChristoph Hellwig return ret; 84357dacad5SJay Sternberg } 84457dacad5SJay Sternberg 8454aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8464aedb705SChristoph Hellwig struct nvme_command *cmnd) 8474aedb705SChristoph Hellwig { 8484aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8494aedb705SChristoph Hellwig 8504aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8514aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8524aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8534aedb705SChristoph Hellwig return BLK_STS_IOERR; 8544aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 8554aedb705SChristoph Hellwig return 0; 8564aedb705SChristoph Hellwig } 8574aedb705SChristoph Hellwig 85857dacad5SJay Sternberg /* 85957dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 86057dacad5SJay Sternberg */ 861fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 86257dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 86357dacad5SJay Sternberg { 86457dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 86557dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 86657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 86757dacad5SJay Sternberg struct request *req = bd->rq; 8689b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 869ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 870ebe6d874SChristoph Hellwig blk_status_t ret; 87157dacad5SJay Sternberg 8729b048119SChristoph Hellwig iod->aborted = 0; 8739b048119SChristoph Hellwig iod->npages = -1; 8749b048119SChristoph Hellwig iod->nents = 0; 8759b048119SChristoph Hellwig 876d1f06f4aSJens Axboe /* 877d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 878d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 879d1f06f4aSJens Axboe */ 8804e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 881d1f06f4aSJens Axboe return BLK_STS_IOERR; 882d1f06f4aSJens Axboe 883f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 884fc17b653SChristoph Hellwig if (ret) 885f4800d6dSChristoph Hellwig return ret; 88657dacad5SJay Sternberg 887fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 888b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 889fc17b653SChristoph Hellwig if (ret) 8909b048119SChristoph Hellwig goto out_free_cmd; 891fc17b653SChristoph Hellwig } 892ba1ca37eSChristoph Hellwig 8934aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 8944aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 8954aedb705SChristoph Hellwig if (ret) 8964aedb705SChristoph Hellwig goto out_unmap_data; 8974aedb705SChristoph Hellwig } 8984aedb705SChristoph Hellwig 899aae239e1SChristoph Hellwig blk_mq_start_request(req); 90004f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 901fc17b653SChristoph Hellwig return BLK_STS_OK; 9024aedb705SChristoph Hellwig out_unmap_data: 9034aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 904f9d03f96SChristoph Hellwig out_free_cmd: 905f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 906ba1ca37eSChristoph Hellwig return ret; 90757dacad5SJay Sternberg } 90857dacad5SJay Sternberg 90977f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 910eee417b0SChristoph Hellwig { 911f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9124aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 913eee417b0SChristoph Hellwig 9144aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9154aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9164aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 917b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9184aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 91977f02a7aSChristoph Hellwig nvme_complete_rq(req); 92057dacad5SJay Sternberg } 92157dacad5SJay Sternberg 922d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 923750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 924d783e0bdSMarta Rybczynska { 925750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 926750dde44SChristoph Hellwig nvmeq->cq_phase; 927d783e0bdSMarta Rybczynska } 928d783e0bdSMarta Rybczynska 929eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 93057dacad5SJay Sternberg { 931eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 93257dacad5SJay Sternberg 933eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 934eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 935eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 936eb281c82SSagi Grimberg } 937adf68f21SChristoph Hellwig 938cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 939cfa27356SChristoph Hellwig { 940cfa27356SChristoph Hellwig if (!nvmeq->qid) 941cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 942cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 943cfa27356SChristoph Hellwig } 944cfa27356SChristoph Hellwig 9455cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 94657dacad5SJay Sternberg { 9475cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 94857dacad5SJay Sternberg struct request *req; 949adf68f21SChristoph Hellwig 95083a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9511b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 952aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 95383a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 95483a12fb7SSagi Grimberg return; 955aae239e1SChristoph Hellwig } 956aae239e1SChristoph Hellwig 957adf68f21SChristoph Hellwig /* 958adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 959adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 960adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 961adf68f21SChristoph Hellwig * for them but rather special case them here. 962adf68f21SChristoph Hellwig */ 96358a8df67SIsrael Rukshin if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) { 9647bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 96583a12fb7SSagi Grimberg cqe->status, &cqe->result); 966a0fa9647SJens Axboe return; 96757dacad5SJay Sternberg } 96857dacad5SJay Sternberg 969cfa27356SChristoph Hellwig req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id); 970604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 97183a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 97283a12fb7SSagi Grimberg } 97357dacad5SJay Sternberg 9745cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9755cb525c8SJens Axboe { 976e2a366a4SAlexey Dobriyan if (++nvmeq->cq_head == nvmeq->q_depth) { 977920d13a8SSagi Grimberg nvmeq->cq_head = 0; 978e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 979920d13a8SSagi Grimberg } 980a0fa9647SJens Axboe } 981a0fa9647SJens Axboe 982324b494cSKeith Busch static inline int nvme_process_cq(struct nvme_queue *nvmeq) 983a0fa9647SJens Axboe { 9841052b8acSJens Axboe int found = 0; 98583a12fb7SSagi Grimberg 9861052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 9871052b8acSJens Axboe found++; 988324b494cSKeith Busch nvme_handle_cqe(nvmeq, nvmeq->cq_head); 9895cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 99057dacad5SJay Sternberg } 99157dacad5SJay Sternberg 992324b494cSKeith Busch if (found) 993eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 9945cb525c8SJens Axboe return found; 99557dacad5SJay Sternberg } 99657dacad5SJay Sternberg 99757dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 99857dacad5SJay Sternberg { 99957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 100068fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10015cb525c8SJens Axboe 10023a7afd8eSChristoph Hellwig /* 10033a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10043a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10053a7afd8eSChristoph Hellwig */ 10063a7afd8eSChristoph Hellwig rmb(); 1007324b494cSKeith Busch if (nvme_process_cq(nvmeq)) 1008324b494cSKeith Busch ret = IRQ_HANDLED; 10093a7afd8eSChristoph Hellwig wmb(); 10105cb525c8SJens Axboe 101168fa9dbeSJens Axboe return ret; 101257dacad5SJay Sternberg } 101357dacad5SJay Sternberg 101457dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 101557dacad5SJay Sternberg { 101657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1017750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 101857dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1019d783e0bdSMarta Rybczynska return IRQ_NONE; 102057dacad5SJay Sternberg } 102157dacad5SJay Sternberg 10220b2a8a9fSChristoph Hellwig /* 1023fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 10240b2a8a9fSChristoph Hellwig * Can be called from any context. 10250b2a8a9fSChristoph Hellwig */ 1026fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1027a0fa9647SJens Axboe { 10283a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1029a0fa9647SJens Axboe 1030fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1031fa059b85SKeith Busch 10323a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1033fa059b85SKeith Busch nvme_process_cq(nvmeq); 10343a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 103591a509f8SChristoph Hellwig } 1036442e19b7SSagi Grimberg 10379743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10387776db1cSKeith Busch { 10397776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1040dabcefabSJens Axboe bool found; 1041dabcefabSJens Axboe 1042dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1043dabcefabSJens Axboe return 0; 1044dabcefabSJens Axboe 10453a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1046324b494cSKeith Busch found = nvme_process_cq(nvmeq); 10473a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1048dabcefabSJens Axboe 1049dabcefabSJens Axboe return found; 1050dabcefabSJens Axboe } 1051dabcefabSJens Axboe 1052ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 105357dacad5SJay Sternberg { 1054f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1055147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 105657dacad5SJay Sternberg struct nvme_command c; 105757dacad5SJay Sternberg 105857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 105957dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1060ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 106104f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 106257dacad5SJay Sternberg } 106357dacad5SJay Sternberg 106457dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 106557dacad5SJay Sternberg { 106657dacad5SJay Sternberg struct nvme_command c; 106757dacad5SJay Sternberg 106857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 106957dacad5SJay Sternberg c.delete_queue.opcode = opcode; 107057dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 107157dacad5SJay Sternberg 10721c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 107357dacad5SJay Sternberg } 107457dacad5SJay Sternberg 107557dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1076a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 107757dacad5SJay Sternberg { 107857dacad5SJay Sternberg struct nvme_command c; 10794b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 10804b04cc6aSJens Axboe 10817c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 10824b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 108357dacad5SJay Sternberg 108457dacad5SJay Sternberg /* 108516772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 108657dacad5SJay Sternberg * is attached to the request. 108757dacad5SJay Sternberg */ 108857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 108957dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 109057dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 109157dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 109257dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 109357dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1094a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 109557dacad5SJay Sternberg 10961c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 109757dacad5SJay Sternberg } 109857dacad5SJay Sternberg 109957dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 110057dacad5SJay Sternberg struct nvme_queue *nvmeq) 110157dacad5SJay Sternberg { 11029abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 110357dacad5SJay Sternberg struct nvme_command c; 110481c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 110557dacad5SJay Sternberg 110657dacad5SJay Sternberg /* 11079abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11089abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11099abd68efSJens Axboe * URGENT. 11109abd68efSJens Axboe */ 11119abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11129abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11139abd68efSJens Axboe 11149abd68efSJens Axboe /* 111516772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 111657dacad5SJay Sternberg * is attached to the request. 111757dacad5SJay Sternberg */ 111857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 111957dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 112057dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 112157dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 112257dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 112357dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 112457dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 112557dacad5SJay Sternberg 11261c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 112757dacad5SJay Sternberg } 112857dacad5SJay Sternberg 112957dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 113057dacad5SJay Sternberg { 113157dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 113257dacad5SJay Sternberg } 113357dacad5SJay Sternberg 113457dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 113557dacad5SJay Sternberg { 113657dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 113757dacad5SJay Sternberg } 113857dacad5SJay Sternberg 11392a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 114057dacad5SJay Sternberg { 1141f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1142f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 114357dacad5SJay Sternberg 114427fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 114527fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1146e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1147e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 114857dacad5SJay Sternberg } 114957dacad5SJay Sternberg 1150b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1151b2a0eb1aSKeith Busch { 1152b2a0eb1aSKeith Busch 1153b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1154b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1155b2a0eb1aSKeith Busch */ 1156b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1157b2a0eb1aSKeith Busch 1158ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1159ad70062cSJianchao Wang switch (dev->ctrl.state) { 1160ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1161ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1162b2a0eb1aSKeith Busch return false; 1163ad70062cSJianchao Wang default: 1164ad70062cSJianchao Wang break; 1165ad70062cSJianchao Wang } 1166b2a0eb1aSKeith Busch 1167b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1168b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1169b2a0eb1aSKeith Busch */ 1170b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1171b2a0eb1aSKeith Busch return false; 1172b2a0eb1aSKeith Busch 1173b2a0eb1aSKeith Busch return true; 1174b2a0eb1aSKeith Busch } 1175b2a0eb1aSKeith Busch 1176b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1177b2a0eb1aSKeith Busch { 1178b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1179b2a0eb1aSKeith Busch u16 pci_status; 1180b2a0eb1aSKeith Busch int result; 1181b2a0eb1aSKeith Busch 1182b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1183b2a0eb1aSKeith Busch &pci_status); 1184b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1185b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1186b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1187b2a0eb1aSKeith Busch csts, pci_status); 1188b2a0eb1aSKeith Busch else 1189b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1190b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1191b2a0eb1aSKeith Busch csts, result); 1192b2a0eb1aSKeith Busch } 1193b2a0eb1aSKeith Busch 119431c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 119557dacad5SJay Sternberg { 1196f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1197f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 119857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 119957dacad5SJay Sternberg struct request *abort_req; 120057dacad5SJay Sternberg struct nvme_command cmd; 1201b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1202b2a0eb1aSKeith Busch 1203651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1204651438bbSWen Xiong * the recovery mechanism will surely fail. 1205651438bbSWen Xiong */ 1206651438bbSWen Xiong mb(); 1207651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1208651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1209651438bbSWen Xiong 1210b2a0eb1aSKeith Busch /* 1211b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1212b2a0eb1aSKeith Busch */ 1213b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1214b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1215b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1216d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1217db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1218b2a0eb1aSKeith Busch } 121957dacad5SJay Sternberg 122031c7c7d2SChristoph Hellwig /* 12217776db1cSKeith Busch * Did we miss an interrupt? 12227776db1cSKeith Busch */ 1223fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1224fa059b85SKeith Busch nvme_poll(req->mq_hctx); 1225fa059b85SKeith Busch else 1226bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1227fa059b85SKeith Busch 1228bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 12297776db1cSKeith Busch dev_warn(dev->ctrl.device, 12307776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12317776db1cSKeith Busch req->tag, nvmeq->qid); 1232db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12337776db1cSKeith Busch } 12347776db1cSKeith Busch 12357776db1cSKeith Busch /* 1236fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1237fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1238fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1239db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1240fd634f41SChristoph Hellwig */ 12414244140dSKeith Busch switch (dev->ctrl.state) { 12424244140dSKeith Busch case NVME_CTRL_CONNECTING: 12432036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 12442036f726SKeith Busch /* fall through */ 12452036f726SKeith Busch case NVME_CTRL_DELETING: 1246b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1247fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1248fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 12492036f726SKeith Busch nvme_dev_disable(dev, true); 125027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1251db8c48e4SChristoph Hellwig return BLK_EH_DONE; 125239a9dd81SKeith Busch case NVME_CTRL_RESETTING: 125339a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 12544244140dSKeith Busch default: 12554244140dSKeith Busch break; 1256fd634f41SChristoph Hellwig } 1257fd634f41SChristoph Hellwig 1258fd634f41SChristoph Hellwig /* 1259e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1260e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1261e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 126231c7c7d2SChristoph Hellwig */ 1263f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12641b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 126557dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 126657dacad5SJay Sternberg req->tag, nvmeq->qid); 1267a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1268d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1269e1569a16SKeith Busch 127027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1271db8c48e4SChristoph Hellwig return BLK_EH_DONE; 127257dacad5SJay Sternberg } 127357dacad5SJay Sternberg 1274e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1275e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1276e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1277e7a2a87dSChristoph Hellwig } 12787bf7d778SKeith Busch iod->aborted = 1; 127957dacad5SJay Sternberg 128057dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 128157dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 128257dacad5SJay Sternberg cmd.abort.cid = req->tag; 128357dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 128457dacad5SJay Sternberg 12851b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12861b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 128757dacad5SJay Sternberg req->tag, nvmeq->qid); 1288e7a2a87dSChristoph Hellwig 1289e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1290eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12916bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12926bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 129331c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 129457dacad5SJay Sternberg } 129557dacad5SJay Sternberg 1296e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1297e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1298e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 129957dacad5SJay Sternberg 130057dacad5SJay Sternberg /* 130157dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 130257dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 130357dacad5SJay Sternberg * as the device then is in a faulty state. 130457dacad5SJay Sternberg */ 130557dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 130657dacad5SJay Sternberg } 130757dacad5SJay Sternberg 130857dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 130957dacad5SJay Sternberg { 13108a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 131157dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 131263223078SChristoph Hellwig if (!nvmeq->sq_cmds) 131363223078SChristoph Hellwig return; 13140f238ff5SLogan Gunthorpe 131563223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 131688a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13178a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 131863223078SChristoph Hellwig } else { 13198a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 132063223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13210f238ff5SLogan Gunthorpe } 132257dacad5SJay Sternberg } 132357dacad5SJay Sternberg 132457dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 132557dacad5SJay Sternberg { 132657dacad5SJay Sternberg int i; 132757dacad5SJay Sternberg 1328d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1329d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1330147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 133157dacad5SJay Sternberg } 133257dacad5SJay Sternberg } 133357dacad5SJay Sternberg 133457dacad5SJay Sternberg /** 133557dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 133640581d1aSBart Van Assche * @nvmeq: queue to suspend 133757dacad5SJay Sternberg */ 133857dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 133957dacad5SJay Sternberg { 13404e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 134157dacad5SJay Sternberg return 1; 134257dacad5SJay Sternberg 13434e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1344d1f06f4aSJens Axboe mb(); 134557dacad5SJay Sternberg 13464e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13471c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1348c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13497c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 13504e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 135157dacad5SJay Sternberg return 0; 135257dacad5SJay Sternberg } 135357dacad5SJay Sternberg 13548fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 13558fae268bSKeith Busch { 13568fae268bSKeith Busch int i; 13578fae268bSKeith Busch 13588fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 13598fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 13608fae268bSKeith Busch } 13618fae268bSKeith Busch 1362a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 136357dacad5SJay Sternberg { 1364147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 136557dacad5SJay Sternberg 1366a5cdb68cSKeith Busch if (shutdown) 1367a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1368a5cdb68cSKeith Busch else 1369b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 137057dacad5SJay Sternberg 1371bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 137257dacad5SJay Sternberg } 137357dacad5SJay Sternberg 1374fa46c6fbSKeith Busch /* 1375fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 1376fa46c6fbSKeith Busch * that can check this device's completion queues have synced. This is the 1377fa46c6fbSKeith Busch * last chance for the driver to see a natural completion before 1378fa46c6fbSKeith Busch * nvme_cancel_request() terminates all incomplete requests. 1379fa46c6fbSKeith Busch */ 1380fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1381fa46c6fbSKeith Busch { 1382fa46c6fbSKeith Busch int i; 1383fa46c6fbSKeith Busch 1384324b494cSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1385324b494cSKeith Busch nvme_process_cq(&dev->queues[i]); 1386fa46c6fbSKeith Busch } 1387fa46c6fbSKeith Busch 138857dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 138957dacad5SJay Sternberg int entry_size) 139057dacad5SJay Sternberg { 139157dacad5SJay Sternberg int q_depth = dev->q_depth; 13925fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13935fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 139457dacad5SJay Sternberg 139557dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 139657dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13975fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 139857dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 139957dacad5SJay Sternberg 140057dacad5SJay Sternberg /* 140157dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 140257dacad5SJay Sternberg * would be better to map queues in system memory with the 140357dacad5SJay Sternberg * original depth 140457dacad5SJay Sternberg */ 140557dacad5SJay Sternberg if (q_depth < 64) 140657dacad5SJay Sternberg return -ENOMEM; 140757dacad5SJay Sternberg } 140857dacad5SJay Sternberg 140957dacad5SJay Sternberg return q_depth; 141057dacad5SJay Sternberg } 141157dacad5SJay Sternberg 141257dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14138a1d09a6SBenjamin Herrenschmidt int qid) 141457dacad5SJay Sternberg { 14150f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1416815c6704SKeith Busch 14170f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14188a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1419bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14200f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14210f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 142263223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 142363223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 142463223078SChristoph Hellwig return 0; 142563223078SChristoph Hellwig } 1426bfac8e9fSAlan Mikhak 14278a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1428bfac8e9fSAlan Mikhak } 14290f238ff5SLogan Gunthorpe } 14300f238ff5SLogan Gunthorpe 14318a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 143257dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 143357dacad5SJay Sternberg if (!nvmeq->sq_cmds) 143457dacad5SJay Sternberg return -ENOMEM; 143557dacad5SJay Sternberg return 0; 143657dacad5SJay Sternberg } 143757dacad5SJay Sternberg 1438a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 143957dacad5SJay Sternberg { 1440147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 144157dacad5SJay Sternberg 144262314e40SKeith Busch if (dev->ctrl.queue_count > qid) 144362314e40SKeith Busch return 0; 144457dacad5SJay Sternberg 1445c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 14468a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 14478a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 144857dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 144957dacad5SJay Sternberg if (!nvmeq->cqes) 145057dacad5SJay Sternberg goto free_nvmeq; 145157dacad5SJay Sternberg 14528a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 145357dacad5SJay Sternberg goto free_cqdma; 145457dacad5SJay Sternberg 145557dacad5SJay Sternberg nvmeq->dev = dev; 14561ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14573a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 145857dacad5SJay Sternberg nvmeq->cq_head = 0; 145957dacad5SJay Sternberg nvmeq->cq_phase = 1; 146057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 146157dacad5SJay Sternberg nvmeq->qid = qid; 1462d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 146357dacad5SJay Sternberg 1464147b27e4SSagi Grimberg return 0; 146557dacad5SJay Sternberg 146657dacad5SJay Sternberg free_cqdma: 14678a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 146857dacad5SJay Sternberg nvmeq->cq_dma_addr); 146957dacad5SJay Sternberg free_nvmeq: 1470147b27e4SSagi Grimberg return -ENOMEM; 147157dacad5SJay Sternberg } 147257dacad5SJay Sternberg 1473dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 147457dacad5SJay Sternberg { 14750ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14760ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14770ff199cbSChristoph Hellwig 14780ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14790ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14800ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14810ff199cbSChristoph Hellwig } else { 14820ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14830ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14840ff199cbSChristoph Hellwig } 148557dacad5SJay Sternberg } 148657dacad5SJay Sternberg 148757dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 148857dacad5SJay Sternberg { 148957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 149057dacad5SJay Sternberg 149157dacad5SJay Sternberg nvmeq->sq_tail = 0; 149204f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 149357dacad5SJay Sternberg nvmeq->cq_head = 0; 149457dacad5SJay Sternberg nvmeq->cq_phase = 1; 149557dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 14968a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1497f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 149857dacad5SJay Sternberg dev->online_queues++; 14993a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 150057dacad5SJay Sternberg } 150157dacad5SJay Sternberg 15024b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 150357dacad5SJay Sternberg { 150457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 150557dacad5SJay Sternberg int result; 15067c349ddeSKeith Busch u16 vector = 0; 150757dacad5SJay Sternberg 1508d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1509d1ed6aa1SChristoph Hellwig 151022b55601SKeith Busch /* 151122b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 151222b55601SKeith Busch * has only one vector available. 151322b55601SKeith Busch */ 15144b04cc6aSJens Axboe if (!polled) 1515a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15164b04cc6aSJens Axboe else 15177c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15184b04cc6aSJens Axboe 1519a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1520ded45505SKeith Busch if (result) 1521ded45505SKeith Busch return result; 152257dacad5SJay Sternberg 152357dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 152457dacad5SJay Sternberg if (result < 0) 1525ded45505SKeith Busch return result; 1526c80b36cdSEdmund Nadolski if (result) 152757dacad5SJay Sternberg goto release_cq; 152857dacad5SJay Sternberg 1529a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1530161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15314b04cc6aSJens Axboe 15327c349ddeSKeith Busch if (!polled) { 1533dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 153457dacad5SJay Sternberg if (result < 0) 153557dacad5SJay Sternberg goto release_sq; 15364b04cc6aSJens Axboe } 153757dacad5SJay Sternberg 15384e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 153957dacad5SJay Sternberg return result; 154057dacad5SJay Sternberg 154157dacad5SJay Sternberg release_sq: 1542f25a2dfcSJianchao Wang dev->online_queues--; 154357dacad5SJay Sternberg adapter_delete_sq(dev, qid); 154457dacad5SJay Sternberg release_cq: 154557dacad5SJay Sternberg adapter_delete_cq(dev, qid); 154657dacad5SJay Sternberg return result; 154757dacad5SJay Sternberg } 154857dacad5SJay Sternberg 1549f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 155057dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 155177f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 155257dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 15530350815aSChristoph Hellwig .init_request = nvme_init_request, 155457dacad5SJay Sternberg .timeout = nvme_timeout, 155557dacad5SJay Sternberg }; 155657dacad5SJay Sternberg 1557f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1558376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1559376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1560376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1561376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1562376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1563376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1564376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1565c6d962aeSChristoph Hellwig .poll = nvme_poll, 1566dabcefabSJens Axboe }; 1567dabcefabSJens Axboe 156857dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 156957dacad5SJay Sternberg { 15701c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 157169d9a99cSKeith Busch /* 157269d9a99cSKeith Busch * If the controller was reset during removal, it's possible 157369d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 157469d9a99cSKeith Busch * queue to flush these to completion. 157569d9a99cSKeith Busch */ 1576c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15771c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 157857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 157957dacad5SJay Sternberg } 158057dacad5SJay Sternberg } 158157dacad5SJay Sternberg 158257dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 158357dacad5SJay Sternberg { 15841c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 158557dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 158657dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1587e3e9d50cSKeith Busch 158838dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 158957dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 159057dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1591d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1592d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 159357dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 159457dacad5SJay Sternberg 159557dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 159657dacad5SJay Sternberg return -ENOMEM; 159734b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 159857dacad5SJay Sternberg 15991c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16001c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 160157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 160257dacad5SJay Sternberg return -ENOMEM; 160357dacad5SJay Sternberg } 16041c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 160557dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16061c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 160757dacad5SJay Sternberg return -ENODEV; 160857dacad5SJay Sternberg } 160957dacad5SJay Sternberg } else 1610c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 161157dacad5SJay Sternberg 161257dacad5SJay Sternberg return 0; 161357dacad5SJay Sternberg } 161457dacad5SJay Sternberg 161597f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 161697f6ef64SXu Yu { 161797f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 161897f6ef64SXu Yu } 161997f6ef64SXu Yu 162097f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 162197f6ef64SXu Yu { 162297f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 162397f6ef64SXu Yu 162497f6ef64SXu Yu if (size <= dev->bar_mapped_size) 162597f6ef64SXu Yu return 0; 162697f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 162797f6ef64SXu Yu return -ENOMEM; 162897f6ef64SXu Yu if (dev->bar) 162997f6ef64SXu Yu iounmap(dev->bar); 163097f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 163197f6ef64SXu Yu if (!dev->bar) { 163297f6ef64SXu Yu dev->bar_mapped_size = 0; 163397f6ef64SXu Yu return -ENOMEM; 163497f6ef64SXu Yu } 163597f6ef64SXu Yu dev->bar_mapped_size = size; 163697f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 163797f6ef64SXu Yu 163897f6ef64SXu Yu return 0; 163997f6ef64SXu Yu } 164097f6ef64SXu Yu 164101ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 164257dacad5SJay Sternberg { 164357dacad5SJay Sternberg int result; 164457dacad5SJay Sternberg u32 aqa; 164557dacad5SJay Sternberg struct nvme_queue *nvmeq; 164657dacad5SJay Sternberg 164797f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 164897f6ef64SXu Yu if (result < 0) 164997f6ef64SXu Yu return result; 165097f6ef64SXu Yu 16518ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 165220d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 165357dacad5SJay Sternberg 16547a67cbeaSChristoph Hellwig if (dev->subsystem && 16557a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16567a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 165757dacad5SJay Sternberg 1658b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 165957dacad5SJay Sternberg if (result < 0) 166057dacad5SJay Sternberg return result; 166157dacad5SJay Sternberg 1662a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1663147b27e4SSagi Grimberg if (result) 1664147b27e4SSagi Grimberg return result; 166557dacad5SJay Sternberg 1666147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 166757dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 166857dacad5SJay Sternberg aqa |= aqa << 16; 166957dacad5SJay Sternberg 16707a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16717a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16727a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 167357dacad5SJay Sternberg 1674c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 167557dacad5SJay Sternberg if (result) 1676d4875622SKeith Busch return result; 167757dacad5SJay Sternberg 167857dacad5SJay Sternberg nvmeq->cq_vector = 0; 1679161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1680dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 168157dacad5SJay Sternberg if (result) { 16827c349ddeSKeith Busch dev->online_queues--; 1683d4875622SKeith Busch return result; 168457dacad5SJay Sternberg } 168557dacad5SJay Sternberg 16864e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 168757dacad5SJay Sternberg return result; 168857dacad5SJay Sternberg } 168957dacad5SJay Sternberg 1690749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 169157dacad5SJay Sternberg { 16924b04cc6aSJens Axboe unsigned i, max, rw_queues; 1693749941f2SChristoph Hellwig int ret = 0; 169457dacad5SJay Sternberg 1695d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1696a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1697749941f2SChristoph Hellwig ret = -ENOMEM; 169857dacad5SJay Sternberg break; 1699749941f2SChristoph Hellwig } 1700749941f2SChristoph Hellwig } 170157dacad5SJay Sternberg 1702d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1703e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1704e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1705e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17064b04cc6aSJens Axboe } else { 17074b04cc6aSJens Axboe rw_queues = max; 17084b04cc6aSJens Axboe } 17094b04cc6aSJens Axboe 1710949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17114b04cc6aSJens Axboe bool polled = i > rw_queues; 17124b04cc6aSJens Axboe 17134b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1714d4875622SKeith Busch if (ret) 171557dacad5SJay Sternberg break; 171657dacad5SJay Sternberg } 171757dacad5SJay Sternberg 1718749941f2SChristoph Hellwig /* 1719749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17208adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17218adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1722749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1723749941f2SChristoph Hellwig */ 1724749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 172557dacad5SJay Sternberg } 172657dacad5SJay Sternberg 1727202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1728202021c1SStephen Bates struct device_attribute *attr, 1729202021c1SStephen Bates char *buf) 1730202021c1SStephen Bates { 1731202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1732202021c1SStephen Bates 1733c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1734202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1735202021c1SStephen Bates } 1736202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1737202021c1SStephen Bates 173888de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 173957dacad5SJay Sternberg { 174088de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 174188de4598SChristoph Hellwig 174288de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 174388de4598SChristoph Hellwig } 174488de4598SChristoph Hellwig 174588de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 174688de4598SChristoph Hellwig { 174788de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 174888de4598SChristoph Hellwig } 174988de4598SChristoph Hellwig 1750f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 175157dacad5SJay Sternberg { 175288de4598SChristoph Hellwig u64 size, offset; 175357dacad5SJay Sternberg resource_size_t bar_size; 175457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17558969f1f8SChristoph Hellwig int bar; 175657dacad5SJay Sternberg 17579fe5c59fSKeith Busch if (dev->cmb_size) 17589fe5c59fSKeith Busch return; 17599fe5c59fSKeith Busch 17607a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1761f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1762f65efd6dSChristoph Hellwig return; 1763202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 176457dacad5SJay Sternberg 176588de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 176688de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17678969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17688969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 176957dacad5SJay Sternberg 177057dacad5SJay Sternberg if (offset > bar_size) 1771f65efd6dSChristoph Hellwig return; 177257dacad5SJay Sternberg 177357dacad5SJay Sternberg /* 177457dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 177557dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 177657dacad5SJay Sternberg * the reported size of the BAR 177757dacad5SJay Sternberg */ 177857dacad5SJay Sternberg if (size > bar_size - offset) 177957dacad5SJay Sternberg size = bar_size - offset; 178057dacad5SJay Sternberg 17810f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 17820f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 17830f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1784f65efd6dSChristoph Hellwig return; 17850f238ff5SLogan Gunthorpe } 17860f238ff5SLogan Gunthorpe 178757dacad5SJay Sternberg dev->cmb_size = size; 17880f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 17890f238ff5SLogan Gunthorpe 17900f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 17910f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 17920f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1793f65efd6dSChristoph Hellwig 1794f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1795f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1796f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1797f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 179857dacad5SJay Sternberg } 179957dacad5SJay Sternberg 180057dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 180157dacad5SJay Sternberg { 18020f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1803f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1804f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18050f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1806f63572dfSJon Derrick } 180757dacad5SJay Sternberg } 180857dacad5SJay Sternberg 180987ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 181057dacad5SJay Sternberg { 18114033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 181287ad72a5SChristoph Hellwig struct nvme_command c; 181387ad72a5SChristoph Hellwig int ret; 181487ad72a5SChristoph Hellwig 181587ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 181687ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 181787ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 181887ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 181987ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 182087ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 182187ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 182287ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 182387ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 182487ad72a5SChristoph Hellwig 182587ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 182687ad72a5SChristoph Hellwig if (ret) { 182787ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 182887ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 182987ad72a5SChristoph Hellwig ret, bits); 183087ad72a5SChristoph Hellwig } 183187ad72a5SChristoph Hellwig return ret; 183287ad72a5SChristoph Hellwig } 183387ad72a5SChristoph Hellwig 183487ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 183587ad72a5SChristoph Hellwig { 183687ad72a5SChristoph Hellwig int i; 183787ad72a5SChristoph Hellwig 183887ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 183987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 184087ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 184187ad72a5SChristoph Hellwig 1842cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1843cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1844cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 184587ad72a5SChristoph Hellwig } 184687ad72a5SChristoph Hellwig 184787ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 184887ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18494033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18504033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18514033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 185287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18537e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 185487ad72a5SChristoph Hellwig } 185587ad72a5SChristoph Hellwig 185692dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 185792dc6895SChristoph Hellwig u32 chunk_size) 185887ad72a5SChristoph Hellwig { 185987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 186092dc6895SChristoph Hellwig u32 max_entries, len; 18614033f35dSChristoph Hellwig dma_addr_t descs_dma; 18622ee0e4edSDan Carpenter int i = 0; 186387ad72a5SChristoph Hellwig void **bufs; 18646fbcde66SMinwoo Im u64 size, tmp; 186587ad72a5SChristoph Hellwig 186687ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 186787ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 186887ad72a5SChristoph Hellwig max_entries = tmp; 1869044a9df1SChristoph Hellwig 1870044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1871044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1872044a9df1SChristoph Hellwig 1873750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 18744033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 187587ad72a5SChristoph Hellwig if (!descs) 187687ad72a5SChristoph Hellwig goto out; 187787ad72a5SChristoph Hellwig 187887ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 187987ad72a5SChristoph Hellwig if (!bufs) 188087ad72a5SChristoph Hellwig goto out_free_descs; 188187ad72a5SChristoph Hellwig 1882244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 188387ad72a5SChristoph Hellwig dma_addr_t dma_addr; 188487ad72a5SChristoph Hellwig 188550cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 188687ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 188787ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 188887ad72a5SChristoph Hellwig if (!bufs[i]) 188987ad72a5SChristoph Hellwig break; 189087ad72a5SChristoph Hellwig 189187ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 189287ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 189387ad72a5SChristoph Hellwig i++; 189487ad72a5SChristoph Hellwig } 189587ad72a5SChristoph Hellwig 189692dc6895SChristoph Hellwig if (!size) 189787ad72a5SChristoph Hellwig goto out_free_bufs; 189887ad72a5SChristoph Hellwig 189987ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 190087ad72a5SChristoph Hellwig dev->host_mem_size = size; 190187ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19024033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 190387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 190487ad72a5SChristoph Hellwig return 0; 190587ad72a5SChristoph Hellwig 190687ad72a5SChristoph Hellwig out_free_bufs: 190787ad72a5SChristoph Hellwig while (--i >= 0) { 190887ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 190987ad72a5SChristoph Hellwig 1910cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1911cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1912cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 191387ad72a5SChristoph Hellwig } 191487ad72a5SChristoph Hellwig 191587ad72a5SChristoph Hellwig kfree(bufs); 191687ad72a5SChristoph Hellwig out_free_descs: 19174033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19184033f35dSChristoph Hellwig descs_dma); 191987ad72a5SChristoph Hellwig out: 192087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 192187ad72a5SChristoph Hellwig return -ENOMEM; 192287ad72a5SChristoph Hellwig } 192387ad72a5SChristoph Hellwig 192492dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 192592dc6895SChristoph Hellwig { 192692dc6895SChristoph Hellwig u32 chunk_size; 192792dc6895SChristoph Hellwig 192892dc6895SChristoph Hellwig /* start big and work our way down */ 192930f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1930044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 193192dc6895SChristoph Hellwig chunk_size /= 2) { 193292dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 193392dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 193492dc6895SChristoph Hellwig return 0; 193592dc6895SChristoph Hellwig nvme_free_host_mem(dev); 193692dc6895SChristoph Hellwig } 193792dc6895SChristoph Hellwig } 193892dc6895SChristoph Hellwig 193992dc6895SChristoph Hellwig return -ENOMEM; 194092dc6895SChristoph Hellwig } 194192dc6895SChristoph Hellwig 19429620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 194387ad72a5SChristoph Hellwig { 194487ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 194587ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 194687ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 194787ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19486fbcde66SMinwoo Im int ret; 194987ad72a5SChristoph Hellwig 195087ad72a5SChristoph Hellwig preferred = min(preferred, max); 195187ad72a5SChristoph Hellwig if (min > max) { 195287ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 195387ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 195487ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 195587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19569620cfbaSChristoph Hellwig return 0; 195787ad72a5SChristoph Hellwig } 195887ad72a5SChristoph Hellwig 195987ad72a5SChristoph Hellwig /* 196087ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 196187ad72a5SChristoph Hellwig */ 196287ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 196387ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 196487ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 196587ad72a5SChristoph Hellwig else 196687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 196787ad72a5SChristoph Hellwig } 196887ad72a5SChristoph Hellwig 196987ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 197092dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 197192dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 197292dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 19739620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 197487ad72a5SChristoph Hellwig } 197587ad72a5SChristoph Hellwig 197692dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 197792dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 197892dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 197992dc6895SChristoph Hellwig } 198092dc6895SChristoph Hellwig 19819620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 19829620cfbaSChristoph Hellwig if (ret) 198387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19849620cfbaSChristoph Hellwig return ret; 198557dacad5SJay Sternberg } 198657dacad5SJay Sternberg 1987612b7286SMing Lei /* 1988612b7286SMing Lei * nirqs is the number of interrupts available for write and read 1989612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 1990612b7286SMing Lei */ 1991612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 19923b6592f7SJens Axboe { 1993612b7286SMing Lei struct nvme_dev *dev = affd->priv; 1994612b7286SMing Lei unsigned int nr_read_queues; 1995c45b1fa2SMing Lei 19963b6592f7SJens Axboe /* 1997612b7286SMing Lei * If there is no interupt available for queues, ensure that 1998612b7286SMing Lei * the default queue is set to 1. The affinity set size is 1999612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2000612b7286SMing Lei * 2001612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2002612b7286SMing Lei * write and read queues. 2003612b7286SMing Lei * 2004612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2005612b7286SMing Lei * queue. 20063b6592f7SJens Axboe */ 2007612b7286SMing Lei if (!nrirqs) { 2008612b7286SMing Lei nrirqs = 1; 2009612b7286SMing Lei nr_read_queues = 0; 2010612b7286SMing Lei } else if (nrirqs == 1 || !write_queues) { 2011612b7286SMing Lei nr_read_queues = 0; 2012612b7286SMing Lei } else if (write_queues >= nrirqs) { 2013612b7286SMing Lei nr_read_queues = 1; 20143b6592f7SJens Axboe } else { 2015612b7286SMing Lei nr_read_queues = nrirqs - write_queues; 20163b6592f7SJens Axboe } 2017612b7286SMing Lei 2018612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2019612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2020612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2021612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2022612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20233b6592f7SJens Axboe } 20243b6592f7SJens Axboe 20256451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20263b6592f7SJens Axboe { 20273b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20283b6592f7SJens Axboe struct irq_affinity affd = { 20293b6592f7SJens Axboe .pre_vectors = 1, 2030612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2031612b7286SMing Lei .priv = dev, 20323b6592f7SJens Axboe }; 20336451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20346451fe73SJens Axboe 20356451fe73SJens Axboe /* 20366451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20376451fe73SJens Axboe * queue left over for non-polled IO. 20386451fe73SJens Axboe */ 20396451fe73SJens Axboe this_p_queues = poll_queues; 20406451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20416451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20426451fe73SJens Axboe irq_queues = 1; 20436451fe73SJens Axboe } else { 2044c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20456451fe73SJens Axboe } 20466451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20473b6592f7SJens Axboe 2048612b7286SMing Lei /* Initialize for the single interrupt case */ 2049612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2050612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20513b6592f7SJens Axboe 205266341331SBenjamin Herrenschmidt /* 205366341331SBenjamin Herrenschmidt * Some Apple controllers require all queues to use the 205466341331SBenjamin Herrenschmidt * first vector. 205566341331SBenjamin Herrenschmidt */ 205666341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 205766341331SBenjamin Herrenschmidt irq_queues = 1; 205866341331SBenjamin Herrenschmidt 2059612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20603b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20613b6592f7SJens Axboe } 20623b6592f7SJens Axboe 20638fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 20648fae268bSKeith Busch { 20658fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 20668fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 20678fae268bSKeith Busch } 20688fae268bSKeith Busch 206957dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 207057dacad5SJay Sternberg { 2071147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 207257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 207397f6ef64SXu Yu int result, nr_io_queues; 207497f6ef64SXu Yu unsigned long size; 207557dacad5SJay Sternberg 20763b6592f7SJens Axboe nr_io_queues = max_io_queues(); 2077d38e9f04SBenjamin Herrenschmidt 2078d38e9f04SBenjamin Herrenschmidt /* 2079d38e9f04SBenjamin Herrenschmidt * If tags are shared with admin queue (Apple bug), then 2080d38e9f04SBenjamin Herrenschmidt * make sure we only use one IO queue. 2081d38e9f04SBenjamin Herrenschmidt */ 2082d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2083d38e9f04SBenjamin Herrenschmidt nr_io_queues = 1; 2084d38e9f04SBenjamin Herrenschmidt 20859a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 20869a0be7abSChristoph Hellwig if (result < 0) 208757dacad5SJay Sternberg return result; 20889a0be7abSChristoph Hellwig 2089f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2090a5229050SKeith Busch return 0; 209157dacad5SJay Sternberg 20924e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 20934e224106SChristoph Hellwig 20940f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 209557dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 209657dacad5SJay Sternberg sizeof(struct nvme_command)); 209757dacad5SJay Sternberg if (result > 0) 209857dacad5SJay Sternberg dev->q_depth = result; 209957dacad5SJay Sternberg else 21000f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 210157dacad5SJay Sternberg } 210257dacad5SJay Sternberg 210357dacad5SJay Sternberg do { 210497f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 210597f6ef64SXu Yu result = nvme_remap_bar(dev, size); 210697f6ef64SXu Yu if (!result) 210757dacad5SJay Sternberg break; 210857dacad5SJay Sternberg if (!--nr_io_queues) 210957dacad5SJay Sternberg return -ENOMEM; 211057dacad5SJay Sternberg } while (1); 211157dacad5SJay Sternberg adminq->q_db = dev->dbs; 211257dacad5SJay Sternberg 21138fae268bSKeith Busch retry: 211457dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21150ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 211657dacad5SJay Sternberg 211757dacad5SJay Sternberg /* 211857dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 211957dacad5SJay Sternberg * setting up the full range we need. 212057dacad5SJay Sternberg */ 2121dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21223b6592f7SJens Axboe 21233b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 212422b55601SKeith Busch if (result <= 0) 2125dca51e78SChristoph Hellwig return -EIO; 21263b6592f7SJens Axboe 212722b55601SKeith Busch dev->num_vecs = result; 21284b04cc6aSJens Axboe result = max(result - 1, 1); 2129e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 213057dacad5SJay Sternberg 213157dacad5SJay Sternberg /* 213257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 213357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 213457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 213557dacad5SJay Sternberg * number of interrupts. 213657dacad5SJay Sternberg */ 2137dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21387c349ddeSKeith Busch if (result) 2139d4875622SKeith Busch return result; 21404e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21418fae268bSKeith Busch 21428fae268bSKeith Busch result = nvme_create_io_queues(dev); 21438fae268bSKeith Busch if (result || dev->online_queues < 2) 21448fae268bSKeith Busch return result; 21458fae268bSKeith Busch 21468fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21478fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21488fae268bSKeith Busch nvme_disable_io_queues(dev); 21498fae268bSKeith Busch nvme_suspend_io_queues(dev); 21508fae268bSKeith Busch goto retry; 21518fae268bSKeith Busch } 21528fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21538fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21548fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21558fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21568fae268bSKeith Busch return 0; 215757dacad5SJay Sternberg } 215857dacad5SJay Sternberg 21592a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2160db3cbfffSKeith Busch { 2161db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2162db3cbfffSKeith Busch 2163db3cbfffSKeith Busch blk_mq_free_request(req); 2164d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2165db3cbfffSKeith Busch } 2166db3cbfffSKeith Busch 21672a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2168db3cbfffSKeith Busch { 2169db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2170db3cbfffSKeith Busch 2171d1ed6aa1SChristoph Hellwig if (error) 2172d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2173db3cbfffSKeith Busch 2174db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2175db3cbfffSKeith Busch } 2176db3cbfffSKeith Busch 2177db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2178db3cbfffSKeith Busch { 2179db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2180db3cbfffSKeith Busch struct request *req; 2181db3cbfffSKeith Busch struct nvme_command cmd; 2182db3cbfffSKeith Busch 2183db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2184db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2185db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2186db3cbfffSKeith Busch 2187eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2188db3cbfffSKeith Busch if (IS_ERR(req)) 2189db3cbfffSKeith Busch return PTR_ERR(req); 2190db3cbfffSKeith Busch 2191db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2192db3cbfffSKeith Busch req->end_io_data = nvmeq; 2193db3cbfffSKeith Busch 2194d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2195db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2196db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2197db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2198db3cbfffSKeith Busch return 0; 2199db3cbfffSKeith Busch } 2200db3cbfffSKeith Busch 22018fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2202db3cbfffSKeith Busch { 22035271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2204db3cbfffSKeith Busch unsigned long timeout; 2205db3cbfffSKeith Busch 2206db3cbfffSKeith Busch retry: 2207db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22085271edd4SChristoph Hellwig while (nr_queues > 0) { 22095271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2210db3cbfffSKeith Busch break; 22115271edd4SChristoph Hellwig nr_queues--; 22125271edd4SChristoph Hellwig sent++; 22135271edd4SChristoph Hellwig } 2214d1ed6aa1SChristoph Hellwig while (sent) { 2215d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2216d1ed6aa1SChristoph Hellwig 2217d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22185271edd4SChristoph Hellwig timeout); 2219db3cbfffSKeith Busch if (timeout == 0) 22205271edd4SChristoph Hellwig return false; 2221d1ed6aa1SChristoph Hellwig 2222d1ed6aa1SChristoph Hellwig sent--; 22235271edd4SChristoph Hellwig if (nr_queues) 2224db3cbfffSKeith Busch goto retry; 2225db3cbfffSKeith Busch } 22265271edd4SChristoph Hellwig return true; 2227db3cbfffSKeith Busch } 2228db3cbfffSKeith Busch 22295d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 223057dacad5SJay Sternberg { 22312b1b7e78SJianchao Wang int ret; 22322b1b7e78SJianchao Wang 22335bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2234c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 223557dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 22368fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2237ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2238ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 223957dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 224057dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 224157dacad5SJay Sternberg dev->tagset.queue_depth = 224257dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2243d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 224457dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 224557dacad5SJay Sternberg dev->tagset.driver_data = dev; 224657dacad5SJay Sternberg 2247d38e9f04SBenjamin Herrenschmidt /* 2248d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2249d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2250d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2251d38e9f04SBenjamin Herrenschmidt */ 2252d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2253d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2254d38e9f04SBenjamin Herrenschmidt 22552b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22562b1b7e78SJianchao Wang if (ret) { 22572b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22582b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22595d02a5c1SKeith Busch return; 22602b1b7e78SJianchao Wang } 22615bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2262949928c1SKeith Busch } else { 2263949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2264949928c1SKeith Busch 2265949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2266949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 226757dacad5SJay Sternberg } 2268949928c1SKeith Busch 2269e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 227057dacad5SJay Sternberg } 227157dacad5SJay Sternberg 2272b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 227357dacad5SJay Sternberg { 2274b00a726aSKeith Busch int result = -ENOMEM; 227557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 227657dacad5SJay Sternberg 227757dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 227857dacad5SJay Sternberg return result; 227957dacad5SJay Sternberg 228057dacad5SJay Sternberg pci_set_master(pdev); 228157dacad5SJay Sternberg 22824fe06923SChristoph Hellwig if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 228357dacad5SJay Sternberg goto disable; 228457dacad5SJay Sternberg 22857a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 228657dacad5SJay Sternberg result = -ENODEV; 2287b00a726aSKeith Busch goto disable; 228857dacad5SJay Sternberg } 228957dacad5SJay Sternberg 229057dacad5SJay Sternberg /* 2291a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2292a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2293a5229050SKeith Busch * adjust this later. 229457dacad5SJay Sternberg */ 2295dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2296dca51e78SChristoph Hellwig if (result < 0) 2297dca51e78SChristoph Hellwig return result; 229857dacad5SJay Sternberg 229920d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23007a67cbeaSChristoph Hellwig 230120d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2302b27c1e68Sweiping zhang io_queue_depth); 2303aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 230420d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23057a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23061f390c1fSStephan Günther 23071f390c1fSStephan Günther /* 230866341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 230966341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 231066341331SBenjamin Herrenschmidt * so we don't bother updating it here. 231166341331SBenjamin Herrenschmidt */ 231266341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 231366341331SBenjamin Herrenschmidt dev->io_sqes = 7; 231466341331SBenjamin Herrenschmidt else 2315c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 23161f390c1fSStephan Günther 23171f390c1fSStephan Günther /* 23181f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23191f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23201f390c1fSStephan Günther */ 23211f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23221f390c1fSStephan Günther dev->q_depth = 2; 23239bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23249bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23251f390c1fSStephan Günther dev->q_depth); 2326d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2327d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 232820d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2329d554b5e1SMartin K. Petersen dev->q_depth = 64; 2330d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2331d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23321f390c1fSStephan Günther } 23331f390c1fSStephan Günther 2334d38e9f04SBenjamin Herrenschmidt /* 2335d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2336d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2337d38e9f04SBenjamin Herrenschmidt */ 2338d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2339d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2340d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2341d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2342d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2343d38e9f04SBenjamin Herrenschmidt } 2344d38e9f04SBenjamin Herrenschmidt 2345d38e9f04SBenjamin Herrenschmidt 2346f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2347202021c1SStephen Bates 2348a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2349a0a3408eSKeith Busch pci_save_state(pdev); 235057dacad5SJay Sternberg return 0; 235157dacad5SJay Sternberg 235257dacad5SJay Sternberg disable: 235357dacad5SJay Sternberg pci_disable_device(pdev); 235457dacad5SJay Sternberg return result; 235557dacad5SJay Sternberg } 235657dacad5SJay Sternberg 235757dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 235857dacad5SJay Sternberg { 2359b00a726aSKeith Busch if (dev->bar) 2360b00a726aSKeith Busch iounmap(dev->bar); 2361a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2362b00a726aSKeith Busch } 2363b00a726aSKeith Busch 2364b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2365b00a726aSKeith Busch { 236657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 236757dacad5SJay Sternberg 2368dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 236957dacad5SJay Sternberg 2370a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2371a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 237257dacad5SJay Sternberg pci_disable_device(pdev); 237357dacad5SJay Sternberg } 2374a0a3408eSKeith Busch } 237557dacad5SJay Sternberg 2376a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 237757dacad5SJay Sternberg { 2378e43269e6SKeith Busch bool dead = true, freeze = false; 2379302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 238057dacad5SJay Sternberg 238177bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2382302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2383302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2384302ad8ccSKeith Busch 2385ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2386e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2387e43269e6SKeith Busch freeze = true; 2388302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2389e43269e6SKeith Busch } 2390302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2391302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 239257dacad5SJay Sternberg } 2393c21377f8SGabriel Krisman Bertazi 2394302ad8ccSKeith Busch /* 2395302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2396302ad8ccSKeith Busch * doing a safe shutdown. 2397302ad8ccSKeith Busch */ 2398e43269e6SKeith Busch if (!dead && shutdown && freeze) 2399302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 240087ad72a5SChristoph Hellwig 24019a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24029a915a5bSJianchao Wang 240364ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24048fae268bSKeith Busch nvme_disable_io_queues(dev); 2405a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 240657dacad5SJay Sternberg } 24078fae268bSKeith Busch nvme_suspend_io_queues(dev); 24088fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2409b00a726aSKeith Busch nvme_pci_disable(dev); 2410fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 241157dacad5SJay Sternberg 2412e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2413e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2414622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2415622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2416302ad8ccSKeith Busch 2417302ad8ccSKeith Busch /* 2418302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2419302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2420302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2421302ad8ccSKeith Busch */ 2422c8e9e9b7SKeith Busch if (shutdown) { 2423302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2424c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2425c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2426c8e9e9b7SKeith Busch } 242777bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 242857dacad5SJay Sternberg } 242957dacad5SJay Sternberg 2430c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2431c1ac9a4bSKeith Busch { 2432c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2433c1ac9a4bSKeith Busch return -EBUSY; 2434c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2435c1ac9a4bSKeith Busch return 0; 2436c1ac9a4bSKeith Busch } 2437c1ac9a4bSKeith Busch 243857dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 243957dacad5SJay Sternberg { 244057dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 244157dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 244257dacad5SJay Sternberg if (!dev->prp_page_pool) 244357dacad5SJay Sternberg return -ENOMEM; 244457dacad5SJay Sternberg 244557dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 244657dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 244757dacad5SJay Sternberg 256, 256, 0); 244857dacad5SJay Sternberg if (!dev->prp_small_pool) { 244957dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 245057dacad5SJay Sternberg return -ENOMEM; 245157dacad5SJay Sternberg } 245257dacad5SJay Sternberg return 0; 245357dacad5SJay Sternberg } 245457dacad5SJay Sternberg 245557dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 245657dacad5SJay Sternberg { 245757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 245857dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 245957dacad5SJay Sternberg } 246057dacad5SJay Sternberg 2461770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2462770597ecSKeith Busch { 2463770597ecSKeith Busch if (dev->tagset.tags) 2464770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2465770597ecSKeith Busch dev->ctrl.tagset = NULL; 2466770597ecSKeith Busch } 2467770597ecSKeith Busch 24681673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 246957dacad5SJay Sternberg { 24701673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 247157dacad5SJay Sternberg 2472f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 247357dacad5SJay Sternberg put_device(dev->dev); 2474770597ecSKeith Busch nvme_free_tagset(dev); 24751c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24761c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 247757dacad5SJay Sternberg kfree(dev->queues); 2478e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2479943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 248057dacad5SJay Sternberg kfree(dev); 248157dacad5SJay Sternberg } 248257dacad5SJay Sternberg 24837c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2484f58944e2SKeith Busch { 2485c1ac9a4bSKeith Busch /* 2486c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2487c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2488c1ac9a4bSKeith Busch */ 2489c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2490d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 249169d9a99cSKeith Busch nvme_dev_disable(dev, false); 24929f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 249303e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2494f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2495f58944e2SKeith Busch } 2496f58944e2SKeith Busch 2497fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 249857dacad5SJay Sternberg { 2499d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2500d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2501a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2502e71afda4SChaitanya Kulkarni int result; 250357dacad5SJay Sternberg 2504e71afda4SChaitanya Kulkarni if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2505e71afda4SChaitanya Kulkarni result = -ENODEV; 2506fd634f41SChristoph Hellwig goto out; 2507e71afda4SChaitanya Kulkarni } 2508fd634f41SChristoph Hellwig 2509fd634f41SChristoph Hellwig /* 2510fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2511fd634f41SChristoph Hellwig * moving on. 2512fd634f41SChristoph Hellwig */ 2513b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2514a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2515d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2516fd634f41SChristoph Hellwig 25175c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2518b00a726aSKeith Busch result = nvme_pci_enable(dev); 251957dacad5SJay Sternberg if (result) 25204726bcf3SKeith Busch goto out_unlock; 252157dacad5SJay Sternberg 252201ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 252357dacad5SJay Sternberg if (result) 25244726bcf3SKeith Busch goto out_unlock; 252557dacad5SJay Sternberg 252657dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 252757dacad5SJay Sternberg if (result) 25284726bcf3SKeith Busch goto out_unlock; 252957dacad5SJay Sternberg 2530943e942eSJens Axboe /* 2531943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2532943e942eSJens Axboe * over a single page. 2533943e942eSJens Axboe */ 25347637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 25357637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2536943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2537a48bc520SChristoph Hellwig 2538a48bc520SChristoph Hellwig /* 2539a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2540a48bc520SChristoph Hellwig */ 2541a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 2542a48bc520SChristoph Hellwig 25435c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25445c959d73SKeith Busch 25455c959d73SKeith Busch /* 25465c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25475c959d73SKeith Busch * initializing procedure here. 25485c959d73SKeith Busch */ 25495c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25505c959d73SKeith Busch dev_warn(dev->ctrl.device, 25515c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2552cee6c269SMinwoo Im result = -EBUSY; 25535c959d73SKeith Busch goto out; 25545c959d73SKeith Busch } 2555943e942eSJens Axboe 2556ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2557ce4541f4SChristoph Hellwig if (result) 2558f58944e2SKeith Busch goto out; 2559ce4541f4SChristoph Hellwig 2560e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2561e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25624f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25634f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2564e286bcfcSScott Bauer else if (was_suspend) 25654f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2566e286bcfcSScott Bauer } else { 2567e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2568e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2569e286bcfcSScott Bauer } 2570a98e58e5SScott Bauer 2571f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2572f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2573f9f38e33SHelen Koike if (result) 2574f9f38e33SHelen Koike dev_warn(dev->dev, 2575f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2576f9f38e33SHelen Koike } 2577f9f38e33SHelen Koike 25789620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25799620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25809620cfbaSChristoph Hellwig if (result < 0) 25819620cfbaSChristoph Hellwig goto out; 25829620cfbaSChristoph Hellwig } 258387ad72a5SChristoph Hellwig 258457dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 258557dacad5SJay Sternberg if (result) 2586f58944e2SKeith Busch goto out; 258757dacad5SJay Sternberg 258821f033f7SKeith Busch /* 258957dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 259057dacad5SJay Sternberg * any working I/O queue. 259157dacad5SJay Sternberg */ 259257dacad5SJay Sternberg if (dev->online_queues < 2) { 25931b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25943b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25955bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2596770597ecSKeith Busch nvme_free_tagset(dev); 259757dacad5SJay Sternberg } else { 259825646264SKeith Busch nvme_start_queues(&dev->ctrl); 2599302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26005d02a5c1SKeith Busch nvme_dev_add(dev); 2601302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 260257dacad5SJay Sternberg } 260357dacad5SJay Sternberg 26042b1b7e78SJianchao Wang /* 26052b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26062b1b7e78SJianchao Wang * recovery. 26072b1b7e78SJianchao Wang */ 26085d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 26092b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26105d02a5c1SKeith Busch "failed to mark controller live state\n"); 2611e71afda4SChaitanya Kulkarni result = -ENODEV; 2612bb8d261eSChristoph Hellwig goto out; 2613bb8d261eSChristoph Hellwig } 261492911a55SChristoph Hellwig 2615d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 261657dacad5SJay Sternberg return; 261757dacad5SJay Sternberg 26184726bcf3SKeith Busch out_unlock: 26194726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 262057dacad5SJay Sternberg out: 26217c1ce408SChaitanya Kulkarni if (result) 26227c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 26237c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 26247c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 262557dacad5SJay Sternberg } 262657dacad5SJay Sternberg 26275c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 262857dacad5SJay Sternberg { 26295c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 263057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 263157dacad5SJay Sternberg 263257dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2633921920abSKeith Busch device_release_driver(&pdev->dev); 26341673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 263557dacad5SJay Sternberg } 263657dacad5SJay Sternberg 26371c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 263857dacad5SJay Sternberg { 26391c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26401c63dc66SChristoph Hellwig return 0; 264157dacad5SJay Sternberg } 26421c63dc66SChristoph Hellwig 26435fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26445fd4ce1bSChristoph Hellwig { 26455fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26465fd4ce1bSChristoph Hellwig return 0; 26475fd4ce1bSChristoph Hellwig } 26485fd4ce1bSChristoph Hellwig 26497fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26507fd8930fSChristoph Hellwig { 26513a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 26527fd8930fSChristoph Hellwig return 0; 26537fd8930fSChristoph Hellwig } 26547fd8930fSChristoph Hellwig 265597c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 265697c12223SKeith Busch { 265797c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 265897c12223SKeith Busch 26592db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 266097c12223SKeith Busch } 266197c12223SKeith Busch 26621c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26631a353d85SMing Lin .name = "pcie", 2664e439bb12SSagi Grimberg .module = THIS_MODULE, 2665e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2666e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26671c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26685fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26697fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26701673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2671f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 267297c12223SKeith Busch .get_address = nvme_pci_get_address, 26731c63dc66SChristoph Hellwig }; 267457dacad5SJay Sternberg 2675b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2676b00a726aSKeith Busch { 2677b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2678b00a726aSKeith Busch 2679a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2680b00a726aSKeith Busch return -ENODEV; 2681b00a726aSKeith Busch 268297f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2683b00a726aSKeith Busch goto release; 2684b00a726aSKeith Busch 2685b00a726aSKeith Busch return 0; 2686b00a726aSKeith Busch release: 2687a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2688b00a726aSKeith Busch return -ENODEV; 2689b00a726aSKeith Busch } 2690b00a726aSKeith Busch 26918427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2692ff5350a8SAndy Lutomirski { 2693ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2694ff5350a8SAndy Lutomirski /* 2695ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2696ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2697ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2698ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2699ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2700ff5350a8SAndy Lutomirski * laptops. 2701ff5350a8SAndy Lutomirski */ 2702ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2703ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2704ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2705ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27068427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27078427bbc2SKai-Heng Feng /* 27088427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2709467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2710467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2711467c77d4SJarosław Janik * ASUS PRIME Z370-A 27128427bbc2SKai-Heng Feng */ 27138427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2714467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2715467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27168427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 27171fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 27181fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 27191fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 27201fae37acSShyjumon N /* 27211fae37acSShyjumon N * Forcing to use host managed nvme power settings for 27221fae37acSShyjumon N * lowest idle power with quick resume latency on 27231fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 27241fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 27251fae37acSShyjumon N */ 27261fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 27271fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 27281fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2729ff5350a8SAndy Lutomirski } 2730ff5350a8SAndy Lutomirski 2731ff5350a8SAndy Lutomirski return 0; 2732ff5350a8SAndy Lutomirski } 2733ff5350a8SAndy Lutomirski 273418119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 273518119775SKeith Busch { 273618119775SKeith Busch struct nvme_dev *dev = data; 273780f513b5SKeith Busch 2738bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 273918119775SKeith Busch flush_work(&dev->ctrl.scan_work); 274080f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 274118119775SKeith Busch } 274218119775SKeith Busch 274357dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 274457dacad5SJay Sternberg { 274557dacad5SJay Sternberg int node, result = -ENOMEM; 274657dacad5SJay Sternberg struct nvme_dev *dev; 2747ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2748943e942eSJens Axboe size_t alloc_size; 274957dacad5SJay Sternberg 275057dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 275157dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27522fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 275357dacad5SJay Sternberg 275457dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 275557dacad5SJay Sternberg if (!dev) 275657dacad5SJay Sternberg return -ENOMEM; 2757147b27e4SSagi Grimberg 27583b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27593b6592f7SJens Axboe GFP_KERNEL, node); 276057dacad5SJay Sternberg if (!dev->queues) 276157dacad5SJay Sternberg goto free; 276257dacad5SJay Sternberg 276357dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 276457dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 276557dacad5SJay Sternberg 2766b00a726aSKeith Busch result = nvme_dev_map(dev); 2767b00a726aSKeith Busch if (result) 2768b00c9b7aSChristophe JAILLET goto put_pci; 2769b00a726aSKeith Busch 2770d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27715c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 277277bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2773f3ca80fcSChristoph Hellwig 2774f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2775f3ca80fcSChristoph Hellwig if (result) 2776b00c9b7aSChristophe JAILLET goto unmap; 2777f3ca80fcSChristoph Hellwig 27788427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2779ff5350a8SAndy Lutomirski 2780943e942eSJens Axboe /* 2781943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2782943e942eSJens Axboe * command we support. 2783943e942eSJens Axboe */ 2784943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2785943e942eSJens Axboe NVME_MAX_SEGS, true); 2786943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2787943e942eSJens Axboe 2788943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2789943e942eSJens Axboe mempool_kfree, 2790943e942eSJens Axboe (void *) alloc_size, 2791943e942eSJens Axboe GFP_KERNEL, node); 2792943e942eSJens Axboe if (!dev->iod_mempool) { 2793943e942eSJens Axboe result = -ENOMEM; 2794943e942eSJens Axboe goto release_pools; 2795943e942eSJens Axboe } 2796943e942eSJens Axboe 2797b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2798b6e44b4cSKeith Busch quirks); 2799b6e44b4cSKeith Busch if (result) 2800b6e44b4cSKeith Busch goto release_mempool; 2801b6e44b4cSKeith Busch 28021b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 28031b3c47c1SSagi Grimberg 2804bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 280580f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 280618119775SKeith Busch async_schedule(nvme_async_probe, dev); 28074caff8fcSSagi Grimberg 280857dacad5SJay Sternberg return 0; 280957dacad5SJay Sternberg 2810b6e44b4cSKeith Busch release_mempool: 2811b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 281257dacad5SJay Sternberg release_pools: 281357dacad5SJay Sternberg nvme_release_prp_pools(dev); 2814b00c9b7aSChristophe JAILLET unmap: 2815b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 281657dacad5SJay Sternberg put_pci: 281757dacad5SJay Sternberg put_device(dev->dev); 281857dacad5SJay Sternberg free: 281957dacad5SJay Sternberg kfree(dev->queues); 282057dacad5SJay Sternberg kfree(dev); 282157dacad5SJay Sternberg return result; 282257dacad5SJay Sternberg } 282357dacad5SJay Sternberg 2824775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 282557dacad5SJay Sternberg { 282657dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2827c1ac9a4bSKeith Busch 2828c1ac9a4bSKeith Busch /* 2829c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 2830c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 2831c1ac9a4bSKeith Busch * with ->remove(). 2832c1ac9a4bSKeith Busch */ 2833c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 2834c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 2835775755edSChristoph Hellwig } 283657dacad5SJay Sternberg 2837775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2838775755edSChristoph Hellwig { 2839f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2840c1ac9a4bSKeith Busch 2841c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 2842c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 284357dacad5SJay Sternberg } 284457dacad5SJay Sternberg 284557dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 284657dacad5SJay Sternberg { 284757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2848c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 284957dacad5SJay Sternberg } 285057dacad5SJay Sternberg 2851f58944e2SKeith Busch /* 2852f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2853f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2854f58944e2SKeith Busch * order to proceed. 2855f58944e2SKeith Busch */ 285657dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 285757dacad5SJay Sternberg { 285857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 285957dacad5SJay Sternberg 2860bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 286157dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28620ff9d4e1SKeith Busch 28636db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28640ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28651d39e692SKeith Busch nvme_dev_disable(dev, true); 2866cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28676db28edaSKeith Busch } 28680ff9d4e1SKeith Busch 2869d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2870d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2871d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2872a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28739fe5c59fSKeith Busch nvme_release_cmb(dev); 287487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 287557dacad5SJay Sternberg nvme_dev_remove_admin(dev); 287657dacad5SJay Sternberg nvme_free_queues(dev, 0); 2877d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 287857dacad5SJay Sternberg nvme_release_prp_pools(dev); 2879b00a726aSKeith Busch nvme_dev_unmap(dev); 28801673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 288157dacad5SJay Sternberg } 288257dacad5SJay Sternberg 288357dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 2884d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2885d916b1beSKeith Busch { 2886d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2887d916b1beSKeith Busch } 2888d916b1beSKeith Busch 2889d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2890d916b1beSKeith Busch { 2891d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2892d916b1beSKeith Busch } 2893d916b1beSKeith Busch 2894d916b1beSKeith Busch static int nvme_resume(struct device *dev) 2895d916b1beSKeith Busch { 2896d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2897d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2898d916b1beSKeith Busch 28994eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 2900d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2901c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 2902d916b1beSKeith Busch return 0; 2903d916b1beSKeith Busch } 2904d916b1beSKeith Busch 290557dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 290657dacad5SJay Sternberg { 290757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 290857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 2909d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2910d916b1beSKeith Busch int ret = -EBUSY; 2911d916b1beSKeith Busch 29124eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 29134eaefe8cSRafael J. Wysocki 2914d916b1beSKeith Busch /* 2915d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 2916d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 2917d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 2918d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 2919d916b1beSKeith Busch * device does not support any non-default power states, shut down the 2920d916b1beSKeith Busch * device fully. 29214eaefe8cSRafael J. Wysocki * 29224eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 29234eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 29244eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 29254eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 2926d916b1beSKeith Busch */ 29274eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 2928cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 2929c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 2930c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 2931d916b1beSKeith Busch 2932d916b1beSKeith Busch nvme_start_freeze(ctrl); 2933d916b1beSKeith Busch nvme_wait_freeze(ctrl); 2934d916b1beSKeith Busch nvme_sync_queues(ctrl); 2935d916b1beSKeith Busch 29365d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 2937d916b1beSKeith Busch goto unfreeze; 2938d916b1beSKeith Busch 2939d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2940d916b1beSKeith Busch if (ret < 0) 2941d916b1beSKeith Busch goto unfreeze; 2942d916b1beSKeith Busch 29437cbb5c6fSMario Limonciello /* 29447cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 29457cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 29467cbb5c6fSMario Limonciello * want pci interfering. 29477cbb5c6fSMario Limonciello */ 29487cbb5c6fSMario Limonciello pci_save_state(pdev); 29497cbb5c6fSMario Limonciello 2950d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 2951d916b1beSKeith Busch if (ret < 0) 2952d916b1beSKeith Busch goto unfreeze; 2953d916b1beSKeith Busch 2954d916b1beSKeith Busch if (ret) { 29557cbb5c6fSMario Limonciello /* discard the saved state */ 29567cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 29577cbb5c6fSMario Limonciello 2958d916b1beSKeith Busch /* 2959d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 296005d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 2961d916b1beSKeith Busch */ 2962c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 2963d916b1beSKeith Busch ctrl->npss = 0; 2964d916b1beSKeith Busch } 2965d916b1beSKeith Busch unfreeze: 2966d916b1beSKeith Busch nvme_unfreeze(ctrl); 2967d916b1beSKeith Busch return ret; 2968d916b1beSKeith Busch } 2969d916b1beSKeith Busch 2970d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 2971d916b1beSKeith Busch { 2972d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2973c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 297457dacad5SJay Sternberg } 297557dacad5SJay Sternberg 2976d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 297757dacad5SJay Sternberg { 297857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 297957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 298057dacad5SJay Sternberg 2981c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 298257dacad5SJay Sternberg } 298357dacad5SJay Sternberg 298421774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 2985d916b1beSKeith Busch .suspend = nvme_suspend, 2986d916b1beSKeith Busch .resume = nvme_resume, 2987d916b1beSKeith Busch .freeze = nvme_simple_suspend, 2988d916b1beSKeith Busch .thaw = nvme_simple_resume, 2989d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 2990d916b1beSKeith Busch .restore = nvme_simple_resume, 2991d916b1beSKeith Busch }; 2992d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 299357dacad5SJay Sternberg 2994a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2995a0a3408eSKeith Busch pci_channel_state_t state) 2996a0a3408eSKeith Busch { 2997a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2998a0a3408eSKeith Busch 2999a0a3408eSKeith Busch /* 3000a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3001a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3002a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3003a0a3408eSKeith Busch */ 3004a0a3408eSKeith Busch switch (state) { 3005a0a3408eSKeith Busch case pci_channel_io_normal: 3006a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3007a0a3408eSKeith Busch case pci_channel_io_frozen: 3008d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3009d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3010a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3011a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3012a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3013d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3014d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3015a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3016a0a3408eSKeith Busch } 3017a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3018a0a3408eSKeith Busch } 3019a0a3408eSKeith Busch 3020a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3021a0a3408eSKeith Busch { 3022a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3023a0a3408eSKeith Busch 30241b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3025a0a3408eSKeith Busch pci_restore_state(pdev); 3026d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3027a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3028a0a3408eSKeith Busch } 3029a0a3408eSKeith Busch 3030a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3031a0a3408eSKeith Busch { 303272cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 303372cd4cc2SKeith Busch 303472cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3035a0a3408eSKeith Busch } 3036a0a3408eSKeith Busch 303757dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 303857dacad5SJay Sternberg .error_detected = nvme_error_detected, 303957dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 304057dacad5SJay Sternberg .resume = nvme_error_resume, 3041775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3042775755edSChristoph Hellwig .reset_done = nvme_reset_done, 304357dacad5SJay Sternberg }; 304457dacad5SJay Sternberg 304557dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3046106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 304708095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3048e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 304999466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 305099466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3051e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 305299466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 305399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3054e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3055f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 3056f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3057f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 305850af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 30599abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 30606c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 30616c6aa2f2SAkinobu Mita NVME_QUIRK_NO_TEMP_THRESH_CHANGE }, 30626299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 30636299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3064540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 30657b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 30667b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 30670302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 30680302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 306954adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 307054adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 30718c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 30728c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3073015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3074015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3075d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3076d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3077d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3078d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3079608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3080608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3081608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3082608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3083ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3084ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 308508b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 308608b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3087f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3088f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3089f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 309057dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 309198f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 309298f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3093124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 309466341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 309566341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3096d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3097d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_SHARED_TAGS }, 309857dacad5SJay Sternberg { 0, } 309957dacad5SJay Sternberg }; 310057dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 310157dacad5SJay Sternberg 310257dacad5SJay Sternberg static struct pci_driver nvme_driver = { 310357dacad5SJay Sternberg .name = "nvme", 310457dacad5SJay Sternberg .id_table = nvme_id_table, 310557dacad5SJay Sternberg .probe = nvme_probe, 310657dacad5SJay Sternberg .remove = nvme_remove, 310757dacad5SJay Sternberg .shutdown = nvme_shutdown, 3108d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 310957dacad5SJay Sternberg .driver = { 311057dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 311157dacad5SJay Sternberg }, 3112d916b1beSKeith Busch #endif 311374d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 311457dacad5SJay Sternberg .err_handler = &nvme_err_handler, 311557dacad5SJay Sternberg }; 311657dacad5SJay Sternberg 311757dacad5SJay Sternberg static int __init nvme_init(void) 311857dacad5SJay Sternberg { 311981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 312081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 312181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3122612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 312317c33167SKeith Busch 312417c33167SKeith Busch write_queues = min(write_queues, num_possible_cpus()); 312517c33167SKeith Busch poll_queues = min(poll_queues, num_possible_cpus()); 31269a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 312757dacad5SJay Sternberg } 312857dacad5SJay Sternberg 312957dacad5SJay Sternberg static void __exit nvme_exit(void) 313057dacad5SJay Sternberg { 313157dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 313203e0f3a6SMing Lei flush_workqueue(nvme_wq); 313357dacad5SJay Sternberg } 313457dacad5SJay Sternberg 313557dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 313657dacad5SJay Sternberg MODULE_LICENSE("GPL"); 313757dacad5SJay Sternberg MODULE_VERSION("1.0"); 313857dacad5SJay Sternberg module_init(nvme_init); 313957dacad5SJay Sternberg module_exit(nvme_exit); 3140