15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 2157dacad5SJay Sternberg #include <linux/t10-pi.h> 2257dacad5SJay Sternberg #include <linux/types.h> 239cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 24a98e58e5SScott Bauer #include <linux/sed-opal.h> 250f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2657dacad5SJay Sternberg 27604c01d5Syupeng #include "trace.h" 2857dacad5SJay Sternberg #include "nvme.h" 2957dacad5SJay Sternberg 3057dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3157dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3257dacad5SJay Sternberg 33a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 34adf68f21SChristoph Hellwig 35943e942eSJens Axboe /* 36943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 37943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 38943e942eSJens Axboe */ 39943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 40943e942eSJens Axboe #define NVME_MAX_SEGS 127 41943e942eSJens Axboe 4257dacad5SJay Sternberg static int use_threaded_interrupts; 4357dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4457dacad5SJay Sternberg 4557dacad5SJay Sternberg static bool use_cmb_sqes = true; 4669f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4757dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4857dacad5SJay Sternberg 4987ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5087ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5187ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5287ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5357dacad5SJay Sternberg 54a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 55a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 56a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 57a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 58a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 59a7a7cbe3SChaitanya Kulkarni 60b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 61b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 62b27c1e68Sweiping zhang .set = io_queue_depth_set, 63b27c1e68Sweiping zhang .get = param_get_int, 64b27c1e68Sweiping zhang }; 65b27c1e68Sweiping zhang 66b27c1e68Sweiping zhang static int io_queue_depth = 1024; 67b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 68b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 69b27c1e68Sweiping zhang 703b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 713b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 723b6592f7SJens Axboe .set = queue_count_set, 733b6592f7SJens Axboe .get = param_get_int, 743b6592f7SJens Axboe }; 753b6592f7SJens Axboe 763b6592f7SJens Axboe static int write_queues; 773b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 783b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 793b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 803b6592f7SJens Axboe "will share a queue set."); 813b6592f7SJens Axboe 82a4668d9bSJens Axboe static int poll_queues = 0; 834b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 844b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 854b04cc6aSJens Axboe 861c63dc66SChristoph Hellwig struct nvme_dev; 871c63dc66SChristoph Hellwig struct nvme_queue; 8857dacad5SJay Sternberg 89a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 908fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 9157dacad5SJay Sternberg 9257dacad5SJay Sternberg /* 931c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 941c63dc66SChristoph Hellwig */ 951c63dc66SChristoph Hellwig struct nvme_dev { 96147b27e4SSagi Grimberg struct nvme_queue *queues; 971c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 981c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 991c63dc66SChristoph Hellwig u32 __iomem *dbs; 1001c63dc66SChristoph Hellwig struct device *dev; 1011c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1021c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1031c63dc66SChristoph Hellwig unsigned online_queues; 1041c63dc66SChristoph Hellwig unsigned max_qid; 105e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 10622b55601SKeith Busch unsigned int num_vecs; 1071c63dc66SChristoph Hellwig int q_depth; 1081c63dc66SChristoph Hellwig u32 db_stride; 1091c63dc66SChristoph Hellwig void __iomem *bar; 11097f6ef64SXu Yu unsigned long bar_mapped_size; 1115c8809e6SChristoph Hellwig struct work_struct remove_work; 11277bf25eaSKeith Busch struct mutex shutdown_lock; 1131c63dc66SChristoph Hellwig bool subsystem; 1141c63dc66SChristoph Hellwig u64 cmb_size; 1150f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1161c63dc66SChristoph Hellwig u32 cmbsz; 117202021c1SStephen Bates u32 cmbloc; 1181c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 11987ad72a5SChristoph Hellwig 120943e942eSJens Axboe mempool_t *iod_mempool; 121943e942eSJens Axboe 12287ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 123f9f38e33SHelen Koike u32 *dbbuf_dbs; 124f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 125f9f38e33SHelen Koike u32 *dbbuf_eis; 126f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 12787ad72a5SChristoph Hellwig 12887ad72a5SChristoph Hellwig /* host memory buffer support: */ 12987ad72a5SChristoph Hellwig u64 host_mem_size; 13087ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1314033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 13287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 13457dacad5SJay Sternberg }; 13557dacad5SJay Sternberg 136b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 137b27c1e68Sweiping zhang { 138b27c1e68Sweiping zhang int n = 0, ret; 139b27c1e68Sweiping zhang 140b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 141b27c1e68Sweiping zhang if (ret != 0 || n < 2) 142b27c1e68Sweiping zhang return -EINVAL; 143b27c1e68Sweiping zhang 144b27c1e68Sweiping zhang return param_set_int(val, kp); 145b27c1e68Sweiping zhang } 146b27c1e68Sweiping zhang 1473b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1483b6592f7SJens Axboe { 1493b6592f7SJens Axboe int n = 0, ret; 1503b6592f7SJens Axboe 1513b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 152e895fedfSBart Van Assche if (ret) 153e895fedfSBart Van Assche return ret; 1543b6592f7SJens Axboe if (n > num_possible_cpus()) 1553b6592f7SJens Axboe n = num_possible_cpus(); 1563b6592f7SJens Axboe 1573b6592f7SJens Axboe return param_set_int(val, kp); 1583b6592f7SJens Axboe } 1593b6592f7SJens Axboe 160f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 161f9f38e33SHelen Koike { 162f9f38e33SHelen Koike return qid * 2 * stride; 163f9f38e33SHelen Koike } 164f9f38e33SHelen Koike 165f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 166f9f38e33SHelen Koike { 167f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 168f9f38e33SHelen Koike } 169f9f38e33SHelen Koike 1701c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1711c63dc66SChristoph Hellwig { 1721c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1731c63dc66SChristoph Hellwig } 1741c63dc66SChristoph Hellwig 17557dacad5SJay Sternberg /* 17657dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 17757dacad5SJay Sternberg * commands and one for I/O commands). 17857dacad5SJay Sternberg */ 17957dacad5SJay Sternberg struct nvme_queue { 18057dacad5SJay Sternberg struct nvme_dev *dev; 1811ab0cd69SJens Axboe spinlock_t sq_lock; 18257dacad5SJay Sternberg struct nvme_command *sq_cmds; 1833a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1843a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 18557dacad5SJay Sternberg volatile struct nvme_completion *cqes; 18657dacad5SJay Sternberg struct blk_mq_tags **tags; 18757dacad5SJay Sternberg dma_addr_t sq_dma_addr; 18857dacad5SJay Sternberg dma_addr_t cq_dma_addr; 18957dacad5SJay Sternberg u32 __iomem *q_db; 19057dacad5SJay Sternberg u16 q_depth; 1917c349ddeSKeith Busch u16 cq_vector; 19257dacad5SJay Sternberg u16 sq_tail; 19304f3eafdSJens Axboe u16 last_sq_tail; 19457dacad5SJay Sternberg u16 cq_head; 19568fa9dbeSJens Axboe u16 last_cq_head; 19657dacad5SJay Sternberg u16 qid; 19757dacad5SJay Sternberg u8 cq_phase; 1984e224106SChristoph Hellwig unsigned long flags; 1994e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20063223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 201d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2027c349ddeSKeith Busch #define NVMEQ_POLLED 3 203f9f38e33SHelen Koike u32 *dbbuf_sq_db; 204f9f38e33SHelen Koike u32 *dbbuf_cq_db; 205f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 206f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 207d1ed6aa1SChristoph Hellwig struct completion delete_done; 20857dacad5SJay Sternberg }; 20957dacad5SJay Sternberg 21057dacad5SJay Sternberg /* 2119b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2129b048119SChristoph Hellwig * 2139b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2149b048119SChristoph Hellwig * to the actual struct scatterlist. 21571bd150cSChristoph Hellwig */ 21671bd150cSChristoph Hellwig struct nvme_iod { 217d49187e9SChristoph Hellwig struct nvme_request req; 218f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 219a7a7cbe3SChaitanya Kulkarni bool use_sgl; 220f4800d6dSChristoph Hellwig int aborted; 22171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22271bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22371bd150cSChristoph Hellwig dma_addr_t first_dma; 224dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 225783b94bdSChristoph Hellwig dma_addr_t meta_dma; 226f4800d6dSChristoph Hellwig struct scatterlist *sg; 22757dacad5SJay Sternberg }; 22857dacad5SJay Sternberg 22957dacad5SJay Sternberg /* 23057dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 23157dacad5SJay Sternberg */ 23257dacad5SJay Sternberg static inline void _nvme_check_size(void) 23357dacad5SJay Sternberg { 23457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 23557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 23657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 23757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 23857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 23957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 24057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 24157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2420add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2430add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 24457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 24557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 246f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 247f9f38e33SHelen Koike } 248f9f38e33SHelen Koike 2493b6592f7SJens Axboe static unsigned int max_io_queues(void) 2503b6592f7SJens Axboe { 2514b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2523b6592f7SJens Axboe } 2533b6592f7SJens Axboe 2543b6592f7SJens Axboe static unsigned int max_queue_count(void) 2553b6592f7SJens Axboe { 2563b6592f7SJens Axboe /* IO queues + admin queue */ 2573b6592f7SJens Axboe return 1 + max_io_queues(); 2583b6592f7SJens Axboe } 2593b6592f7SJens Axboe 260f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 261f9f38e33SHelen Koike { 2623b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 263f9f38e33SHelen Koike } 264f9f38e33SHelen Koike 265f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 266f9f38e33SHelen Koike { 267f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 268f9f38e33SHelen Koike 269f9f38e33SHelen Koike if (dev->dbbuf_dbs) 270f9f38e33SHelen Koike return 0; 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 273f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 274f9f38e33SHelen Koike GFP_KERNEL); 275f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 276f9f38e33SHelen Koike return -ENOMEM; 277f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 278f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 279f9f38e33SHelen Koike GFP_KERNEL); 280f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 281f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 282f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 283f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 284f9f38e33SHelen Koike return -ENOMEM; 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike 287f9f38e33SHelen Koike return 0; 288f9f38e33SHelen Koike } 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 291f9f38e33SHelen Koike { 292f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 293f9f38e33SHelen Koike 294f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 295f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 296f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 297f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 298f9f38e33SHelen Koike } 299f9f38e33SHelen Koike if (dev->dbbuf_eis) { 300f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 301f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 302f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike } 305f9f38e33SHelen Koike 306f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 307f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 308f9f38e33SHelen Koike { 309f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 310f9f38e33SHelen Koike return; 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 313f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 314f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 315f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 316f9f38e33SHelen Koike } 317f9f38e33SHelen Koike 318f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 319f9f38e33SHelen Koike { 320f9f38e33SHelen Koike struct nvme_command c; 321f9f38e33SHelen Koike 322f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 323f9f38e33SHelen Koike return; 324f9f38e33SHelen Koike 325f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 326f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 327f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 328f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3319bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 332f9f38e33SHelen Koike /* Free memory and continue on */ 333f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 334f9f38e33SHelen Koike } 335f9f38e33SHelen Koike } 336f9f38e33SHelen Koike 337f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 338f9f38e33SHelen Koike { 339f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 340f9f38e33SHelen Koike } 341f9f38e33SHelen Koike 342f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 343f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 344f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 345f9f38e33SHelen Koike { 346f9f38e33SHelen Koike if (dbbuf_db) { 347f9f38e33SHelen Koike u16 old_value; 348f9f38e33SHelen Koike 349f9f38e33SHelen Koike /* 350f9f38e33SHelen Koike * Ensure that the queue is written before updating 351f9f38e33SHelen Koike * the doorbell in memory 352f9f38e33SHelen Koike */ 353f9f38e33SHelen Koike wmb(); 354f9f38e33SHelen Koike 355f9f38e33SHelen Koike old_value = *dbbuf_db; 356f9f38e33SHelen Koike *dbbuf_db = value; 357f9f38e33SHelen Koike 358f1ed3df2SMichal Wnukowski /* 359f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 360f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 361f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 362f1ed3df2SMichal Wnukowski * the doorbell. 363f1ed3df2SMichal Wnukowski */ 364f1ed3df2SMichal Wnukowski mb(); 365f1ed3df2SMichal Wnukowski 366f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 367f9f38e33SHelen Koike return false; 368f9f38e33SHelen Koike } 369f9f38e33SHelen Koike 370f9f38e33SHelen Koike return true; 37157dacad5SJay Sternberg } 37257dacad5SJay Sternberg 37357dacad5SJay Sternberg /* 37457dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37557dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37657dacad5SJay Sternberg * the I/O. 37757dacad5SJay Sternberg */ 37857dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 37957dacad5SJay Sternberg { 3805fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3815fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 38257dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38357dacad5SJay Sternberg } 38457dacad5SJay Sternberg 385a7a7cbe3SChaitanya Kulkarni /* 386a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 387a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 388a7a7cbe3SChaitanya Kulkarni */ 389a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 390f4800d6dSChristoph Hellwig { 391a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 392f4800d6dSChristoph Hellwig } 393f4800d6dSChristoph Hellwig 394a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 395a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 39657dacad5SJay Sternberg { 397a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 398a7a7cbe3SChaitanya Kulkarni 399a7a7cbe3SChaitanya Kulkarni if (use_sgl) 400a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 401a7a7cbe3SChaitanya Kulkarni else 402a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 403a7a7cbe3SChaitanya Kulkarni 404a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 405a7a7cbe3SChaitanya Kulkarni } 406a7a7cbe3SChaitanya Kulkarni 40757dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40857dacad5SJay Sternberg unsigned int hctx_idx) 40957dacad5SJay Sternberg { 41057dacad5SJay Sternberg struct nvme_dev *dev = data; 411147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 41257dacad5SJay Sternberg 41357dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 41457dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 41557dacad5SJay Sternberg WARN_ON(nvmeq->tags); 41657dacad5SJay Sternberg 41757dacad5SJay Sternberg hctx->driver_data = nvmeq; 41857dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 41957dacad5SJay Sternberg return 0; 42057dacad5SJay Sternberg } 42157dacad5SJay Sternberg 42257dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 42357dacad5SJay Sternberg { 42457dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 42557dacad5SJay Sternberg 42657dacad5SJay Sternberg nvmeq->tags = NULL; 42757dacad5SJay Sternberg } 42857dacad5SJay Sternberg 42957dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 43057dacad5SJay Sternberg unsigned int hctx_idx) 43157dacad5SJay Sternberg { 43257dacad5SJay Sternberg struct nvme_dev *dev = data; 433147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 43457dacad5SJay Sternberg 43557dacad5SJay Sternberg if (!nvmeq->tags) 43657dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 43757dacad5SJay Sternberg 43857dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 43957dacad5SJay Sternberg hctx->driver_data = nvmeq; 44057dacad5SJay Sternberg return 0; 44157dacad5SJay Sternberg } 44257dacad5SJay Sternberg 443d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 444d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 44557dacad5SJay Sternberg { 446d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 447f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4480350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 449147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 45057dacad5SJay Sternberg 45157dacad5SJay Sternberg BUG_ON(!nvmeq); 452f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 45359e29ce6SSagi Grimberg 45459e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 45557dacad5SJay Sternberg return 0; 45657dacad5SJay Sternberg } 45757dacad5SJay Sternberg 4583b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4593b6592f7SJens Axboe { 4603b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4613b6592f7SJens Axboe if (dev->num_vecs > 1) 4623b6592f7SJens Axboe return 1; 4633b6592f7SJens Axboe 4643b6592f7SJens Axboe return 0; 4653b6592f7SJens Axboe } 4663b6592f7SJens Axboe 467dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 468dca51e78SChristoph Hellwig { 469dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4703b6592f7SJens Axboe int i, qoff, offset; 471dca51e78SChristoph Hellwig 4723b6592f7SJens Axboe offset = queue_irq_offset(dev); 4733b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4743b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4753b6592f7SJens Axboe 4763b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4773b6592f7SJens Axboe if (!map->nr_queues) { 478e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4797e849dd9SChristoph Hellwig continue; 4803b6592f7SJens Axboe } 4813b6592f7SJens Axboe 4824b04cc6aSJens Axboe /* 4834b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4844b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4854b04cc6aSJens Axboe */ 4863b6592f7SJens Axboe map->queue_offset = qoff; 487e20ba6e1SChristoph Hellwig if (i != HCTX_TYPE_POLL) 4883b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4894b04cc6aSJens Axboe else 4904b04cc6aSJens Axboe blk_mq_map_queues(map); 4913b6592f7SJens Axboe qoff += map->nr_queues; 4923b6592f7SJens Axboe offset += map->nr_queues; 4933b6592f7SJens Axboe } 4943b6592f7SJens Axboe 4953b6592f7SJens Axboe return 0; 496dca51e78SChristoph Hellwig } 497dca51e78SChristoph Hellwig 49804f3eafdSJens Axboe /* 49904f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 50004f3eafdSJens Axboe */ 50104f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 50204f3eafdSJens Axboe { 50304f3eafdSJens Axboe if (!write_sq) { 50404f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 50504f3eafdSJens Axboe 50604f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 50704f3eafdSJens Axboe next_tail = 0; 50804f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 50904f3eafdSJens Axboe return; 51004f3eafdSJens Axboe } 51104f3eafdSJens Axboe 51204f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 51304f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 51404f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 51504f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 51604f3eafdSJens Axboe } 51704f3eafdSJens Axboe 51857dacad5SJay Sternberg /** 51990ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 52057dacad5SJay Sternberg * @nvmeq: The queue to use 52157dacad5SJay Sternberg * @cmd: The command to send 52204f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 52357dacad5SJay Sternberg */ 52404f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 52504f3eafdSJens Axboe bool write_sq) 52657dacad5SJay Sternberg { 52790ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 52890ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 52990ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 53090ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 53104f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 53204f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 53304f3eafdSJens Axboe } 53404f3eafdSJens Axboe 53504f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 53604f3eafdSJens Axboe { 53704f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 53804f3eafdSJens Axboe 53904f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 54004f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 54104f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 54290ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 54357dacad5SJay Sternberg } 54457dacad5SJay Sternberg 545a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 54657dacad5SJay Sternberg { 547f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 548a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 54957dacad5SJay Sternberg } 55057dacad5SJay Sternberg 551955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 552955b1b5aSMinwoo Im { 553955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 55420469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 555955b1b5aSMinwoo Im unsigned int avg_seg_size; 556955b1b5aSMinwoo Im 55720469a37SKeith Busch if (nseg == 0) 55820469a37SKeith Busch return false; 55920469a37SKeith Busch 56020469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 561955b1b5aSMinwoo Im 562955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 563955b1b5aSMinwoo Im return false; 564955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 565955b1b5aSMinwoo Im return false; 566955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 567955b1b5aSMinwoo Im return false; 568955b1b5aSMinwoo Im return true; 569955b1b5aSMinwoo Im } 570955b1b5aSMinwoo Im 5717fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 57257dacad5SJay Sternberg { 573f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5747fe07d14SChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 5757fe07d14SChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 576a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 577a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 57857dacad5SJay Sternberg int i; 57957dacad5SJay Sternberg 580dff824b2SChristoph Hellwig if (iod->dma_len) { 581dff824b2SChristoph Hellwig dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir); 582dff824b2SChristoph Hellwig return; 583dff824b2SChristoph Hellwig } 584dff824b2SChristoph Hellwig 585dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 586dff824b2SChristoph Hellwig 5877fe07d14SChristoph Hellwig /* P2PDMA requests do not need to be unmapped */ 5887fe07d14SChristoph Hellwig if (!is_pci_p2pdma_page(sg_page(iod->sg))) 589dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5907fe07d14SChristoph Hellwig 5917fe07d14SChristoph Hellwig 59257dacad5SJay Sternberg if (iod->npages == 0) 593a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 594a7a7cbe3SChaitanya Kulkarni dma_addr); 595a7a7cbe3SChaitanya Kulkarni 59657dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 597a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 598a7a7cbe3SChaitanya Kulkarni 599a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 600a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 601a7a7cbe3SChaitanya Kulkarni 602a7a7cbe3SChaitanya Kulkarni next_dma_addr = 603a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 604a7a7cbe3SChaitanya Kulkarni } else { 605a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 606a7a7cbe3SChaitanya Kulkarni 607a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 608a7a7cbe3SChaitanya Kulkarni } 609a7a7cbe3SChaitanya Kulkarni 610a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 611a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 61257dacad5SJay Sternberg } 61357dacad5SJay Sternberg 614943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 61557dacad5SJay Sternberg } 61657dacad5SJay Sternberg 617d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 618d0877473SKeith Busch { 619d0877473SKeith Busch int i; 620d0877473SKeith Busch struct scatterlist *sg; 621d0877473SKeith Busch 622d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 623d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 624d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 625d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 626d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 627d0877473SKeith Busch sg_dma_len(sg)); 628d0877473SKeith Busch } 629d0877473SKeith Busch } 630d0877473SKeith Busch 631a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 632a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 63357dacad5SJay Sternberg { 634f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 63557dacad5SJay Sternberg struct dma_pool *pool; 636b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 63757dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 63857dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 63957dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6405fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 64157dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 64257dacad5SJay Sternberg __le64 *prp_list; 643a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 64457dacad5SJay Sternberg dma_addr_t prp_dma; 64557dacad5SJay Sternberg int nprps, i; 64657dacad5SJay Sternberg 64757dacad5SJay Sternberg length -= (page_size - offset); 6485228b328SJan H. Schönherr if (length <= 0) { 6495228b328SJan H. Schönherr iod->first_dma = 0; 650a7a7cbe3SChaitanya Kulkarni goto done; 6515228b328SJan H. Schönherr } 65257dacad5SJay Sternberg 65357dacad5SJay Sternberg dma_len -= (page_size - offset); 65457dacad5SJay Sternberg if (dma_len) { 65557dacad5SJay Sternberg dma_addr += (page_size - offset); 65657dacad5SJay Sternberg } else { 65757dacad5SJay Sternberg sg = sg_next(sg); 65857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 66057dacad5SJay Sternberg } 66157dacad5SJay Sternberg 66257dacad5SJay Sternberg if (length <= page_size) { 66357dacad5SJay Sternberg iod->first_dma = dma_addr; 664a7a7cbe3SChaitanya Kulkarni goto done; 66557dacad5SJay Sternberg } 66657dacad5SJay Sternberg 66757dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 66857dacad5SJay Sternberg if (nprps <= (256 / 8)) { 66957dacad5SJay Sternberg pool = dev->prp_small_pool; 67057dacad5SJay Sternberg iod->npages = 0; 67157dacad5SJay Sternberg } else { 67257dacad5SJay Sternberg pool = dev->prp_page_pool; 67357dacad5SJay Sternberg iod->npages = 1; 67457dacad5SJay Sternberg } 67557dacad5SJay Sternberg 67669d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67757dacad5SJay Sternberg if (!prp_list) { 67857dacad5SJay Sternberg iod->first_dma = dma_addr; 67957dacad5SJay Sternberg iod->npages = -1; 68086eea289SKeith Busch return BLK_STS_RESOURCE; 68157dacad5SJay Sternberg } 68257dacad5SJay Sternberg list[0] = prp_list; 68357dacad5SJay Sternberg iod->first_dma = prp_dma; 68457dacad5SJay Sternberg i = 0; 68557dacad5SJay Sternberg for (;;) { 68657dacad5SJay Sternberg if (i == page_size >> 3) { 68757dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 68869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68957dacad5SJay Sternberg if (!prp_list) 69086eea289SKeith Busch return BLK_STS_RESOURCE; 69157dacad5SJay Sternberg list[iod->npages++] = prp_list; 69257dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 69357dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 69457dacad5SJay Sternberg i = 1; 69557dacad5SJay Sternberg } 69657dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 69757dacad5SJay Sternberg dma_len -= page_size; 69857dacad5SJay Sternberg dma_addr += page_size; 69957dacad5SJay Sternberg length -= page_size; 70057dacad5SJay Sternberg if (length <= 0) 70157dacad5SJay Sternberg break; 70257dacad5SJay Sternberg if (dma_len > 0) 70357dacad5SJay Sternberg continue; 70486eea289SKeith Busch if (unlikely(dma_len < 0)) 70586eea289SKeith Busch goto bad_sgl; 70657dacad5SJay Sternberg sg = sg_next(sg); 70757dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 70857dacad5SJay Sternberg dma_len = sg_dma_len(sg); 70957dacad5SJay Sternberg } 71057dacad5SJay Sternberg 711a7a7cbe3SChaitanya Kulkarni done: 712a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 713a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 714a7a7cbe3SChaitanya Kulkarni 71586eea289SKeith Busch return BLK_STS_OK; 71686eea289SKeith Busch 71786eea289SKeith Busch bad_sgl: 718d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 719d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 720d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 72186eea289SKeith Busch return BLK_STS_IOERR; 72257dacad5SJay Sternberg } 72357dacad5SJay Sternberg 724a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 725a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 726a7a7cbe3SChaitanya Kulkarni { 727a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 728a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 729a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 730a7a7cbe3SChaitanya Kulkarni } 731a7a7cbe3SChaitanya Kulkarni 732a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 733a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 734a7a7cbe3SChaitanya Kulkarni { 735a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 736a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 737a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 738a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 739a7a7cbe3SChaitanya Kulkarni } else { 740a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 741a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 742a7a7cbe3SChaitanya Kulkarni } 743a7a7cbe3SChaitanya Kulkarni } 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 746b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 747a7a7cbe3SChaitanya Kulkarni { 748a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 749a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 750a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 751a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 752a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 753b0f2853bSChristoph Hellwig int i = 0; 754a7a7cbe3SChaitanya Kulkarni 755a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 756a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 757a7a7cbe3SChaitanya Kulkarni 758b0f2853bSChristoph Hellwig if (entries == 1) { 759a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 760a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 761a7a7cbe3SChaitanya Kulkarni } 762a7a7cbe3SChaitanya Kulkarni 763a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 764a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 765a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 766a7a7cbe3SChaitanya Kulkarni } else { 767a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 768a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 769a7a7cbe3SChaitanya Kulkarni } 770a7a7cbe3SChaitanya Kulkarni 771a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 772a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 773a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 774a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 775a7a7cbe3SChaitanya Kulkarni } 776a7a7cbe3SChaitanya Kulkarni 777a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 778a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 779a7a7cbe3SChaitanya Kulkarni 780a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 781a7a7cbe3SChaitanya Kulkarni 782a7a7cbe3SChaitanya Kulkarni do { 783a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 784a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 785a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 786a7a7cbe3SChaitanya Kulkarni 787a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 788a7a7cbe3SChaitanya Kulkarni if (!sg_list) 789a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 790a7a7cbe3SChaitanya Kulkarni 791a7a7cbe3SChaitanya Kulkarni i = 0; 792a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 793a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 794a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 795a7a7cbe3SChaitanya Kulkarni } 796a7a7cbe3SChaitanya Kulkarni 797a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 798a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 799b0f2853bSChristoph Hellwig } while (--entries > 0); 800a7a7cbe3SChaitanya Kulkarni 801a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 802a7a7cbe3SChaitanya Kulkarni } 803a7a7cbe3SChaitanya Kulkarni 804dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 805dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 806dff824b2SChristoph Hellwig struct bio_vec *bv) 807dff824b2SChristoph Hellwig { 808dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 809dff824b2SChristoph Hellwig unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; 810dff824b2SChristoph Hellwig 811dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 812dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 813dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 814dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 815dff824b2SChristoph Hellwig 816dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 817dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 818dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 819dff824b2SChristoph Hellwig return 0; 820dff824b2SChristoph Hellwig } 821dff824b2SChristoph Hellwig 82229791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 82329791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 82429791057SChristoph Hellwig struct bio_vec *bv) 82529791057SChristoph Hellwig { 82629791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82729791057SChristoph Hellwig 82829791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 82929791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 83029791057SChristoph Hellwig return BLK_STS_RESOURCE; 83129791057SChristoph Hellwig iod->dma_len = bv->bv_len; 83229791057SChristoph Hellwig 83329791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 83429791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 83529791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 83629791057SChristoph Hellwig return 0; 83729791057SChristoph Hellwig } 83829791057SChristoph Hellwig 839fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 840b131c61dSChristoph Hellwig struct nvme_command *cmnd) 84157dacad5SJay Sternberg { 842f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 843ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 844ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 845ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 846fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 847b0f2853bSChristoph Hellwig int nr_mapped; 84857dacad5SJay Sternberg 849dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 850dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 851dff824b2SChristoph Hellwig 852dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 853dff824b2SChristoph Hellwig if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 854dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 855dff824b2SChristoph Hellwig &cmnd->rw, &bv); 85629791057SChristoph Hellwig 85729791057SChristoph Hellwig if (iod->nvmeq->qid && 85829791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 85929791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 86029791057SChristoph Hellwig &cmnd->rw, &bv); 861dff824b2SChristoph Hellwig } 862dff824b2SChristoph Hellwig } 863dff824b2SChristoph Hellwig 864dff824b2SChristoph Hellwig iod->dma_len = 0; 8659b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8669b048119SChristoph Hellwig if (!iod->sg) 8679b048119SChristoph Hellwig return BLK_STS_RESOURCE; 8689b048119SChristoph Hellwig 8699b048119SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 8709b048119SChristoph Hellwig 871f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 872ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 873ba1ca37eSChristoph Hellwig if (!iod->nents) 874ba1ca37eSChristoph Hellwig goto out; 875ba1ca37eSChristoph Hellwig 876fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 877e0596ab2SLogan Gunthorpe 878e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 879e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 880e0596ab2SLogan Gunthorpe dma_dir); 881e0596ab2SLogan Gunthorpe else 882e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 883e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 884b0f2853bSChristoph Hellwig if (!nr_mapped) 885ba1ca37eSChristoph Hellwig goto out; 886ba1ca37eSChristoph Hellwig 887955b1b5aSMinwoo Im if (iod->use_sgl) 888b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 889a7a7cbe3SChaitanya Kulkarni else 890a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 891ba1ca37eSChristoph Hellwig out: 8924aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8937fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 894ba1ca37eSChristoph Hellwig return ret; 89557dacad5SJay Sternberg } 89657dacad5SJay Sternberg 8974aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8984aedb705SChristoph Hellwig struct nvme_command *cmnd) 8994aedb705SChristoph Hellwig { 9004aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9014aedb705SChristoph Hellwig 9024aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 9034aedb705SChristoph Hellwig rq_dma_dir(req), 0); 9044aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 9054aedb705SChristoph Hellwig return BLK_STS_IOERR; 9064aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 9074aedb705SChristoph Hellwig return 0; 9084aedb705SChristoph Hellwig } 9094aedb705SChristoph Hellwig 91057dacad5SJay Sternberg /* 91157dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 91257dacad5SJay Sternberg */ 913fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 91457dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 91557dacad5SJay Sternberg { 91657dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 91757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 91857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 91957dacad5SJay Sternberg struct request *req = bd->rq; 9209b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 921ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 922ebe6d874SChristoph Hellwig blk_status_t ret; 92357dacad5SJay Sternberg 9249b048119SChristoph Hellwig iod->aborted = 0; 9259b048119SChristoph Hellwig iod->npages = -1; 9269b048119SChristoph Hellwig iod->nents = 0; 9279b048119SChristoph Hellwig 928d1f06f4aSJens Axboe /* 929d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 930d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 931d1f06f4aSJens Axboe */ 9324e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 933d1f06f4aSJens Axboe return BLK_STS_IOERR; 934d1f06f4aSJens Axboe 935f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 936fc17b653SChristoph Hellwig if (ret) 937f4800d6dSChristoph Hellwig return ret; 93857dacad5SJay Sternberg 939fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 940b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 941fc17b653SChristoph Hellwig if (ret) 9429b048119SChristoph Hellwig goto out_free_cmd; 943fc17b653SChristoph Hellwig } 944ba1ca37eSChristoph Hellwig 9454aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 9464aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 9474aedb705SChristoph Hellwig if (ret) 9484aedb705SChristoph Hellwig goto out_unmap_data; 9494aedb705SChristoph Hellwig } 9504aedb705SChristoph Hellwig 951aae239e1SChristoph Hellwig blk_mq_start_request(req); 95204f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 953fc17b653SChristoph Hellwig return BLK_STS_OK; 9544aedb705SChristoph Hellwig out_unmap_data: 9554aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 956f9d03f96SChristoph Hellwig out_free_cmd: 957f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 958ba1ca37eSChristoph Hellwig return ret; 95957dacad5SJay Sternberg } 96057dacad5SJay Sternberg 96177f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 962eee417b0SChristoph Hellwig { 963f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9644aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 965eee417b0SChristoph Hellwig 966915f04c9SChristoph Hellwig nvme_cleanup_cmd(req); 9674aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9684aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9694aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 970b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9714aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 97277f02a7aSChristoph Hellwig nvme_complete_rq(req); 97357dacad5SJay Sternberg } 97457dacad5SJay Sternberg 975d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 976750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 977d783e0bdSMarta Rybczynska { 978750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 979750dde44SChristoph Hellwig nvmeq->cq_phase; 980d783e0bdSMarta Rybczynska } 981d783e0bdSMarta Rybczynska 982eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 98357dacad5SJay Sternberg { 984eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 98557dacad5SJay Sternberg 986eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 987eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 988eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 989eb281c82SSagi Grimberg } 990adf68f21SChristoph Hellwig 9915cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 99257dacad5SJay Sternberg { 9935cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 99457dacad5SJay Sternberg struct request *req; 995adf68f21SChristoph Hellwig 99683a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9971b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 998aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 99983a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 100083a12fb7SSagi Grimberg return; 1001aae239e1SChristoph Hellwig } 1002aae239e1SChristoph Hellwig 1003adf68f21SChristoph Hellwig /* 1004adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1005adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1006adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1007adf68f21SChristoph Hellwig * for them but rather special case them here. 1008adf68f21SChristoph Hellwig */ 1009adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 101038dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 10117bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 101283a12fb7SSagi Grimberg cqe->status, &cqe->result); 1013a0fa9647SJens Axboe return; 101457dacad5SJay Sternberg } 101557dacad5SJay Sternberg 101683a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 1017604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 101883a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 101983a12fb7SSagi Grimberg } 102057dacad5SJay Sternberg 10215cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 102283a12fb7SSagi Grimberg { 10235cb525c8SJens Axboe while (start != end) { 10245cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 10255cb525c8SJens Axboe if (++start == nvmeq->q_depth) 10265cb525c8SJens Axboe start = 0; 10275cb525c8SJens Axboe } 10285cb525c8SJens Axboe } 102983a12fb7SSagi Grimberg 10305cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10315cb525c8SJens Axboe { 1032dcca1662SHongbo Yao if (nvmeq->cq_head == nvmeq->q_depth - 1) { 1033920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1034920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1035dcca1662SHongbo Yao } else { 1036dcca1662SHongbo Yao nvmeq->cq_head++; 1037920d13a8SSagi Grimberg } 1038a0fa9647SJens Axboe } 1039a0fa9647SJens Axboe 10401052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10411052b8acSJens Axboe u16 *end, unsigned int tag) 1042a0fa9647SJens Axboe { 10431052b8acSJens Axboe int found = 0; 104483a12fb7SSagi Grimberg 10455cb525c8SJens Axboe *start = nvmeq->cq_head; 10461052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10471052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10481052b8acSJens Axboe found++; 10495cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 105057dacad5SJay Sternberg } 10515cb525c8SJens Axboe *end = nvmeq->cq_head; 105257dacad5SJay Sternberg 10535cb525c8SJens Axboe if (*start != *end) 1054eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10555cb525c8SJens Axboe return found; 105657dacad5SJay Sternberg } 105757dacad5SJay Sternberg 105857dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 105957dacad5SJay Sternberg { 106057dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 106168fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10625cb525c8SJens Axboe u16 start, end; 10635cb525c8SJens Axboe 10643a7afd8eSChristoph Hellwig /* 10653a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10663a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10673a7afd8eSChristoph Hellwig */ 10683a7afd8eSChristoph Hellwig rmb(); 106968fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 107068fa9dbeSJens Axboe ret = IRQ_HANDLED; 10715cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 107268fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10733a7afd8eSChristoph Hellwig wmb(); 10745cb525c8SJens Axboe 107568fa9dbeSJens Axboe if (start != end) { 10765cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10775cb525c8SJens Axboe return IRQ_HANDLED; 107857dacad5SJay Sternberg } 107957dacad5SJay Sternberg 108068fa9dbeSJens Axboe return ret; 108157dacad5SJay Sternberg } 108257dacad5SJay Sternberg 108357dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 108457dacad5SJay Sternberg { 108557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1086750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 108757dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1088d783e0bdSMarta Rybczynska return IRQ_NONE; 108957dacad5SJay Sternberg } 109057dacad5SJay Sternberg 10910b2a8a9fSChristoph Hellwig /* 10920b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10930b2a8a9fSChristoph Hellwig * Can be called from any context. 10940b2a8a9fSChristoph Hellwig */ 10950b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1096a0fa9647SJens Axboe { 10973a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10985cb525c8SJens Axboe u16 start, end; 10991052b8acSJens Axboe int found; 1100a0fa9647SJens Axboe 11013a7afd8eSChristoph Hellwig /* 11023a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 11033a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 11043a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 11053a7afd8eSChristoph Hellwig */ 11067c349ddeSKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 11073a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 110891a509f8SChristoph Hellwig found = nvme_process_cq(nvmeq, &start, &end, tag); 110991a509f8SChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 111091a509f8SChristoph Hellwig } else { 11113a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 11125cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 11133a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 111491a509f8SChristoph Hellwig } 1115442e19b7SSagi Grimberg 11165cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1117442e19b7SSagi Grimberg return found; 1118a0fa9647SJens Axboe } 1119a0fa9647SJens Axboe 11209743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 11217776db1cSKeith Busch { 11227776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1123dabcefabSJens Axboe u16 start, end; 1124dabcefabSJens Axboe bool found; 1125dabcefabSJens Axboe 1126dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1127dabcefabSJens Axboe return 0; 1128dabcefabSJens Axboe 11293a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 11309743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 11313a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1132dabcefabSJens Axboe 1133dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1134dabcefabSJens Axboe return found; 1135dabcefabSJens Axboe } 1136dabcefabSJens Axboe 1137ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 113857dacad5SJay Sternberg { 1139f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1140147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 114157dacad5SJay Sternberg struct nvme_command c; 114257dacad5SJay Sternberg 114357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 114457dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1145ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 114604f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 114757dacad5SJay Sternberg } 114857dacad5SJay Sternberg 114957dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 115057dacad5SJay Sternberg { 115157dacad5SJay Sternberg struct nvme_command c; 115257dacad5SJay Sternberg 115357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 115457dacad5SJay Sternberg c.delete_queue.opcode = opcode; 115557dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 115657dacad5SJay Sternberg 11571c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 115857dacad5SJay Sternberg } 115957dacad5SJay Sternberg 116057dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1161a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 116257dacad5SJay Sternberg { 116357dacad5SJay Sternberg struct nvme_command c; 11644b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11654b04cc6aSJens Axboe 11667c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11674b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 116857dacad5SJay Sternberg 116957dacad5SJay Sternberg /* 117016772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 117157dacad5SJay Sternberg * is attached to the request. 117257dacad5SJay Sternberg */ 117357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 117457dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 117557dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 117657dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 117757dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 117857dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1179a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 118057dacad5SJay Sternberg 11811c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 118257dacad5SJay Sternberg } 118357dacad5SJay Sternberg 118457dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 118557dacad5SJay Sternberg struct nvme_queue *nvmeq) 118657dacad5SJay Sternberg { 11879abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 118857dacad5SJay Sternberg struct nvme_command c; 118981c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 119057dacad5SJay Sternberg 119157dacad5SJay Sternberg /* 11929abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11939abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11949abd68efSJens Axboe * URGENT. 11959abd68efSJens Axboe */ 11969abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11979abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11989abd68efSJens Axboe 11999abd68efSJens Axboe /* 120016772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 120157dacad5SJay Sternberg * is attached to the request. 120257dacad5SJay Sternberg */ 120357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 120457dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 120557dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 120657dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 120757dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 120857dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 120957dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 121057dacad5SJay Sternberg 12111c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 121257dacad5SJay Sternberg } 121357dacad5SJay Sternberg 121457dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 121557dacad5SJay Sternberg { 121657dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 121757dacad5SJay Sternberg } 121857dacad5SJay Sternberg 121957dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 122057dacad5SJay Sternberg { 122157dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 122257dacad5SJay Sternberg } 122357dacad5SJay Sternberg 12242a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 122557dacad5SJay Sternberg { 1226f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1227f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 122857dacad5SJay Sternberg 122927fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 123027fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1231e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1232e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 123357dacad5SJay Sternberg } 123457dacad5SJay Sternberg 1235b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1236b2a0eb1aSKeith Busch { 1237b2a0eb1aSKeith Busch 1238b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1239b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1240b2a0eb1aSKeith Busch */ 1241b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1242b2a0eb1aSKeith Busch 1243ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1244ad70062cSJianchao Wang switch (dev->ctrl.state) { 1245ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1246ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1247b2a0eb1aSKeith Busch return false; 1248ad70062cSJianchao Wang default: 1249ad70062cSJianchao Wang break; 1250ad70062cSJianchao Wang } 1251b2a0eb1aSKeith Busch 1252b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1253b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1254b2a0eb1aSKeith Busch */ 1255b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1256b2a0eb1aSKeith Busch return false; 1257b2a0eb1aSKeith Busch 1258b2a0eb1aSKeith Busch return true; 1259b2a0eb1aSKeith Busch } 1260b2a0eb1aSKeith Busch 1261b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1262b2a0eb1aSKeith Busch { 1263b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1264b2a0eb1aSKeith Busch u16 pci_status; 1265b2a0eb1aSKeith Busch int result; 1266b2a0eb1aSKeith Busch 1267b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1268b2a0eb1aSKeith Busch &pci_status); 1269b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1270b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1271b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1272b2a0eb1aSKeith Busch csts, pci_status); 1273b2a0eb1aSKeith Busch else 1274b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1275b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1276b2a0eb1aSKeith Busch csts, result); 1277b2a0eb1aSKeith Busch } 1278b2a0eb1aSKeith Busch 127931c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 128057dacad5SJay Sternberg { 1281f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1282f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 128357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 128457dacad5SJay Sternberg struct request *abort_req; 128557dacad5SJay Sternberg struct nvme_command cmd; 1286b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1287b2a0eb1aSKeith Busch 1288651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1289651438bbSWen Xiong * the recovery mechanism will surely fail. 1290651438bbSWen Xiong */ 1291651438bbSWen Xiong mb(); 1292651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1293651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1294651438bbSWen Xiong 1295b2a0eb1aSKeith Busch /* 1296b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1297b2a0eb1aSKeith Busch */ 1298b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1299b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1300b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1301d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1302db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1303b2a0eb1aSKeith Busch } 130457dacad5SJay Sternberg 130531c7c7d2SChristoph Hellwig /* 13067776db1cSKeith Busch * Did we miss an interrupt? 13077776db1cSKeith Busch */ 13080b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 13097776db1cSKeith Busch dev_warn(dev->ctrl.device, 13107776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13117776db1cSKeith Busch req->tag, nvmeq->qid); 1312db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13137776db1cSKeith Busch } 13147776db1cSKeith Busch 13157776db1cSKeith Busch /* 1316fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1317fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1318fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1319db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1320fd634f41SChristoph Hellwig */ 13214244140dSKeith Busch switch (dev->ctrl.state) { 13224244140dSKeith Busch case NVME_CTRL_CONNECTING: 13234244140dSKeith Busch case NVME_CTRL_RESETTING: 1324b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1325fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1326fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1327a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 132827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1329db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13304244140dSKeith Busch default: 13314244140dSKeith Busch break; 1332fd634f41SChristoph Hellwig } 1333fd634f41SChristoph Hellwig 1334fd634f41SChristoph Hellwig /* 1335e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1336e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1337e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 133831c7c7d2SChristoph Hellwig */ 1339f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13401b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 134157dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 134257dacad5SJay Sternberg req->tag, nvmeq->qid); 1343a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1344d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1345e1569a16SKeith Busch 134627fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1347db8c48e4SChristoph Hellwig return BLK_EH_DONE; 134857dacad5SJay Sternberg } 134957dacad5SJay Sternberg 1350e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1351e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1352e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1353e7a2a87dSChristoph Hellwig } 13547bf7d778SKeith Busch iod->aborted = 1; 135557dacad5SJay Sternberg 135657dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 135757dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 135857dacad5SJay Sternberg cmd.abort.cid = req->tag; 135957dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 136057dacad5SJay Sternberg 13611b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13621b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 136357dacad5SJay Sternberg req->tag, nvmeq->qid); 1364e7a2a87dSChristoph Hellwig 1365e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1366eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13676bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13686bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 136931c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 137057dacad5SJay Sternberg } 137157dacad5SJay Sternberg 1372e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1373e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1374e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 137557dacad5SJay Sternberg 137657dacad5SJay Sternberg /* 137757dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 137857dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 137957dacad5SJay Sternberg * as the device then is in a faulty state. 138057dacad5SJay Sternberg */ 138157dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 138257dacad5SJay Sternberg } 138357dacad5SJay Sternberg 138457dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 138557dacad5SJay Sternberg { 138688a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth), 138757dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 138863223078SChristoph Hellwig if (!nvmeq->sq_cmds) 138963223078SChristoph Hellwig return; 13900f238ff5SLogan Gunthorpe 139163223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 139288a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 139363223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 139463223078SChristoph Hellwig } else { 139588a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth), 139663223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13970f238ff5SLogan Gunthorpe } 139857dacad5SJay Sternberg } 139957dacad5SJay Sternberg 140057dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 140157dacad5SJay Sternberg { 140257dacad5SJay Sternberg int i; 140357dacad5SJay Sternberg 1404d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1405d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1406147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 140757dacad5SJay Sternberg } 140857dacad5SJay Sternberg } 140957dacad5SJay Sternberg 141057dacad5SJay Sternberg /** 141157dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 141240581d1aSBart Van Assche * @nvmeq: queue to suspend 141357dacad5SJay Sternberg */ 141457dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 141557dacad5SJay Sternberg { 14164e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 141757dacad5SJay Sternberg return 1; 141857dacad5SJay Sternberg 14194e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1420d1f06f4aSJens Axboe mb(); 142157dacad5SJay Sternberg 14224e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14231c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1424c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 14257c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14264e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 142757dacad5SJay Sternberg return 0; 142857dacad5SJay Sternberg } 142957dacad5SJay Sternberg 14308fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14318fae268bSKeith Busch { 14328fae268bSKeith Busch int i; 14338fae268bSKeith Busch 14348fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14358fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14368fae268bSKeith Busch } 14378fae268bSKeith Busch 1438a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 143957dacad5SJay Sternberg { 1440147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 144157dacad5SJay Sternberg 1442a5cdb68cSKeith Busch if (shutdown) 1443a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1444a5cdb68cSKeith Busch else 144520d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 144657dacad5SJay Sternberg 14470b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 144857dacad5SJay Sternberg } 144957dacad5SJay Sternberg 145057dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 145157dacad5SJay Sternberg int entry_size) 145257dacad5SJay Sternberg { 145357dacad5SJay Sternberg int q_depth = dev->q_depth; 14545fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14555fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 145657dacad5SJay Sternberg 145757dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 145857dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14595fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 146057dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 146157dacad5SJay Sternberg 146257dacad5SJay Sternberg /* 146357dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 146457dacad5SJay Sternberg * would be better to map queues in system memory with the 146557dacad5SJay Sternberg * original depth 146657dacad5SJay Sternberg */ 146757dacad5SJay Sternberg if (q_depth < 64) 146857dacad5SJay Sternberg return -ENOMEM; 146957dacad5SJay Sternberg } 147057dacad5SJay Sternberg 147157dacad5SJay Sternberg return q_depth; 147257dacad5SJay Sternberg } 147357dacad5SJay Sternberg 147457dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 147557dacad5SJay Sternberg int qid, int depth) 147657dacad5SJay Sternberg { 14770f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1478815c6704SKeith Busch 14790f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14800f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14810f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14820f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 148363223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 148463223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 148563223078SChristoph Hellwig return 0; 148663223078SChristoph Hellwig } 14870f238ff5SLogan Gunthorpe } 14880f238ff5SLogan Gunthorpe 148957dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 149057dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 149157dacad5SJay Sternberg if (!nvmeq->sq_cmds) 149257dacad5SJay Sternberg return -ENOMEM; 149357dacad5SJay Sternberg return 0; 149457dacad5SJay Sternberg } 149557dacad5SJay Sternberg 1496a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 149757dacad5SJay Sternberg { 1498147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 149957dacad5SJay Sternberg 150062314e40SKeith Busch if (dev->ctrl.queue_count > qid) 150162314e40SKeith Busch return 0; 150257dacad5SJay Sternberg 1503750afb08SLuis Chamberlain nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), 150457dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 150557dacad5SJay Sternberg if (!nvmeq->cqes) 150657dacad5SJay Sternberg goto free_nvmeq; 150757dacad5SJay Sternberg 150857dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 150957dacad5SJay Sternberg goto free_cqdma; 151057dacad5SJay Sternberg 151157dacad5SJay Sternberg nvmeq->dev = dev; 15121ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15133a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 151457dacad5SJay Sternberg nvmeq->cq_head = 0; 151557dacad5SJay Sternberg nvmeq->cq_phase = 1; 151657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 151757dacad5SJay Sternberg nvmeq->q_depth = depth; 151857dacad5SJay Sternberg nvmeq->qid = qid; 1519d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 152057dacad5SJay Sternberg 1521147b27e4SSagi Grimberg return 0; 152257dacad5SJay Sternberg 152357dacad5SJay Sternberg free_cqdma: 152457dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 152557dacad5SJay Sternberg nvmeq->cq_dma_addr); 152657dacad5SJay Sternberg free_nvmeq: 1527147b27e4SSagi Grimberg return -ENOMEM; 152857dacad5SJay Sternberg } 152957dacad5SJay Sternberg 1530dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 153157dacad5SJay Sternberg { 15320ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15330ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15340ff199cbSChristoph Hellwig 15350ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15360ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15370ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15380ff199cbSChristoph Hellwig } else { 15390ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15400ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15410ff199cbSChristoph Hellwig } 154257dacad5SJay Sternberg } 154357dacad5SJay Sternberg 154457dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 154557dacad5SJay Sternberg { 154657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 154757dacad5SJay Sternberg 154857dacad5SJay Sternberg nvmeq->sq_tail = 0; 154904f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 155057dacad5SJay Sternberg nvmeq->cq_head = 0; 155157dacad5SJay Sternberg nvmeq->cq_phase = 1; 155257dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 155357dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1554f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 155557dacad5SJay Sternberg dev->online_queues++; 15563a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 155757dacad5SJay Sternberg } 155857dacad5SJay Sternberg 15594b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 156057dacad5SJay Sternberg { 156157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 156257dacad5SJay Sternberg int result; 15637c349ddeSKeith Busch u16 vector = 0; 156457dacad5SJay Sternberg 1565d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1566d1ed6aa1SChristoph Hellwig 156722b55601SKeith Busch /* 156822b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 156922b55601SKeith Busch * has only one vector available. 157022b55601SKeith Busch */ 15714b04cc6aSJens Axboe if (!polled) 1572a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15734b04cc6aSJens Axboe else 15747c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15754b04cc6aSJens Axboe 1576a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1577ded45505SKeith Busch if (result) 1578ded45505SKeith Busch return result; 157957dacad5SJay Sternberg 158057dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 158157dacad5SJay Sternberg if (result < 0) 1582ded45505SKeith Busch return result; 1583ded45505SKeith Busch else if (result) 158457dacad5SJay Sternberg goto release_cq; 158557dacad5SJay Sternberg 1586a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1587161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15884b04cc6aSJens Axboe 15897c349ddeSKeith Busch if (!polled) { 15907c349ddeSKeith Busch nvmeq->cq_vector = vector; 1591dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 159257dacad5SJay Sternberg if (result < 0) 159357dacad5SJay Sternberg goto release_sq; 15944b04cc6aSJens Axboe } 159557dacad5SJay Sternberg 15964e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 159757dacad5SJay Sternberg return result; 159857dacad5SJay Sternberg 159957dacad5SJay Sternberg release_sq: 1600f25a2dfcSJianchao Wang dev->online_queues--; 160157dacad5SJay Sternberg adapter_delete_sq(dev, qid); 160257dacad5SJay Sternberg release_cq: 160357dacad5SJay Sternberg adapter_delete_cq(dev, qid); 160457dacad5SJay Sternberg return result; 160557dacad5SJay Sternberg } 160657dacad5SJay Sternberg 1607f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 160857dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 160977f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 161057dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 161157dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 16120350815aSChristoph Hellwig .init_request = nvme_init_request, 161357dacad5SJay Sternberg .timeout = nvme_timeout, 161457dacad5SJay Sternberg }; 161557dacad5SJay Sternberg 1616f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1617376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1618376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1619376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1620376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1621376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1622376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1623376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1624c6d962aeSChristoph Hellwig .poll = nvme_poll, 1625dabcefabSJens Axboe }; 1626dabcefabSJens Axboe 162757dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 162857dacad5SJay Sternberg { 16291c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 163069d9a99cSKeith Busch /* 163169d9a99cSKeith Busch * If the controller was reset during removal, it's possible 163269d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 163369d9a99cSKeith Busch * queue to flush these to completion. 163469d9a99cSKeith Busch */ 1635c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16361c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 163757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 163857dacad5SJay Sternberg } 163957dacad5SJay Sternberg } 164057dacad5SJay Sternberg 164157dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 164257dacad5SJay Sternberg { 16431c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 164457dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 164557dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1646e3e9d50cSKeith Busch 164738dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 164857dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 164957dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1650d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1651d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 165257dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 165357dacad5SJay Sternberg 165457dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 165557dacad5SJay Sternberg return -ENOMEM; 165634b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 165757dacad5SJay Sternberg 16581c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16591c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 166057dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 166157dacad5SJay Sternberg return -ENOMEM; 166257dacad5SJay Sternberg } 16631c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 166457dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16651c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 166657dacad5SJay Sternberg return -ENODEV; 166757dacad5SJay Sternberg } 166857dacad5SJay Sternberg } else 1669c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 167057dacad5SJay Sternberg 167157dacad5SJay Sternberg return 0; 167257dacad5SJay Sternberg } 167357dacad5SJay Sternberg 167497f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 167597f6ef64SXu Yu { 167697f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 167797f6ef64SXu Yu } 167897f6ef64SXu Yu 167997f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 168097f6ef64SXu Yu { 168197f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 168297f6ef64SXu Yu 168397f6ef64SXu Yu if (size <= dev->bar_mapped_size) 168497f6ef64SXu Yu return 0; 168597f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 168697f6ef64SXu Yu return -ENOMEM; 168797f6ef64SXu Yu if (dev->bar) 168897f6ef64SXu Yu iounmap(dev->bar); 168997f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 169097f6ef64SXu Yu if (!dev->bar) { 169197f6ef64SXu Yu dev->bar_mapped_size = 0; 169297f6ef64SXu Yu return -ENOMEM; 169397f6ef64SXu Yu } 169497f6ef64SXu Yu dev->bar_mapped_size = size; 169597f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 169697f6ef64SXu Yu 169797f6ef64SXu Yu return 0; 169897f6ef64SXu Yu } 169997f6ef64SXu Yu 170001ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 170157dacad5SJay Sternberg { 170257dacad5SJay Sternberg int result; 170357dacad5SJay Sternberg u32 aqa; 170457dacad5SJay Sternberg struct nvme_queue *nvmeq; 170557dacad5SJay Sternberg 170697f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 170797f6ef64SXu Yu if (result < 0) 170897f6ef64SXu Yu return result; 170997f6ef64SXu Yu 17108ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 171120d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 171257dacad5SJay Sternberg 17137a67cbeaSChristoph Hellwig if (dev->subsystem && 17147a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17157a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 171657dacad5SJay Sternberg 171720d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 171857dacad5SJay Sternberg if (result < 0) 171957dacad5SJay Sternberg return result; 172057dacad5SJay Sternberg 1721a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1722147b27e4SSagi Grimberg if (result) 1723147b27e4SSagi Grimberg return result; 172457dacad5SJay Sternberg 1725147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 172657dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 172757dacad5SJay Sternberg aqa |= aqa << 16; 172857dacad5SJay Sternberg 17297a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17307a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17317a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 173257dacad5SJay Sternberg 173320d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 173457dacad5SJay Sternberg if (result) 1735d4875622SKeith Busch return result; 173657dacad5SJay Sternberg 173757dacad5SJay Sternberg nvmeq->cq_vector = 0; 1738161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1739dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 174057dacad5SJay Sternberg if (result) { 17417c349ddeSKeith Busch dev->online_queues--; 1742d4875622SKeith Busch return result; 174357dacad5SJay Sternberg } 174457dacad5SJay Sternberg 17454e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 174657dacad5SJay Sternberg return result; 174757dacad5SJay Sternberg } 174857dacad5SJay Sternberg 1749749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 175057dacad5SJay Sternberg { 17514b04cc6aSJens Axboe unsigned i, max, rw_queues; 1752749941f2SChristoph Hellwig int ret = 0; 175357dacad5SJay Sternberg 1754d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1755a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1756749941f2SChristoph Hellwig ret = -ENOMEM; 175757dacad5SJay Sternberg break; 1758749941f2SChristoph Hellwig } 1759749941f2SChristoph Hellwig } 176057dacad5SJay Sternberg 1761d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1762e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1763e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1764e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17654b04cc6aSJens Axboe } else { 17664b04cc6aSJens Axboe rw_queues = max; 17674b04cc6aSJens Axboe } 17684b04cc6aSJens Axboe 1769949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17704b04cc6aSJens Axboe bool polled = i > rw_queues; 17714b04cc6aSJens Axboe 17724b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1773d4875622SKeith Busch if (ret) 177457dacad5SJay Sternberg break; 177557dacad5SJay Sternberg } 177657dacad5SJay Sternberg 1777749941f2SChristoph Hellwig /* 1778749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17798adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17808adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1781749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1782749941f2SChristoph Hellwig */ 1783749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 178457dacad5SJay Sternberg } 178557dacad5SJay Sternberg 1786202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1787202021c1SStephen Bates struct device_attribute *attr, 1788202021c1SStephen Bates char *buf) 1789202021c1SStephen Bates { 1790202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1791202021c1SStephen Bates 1792c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1793202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1794202021c1SStephen Bates } 1795202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1796202021c1SStephen Bates 179788de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 179857dacad5SJay Sternberg { 179988de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 180088de4598SChristoph Hellwig 180188de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 180288de4598SChristoph Hellwig } 180388de4598SChristoph Hellwig 180488de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 180588de4598SChristoph Hellwig { 180688de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 180788de4598SChristoph Hellwig } 180888de4598SChristoph Hellwig 1809f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 181057dacad5SJay Sternberg { 181188de4598SChristoph Hellwig u64 size, offset; 181257dacad5SJay Sternberg resource_size_t bar_size; 181357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 18148969f1f8SChristoph Hellwig int bar; 181557dacad5SJay Sternberg 18169fe5c59fSKeith Busch if (dev->cmb_size) 18179fe5c59fSKeith Busch return; 18189fe5c59fSKeith Busch 18197a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1820f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1821f65efd6dSChristoph Hellwig return; 1822202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 182357dacad5SJay Sternberg 182488de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 182588de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18268969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18278969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 182857dacad5SJay Sternberg 182957dacad5SJay Sternberg if (offset > bar_size) 1830f65efd6dSChristoph Hellwig return; 183157dacad5SJay Sternberg 183257dacad5SJay Sternberg /* 183357dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 183457dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 183557dacad5SJay Sternberg * the reported size of the BAR 183657dacad5SJay Sternberg */ 183757dacad5SJay Sternberg if (size > bar_size - offset) 183857dacad5SJay Sternberg size = bar_size - offset; 183957dacad5SJay Sternberg 18400f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18410f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18420f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1843f65efd6dSChristoph Hellwig return; 18440f238ff5SLogan Gunthorpe } 18450f238ff5SLogan Gunthorpe 184657dacad5SJay Sternberg dev->cmb_size = size; 18470f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18480f238ff5SLogan Gunthorpe 18490f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18500f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18510f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1852f65efd6dSChristoph Hellwig 1853f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1854f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1855f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1856f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 185757dacad5SJay Sternberg } 185857dacad5SJay Sternberg 185957dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 186057dacad5SJay Sternberg { 18610f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1862f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1863f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18640f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1865f63572dfSJon Derrick } 186657dacad5SJay Sternberg } 186757dacad5SJay Sternberg 186887ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 186957dacad5SJay Sternberg { 18704033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 187187ad72a5SChristoph Hellwig struct nvme_command c; 187287ad72a5SChristoph Hellwig int ret; 187387ad72a5SChristoph Hellwig 187487ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 187587ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 187687ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 187787ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 187887ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 187987ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 188087ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 188187ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 188287ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 188387ad72a5SChristoph Hellwig 188487ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 188587ad72a5SChristoph Hellwig if (ret) { 188687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 188787ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 188887ad72a5SChristoph Hellwig ret, bits); 188987ad72a5SChristoph Hellwig } 189087ad72a5SChristoph Hellwig return ret; 189187ad72a5SChristoph Hellwig } 189287ad72a5SChristoph Hellwig 189387ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 189487ad72a5SChristoph Hellwig { 189587ad72a5SChristoph Hellwig int i; 189687ad72a5SChristoph Hellwig 189787ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 189887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 189987ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 190087ad72a5SChristoph Hellwig 1901cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1902cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1903cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 190487ad72a5SChristoph Hellwig } 190587ad72a5SChristoph Hellwig 190687ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 190787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19084033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 19094033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 19104033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 191187ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 19127e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 191387ad72a5SChristoph Hellwig } 191487ad72a5SChristoph Hellwig 191592dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 191692dc6895SChristoph Hellwig u32 chunk_size) 191787ad72a5SChristoph Hellwig { 191887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 191992dc6895SChristoph Hellwig u32 max_entries, len; 19204033f35dSChristoph Hellwig dma_addr_t descs_dma; 19212ee0e4edSDan Carpenter int i = 0; 192287ad72a5SChristoph Hellwig void **bufs; 19236fbcde66SMinwoo Im u64 size, tmp; 192487ad72a5SChristoph Hellwig 192587ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 192687ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 192787ad72a5SChristoph Hellwig max_entries = tmp; 1928044a9df1SChristoph Hellwig 1929044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1930044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1931044a9df1SChristoph Hellwig 1932750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19334033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 193487ad72a5SChristoph Hellwig if (!descs) 193587ad72a5SChristoph Hellwig goto out; 193687ad72a5SChristoph Hellwig 193787ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 193887ad72a5SChristoph Hellwig if (!bufs) 193987ad72a5SChristoph Hellwig goto out_free_descs; 194087ad72a5SChristoph Hellwig 1941244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 194287ad72a5SChristoph Hellwig dma_addr_t dma_addr; 194387ad72a5SChristoph Hellwig 194450cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 194587ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 194687ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 194787ad72a5SChristoph Hellwig if (!bufs[i]) 194887ad72a5SChristoph Hellwig break; 194987ad72a5SChristoph Hellwig 195087ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 195187ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 195287ad72a5SChristoph Hellwig i++; 195387ad72a5SChristoph Hellwig } 195487ad72a5SChristoph Hellwig 195592dc6895SChristoph Hellwig if (!size) 195687ad72a5SChristoph Hellwig goto out_free_bufs; 195787ad72a5SChristoph Hellwig 195887ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 195987ad72a5SChristoph Hellwig dev->host_mem_size = size; 196087ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19614033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 196287ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 196387ad72a5SChristoph Hellwig return 0; 196487ad72a5SChristoph Hellwig 196587ad72a5SChristoph Hellwig out_free_bufs: 196687ad72a5SChristoph Hellwig while (--i >= 0) { 196787ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 196887ad72a5SChristoph Hellwig 1969cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1970cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1971cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 197287ad72a5SChristoph Hellwig } 197387ad72a5SChristoph Hellwig 197487ad72a5SChristoph Hellwig kfree(bufs); 197587ad72a5SChristoph Hellwig out_free_descs: 19764033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19774033f35dSChristoph Hellwig descs_dma); 197887ad72a5SChristoph Hellwig out: 197987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 198087ad72a5SChristoph Hellwig return -ENOMEM; 198187ad72a5SChristoph Hellwig } 198287ad72a5SChristoph Hellwig 198392dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 198492dc6895SChristoph Hellwig { 198592dc6895SChristoph Hellwig u32 chunk_size; 198692dc6895SChristoph Hellwig 198792dc6895SChristoph Hellwig /* start big and work our way down */ 198830f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1989044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 199092dc6895SChristoph Hellwig chunk_size /= 2) { 199192dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 199292dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 199392dc6895SChristoph Hellwig return 0; 199492dc6895SChristoph Hellwig nvme_free_host_mem(dev); 199592dc6895SChristoph Hellwig } 199692dc6895SChristoph Hellwig } 199792dc6895SChristoph Hellwig 199892dc6895SChristoph Hellwig return -ENOMEM; 199992dc6895SChristoph Hellwig } 200092dc6895SChristoph Hellwig 20019620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 200287ad72a5SChristoph Hellwig { 200387ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 200487ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 200587ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 200687ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20076fbcde66SMinwoo Im int ret; 200887ad72a5SChristoph Hellwig 200987ad72a5SChristoph Hellwig preferred = min(preferred, max); 201087ad72a5SChristoph Hellwig if (min > max) { 201187ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 201287ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 201387ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 201487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20159620cfbaSChristoph Hellwig return 0; 201687ad72a5SChristoph Hellwig } 201787ad72a5SChristoph Hellwig 201887ad72a5SChristoph Hellwig /* 201987ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 202087ad72a5SChristoph Hellwig */ 202187ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 202287ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 202387ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 202487ad72a5SChristoph Hellwig else 202587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 202687ad72a5SChristoph Hellwig } 202787ad72a5SChristoph Hellwig 202887ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 202992dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 203092dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 203192dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20329620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 203387ad72a5SChristoph Hellwig } 203487ad72a5SChristoph Hellwig 203592dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 203692dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 203792dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 203892dc6895SChristoph Hellwig } 203992dc6895SChristoph Hellwig 20409620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20419620cfbaSChristoph Hellwig if (ret) 204287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20439620cfbaSChristoph Hellwig return ret; 204457dacad5SJay Sternberg } 204557dacad5SJay Sternberg 2046612b7286SMing Lei /* 2047612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2048612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2049612b7286SMing Lei */ 2050612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20513b6592f7SJens Axboe { 2052612b7286SMing Lei struct nvme_dev *dev = affd->priv; 2053612b7286SMing Lei unsigned int nr_read_queues; 2054c45b1fa2SMing Lei 20553b6592f7SJens Axboe /* 2056612b7286SMing Lei * If there is no interupt available for queues, ensure that 2057612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2058612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2059612b7286SMing Lei * 2060612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2061612b7286SMing Lei * write and read queues. 2062612b7286SMing Lei * 2063612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2064612b7286SMing Lei * queue. 20653b6592f7SJens Axboe */ 2066612b7286SMing Lei if (!nrirqs) { 2067612b7286SMing Lei nrirqs = 1; 2068612b7286SMing Lei nr_read_queues = 0; 2069612b7286SMing Lei } else if (nrirqs == 1 || !write_queues) { 2070612b7286SMing Lei nr_read_queues = 0; 2071612b7286SMing Lei } else if (write_queues >= nrirqs) { 2072612b7286SMing Lei nr_read_queues = 1; 20733b6592f7SJens Axboe } else { 2074612b7286SMing Lei nr_read_queues = nrirqs - write_queues; 20753b6592f7SJens Axboe } 2076612b7286SMing Lei 2077612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2078612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2079612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2080612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2081612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20823b6592f7SJens Axboe } 20833b6592f7SJens Axboe 20846451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20853b6592f7SJens Axboe { 20863b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20873b6592f7SJens Axboe struct irq_affinity affd = { 20883b6592f7SJens Axboe .pre_vectors = 1, 2089612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2090612b7286SMing Lei .priv = dev, 20913b6592f7SJens Axboe }; 20926451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20936451fe73SJens Axboe 20946451fe73SJens Axboe /* 20956451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20966451fe73SJens Axboe * queue left over for non-polled IO. 20976451fe73SJens Axboe */ 20986451fe73SJens Axboe this_p_queues = poll_queues; 20996451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 21006451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 21016451fe73SJens Axboe irq_queues = 1; 21026451fe73SJens Axboe } else { 2103c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 21046451fe73SJens Axboe } 21056451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 21063b6592f7SJens Axboe 2107612b7286SMing Lei /* Initialize for the single interrupt case */ 2108612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2109612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 21103b6592f7SJens Axboe 2111612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 21123b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 21133b6592f7SJens Axboe } 21143b6592f7SJens Axboe 21158fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 21168fae268bSKeith Busch { 21178fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 21188fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 21198fae268bSKeith Busch } 21208fae268bSKeith Busch 212157dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 212257dacad5SJay Sternberg { 2123147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 212457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 212597f6ef64SXu Yu int result, nr_io_queues; 212697f6ef64SXu Yu unsigned long size; 212757dacad5SJay Sternberg 21283b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21299a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21309a0be7abSChristoph Hellwig if (result < 0) 213157dacad5SJay Sternberg return result; 21329a0be7abSChristoph Hellwig 2133f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2134a5229050SKeith Busch return 0; 213557dacad5SJay Sternberg 21364e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21374e224106SChristoph Hellwig 21380f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 213957dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 214057dacad5SJay Sternberg sizeof(struct nvme_command)); 214157dacad5SJay Sternberg if (result > 0) 214257dacad5SJay Sternberg dev->q_depth = result; 214357dacad5SJay Sternberg else 21440f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 214557dacad5SJay Sternberg } 214657dacad5SJay Sternberg 214757dacad5SJay Sternberg do { 214897f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 214997f6ef64SXu Yu result = nvme_remap_bar(dev, size); 215097f6ef64SXu Yu if (!result) 215157dacad5SJay Sternberg break; 215257dacad5SJay Sternberg if (!--nr_io_queues) 215357dacad5SJay Sternberg return -ENOMEM; 215457dacad5SJay Sternberg } while (1); 215557dacad5SJay Sternberg adminq->q_db = dev->dbs; 215657dacad5SJay Sternberg 21578fae268bSKeith Busch retry: 215857dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21590ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 216057dacad5SJay Sternberg 216157dacad5SJay Sternberg /* 216257dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 216357dacad5SJay Sternberg * setting up the full range we need. 216457dacad5SJay Sternberg */ 2165dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21663b6592f7SJens Axboe 21673b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 216822b55601SKeith Busch if (result <= 0) 2169dca51e78SChristoph Hellwig return -EIO; 21703b6592f7SJens Axboe 217122b55601SKeith Busch dev->num_vecs = result; 21724b04cc6aSJens Axboe result = max(result - 1, 1); 2173e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 217457dacad5SJay Sternberg 217557dacad5SJay Sternberg /* 217657dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 217757dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 217857dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 217957dacad5SJay Sternberg * number of interrupts. 218057dacad5SJay Sternberg */ 2181dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21827c349ddeSKeith Busch if (result) 2183d4875622SKeith Busch return result; 21844e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21858fae268bSKeith Busch 21868fae268bSKeith Busch result = nvme_create_io_queues(dev); 21878fae268bSKeith Busch if (result || dev->online_queues < 2) 21888fae268bSKeith Busch return result; 21898fae268bSKeith Busch 21908fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21918fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21928fae268bSKeith Busch nvme_disable_io_queues(dev); 21938fae268bSKeith Busch nvme_suspend_io_queues(dev); 21948fae268bSKeith Busch goto retry; 21958fae268bSKeith Busch } 21968fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21978fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21988fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21998fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 22008fae268bSKeith Busch return 0; 220157dacad5SJay Sternberg } 220257dacad5SJay Sternberg 22032a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2204db3cbfffSKeith Busch { 2205db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2206db3cbfffSKeith Busch 2207db3cbfffSKeith Busch blk_mq_free_request(req); 2208d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2209db3cbfffSKeith Busch } 2210db3cbfffSKeith Busch 22112a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2212db3cbfffSKeith Busch { 2213db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2214db3cbfffSKeith Busch 2215d1ed6aa1SChristoph Hellwig if (error) 2216d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2217db3cbfffSKeith Busch 2218db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2219db3cbfffSKeith Busch } 2220db3cbfffSKeith Busch 2221db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2222db3cbfffSKeith Busch { 2223db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2224db3cbfffSKeith Busch struct request *req; 2225db3cbfffSKeith Busch struct nvme_command cmd; 2226db3cbfffSKeith Busch 2227db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2228db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2229db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2230db3cbfffSKeith Busch 2231eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2232db3cbfffSKeith Busch if (IS_ERR(req)) 2233db3cbfffSKeith Busch return PTR_ERR(req); 2234db3cbfffSKeith Busch 2235db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2236db3cbfffSKeith Busch req->end_io_data = nvmeq; 2237db3cbfffSKeith Busch 2238d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2239db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2240db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2241db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2242db3cbfffSKeith Busch return 0; 2243db3cbfffSKeith Busch } 2244db3cbfffSKeith Busch 22458fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2246db3cbfffSKeith Busch { 22475271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2248db3cbfffSKeith Busch unsigned long timeout; 2249db3cbfffSKeith Busch 2250db3cbfffSKeith Busch retry: 2251db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22525271edd4SChristoph Hellwig while (nr_queues > 0) { 22535271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2254db3cbfffSKeith Busch break; 22555271edd4SChristoph Hellwig nr_queues--; 22565271edd4SChristoph Hellwig sent++; 22575271edd4SChristoph Hellwig } 2258d1ed6aa1SChristoph Hellwig while (sent) { 2259d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2260d1ed6aa1SChristoph Hellwig 2261d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22625271edd4SChristoph Hellwig timeout); 2263db3cbfffSKeith Busch if (timeout == 0) 22645271edd4SChristoph Hellwig return false; 2265d1ed6aa1SChristoph Hellwig 2266d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2267d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2268d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2269d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2270d1ed6aa1SChristoph Hellwig 2271d1ed6aa1SChristoph Hellwig sent--; 22725271edd4SChristoph Hellwig if (nr_queues) 2273db3cbfffSKeith Busch goto retry; 2274db3cbfffSKeith Busch } 22755271edd4SChristoph Hellwig return true; 2276db3cbfffSKeith Busch } 2277db3cbfffSKeith Busch 227857dacad5SJay Sternberg /* 22792b1b7e78SJianchao Wang * return error value only when tagset allocation failed 228057dacad5SJay Sternberg */ 228157dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 228257dacad5SJay Sternberg { 22832b1b7e78SJianchao Wang int ret; 22842b1b7e78SJianchao Wang 22855bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2286c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 228757dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2288ed92ad37SChristoph Hellwig dev->tagset.nr_maps = 2; /* default + read */ 2289ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2290ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 229157dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 229257dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 229357dacad5SJay Sternberg dev->tagset.queue_depth = 229457dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2295d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 229657dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 229757dacad5SJay Sternberg dev->tagset.driver_data = dev; 229857dacad5SJay Sternberg 22992b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 23002b1b7e78SJianchao Wang if (ret) { 23012b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23022b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 23032b1b7e78SJianchao Wang return ret; 23042b1b7e78SJianchao Wang } 23055bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2306f9f38e33SHelen Koike 2307f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2308949928c1SKeith Busch } else { 2309949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2310949928c1SKeith Busch 2311949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2312949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 231357dacad5SJay Sternberg } 2314949928c1SKeith Busch 231557dacad5SJay Sternberg return 0; 231657dacad5SJay Sternberg } 231757dacad5SJay Sternberg 2318b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 231957dacad5SJay Sternberg { 2320b00a726aSKeith Busch int result = -ENOMEM; 232157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 232257dacad5SJay Sternberg 232357dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 232457dacad5SJay Sternberg return result; 232557dacad5SJay Sternberg 232657dacad5SJay Sternberg pci_set_master(pdev); 232757dacad5SJay Sternberg 232857dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 232957dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 233057dacad5SJay Sternberg goto disable; 233157dacad5SJay Sternberg 23327a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 233357dacad5SJay Sternberg result = -ENODEV; 2334b00a726aSKeith Busch goto disable; 233557dacad5SJay Sternberg } 233657dacad5SJay Sternberg 233757dacad5SJay Sternberg /* 2338a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2339a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2340a5229050SKeith Busch * adjust this later. 234157dacad5SJay Sternberg */ 2342dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2343dca51e78SChristoph Hellwig if (result < 0) 2344dca51e78SChristoph Hellwig return result; 234557dacad5SJay Sternberg 234620d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23477a67cbeaSChristoph Hellwig 234820d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2349b27c1e68Sweiping zhang io_queue_depth); 235020d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23517a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23521f390c1fSStephan Günther 23531f390c1fSStephan Günther /* 23541f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23551f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23561f390c1fSStephan Günther */ 23571f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23581f390c1fSStephan Günther dev->q_depth = 2; 23599bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23609bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23611f390c1fSStephan Günther dev->q_depth); 2362d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2363d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 236420d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2365d554b5e1SMartin K. Petersen dev->q_depth = 64; 2366d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2367d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23681f390c1fSStephan Günther } 23691f390c1fSStephan Günther 2370f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2371202021c1SStephen Bates 2372a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2373a0a3408eSKeith Busch pci_save_state(pdev); 237457dacad5SJay Sternberg return 0; 237557dacad5SJay Sternberg 237657dacad5SJay Sternberg disable: 237757dacad5SJay Sternberg pci_disable_device(pdev); 237857dacad5SJay Sternberg return result; 237957dacad5SJay Sternberg } 238057dacad5SJay Sternberg 238157dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 238257dacad5SJay Sternberg { 2383b00a726aSKeith Busch if (dev->bar) 2384b00a726aSKeith Busch iounmap(dev->bar); 2385a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2386b00a726aSKeith Busch } 2387b00a726aSKeith Busch 2388b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2389b00a726aSKeith Busch { 239057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 239157dacad5SJay Sternberg 2392dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 239357dacad5SJay Sternberg 2394a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2395a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 239657dacad5SJay Sternberg pci_disable_device(pdev); 239757dacad5SJay Sternberg } 2398a0a3408eSKeith Busch } 239957dacad5SJay Sternberg 2400a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 240157dacad5SJay Sternberg { 2402302ad8ccSKeith Busch bool dead = true; 2403302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 240457dacad5SJay Sternberg 240577bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2406302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2407302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2408302ad8ccSKeith Busch 2409ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2410ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2411302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2412302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2413302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 241457dacad5SJay Sternberg } 2415c21377f8SGabriel Krisman Bertazi 2416302ad8ccSKeith Busch /* 2417302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2418302ad8ccSKeith Busch * doing a safe shutdown. 2419302ad8ccSKeith Busch */ 242087ad72a5SChristoph Hellwig if (!dead) { 242187ad72a5SChristoph Hellwig if (shutdown) 2422302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 24239a915a5bSJianchao Wang } 242487ad72a5SChristoph Hellwig 24259a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24269a915a5bSJianchao Wang 242764ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24288fae268bSKeith Busch nvme_disable_io_queues(dev); 2429a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 243057dacad5SJay Sternberg } 24318fae268bSKeith Busch nvme_suspend_io_queues(dev); 24328fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2433b00a726aSKeith Busch nvme_pci_disable(dev); 243457dacad5SJay Sternberg 2435e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2436e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2437302ad8ccSKeith Busch 2438302ad8ccSKeith Busch /* 2439302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2440302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2441302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2442302ad8ccSKeith Busch */ 2443302ad8ccSKeith Busch if (shutdown) 2444302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 244577bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 244657dacad5SJay Sternberg } 244757dacad5SJay Sternberg 244857dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 244957dacad5SJay Sternberg { 245057dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 245157dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 245257dacad5SJay Sternberg if (!dev->prp_page_pool) 245357dacad5SJay Sternberg return -ENOMEM; 245457dacad5SJay Sternberg 245557dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 245657dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 245757dacad5SJay Sternberg 256, 256, 0); 245857dacad5SJay Sternberg if (!dev->prp_small_pool) { 245957dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 246057dacad5SJay Sternberg return -ENOMEM; 246157dacad5SJay Sternberg } 246257dacad5SJay Sternberg return 0; 246357dacad5SJay Sternberg } 246457dacad5SJay Sternberg 246557dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 246657dacad5SJay Sternberg { 246757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 246857dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 246957dacad5SJay Sternberg } 247057dacad5SJay Sternberg 24711673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 247257dacad5SJay Sternberg { 24731673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 247457dacad5SJay Sternberg 2475f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 247657dacad5SJay Sternberg put_device(dev->dev); 247757dacad5SJay Sternberg if (dev->tagset.tags) 247857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24791c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24801c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 248157dacad5SJay Sternberg kfree(dev->queues); 2482e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2483943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 248457dacad5SJay Sternberg kfree(dev); 248557dacad5SJay Sternberg } 248657dacad5SJay Sternberg 2487f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2488f58944e2SKeith Busch { 2489237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2490f58944e2SKeith Busch 2491d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 249269d9a99cSKeith Busch nvme_dev_disable(dev, false); 24939f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 249403e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2495f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2496f58944e2SKeith Busch } 2497f58944e2SKeith Busch 2498fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 249957dacad5SJay Sternberg { 2500d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2501d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2502a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2503f58944e2SKeith Busch int result = -ENODEV; 25042b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 250557dacad5SJay Sternberg 250682b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2507fd634f41SChristoph Hellwig goto out; 2508fd634f41SChristoph Hellwig 2509fd634f41SChristoph Hellwig /* 2510fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2511fd634f41SChristoph Hellwig * moving on. 2512fd634f41SChristoph Hellwig */ 2513b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2514a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2515fd634f41SChristoph Hellwig 25165c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2517b00a726aSKeith Busch result = nvme_pci_enable(dev); 251857dacad5SJay Sternberg if (result) 25194726bcf3SKeith Busch goto out_unlock; 252057dacad5SJay Sternberg 252101ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 252257dacad5SJay Sternberg if (result) 25234726bcf3SKeith Busch goto out_unlock; 252457dacad5SJay Sternberg 252557dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 252657dacad5SJay Sternberg if (result) 25274726bcf3SKeith Busch goto out_unlock; 252857dacad5SJay Sternberg 2529943e942eSJens Axboe /* 2530943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2531943e942eSJens Axboe * over a single page. 2532943e942eSJens Axboe */ 2533943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2534943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 25355c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25365c959d73SKeith Busch 25375c959d73SKeith Busch /* 25385c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25395c959d73SKeith Busch * initializing procedure here. 25405c959d73SKeith Busch */ 25415c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25425c959d73SKeith Busch dev_warn(dev->ctrl.device, 25435c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 25445c959d73SKeith Busch goto out; 25455c959d73SKeith Busch } 2546943e942eSJens Axboe 2547ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2548ce4541f4SChristoph Hellwig if (result) 2549f58944e2SKeith Busch goto out; 2550ce4541f4SChristoph Hellwig 2551e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2552e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25534f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25544f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2555e286bcfcSScott Bauer else if (was_suspend) 25564f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2557e286bcfcSScott Bauer } else { 2558e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2559e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2560e286bcfcSScott Bauer } 2561a98e58e5SScott Bauer 2562f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2563f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2564f9f38e33SHelen Koike if (result) 2565f9f38e33SHelen Koike dev_warn(dev->dev, 2566f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2567f9f38e33SHelen Koike } 2568f9f38e33SHelen Koike 25699620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25709620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25719620cfbaSChristoph Hellwig if (result < 0) 25729620cfbaSChristoph Hellwig goto out; 25739620cfbaSChristoph Hellwig } 257487ad72a5SChristoph Hellwig 257557dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 257657dacad5SJay Sternberg if (result) 2577f58944e2SKeith Busch goto out; 257857dacad5SJay Sternberg 257921f033f7SKeith Busch /* 258057dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 258157dacad5SJay Sternberg * any working I/O queue. 258257dacad5SJay Sternberg */ 258357dacad5SJay Sternberg if (dev->online_queues < 2) { 25841b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25853b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25865bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 25872b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 258857dacad5SJay Sternberg } else { 258925646264SKeith Busch nvme_start_queues(&dev->ctrl); 2590302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 25912b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 25922b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 25932b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2594302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 259557dacad5SJay Sternberg } 259657dacad5SJay Sternberg 25972b1b7e78SJianchao Wang /* 25982b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 25992b1b7e78SJianchao Wang * recovery. 26002b1b7e78SJianchao Wang */ 26012b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 26022b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26032b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2604bb8d261eSChristoph Hellwig goto out; 2605bb8d261eSChristoph Hellwig } 260692911a55SChristoph Hellwig 2607d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 260857dacad5SJay Sternberg return; 260957dacad5SJay Sternberg 26104726bcf3SKeith Busch out_unlock: 26114726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 261257dacad5SJay Sternberg out: 2613f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 261457dacad5SJay Sternberg } 261557dacad5SJay Sternberg 26165c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 261757dacad5SJay Sternberg { 26185c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 261957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 262057dacad5SJay Sternberg 262157dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2622921920abSKeith Busch device_release_driver(&pdev->dev); 26231673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 262457dacad5SJay Sternberg } 262557dacad5SJay Sternberg 26261c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 262757dacad5SJay Sternberg { 26281c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26291c63dc66SChristoph Hellwig return 0; 263057dacad5SJay Sternberg } 26311c63dc66SChristoph Hellwig 26325fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26335fd4ce1bSChristoph Hellwig { 26345fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26355fd4ce1bSChristoph Hellwig return 0; 26365fd4ce1bSChristoph Hellwig } 26375fd4ce1bSChristoph Hellwig 26387fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26397fd8930fSChristoph Hellwig { 26407fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26417fd8930fSChristoph Hellwig return 0; 26427fd8930fSChristoph Hellwig } 26437fd8930fSChristoph Hellwig 264497c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 264597c12223SKeith Busch { 264697c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 264797c12223SKeith Busch 264897c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 264997c12223SKeith Busch } 265097c12223SKeith Busch 26511c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26521a353d85SMing Lin .name = "pcie", 2653e439bb12SSagi Grimberg .module = THIS_MODULE, 2654e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2655e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26561c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26575fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26587fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26591673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2660f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 266197c12223SKeith Busch .get_address = nvme_pci_get_address, 26621c63dc66SChristoph Hellwig }; 266357dacad5SJay Sternberg 2664b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2665b00a726aSKeith Busch { 2666b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2667b00a726aSKeith Busch 2668a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2669b00a726aSKeith Busch return -ENODEV; 2670b00a726aSKeith Busch 267197f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2672b00a726aSKeith Busch goto release; 2673b00a726aSKeith Busch 2674b00a726aSKeith Busch return 0; 2675b00a726aSKeith Busch release: 2676a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2677b00a726aSKeith Busch return -ENODEV; 2678b00a726aSKeith Busch } 2679b00a726aSKeith Busch 26808427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2681ff5350a8SAndy Lutomirski { 2682ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2683ff5350a8SAndy Lutomirski /* 2684ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2685ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2686ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2687ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2688ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2689ff5350a8SAndy Lutomirski * laptops. 2690ff5350a8SAndy Lutomirski */ 2691ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2692ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2693ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2694ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 26958427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 26968427bbc2SKai-Heng Feng /* 26978427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2698467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2699467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2700467c77d4SJarosław Janik * ASUS PRIME Z370-A 27018427bbc2SKai-Heng Feng */ 27028427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2703467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2704467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27058427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2706ff5350a8SAndy Lutomirski } 2707ff5350a8SAndy Lutomirski 2708ff5350a8SAndy Lutomirski return 0; 2709ff5350a8SAndy Lutomirski } 2710ff5350a8SAndy Lutomirski 271118119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 271218119775SKeith Busch { 271318119775SKeith Busch struct nvme_dev *dev = data; 271480f513b5SKeith Busch 271518119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 271618119775SKeith Busch flush_work(&dev->ctrl.scan_work); 271780f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 271818119775SKeith Busch } 271918119775SKeith Busch 272057dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 272157dacad5SJay Sternberg { 272257dacad5SJay Sternberg int node, result = -ENOMEM; 272357dacad5SJay Sternberg struct nvme_dev *dev; 2724ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2725943e942eSJens Axboe size_t alloc_size; 272657dacad5SJay Sternberg 272757dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 272857dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27292fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 273057dacad5SJay Sternberg 273157dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 273257dacad5SJay Sternberg if (!dev) 273357dacad5SJay Sternberg return -ENOMEM; 2734147b27e4SSagi Grimberg 27353b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27363b6592f7SJens Axboe GFP_KERNEL, node); 273757dacad5SJay Sternberg if (!dev->queues) 273857dacad5SJay Sternberg goto free; 273957dacad5SJay Sternberg 274057dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 274157dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 274257dacad5SJay Sternberg 2743b00a726aSKeith Busch result = nvme_dev_map(dev); 2744b00a726aSKeith Busch if (result) 2745b00c9b7aSChristophe JAILLET goto put_pci; 2746b00a726aSKeith Busch 2747d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27485c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 274977bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2750f3ca80fcSChristoph Hellwig 2751f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2752f3ca80fcSChristoph Hellwig if (result) 2753b00c9b7aSChristophe JAILLET goto unmap; 2754f3ca80fcSChristoph Hellwig 27558427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2756ff5350a8SAndy Lutomirski 2757943e942eSJens Axboe /* 2758943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2759943e942eSJens Axboe * command we support. 2760943e942eSJens Axboe */ 2761943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2762943e942eSJens Axboe NVME_MAX_SEGS, true); 2763943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2764943e942eSJens Axboe 2765943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2766943e942eSJens Axboe mempool_kfree, 2767943e942eSJens Axboe (void *) alloc_size, 2768943e942eSJens Axboe GFP_KERNEL, node); 2769943e942eSJens Axboe if (!dev->iod_mempool) { 2770943e942eSJens Axboe result = -ENOMEM; 2771943e942eSJens Axboe goto release_pools; 2772943e942eSJens Axboe } 2773943e942eSJens Axboe 2774b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2775b6e44b4cSKeith Busch quirks); 2776b6e44b4cSKeith Busch if (result) 2777b6e44b4cSKeith Busch goto release_mempool; 2778b6e44b4cSKeith Busch 27791b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27801b3c47c1SSagi Grimberg 278180f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 278218119775SKeith Busch async_schedule(nvme_async_probe, dev); 27834caff8fcSSagi Grimberg 278457dacad5SJay Sternberg return 0; 278557dacad5SJay Sternberg 2786b6e44b4cSKeith Busch release_mempool: 2787b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 278857dacad5SJay Sternberg release_pools: 278957dacad5SJay Sternberg nvme_release_prp_pools(dev); 2790b00c9b7aSChristophe JAILLET unmap: 2791b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 279257dacad5SJay Sternberg put_pci: 279357dacad5SJay Sternberg put_device(dev->dev); 279457dacad5SJay Sternberg free: 279557dacad5SJay Sternberg kfree(dev->queues); 279657dacad5SJay Sternberg kfree(dev); 279757dacad5SJay Sternberg return result; 279857dacad5SJay Sternberg } 279957dacad5SJay Sternberg 2800775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 280157dacad5SJay Sternberg { 280257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2803a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2804775755edSChristoph Hellwig } 280557dacad5SJay Sternberg 2806775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2807775755edSChristoph Hellwig { 2808f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 280979c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 281057dacad5SJay Sternberg } 281157dacad5SJay Sternberg 281257dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 281357dacad5SJay Sternberg { 281457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2815a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 281657dacad5SJay Sternberg } 281757dacad5SJay Sternberg 2818f58944e2SKeith Busch /* 2819f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2820f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2821f58944e2SKeith Busch * order to proceed. 2822f58944e2SKeith Busch */ 282357dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 282457dacad5SJay Sternberg { 282557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 282657dacad5SJay Sternberg 2827bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 282857dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28290ff9d4e1SKeith Busch 28306db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28310ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28321d39e692SKeith Busch nvme_dev_disable(dev, true); 2833cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28346db28edaSKeith Busch } 28350ff9d4e1SKeith Busch 2836d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2837d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2838d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2839a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28409fe5c59fSKeith Busch nvme_release_cmb(dev); 284187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 284257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 284357dacad5SJay Sternberg nvme_free_queues(dev, 0); 2844d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 284557dacad5SJay Sternberg nvme_release_prp_pools(dev); 2846b00a726aSKeith Busch nvme_dev_unmap(dev); 28471673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 284857dacad5SJay Sternberg } 284957dacad5SJay Sternberg 285057dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 285157dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 285257dacad5SJay Sternberg { 285357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 285457dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 285557dacad5SJay Sternberg 2856a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 285757dacad5SJay Sternberg return 0; 285857dacad5SJay Sternberg } 285957dacad5SJay Sternberg 286057dacad5SJay Sternberg static int nvme_resume(struct device *dev) 286157dacad5SJay Sternberg { 286257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 286357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 286457dacad5SJay Sternberg 2865d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 286657dacad5SJay Sternberg return 0; 286757dacad5SJay Sternberg } 286857dacad5SJay Sternberg #endif 286957dacad5SJay Sternberg 287057dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 287157dacad5SJay Sternberg 2872a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2873a0a3408eSKeith Busch pci_channel_state_t state) 2874a0a3408eSKeith Busch { 2875a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2876a0a3408eSKeith Busch 2877a0a3408eSKeith Busch /* 2878a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2879a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2880a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2881a0a3408eSKeith Busch */ 2882a0a3408eSKeith Busch switch (state) { 2883a0a3408eSKeith Busch case pci_channel_io_normal: 2884a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2885a0a3408eSKeith Busch case pci_channel_io_frozen: 2886d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2887d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2888a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2889a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2890a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2891d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2892d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2893a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2894a0a3408eSKeith Busch } 2895a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2896a0a3408eSKeith Busch } 2897a0a3408eSKeith Busch 2898a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2899a0a3408eSKeith Busch { 2900a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2901a0a3408eSKeith Busch 29021b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2903a0a3408eSKeith Busch pci_restore_state(pdev); 2904d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2905a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2906a0a3408eSKeith Busch } 2907a0a3408eSKeith Busch 2908a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2909a0a3408eSKeith Busch { 291072cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 291172cd4cc2SKeith Busch 291272cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2913a0a3408eSKeith Busch } 2914a0a3408eSKeith Busch 291557dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 291657dacad5SJay Sternberg .error_detected = nvme_error_detected, 291757dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 291857dacad5SJay Sternberg .resume = nvme_error_resume, 2919775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2920775755edSChristoph Hellwig .reset_done = nvme_reset_done, 292157dacad5SJay Sternberg }; 292257dacad5SJay Sternberg 292357dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2924106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 292508095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2926e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 292799466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 292899466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2929e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 293099466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 293199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2932e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2933f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2934f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2935f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 293650af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 29379abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 29389abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 29396299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 29406299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 2941540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 29427b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 29437b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 29440302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 29450302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 294654adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 294754adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 29488c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 29498c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2950015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2951015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2952d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2953d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2954d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2955d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2956608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2957608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2958608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2959608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2960ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2961ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 296257dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2963c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2964124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 296557dacad5SJay Sternberg { 0, } 296657dacad5SJay Sternberg }; 296757dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 296857dacad5SJay Sternberg 296957dacad5SJay Sternberg static struct pci_driver nvme_driver = { 297057dacad5SJay Sternberg .name = "nvme", 297157dacad5SJay Sternberg .id_table = nvme_id_table, 297257dacad5SJay Sternberg .probe = nvme_probe, 297357dacad5SJay Sternberg .remove = nvme_remove, 297457dacad5SJay Sternberg .shutdown = nvme_shutdown, 297557dacad5SJay Sternberg .driver = { 297657dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 297757dacad5SJay Sternberg }, 297874d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 297957dacad5SJay Sternberg .err_handler = &nvme_err_handler, 298057dacad5SJay Sternberg }; 298157dacad5SJay Sternberg 298257dacad5SJay Sternberg static int __init nvme_init(void) 298357dacad5SJay Sternberg { 2984612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 29859a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 298657dacad5SJay Sternberg } 298757dacad5SJay Sternberg 298857dacad5SJay Sternberg static void __exit nvme_exit(void) 298957dacad5SJay Sternberg { 299057dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 299103e0f3a6SMing Lei flush_workqueue(nvme_wq); 299257dacad5SJay Sternberg _nvme_check_size(); 299357dacad5SJay Sternberg } 299457dacad5SJay Sternberg 299557dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 299657dacad5SJay Sternberg MODULE_LICENSE("GPL"); 299757dacad5SJay Sternberg MODULE_VERSION("1.0"); 299857dacad5SJay Sternberg module_init(nvme_init); 299957dacad5SJay Sternberg module_exit(nvme_exit); 3000