15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1457dacad5SJay Sternberg #include <linux/init.h> 1557dacad5SJay Sternberg #include <linux/interrupt.h> 1657dacad5SJay Sternberg #include <linux/io.h> 1757dacad5SJay Sternberg #include <linux/mm.h> 1857dacad5SJay Sternberg #include <linux/module.h> 1977bf25eaSKeith Busch #include <linux/mutex.h> 20d0877473SKeith Busch #include <linux/once.h> 2157dacad5SJay Sternberg #include <linux/pci.h> 22d916b1beSKeith Busch #include <linux/suspend.h> 2357dacad5SJay Sternberg #include <linux/t10-pi.h> 2457dacad5SJay Sternberg #include <linux/types.h> 259cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2620d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 27a98e58e5SScott Bauer #include <linux/sed-opal.h> 280f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2957dacad5SJay Sternberg 30604c01d5Syupeng #include "trace.h" 3157dacad5SJay Sternberg #include "nvme.h" 3257dacad5SJay Sternberg 33c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 348a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3557dacad5SJay Sternberg 36a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 37adf68f21SChristoph Hellwig 38943e942eSJens Axboe /* 39943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 40943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 41943e942eSJens Axboe */ 42943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 43943e942eSJens Axboe #define NVME_MAX_SEGS 127 44943e942eSJens Axboe 4557dacad5SJay Sternberg static int use_threaded_interrupts; 4657dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4757dacad5SJay Sternberg 4857dacad5SJay Sternberg static bool use_cmb_sqes = true; 4969f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5057dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5157dacad5SJay Sternberg 5287ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5387ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5487ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5587ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5657dacad5SJay Sternberg 57a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 58a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 59a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 60a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 61a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 62a7a7cbe3SChaitanya Kulkarni 63*27453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 64*27453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 65b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 66b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 67b27c1e68Sweiping zhang .set = io_queue_depth_set, 6861f3b896SChaitanya Kulkarni .get = param_get_uint, 69b27c1e68Sweiping zhang }; 70b27c1e68Sweiping zhang 7161f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 72b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 73*27453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 74b27c1e68Sweiping zhang 759c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 769c9e76d5SWeiping Zhang { 779c9e76d5SWeiping Zhang unsigned int n; 789c9e76d5SWeiping Zhang int ret; 799c9e76d5SWeiping Zhang 809c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 819c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 829c9e76d5SWeiping Zhang return -EINVAL; 839c9e76d5SWeiping Zhang return param_set_uint(val, kp); 849c9e76d5SWeiping Zhang } 859c9e76d5SWeiping Zhang 869c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 879c9e76d5SWeiping Zhang .set = io_queue_count_set, 889c9e76d5SWeiping Zhang .get = param_get_uint, 899c9e76d5SWeiping Zhang }; 909c9e76d5SWeiping Zhang 913f68baf7SKeith Busch static unsigned int write_queues; 929c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 933b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 943b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 953b6592f7SJens Axboe "will share a queue set."); 963b6592f7SJens Axboe 973f68baf7SKeith Busch static unsigned int poll_queues; 989c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 994b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1004b04cc6aSJens Axboe 101df4f9bc4SDavid E. Box static bool noacpi; 102df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 103df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 104df4f9bc4SDavid E. Box 1051c63dc66SChristoph Hellwig struct nvme_dev; 1061c63dc66SChristoph Hellwig struct nvme_queue; 10757dacad5SJay Sternberg 108a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1098fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11057dacad5SJay Sternberg 11157dacad5SJay Sternberg /* 1121c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1131c63dc66SChristoph Hellwig */ 1141c63dc66SChristoph Hellwig struct nvme_dev { 115147b27e4SSagi Grimberg struct nvme_queue *queues; 1161c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1171c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1181c63dc66SChristoph Hellwig u32 __iomem *dbs; 1191c63dc66SChristoph Hellwig struct device *dev; 1201c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1211c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1221c63dc66SChristoph Hellwig unsigned online_queues; 1231c63dc66SChristoph Hellwig unsigned max_qid; 124e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12522b55601SKeith Busch unsigned int num_vecs; 1267442ddceSJohn Garry u32 q_depth; 127c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1281c63dc66SChristoph Hellwig u32 db_stride; 1291c63dc66SChristoph Hellwig void __iomem *bar; 13097f6ef64SXu Yu unsigned long bar_mapped_size; 1315c8809e6SChristoph Hellwig struct work_struct remove_work; 13277bf25eaSKeith Busch struct mutex shutdown_lock; 1331c63dc66SChristoph Hellwig bool subsystem; 1341c63dc66SChristoph Hellwig u64 cmb_size; 1350f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1361c63dc66SChristoph Hellwig u32 cmbsz; 137202021c1SStephen Bates u32 cmbloc; 1381c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 139d916b1beSKeith Busch u32 last_ps; 14087ad72a5SChristoph Hellwig 141943e942eSJens Axboe mempool_t *iod_mempool; 142943e942eSJens Axboe 14387ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 144f9f38e33SHelen Koike u32 *dbbuf_dbs; 145f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 146f9f38e33SHelen Koike u32 *dbbuf_eis; 147f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 14887ad72a5SChristoph Hellwig 14987ad72a5SChristoph Hellwig /* host memory buffer support: */ 15087ad72a5SChristoph Hellwig u64 host_mem_size; 15187ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1524033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15487ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1552a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1562a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1572a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 15857dacad5SJay Sternberg }; 15957dacad5SJay Sternberg 160b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 161b27c1e68Sweiping zhang { 162*27453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 163*27453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 164b27c1e68Sweiping zhang } 165b27c1e68Sweiping zhang 166f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 167f9f38e33SHelen Koike { 168f9f38e33SHelen Koike return qid * 2 * stride; 169f9f38e33SHelen Koike } 170f9f38e33SHelen Koike 171f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 172f9f38e33SHelen Koike { 173f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 174f9f38e33SHelen Koike } 175f9f38e33SHelen Koike 1761c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1771c63dc66SChristoph Hellwig { 1781c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1791c63dc66SChristoph Hellwig } 1801c63dc66SChristoph Hellwig 18157dacad5SJay Sternberg /* 18257dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18357dacad5SJay Sternberg * commands and one for I/O commands). 18457dacad5SJay Sternberg */ 18557dacad5SJay Sternberg struct nvme_queue { 18657dacad5SJay Sternberg struct nvme_dev *dev; 1871ab0cd69SJens Axboe spinlock_t sq_lock; 188c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1893a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1903a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19174943d45SKeith Busch struct nvme_completion *cqes; 19257dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19357dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19457dacad5SJay Sternberg u32 __iomem *q_db; 1957442ddceSJohn Garry u32 q_depth; 1967c349ddeSKeith Busch u16 cq_vector; 19757dacad5SJay Sternberg u16 sq_tail; 19838210800SKeith Busch u16 last_sq_tail; 19957dacad5SJay Sternberg u16 cq_head; 20057dacad5SJay Sternberg u16 qid; 20157dacad5SJay Sternberg u8 cq_phase; 202c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2034e224106SChristoph Hellwig unsigned long flags; 2044e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20563223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 206d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2077c349ddeSKeith Busch #define NVMEQ_POLLED 3 208f9f38e33SHelen Koike u32 *dbbuf_sq_db; 209f9f38e33SHelen Koike u32 *dbbuf_cq_db; 210f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 211f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 212d1ed6aa1SChristoph Hellwig struct completion delete_done; 21357dacad5SJay Sternberg }; 21457dacad5SJay Sternberg 21557dacad5SJay Sternberg /* 2169b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2179b048119SChristoph Hellwig * 2189b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2199b048119SChristoph Hellwig * to the actual struct scatterlist. 22071bd150cSChristoph Hellwig */ 22171bd150cSChristoph Hellwig struct nvme_iod { 222d49187e9SChristoph Hellwig struct nvme_request req; 223af7fae85SKeith Busch struct nvme_command cmd; 224f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 225a7a7cbe3SChaitanya Kulkarni bool use_sgl; 226f4800d6dSChristoph Hellwig int aborted; 22771bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22871bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22971bd150cSChristoph Hellwig dma_addr_t first_dma; 230dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 231783b94bdSChristoph Hellwig dma_addr_t meta_dma; 232f4800d6dSChristoph Hellwig struct scatterlist *sg; 23357dacad5SJay Sternberg }; 23457dacad5SJay Sternberg 2352a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2363b6592f7SJens Axboe { 2372a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 238f9f38e33SHelen Koike } 239f9f38e33SHelen Koike 240f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 241f9f38e33SHelen Koike { 2422a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 243f9f38e33SHelen Koike 244f9f38e33SHelen Koike if (dev->dbbuf_dbs) 245f9f38e33SHelen Koike return 0; 246f9f38e33SHelen Koike 247f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 248f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 249f9f38e33SHelen Koike GFP_KERNEL); 250f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 251f9f38e33SHelen Koike return -ENOMEM; 252f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 253f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 254f9f38e33SHelen Koike GFP_KERNEL); 255f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 256f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 257f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 258f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 259f9f38e33SHelen Koike return -ENOMEM; 260f9f38e33SHelen Koike } 261f9f38e33SHelen Koike 262f9f38e33SHelen Koike return 0; 263f9f38e33SHelen Koike } 264f9f38e33SHelen Koike 265f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 266f9f38e33SHelen Koike { 2672a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 268f9f38e33SHelen Koike 269f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 270f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 271f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 272f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 273f9f38e33SHelen Koike } 274f9f38e33SHelen Koike if (dev->dbbuf_eis) { 275f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 276f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 277f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 278f9f38e33SHelen Koike } 279f9f38e33SHelen Koike } 280f9f38e33SHelen Koike 281f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 282f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 283f9f38e33SHelen Koike { 284f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 285f9f38e33SHelen Koike return; 286f9f38e33SHelen Koike 287f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 288f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 289f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 290f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 291f9f38e33SHelen Koike } 292f9f38e33SHelen Koike 2930f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 2940f0d2c87SMinwoo Im { 2950f0d2c87SMinwoo Im if (!nvmeq->qid) 2960f0d2c87SMinwoo Im return; 2970f0d2c87SMinwoo Im 2980f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 2990f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3000f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3010f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3020f0d2c87SMinwoo Im } 3030f0d2c87SMinwoo Im 304f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 305f9f38e33SHelen Koike { 306f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3070f0d2c87SMinwoo Im unsigned int i; 308f9f38e33SHelen Koike 309f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 310f9f38e33SHelen Koike return; 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 313f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 314f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 315f9f38e33SHelen Koike 316f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3179bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 318f9f38e33SHelen Koike /* Free memory and continue on */ 319f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3200f0d2c87SMinwoo Im 3210f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3220f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 323f9f38e33SHelen Koike } 324f9f38e33SHelen Koike } 325f9f38e33SHelen Koike 326f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 327f9f38e33SHelen Koike { 328f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 329f9f38e33SHelen Koike } 330f9f38e33SHelen Koike 331f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 332f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 333f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 334f9f38e33SHelen Koike { 335f9f38e33SHelen Koike if (dbbuf_db) { 336f9f38e33SHelen Koike u16 old_value; 337f9f38e33SHelen Koike 338f9f38e33SHelen Koike /* 339f9f38e33SHelen Koike * Ensure that the queue is written before updating 340f9f38e33SHelen Koike * the doorbell in memory 341f9f38e33SHelen Koike */ 342f9f38e33SHelen Koike wmb(); 343f9f38e33SHelen Koike 344f9f38e33SHelen Koike old_value = *dbbuf_db; 345f9f38e33SHelen Koike *dbbuf_db = value; 346f9f38e33SHelen Koike 347f1ed3df2SMichal Wnukowski /* 348f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 349f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 350f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 351f1ed3df2SMichal Wnukowski * the doorbell. 352f1ed3df2SMichal Wnukowski */ 353f1ed3df2SMichal Wnukowski mb(); 354f1ed3df2SMichal Wnukowski 355f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 356f9f38e33SHelen Koike return false; 357f9f38e33SHelen Koike } 358f9f38e33SHelen Koike 359f9f38e33SHelen Koike return true; 36057dacad5SJay Sternberg } 36157dacad5SJay Sternberg 36257dacad5SJay Sternberg /* 36357dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 36457dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 36557dacad5SJay Sternberg * the I/O. 36657dacad5SJay Sternberg */ 367b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 36857dacad5SJay Sternberg { 369b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3706c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 37157dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 37257dacad5SJay Sternberg } 37357dacad5SJay Sternberg 374a7a7cbe3SChaitanya Kulkarni /* 375a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 376a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 377a7a7cbe3SChaitanya Kulkarni */ 378b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 379f4800d6dSChristoph Hellwig { 380b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 381b13c6393SChaitanya Kulkarni PAGE_SIZE); 382f4800d6dSChristoph Hellwig } 383f4800d6dSChristoph Hellwig 384b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 38557dacad5SJay Sternberg { 386b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 387a7a7cbe3SChaitanya Kulkarni 388b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 389b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 390a7a7cbe3SChaitanya Kulkarni } 391a7a7cbe3SChaitanya Kulkarni 39257dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39357dacad5SJay Sternberg unsigned int hctx_idx) 39457dacad5SJay Sternberg { 39557dacad5SJay Sternberg struct nvme_dev *dev = data; 396147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 39757dacad5SJay Sternberg 39857dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 39957dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40057dacad5SJay Sternberg 40157dacad5SJay Sternberg hctx->driver_data = nvmeq; 40257dacad5SJay Sternberg return 0; 40357dacad5SJay Sternberg } 40457dacad5SJay Sternberg 40557dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40657dacad5SJay Sternberg unsigned int hctx_idx) 40757dacad5SJay Sternberg { 40857dacad5SJay Sternberg struct nvme_dev *dev = data; 409147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41057dacad5SJay Sternberg 41157dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41257dacad5SJay Sternberg hctx->driver_data = nvmeq; 41357dacad5SJay Sternberg return 0; 41457dacad5SJay Sternberg } 41557dacad5SJay Sternberg 416d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 417d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 41857dacad5SJay Sternberg { 419d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 420f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4210350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 422147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 42357dacad5SJay Sternberg 42457dacad5SJay Sternberg BUG_ON(!nvmeq); 425f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 42659e29ce6SSagi Grimberg 42759e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 428f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 42957dacad5SJay Sternberg return 0; 43057dacad5SJay Sternberg } 43157dacad5SJay Sternberg 4323b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4333b6592f7SJens Axboe { 4343b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4353b6592f7SJens Axboe if (dev->num_vecs > 1) 4363b6592f7SJens Axboe return 1; 4373b6592f7SJens Axboe 4383b6592f7SJens Axboe return 0; 4393b6592f7SJens Axboe } 4403b6592f7SJens Axboe 441dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 442dca51e78SChristoph Hellwig { 443dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4443b6592f7SJens Axboe int i, qoff, offset; 445dca51e78SChristoph Hellwig 4463b6592f7SJens Axboe offset = queue_irq_offset(dev); 4473b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4483b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4493b6592f7SJens Axboe 4503b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4513b6592f7SJens Axboe if (!map->nr_queues) { 452e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4537e849dd9SChristoph Hellwig continue; 4543b6592f7SJens Axboe } 4553b6592f7SJens Axboe 4564b04cc6aSJens Axboe /* 4574b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4584b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4594b04cc6aSJens Axboe */ 4603b6592f7SJens Axboe map->queue_offset = qoff; 461cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4623b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4634b04cc6aSJens Axboe else 4644b04cc6aSJens Axboe blk_mq_map_queues(map); 4653b6592f7SJens Axboe qoff += map->nr_queues; 4663b6592f7SJens Axboe offset += map->nr_queues; 4673b6592f7SJens Axboe } 4683b6592f7SJens Axboe 4693b6592f7SJens Axboe return 0; 470dca51e78SChristoph Hellwig } 471dca51e78SChristoph Hellwig 47238210800SKeith Busch /* 47338210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47438210800SKeith Busch */ 47538210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47604f3eafdSJens Axboe { 47738210800SKeith Busch if (!write_sq) { 47838210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 47938210800SKeith Busch 48038210800SKeith Busch if (next_tail == nvmeq->q_depth) 48138210800SKeith Busch next_tail = 0; 48238210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 48338210800SKeith Busch return; 48438210800SKeith Busch } 48538210800SKeith Busch 48604f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 48704f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 48804f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 48938210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 49004f3eafdSJens Axboe } 49104f3eafdSJens Axboe 49257dacad5SJay Sternberg /** 49390ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 49457dacad5SJay Sternberg * @nvmeq: The queue to use 49557dacad5SJay Sternberg * @cmd: The command to send 49604f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 49757dacad5SJay Sternberg */ 49804f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 49904f3eafdSJens Axboe bool write_sq) 50057dacad5SJay Sternberg { 50190ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 502c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 503c1e0cc7eSBenjamin Herrenschmidt cmd, sizeof(*cmd)); 50490ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 50590ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 50638210800SKeith Busch nvme_write_sq_db(nvmeq, write_sq); 50704f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 50804f3eafdSJens Axboe } 50904f3eafdSJens Axboe 51004f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 51104f3eafdSJens Axboe { 51204f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 51304f3eafdSJens Axboe 51404f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 51538210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 51638210800SKeith Busch nvme_write_sq_db(nvmeq, true); 51790ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 51857dacad5SJay Sternberg } 51957dacad5SJay Sternberg 520a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 52157dacad5SJay Sternberg { 522f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 523a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 52457dacad5SJay Sternberg } 52557dacad5SJay Sternberg 526955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 527955b1b5aSMinwoo Im { 528955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 52920469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 530955b1b5aSMinwoo Im unsigned int avg_seg_size; 531955b1b5aSMinwoo Im 53220469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 533955b1b5aSMinwoo Im 534253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 535955b1b5aSMinwoo Im return false; 536955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 537955b1b5aSMinwoo Im return false; 538955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 539955b1b5aSMinwoo Im return false; 540955b1b5aSMinwoo Im return true; 541955b1b5aSMinwoo Im } 542955b1b5aSMinwoo Im 5439275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 54457dacad5SJay Sternberg { 5456c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5469275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5479275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 54857dacad5SJay Sternberg int i; 54957dacad5SJay Sternberg 5509275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5519275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5529275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5539275c206SChristoph Hellwig 5549275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5559275c206SChristoph Hellwig dma_addr = next_dma_addr; 556dff824b2SChristoph Hellwig } 5579275c206SChristoph Hellwig } 5589275c206SChristoph Hellwig 5599275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5609275c206SChristoph Hellwig { 5619275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5629275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5639275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5649275c206SChristoph Hellwig int i; 5659275c206SChristoph Hellwig 5669275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5679275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5689275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5699275c206SChristoph Hellwig 5709275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5719275c206SChristoph Hellwig dma_addr = next_dma_addr; 5729275c206SChristoph Hellwig } 5739275c206SChristoph Hellwig } 5749275c206SChristoph Hellwig 5759275c206SChristoph Hellwig static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 5769275c206SChristoph Hellwig { 5779275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 578dff824b2SChristoph Hellwig 5797f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5807f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5817f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5827f73eac3SLogan Gunthorpe else 583dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5849275c206SChristoph Hellwig } 5857fe07d14SChristoph Hellwig 5869275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5879275c206SChristoph Hellwig { 5889275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5897fe07d14SChristoph Hellwig 5909275c206SChristoph Hellwig if (iod->dma_len) { 5919275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5929275c206SChristoph Hellwig rq_dma_dir(req)); 5939275c206SChristoph Hellwig return; 5949275c206SChristoph Hellwig } 5959275c206SChristoph Hellwig 5969275c206SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 5979275c206SChristoph Hellwig 5989275c206SChristoph Hellwig nvme_unmap_sg(dev, req); 59957dacad5SJay Sternberg if (iod->npages == 0) 600a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 6019275c206SChristoph Hellwig iod->first_dma); 6029275c206SChristoph Hellwig else if (iod->use_sgl) 6039275c206SChristoph Hellwig nvme_free_sgls(dev, req); 6049275c206SChristoph Hellwig else 6059275c206SChristoph Hellwig nvme_free_prps(dev, req); 606943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 60757dacad5SJay Sternberg } 60857dacad5SJay Sternberg 609d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 610d0877473SKeith Busch { 611d0877473SKeith Busch int i; 612d0877473SKeith Busch struct scatterlist *sg; 613d0877473SKeith Busch 614d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 615d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 616d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 617d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 618d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 619d0877473SKeith Busch sg_dma_len(sg)); 620d0877473SKeith Busch } 621d0877473SKeith Busch } 622d0877473SKeith Busch 623a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 624a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 62557dacad5SJay Sternberg { 626f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 62757dacad5SJay Sternberg struct dma_pool *pool; 628b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 62957dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 63057dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 63157dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6326c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 63357dacad5SJay Sternberg __le64 *prp_list; 634a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 63557dacad5SJay Sternberg dma_addr_t prp_dma; 63657dacad5SJay Sternberg int nprps, i; 63757dacad5SJay Sternberg 6386c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6395228b328SJan H. Schönherr if (length <= 0) { 6405228b328SJan H. Schönherr iod->first_dma = 0; 641a7a7cbe3SChaitanya Kulkarni goto done; 6425228b328SJan H. Schönherr } 64357dacad5SJay Sternberg 6446c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 64557dacad5SJay Sternberg if (dma_len) { 6466c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 64757dacad5SJay Sternberg } else { 64857dacad5SJay Sternberg sg = sg_next(sg); 64957dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65057dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65157dacad5SJay Sternberg } 65257dacad5SJay Sternberg 6536c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 65457dacad5SJay Sternberg iod->first_dma = dma_addr; 655a7a7cbe3SChaitanya Kulkarni goto done; 65657dacad5SJay Sternberg } 65757dacad5SJay Sternberg 6586c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 65957dacad5SJay Sternberg if (nprps <= (256 / 8)) { 66057dacad5SJay Sternberg pool = dev->prp_small_pool; 66157dacad5SJay Sternberg iod->npages = 0; 66257dacad5SJay Sternberg } else { 66357dacad5SJay Sternberg pool = dev->prp_page_pool; 66457dacad5SJay Sternberg iod->npages = 1; 66557dacad5SJay Sternberg } 66657dacad5SJay Sternberg 66769d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 66857dacad5SJay Sternberg if (!prp_list) { 66957dacad5SJay Sternberg iod->first_dma = dma_addr; 67057dacad5SJay Sternberg iod->npages = -1; 67186eea289SKeith Busch return BLK_STS_RESOURCE; 67257dacad5SJay Sternberg } 67357dacad5SJay Sternberg list[0] = prp_list; 67457dacad5SJay Sternberg iod->first_dma = prp_dma; 67557dacad5SJay Sternberg i = 0; 67657dacad5SJay Sternberg for (;;) { 6776c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 67857dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 67969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68057dacad5SJay Sternberg if (!prp_list) 681fa073216SChristoph Hellwig goto free_prps; 68257dacad5SJay Sternberg list[iod->npages++] = prp_list; 68357dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 68457dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 68557dacad5SJay Sternberg i = 1; 68657dacad5SJay Sternberg } 68757dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6886c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6896c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6906c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 69157dacad5SJay Sternberg if (length <= 0) 69257dacad5SJay Sternberg break; 69357dacad5SJay Sternberg if (dma_len > 0) 69457dacad5SJay Sternberg continue; 69586eea289SKeith Busch if (unlikely(dma_len < 0)) 69686eea289SKeith Busch goto bad_sgl; 69757dacad5SJay Sternberg sg = sg_next(sg); 69857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 70057dacad5SJay Sternberg } 701a7a7cbe3SChaitanya Kulkarni done: 702a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 703a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 70486eea289SKeith Busch return BLK_STS_OK; 705fa073216SChristoph Hellwig free_prps: 706fa073216SChristoph Hellwig nvme_free_prps(dev, req); 707fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 70886eea289SKeith Busch bad_sgl: 709d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 710d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 711d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 71286eea289SKeith Busch return BLK_STS_IOERR; 71357dacad5SJay Sternberg } 71457dacad5SJay Sternberg 715a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 716a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 717a7a7cbe3SChaitanya Kulkarni { 718a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 719a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 720a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 721a7a7cbe3SChaitanya Kulkarni } 722a7a7cbe3SChaitanya Kulkarni 723a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 724a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 725a7a7cbe3SChaitanya Kulkarni { 726a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 727a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 728a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 729a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 730a7a7cbe3SChaitanya Kulkarni } else { 731a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 732a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 733a7a7cbe3SChaitanya Kulkarni } 734a7a7cbe3SChaitanya Kulkarni } 735a7a7cbe3SChaitanya Kulkarni 736a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 737b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 738a7a7cbe3SChaitanya Kulkarni { 739a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 740a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 741a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 742a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 743a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 744b0f2853bSChristoph Hellwig int i = 0; 745a7a7cbe3SChaitanya Kulkarni 746a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 747a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 748a7a7cbe3SChaitanya Kulkarni 749b0f2853bSChristoph Hellwig if (entries == 1) { 750a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 751a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 752a7a7cbe3SChaitanya Kulkarni } 753a7a7cbe3SChaitanya Kulkarni 754a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 755a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 756a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 757a7a7cbe3SChaitanya Kulkarni } else { 758a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 759a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 760a7a7cbe3SChaitanya Kulkarni } 761a7a7cbe3SChaitanya Kulkarni 762a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 763a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 764a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 765a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 766a7a7cbe3SChaitanya Kulkarni } 767a7a7cbe3SChaitanya Kulkarni 768a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 769a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 770a7a7cbe3SChaitanya Kulkarni 771a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni do { 774a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 775a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 776a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 777a7a7cbe3SChaitanya Kulkarni 778a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 779a7a7cbe3SChaitanya Kulkarni if (!sg_list) 780fa073216SChristoph Hellwig goto free_sgls; 781a7a7cbe3SChaitanya Kulkarni 782a7a7cbe3SChaitanya Kulkarni i = 0; 783a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 784a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 785a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 786a7a7cbe3SChaitanya Kulkarni } 787a7a7cbe3SChaitanya Kulkarni 788a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 789a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 790b0f2853bSChristoph Hellwig } while (--entries > 0); 791a7a7cbe3SChaitanya Kulkarni 792a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 793fa073216SChristoph Hellwig free_sgls: 794fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 795fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 796a7a7cbe3SChaitanya Kulkarni } 797a7a7cbe3SChaitanya Kulkarni 798dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 799dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 800dff824b2SChristoph Hellwig struct bio_vec *bv) 801dff824b2SChristoph Hellwig { 802dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8036c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 8046c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 805dff824b2SChristoph Hellwig 806dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 807dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 808dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 809dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 810dff824b2SChristoph Hellwig 811dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 812dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 813dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 814359c1f88SBaolin Wang return BLK_STS_OK; 815dff824b2SChristoph Hellwig } 816dff824b2SChristoph Hellwig 81729791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 81829791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 81929791057SChristoph Hellwig struct bio_vec *bv) 82029791057SChristoph Hellwig { 82129791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82229791057SChristoph Hellwig 82329791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 82429791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 82529791057SChristoph Hellwig return BLK_STS_RESOURCE; 82629791057SChristoph Hellwig iod->dma_len = bv->bv_len; 82729791057SChristoph Hellwig 828049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 82929791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 83029791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 83129791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 832359c1f88SBaolin Wang return BLK_STS_OK; 83329791057SChristoph Hellwig } 83429791057SChristoph Hellwig 835fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 836b131c61dSChristoph Hellwig struct nvme_command *cmnd) 83757dacad5SJay Sternberg { 838f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 83970479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 840b0f2853bSChristoph Hellwig int nr_mapped; 84157dacad5SJay Sternberg 842dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 843dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 844dff824b2SChristoph Hellwig 845dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8466c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 847dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 848dff824b2SChristoph Hellwig &cmnd->rw, &bv); 84929791057SChristoph Hellwig 850e51183beSNiklas Cassel if (iod->nvmeq->qid && sgl_threshold && 851253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 85229791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 85329791057SChristoph Hellwig &cmnd->rw, &bv); 854dff824b2SChristoph Hellwig } 855dff824b2SChristoph Hellwig } 856dff824b2SChristoph Hellwig 857dff824b2SChristoph Hellwig iod->dma_len = 0; 8589b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8599b048119SChristoph Hellwig if (!iod->sg) 8609b048119SChristoph Hellwig return BLK_STS_RESOURCE; 861f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 86270479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 863ba1ca37eSChristoph Hellwig if (!iod->nents) 864fa073216SChristoph Hellwig goto out_free_sg; 865ba1ca37eSChristoph Hellwig 866e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8672b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8682b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 869e0596ab2SLogan Gunthorpe else 870e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 87170479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 872b0f2853bSChristoph Hellwig if (!nr_mapped) 873fa073216SChristoph Hellwig goto out_free_sg; 874ba1ca37eSChristoph Hellwig 87570479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 876955b1b5aSMinwoo Im if (iod->use_sgl) 877b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 878a7a7cbe3SChaitanya Kulkarni else 879a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8804aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 881fa073216SChristoph Hellwig goto out_unmap_sg; 882fa073216SChristoph Hellwig return BLK_STS_OK; 883fa073216SChristoph Hellwig 884fa073216SChristoph Hellwig out_unmap_sg: 885fa073216SChristoph Hellwig nvme_unmap_sg(dev, req); 886fa073216SChristoph Hellwig out_free_sg: 887fa073216SChristoph Hellwig mempool_free(iod->sg, dev->iod_mempool); 888ba1ca37eSChristoph Hellwig return ret; 88957dacad5SJay Sternberg } 89057dacad5SJay Sternberg 8914aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8924aedb705SChristoph Hellwig struct nvme_command *cmnd) 8934aedb705SChristoph Hellwig { 8944aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8954aedb705SChristoph Hellwig 8964aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8974aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8984aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8994aedb705SChristoph Hellwig return BLK_STS_IOERR; 9004aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 901359c1f88SBaolin Wang return BLK_STS_OK; 9024aedb705SChristoph Hellwig } 9034aedb705SChristoph Hellwig 90457dacad5SJay Sternberg /* 90557dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 90657dacad5SJay Sternberg */ 907fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 90857dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 90957dacad5SJay Sternberg { 91057dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 91157dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 91257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 91357dacad5SJay Sternberg struct request *req = bd->rq; 9149b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 915af7fae85SKeith Busch struct nvme_command *cmnd = &iod->cmd; 916ebe6d874SChristoph Hellwig blk_status_t ret; 91757dacad5SJay Sternberg 9189b048119SChristoph Hellwig iod->aborted = 0; 9199b048119SChristoph Hellwig iod->npages = -1; 9209b048119SChristoph Hellwig iod->nents = 0; 9219b048119SChristoph Hellwig 922d1f06f4aSJens Axboe /* 923d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 924d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 925d1f06f4aSJens Axboe */ 9264e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 927d1f06f4aSJens Axboe return BLK_STS_IOERR; 928d1f06f4aSJens Axboe 929d4060d2bSTao Chiu if (!nvme_check_ready(&dev->ctrl, req, true)) 930d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 931d4060d2bSTao Chiu 932f4b9e6c9SKeith Busch ret = nvme_setup_cmd(ns, req); 933fc17b653SChristoph Hellwig if (ret) 934f4800d6dSChristoph Hellwig return ret; 93557dacad5SJay Sternberg 936fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 937af7fae85SKeith Busch ret = nvme_map_data(dev, req, cmnd); 938fc17b653SChristoph Hellwig if (ret) 9399b048119SChristoph Hellwig goto out_free_cmd; 940fc17b653SChristoph Hellwig } 941ba1ca37eSChristoph Hellwig 9424aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 943af7fae85SKeith Busch ret = nvme_map_metadata(dev, req, cmnd); 9444aedb705SChristoph Hellwig if (ret) 9454aedb705SChristoph Hellwig goto out_unmap_data; 9464aedb705SChristoph Hellwig } 9474aedb705SChristoph Hellwig 948aae239e1SChristoph Hellwig blk_mq_start_request(req); 949af7fae85SKeith Busch nvme_submit_cmd(nvmeq, cmnd, bd->last); 950fc17b653SChristoph Hellwig return BLK_STS_OK; 9514aedb705SChristoph Hellwig out_unmap_data: 9524aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 953f9d03f96SChristoph Hellwig out_free_cmd: 954f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 955ba1ca37eSChristoph Hellwig return ret; 95657dacad5SJay Sternberg } 95757dacad5SJay Sternberg 95877f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 959eee417b0SChristoph Hellwig { 960f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9614aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 962eee417b0SChristoph Hellwig 9634aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9644aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9654aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 966b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9674aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 96877f02a7aSChristoph Hellwig nvme_complete_rq(req); 96957dacad5SJay Sternberg } 97057dacad5SJay Sternberg 971d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 972750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 973d783e0bdSMarta Rybczynska { 97474943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 97574943d45SKeith Busch 97674943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 977d783e0bdSMarta Rybczynska } 978d783e0bdSMarta Rybczynska 979eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 98057dacad5SJay Sternberg { 981eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 98257dacad5SJay Sternberg 983eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 984eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 985eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 986eb281c82SSagi Grimberg } 987adf68f21SChristoph Hellwig 988cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 989cfa27356SChristoph Hellwig { 990cfa27356SChristoph Hellwig if (!nvmeq->qid) 991cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 992cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 993cfa27356SChristoph Hellwig } 994cfa27356SChristoph Hellwig 9955cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 99657dacad5SJay Sternberg { 99774943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 99862df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 99957dacad5SJay Sternberg struct request *req; 1000adf68f21SChristoph Hellwig 1001adf68f21SChristoph Hellwig /* 1002adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1003adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1004adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1005adf68f21SChristoph Hellwig * for them but rather special case them here. 1006adf68f21SChristoph Hellwig */ 100762df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10087bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 100983a12fb7SSagi Grimberg cqe->status, &cqe->result); 1010a0fa9647SJens Axboe return; 101157dacad5SJay Sternberg } 101257dacad5SJay Sternberg 101362df8016SLalithambika Krishnakumar req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id); 101450b7c243SXianting Tian if (unlikely(!req)) { 101550b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 101650b7c243SXianting Tian "invalid id %d completed on queue %d\n", 101762df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 101850b7c243SXianting Tian return; 101950b7c243SXianting Tian } 102050b7c243SXianting Tian 1021604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 10222eb81a33SChristoph Hellwig if (!nvme_try_complete_req(req, cqe->status, cqe->result)) 1023ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 102483a12fb7SSagi Grimberg } 102557dacad5SJay Sternberg 10265cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10275cb525c8SJens Axboe { 1028a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1029a8de6639SAlexey Dobriyan 1030a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1031920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1032e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1033a8de6639SAlexey Dobriyan } else { 1034a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1035920d13a8SSagi Grimberg } 1036a0fa9647SJens Axboe } 1037a0fa9647SJens Axboe 1038324b494cSKeith Busch static inline int nvme_process_cq(struct nvme_queue *nvmeq) 1039a0fa9647SJens Axboe { 10401052b8acSJens Axboe int found = 0; 104183a12fb7SSagi Grimberg 10421052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10431052b8acSJens Axboe found++; 1044b69e2ef2SKeith Busch /* 1045b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1046b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1047b69e2ef2SKeith Busch */ 1048b69e2ef2SKeith Busch dma_rmb(); 1049324b494cSKeith Busch nvme_handle_cqe(nvmeq, nvmeq->cq_head); 10505cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 105157dacad5SJay Sternberg } 105257dacad5SJay Sternberg 1053324b494cSKeith Busch if (found) 1054eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10555cb525c8SJens Axboe return found; 105657dacad5SJay Sternberg } 105757dacad5SJay Sternberg 105857dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 105957dacad5SJay Sternberg { 106057dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10615cb525c8SJens Axboe 1062324b494cSKeith Busch if (nvme_process_cq(nvmeq)) 106305fae499SChaitanya Kulkarni return IRQ_HANDLED; 106405fae499SChaitanya Kulkarni return IRQ_NONE; 106557dacad5SJay Sternberg } 106657dacad5SJay Sternberg 106757dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 106857dacad5SJay Sternberg { 106957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10704e523547SBaolin Wang 1071750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 107257dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1073d783e0bdSMarta Rybczynska return IRQ_NONE; 107457dacad5SJay Sternberg } 107557dacad5SJay Sternberg 10760b2a8a9fSChristoph Hellwig /* 1077fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 10780b2a8a9fSChristoph Hellwig * Can be called from any context. 10790b2a8a9fSChristoph Hellwig */ 1080fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1081a0fa9647SJens Axboe { 10823a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1083a0fa9647SJens Axboe 1084fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1085fa059b85SKeith Busch 10863a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1087fa059b85SKeith Busch nvme_process_cq(nvmeq); 10883a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 108991a509f8SChristoph Hellwig } 1090442e19b7SSagi Grimberg 10919743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10927776db1cSKeith Busch { 10937776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1094dabcefabSJens Axboe bool found; 1095dabcefabSJens Axboe 1096dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1097dabcefabSJens Axboe return 0; 1098dabcefabSJens Axboe 10993a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1100324b494cSKeith Busch found = nvme_process_cq(nvmeq); 11013a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1102dabcefabSJens Axboe 1103dabcefabSJens Axboe return found; 1104dabcefabSJens Axboe } 1105dabcefabSJens Axboe 1106ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 110757dacad5SJay Sternberg { 1108f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1109147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1110f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 111157dacad5SJay Sternberg 111257dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1113ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 111404f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 111557dacad5SJay Sternberg } 111657dacad5SJay Sternberg 111757dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 111857dacad5SJay Sternberg { 1119f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 112057dacad5SJay Sternberg 112157dacad5SJay Sternberg c.delete_queue.opcode = opcode; 112257dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 112357dacad5SJay Sternberg 11241c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 112557dacad5SJay Sternberg } 112657dacad5SJay Sternberg 112757dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1128a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 112957dacad5SJay Sternberg { 1130f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 11314b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11324b04cc6aSJens Axboe 11337c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11344b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 113557dacad5SJay Sternberg 113657dacad5SJay Sternberg /* 113716772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 113857dacad5SJay Sternberg * is attached to the request. 113957dacad5SJay Sternberg */ 114057dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 114157dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 114257dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 114357dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 114457dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1145a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 114657dacad5SJay Sternberg 11471c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 114857dacad5SJay Sternberg } 114957dacad5SJay Sternberg 115057dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 115157dacad5SJay Sternberg struct nvme_queue *nvmeq) 115257dacad5SJay Sternberg { 11539abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1154f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 115581c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 115657dacad5SJay Sternberg 115757dacad5SJay Sternberg /* 11589abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11599abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11609abd68efSJens Axboe * URGENT. 11619abd68efSJens Axboe */ 11629abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11639abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11649abd68efSJens Axboe 11659abd68efSJens Axboe /* 116616772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 116757dacad5SJay Sternberg * is attached to the request. 116857dacad5SJay Sternberg */ 116957dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 117057dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 117157dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 117257dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 117357dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 117457dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 117557dacad5SJay Sternberg 11761c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 117757dacad5SJay Sternberg } 117857dacad5SJay Sternberg 117957dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 118057dacad5SJay Sternberg { 118157dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 118257dacad5SJay Sternberg } 118357dacad5SJay Sternberg 118457dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 118557dacad5SJay Sternberg { 118657dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 118757dacad5SJay Sternberg } 118857dacad5SJay Sternberg 11892a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 119057dacad5SJay Sternberg { 1191f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1192f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 119357dacad5SJay Sternberg 119427fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 119527fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1196e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1197e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 119857dacad5SJay Sternberg } 119957dacad5SJay Sternberg 1200b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1201b2a0eb1aSKeith Busch { 1202b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1203b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1204b2a0eb1aSKeith Busch */ 1205b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1206b2a0eb1aSKeith Busch 1207ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1208ad70062cSJianchao Wang switch (dev->ctrl.state) { 1209ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1210ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1211b2a0eb1aSKeith Busch return false; 1212ad70062cSJianchao Wang default: 1213ad70062cSJianchao Wang break; 1214ad70062cSJianchao Wang } 1215b2a0eb1aSKeith Busch 1216b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1217b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1218b2a0eb1aSKeith Busch */ 1219b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1220b2a0eb1aSKeith Busch return false; 1221b2a0eb1aSKeith Busch 1222b2a0eb1aSKeith Busch return true; 1223b2a0eb1aSKeith Busch } 1224b2a0eb1aSKeith Busch 1225b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1226b2a0eb1aSKeith Busch { 1227b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1228b2a0eb1aSKeith Busch u16 pci_status; 1229b2a0eb1aSKeith Busch int result; 1230b2a0eb1aSKeith Busch 1231b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1232b2a0eb1aSKeith Busch &pci_status); 1233b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1234b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1235b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1236b2a0eb1aSKeith Busch csts, pci_status); 1237b2a0eb1aSKeith Busch else 1238b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1239b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1240b2a0eb1aSKeith Busch csts, result); 1241b2a0eb1aSKeith Busch } 1242b2a0eb1aSKeith Busch 124331c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 124457dacad5SJay Sternberg { 1245f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1246f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 124757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 124857dacad5SJay Sternberg struct request *abort_req; 1249f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1250b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1251b2a0eb1aSKeith Busch 1252651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1253651438bbSWen Xiong * the recovery mechanism will surely fail. 1254651438bbSWen Xiong */ 1255651438bbSWen Xiong mb(); 1256651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1257651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1258651438bbSWen Xiong 1259b2a0eb1aSKeith Busch /* 1260b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1261b2a0eb1aSKeith Busch */ 1262b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1263b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1264b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1265d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1266db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1267b2a0eb1aSKeith Busch } 126857dacad5SJay Sternberg 126931c7c7d2SChristoph Hellwig /* 12707776db1cSKeith Busch * Did we miss an interrupt? 12717776db1cSKeith Busch */ 1272fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1273fa059b85SKeith Busch nvme_poll(req->mq_hctx); 1274fa059b85SKeith Busch else 1275bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1276fa059b85SKeith Busch 1277bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 12787776db1cSKeith Busch dev_warn(dev->ctrl.device, 12797776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12807776db1cSKeith Busch req->tag, nvmeq->qid); 1281db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12827776db1cSKeith Busch } 12837776db1cSKeith Busch 12847776db1cSKeith Busch /* 1285fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1286fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1287fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1288db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1289fd634f41SChristoph Hellwig */ 12904244140dSKeith Busch switch (dev->ctrl.state) { 12914244140dSKeith Busch case NVME_CTRL_CONNECTING: 12922036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1293df561f66SGustavo A. R. Silva fallthrough; 12942036f726SKeith Busch case NVME_CTRL_DELETING: 1295b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1296fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1297fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 129827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 12997ad92f65STong Zhang nvme_dev_disable(dev, true); 1300db8c48e4SChristoph Hellwig return BLK_EH_DONE; 130139a9dd81SKeith Busch case NVME_CTRL_RESETTING: 130239a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13034244140dSKeith Busch default: 13044244140dSKeith Busch break; 1305fd634f41SChristoph Hellwig } 1306fd634f41SChristoph Hellwig 1307fd634f41SChristoph Hellwig /* 1308e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1309e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1310e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 131131c7c7d2SChristoph Hellwig */ 1312f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13131b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 131457dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 131557dacad5SJay Sternberg req->tag, nvmeq->qid); 13167ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1317a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1318d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1319e1569a16SKeith Busch 1320db8c48e4SChristoph Hellwig return BLK_EH_DONE; 132157dacad5SJay Sternberg } 132257dacad5SJay Sternberg 1323e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1324e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1325e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1326e7a2a87dSChristoph Hellwig } 13277bf7d778SKeith Busch iod->aborted = 1; 132857dacad5SJay Sternberg 132957dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 133057dacad5SJay Sternberg cmd.abort.cid = req->tag; 133157dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 133257dacad5SJay Sternberg 13331b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13341b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 133557dacad5SJay Sternberg req->tag, nvmeq->qid); 1336e7a2a87dSChristoph Hellwig 1337e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 133839dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 13396bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13406bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 134131c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 134257dacad5SJay Sternberg } 134357dacad5SJay Sternberg 1344e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 13458eeed0b5SGuoqing Jiang blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio); 134657dacad5SJay Sternberg 134757dacad5SJay Sternberg /* 134857dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 134957dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 135057dacad5SJay Sternberg * as the device then is in a faulty state. 135157dacad5SJay Sternberg */ 135257dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 135357dacad5SJay Sternberg } 135457dacad5SJay Sternberg 135557dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 135657dacad5SJay Sternberg { 13578a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 135857dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 135963223078SChristoph Hellwig if (!nvmeq->sq_cmds) 136063223078SChristoph Hellwig return; 13610f238ff5SLogan Gunthorpe 136263223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 136388a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13648a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 136563223078SChristoph Hellwig } else { 13668a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 136763223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13680f238ff5SLogan Gunthorpe } 136957dacad5SJay Sternberg } 137057dacad5SJay Sternberg 137157dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 137257dacad5SJay Sternberg { 137357dacad5SJay Sternberg int i; 137457dacad5SJay Sternberg 1375d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1376d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1377147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 137857dacad5SJay Sternberg } 137957dacad5SJay Sternberg } 138057dacad5SJay Sternberg 138157dacad5SJay Sternberg /** 138257dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 138340581d1aSBart Van Assche * @nvmeq: queue to suspend 138457dacad5SJay Sternberg */ 138557dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 138657dacad5SJay Sternberg { 13874e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 138857dacad5SJay Sternberg return 1; 138957dacad5SJay Sternberg 13904e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1391d1f06f4aSJens Axboe mb(); 139257dacad5SJay Sternberg 13934e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13941c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1395c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13967c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 13974e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 139857dacad5SJay Sternberg return 0; 139957dacad5SJay Sternberg } 140057dacad5SJay Sternberg 14018fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14028fae268bSKeith Busch { 14038fae268bSKeith Busch int i; 14048fae268bSKeith Busch 14058fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14068fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14078fae268bSKeith Busch } 14088fae268bSKeith Busch 1409a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 141057dacad5SJay Sternberg { 1411147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 141257dacad5SJay Sternberg 1413a5cdb68cSKeith Busch if (shutdown) 1414a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1415a5cdb68cSKeith Busch else 1416b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 141757dacad5SJay Sternberg 1418bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 141957dacad5SJay Sternberg } 142057dacad5SJay Sternberg 1421fa46c6fbSKeith Busch /* 1422fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 14239210c075SDongli Zhang * that can check this device's completion queues have synced, except 14249210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 14259210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1426fa46c6fbSKeith Busch */ 1427fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1428fa46c6fbSKeith Busch { 1429fa46c6fbSKeith Busch int i; 1430fa46c6fbSKeith Busch 14319210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 14329210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1433324b494cSKeith Busch nvme_process_cq(&dev->queues[i]); 14349210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 14359210c075SDongli Zhang } 1436fa46c6fbSKeith Busch } 1437fa46c6fbSKeith Busch 143857dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 143957dacad5SJay Sternberg int entry_size) 144057dacad5SJay Sternberg { 144157dacad5SJay Sternberg int q_depth = dev->q_depth; 14425fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14436c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 144457dacad5SJay Sternberg 144557dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 144657dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14474e523547SBaolin Wang 14486c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 144957dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 145057dacad5SJay Sternberg 145157dacad5SJay Sternberg /* 145257dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 145357dacad5SJay Sternberg * would be better to map queues in system memory with the 145457dacad5SJay Sternberg * original depth 145557dacad5SJay Sternberg */ 145657dacad5SJay Sternberg if (q_depth < 64) 145757dacad5SJay Sternberg return -ENOMEM; 145857dacad5SJay Sternberg } 145957dacad5SJay Sternberg 146057dacad5SJay Sternberg return q_depth; 146157dacad5SJay Sternberg } 146257dacad5SJay Sternberg 146357dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14648a1d09a6SBenjamin Herrenschmidt int qid) 146557dacad5SJay Sternberg { 14660f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1467815c6704SKeith Busch 14680f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14698a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1470bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14710f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14720f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 147363223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 147463223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 147563223078SChristoph Hellwig return 0; 147663223078SChristoph Hellwig } 1477bfac8e9fSAlan Mikhak 14788a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1479bfac8e9fSAlan Mikhak } 14800f238ff5SLogan Gunthorpe } 14810f238ff5SLogan Gunthorpe 14828a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 148357dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 148457dacad5SJay Sternberg if (!nvmeq->sq_cmds) 148557dacad5SJay Sternberg return -ENOMEM; 148657dacad5SJay Sternberg return 0; 148757dacad5SJay Sternberg } 148857dacad5SJay Sternberg 1489a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 149057dacad5SJay Sternberg { 1491147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 149257dacad5SJay Sternberg 149362314e40SKeith Busch if (dev->ctrl.queue_count > qid) 149462314e40SKeith Busch return 0; 149557dacad5SJay Sternberg 1496c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 14978a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 14988a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 149957dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 150057dacad5SJay Sternberg if (!nvmeq->cqes) 150157dacad5SJay Sternberg goto free_nvmeq; 150257dacad5SJay Sternberg 15038a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 150457dacad5SJay Sternberg goto free_cqdma; 150557dacad5SJay Sternberg 150657dacad5SJay Sternberg nvmeq->dev = dev; 15071ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15083a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 150957dacad5SJay Sternberg nvmeq->cq_head = 0; 151057dacad5SJay Sternberg nvmeq->cq_phase = 1; 151157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 151257dacad5SJay Sternberg nvmeq->qid = qid; 1513d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 151457dacad5SJay Sternberg 1515147b27e4SSagi Grimberg return 0; 151657dacad5SJay Sternberg 151757dacad5SJay Sternberg free_cqdma: 15188a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 151957dacad5SJay Sternberg nvmeq->cq_dma_addr); 152057dacad5SJay Sternberg free_nvmeq: 1521147b27e4SSagi Grimberg return -ENOMEM; 152257dacad5SJay Sternberg } 152357dacad5SJay Sternberg 1524dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 152557dacad5SJay Sternberg { 15260ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15270ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15280ff199cbSChristoph Hellwig 15290ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15300ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15310ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15320ff199cbSChristoph Hellwig } else { 15330ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15340ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15350ff199cbSChristoph Hellwig } 153657dacad5SJay Sternberg } 153757dacad5SJay Sternberg 153857dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 153957dacad5SJay Sternberg { 154057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 154157dacad5SJay Sternberg 154257dacad5SJay Sternberg nvmeq->sq_tail = 0; 154338210800SKeith Busch nvmeq->last_sq_tail = 0; 154457dacad5SJay Sternberg nvmeq->cq_head = 0; 154557dacad5SJay Sternberg nvmeq->cq_phase = 1; 154657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15478a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1548f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 154957dacad5SJay Sternberg dev->online_queues++; 15503a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 155157dacad5SJay Sternberg } 155257dacad5SJay Sternberg 1553e4b9852aSCasey Chen /* 1554e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1555e4b9852aSCasey Chen */ 1556e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1557e4b9852aSCasey Chen { 1558e4b9852aSCasey Chen /* 1559e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1560e4b9852aSCasey Chen */ 1561e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1562e4b9852aSCasey Chen return -ENODEV; 1563e4b9852aSCasey Chen 1564e4b9852aSCasey Chen /* 1565e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1566e4b9852aSCasey Chen */ 1567e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1568e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1569e4b9852aSCasey Chen return -ENODEV; 1570e4b9852aSCasey Chen } 1571e4b9852aSCasey Chen 1572e4b9852aSCasey Chen return 0; 1573e4b9852aSCasey Chen } 1574e4b9852aSCasey Chen 15754b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 157657dacad5SJay Sternberg { 157757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 157857dacad5SJay Sternberg int result; 15797c349ddeSKeith Busch u16 vector = 0; 158057dacad5SJay Sternberg 1581d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1582d1ed6aa1SChristoph Hellwig 158322b55601SKeith Busch /* 158422b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 158522b55601SKeith Busch * has only one vector available. 158622b55601SKeith Busch */ 15874b04cc6aSJens Axboe if (!polled) 1588a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15894b04cc6aSJens Axboe else 15907c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15914b04cc6aSJens Axboe 1592a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1593ded45505SKeith Busch if (result) 1594ded45505SKeith Busch return result; 159557dacad5SJay Sternberg 159657dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 159757dacad5SJay Sternberg if (result < 0) 1598ded45505SKeith Busch return result; 1599c80b36cdSEdmund Nadolski if (result) 160057dacad5SJay Sternberg goto release_cq; 160157dacad5SJay Sternberg 1602a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16034b04cc6aSJens Axboe 1604e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1605e4b9852aSCasey Chen if (result) 1606e4b9852aSCasey Chen return result; 1607e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 16087c349ddeSKeith Busch if (!polled) { 1609dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 161057dacad5SJay Sternberg if (result < 0) 161157dacad5SJay Sternberg goto release_sq; 16124b04cc6aSJens Axboe } 161357dacad5SJay Sternberg 16144e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1615e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 161657dacad5SJay Sternberg return result; 161757dacad5SJay Sternberg 161857dacad5SJay Sternberg release_sq: 1619f25a2dfcSJianchao Wang dev->online_queues--; 1620e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 162157dacad5SJay Sternberg adapter_delete_sq(dev, qid); 162257dacad5SJay Sternberg release_cq: 162357dacad5SJay Sternberg adapter_delete_cq(dev, qid); 162457dacad5SJay Sternberg return result; 162557dacad5SJay Sternberg } 162657dacad5SJay Sternberg 1627f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 162857dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 162977f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 163057dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 16310350815aSChristoph Hellwig .init_request = nvme_init_request, 163257dacad5SJay Sternberg .timeout = nvme_timeout, 163357dacad5SJay Sternberg }; 163457dacad5SJay Sternberg 1635f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1636376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1637376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1638376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1639376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1640376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1641376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1642376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1643c6d962aeSChristoph Hellwig .poll = nvme_poll, 1644dabcefabSJens Axboe }; 1645dabcefabSJens Axboe 164657dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 164757dacad5SJay Sternberg { 16481c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 164969d9a99cSKeith Busch /* 165069d9a99cSKeith Busch * If the controller was reset during removal, it's possible 165169d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 165269d9a99cSKeith Busch * queue to flush these to completion. 165369d9a99cSKeith Busch */ 1654c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16551c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 165657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 165757dacad5SJay Sternberg } 165857dacad5SJay Sternberg } 165957dacad5SJay Sternberg 166057dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 166157dacad5SJay Sternberg { 16621c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 166357dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 166457dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1665e3e9d50cSKeith Busch 166638dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1667dc96f938SChaitanya Kulkarni dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; 1668d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1669d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1670d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 167157dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 167257dacad5SJay Sternberg 167357dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 167457dacad5SJay Sternberg return -ENOMEM; 167534b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 167657dacad5SJay Sternberg 16771c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16781c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 167957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 168057dacad5SJay Sternberg return -ENOMEM; 168157dacad5SJay Sternberg } 16821c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 168357dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16841c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 168557dacad5SJay Sternberg return -ENODEV; 168657dacad5SJay Sternberg } 168757dacad5SJay Sternberg } else 1688c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 168957dacad5SJay Sternberg 169057dacad5SJay Sternberg return 0; 169157dacad5SJay Sternberg } 169257dacad5SJay Sternberg 169397f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 169497f6ef64SXu Yu { 169597f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 169697f6ef64SXu Yu } 169797f6ef64SXu Yu 169897f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 169997f6ef64SXu Yu { 170097f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 170197f6ef64SXu Yu 170297f6ef64SXu Yu if (size <= dev->bar_mapped_size) 170397f6ef64SXu Yu return 0; 170497f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 170597f6ef64SXu Yu return -ENOMEM; 170697f6ef64SXu Yu if (dev->bar) 170797f6ef64SXu Yu iounmap(dev->bar); 170897f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 170997f6ef64SXu Yu if (!dev->bar) { 171097f6ef64SXu Yu dev->bar_mapped_size = 0; 171197f6ef64SXu Yu return -ENOMEM; 171297f6ef64SXu Yu } 171397f6ef64SXu Yu dev->bar_mapped_size = size; 171497f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 171597f6ef64SXu Yu 171697f6ef64SXu Yu return 0; 171797f6ef64SXu Yu } 171897f6ef64SXu Yu 171901ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 172057dacad5SJay Sternberg { 172157dacad5SJay Sternberg int result; 172257dacad5SJay Sternberg u32 aqa; 172357dacad5SJay Sternberg struct nvme_queue *nvmeq; 172457dacad5SJay Sternberg 172597f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 172697f6ef64SXu Yu if (result < 0) 172797f6ef64SXu Yu return result; 172897f6ef64SXu Yu 17298ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 173020d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 173157dacad5SJay Sternberg 17327a67cbeaSChristoph Hellwig if (dev->subsystem && 17337a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17347a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 173557dacad5SJay Sternberg 1736b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 173757dacad5SJay Sternberg if (result < 0) 173857dacad5SJay Sternberg return result; 173957dacad5SJay Sternberg 1740a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1741147b27e4SSagi Grimberg if (result) 1742147b27e4SSagi Grimberg return result; 174357dacad5SJay Sternberg 1744635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1745635333e4SMax Gurtovoy 1746147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 174757dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 174857dacad5SJay Sternberg aqa |= aqa << 16; 174957dacad5SJay Sternberg 17507a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17517a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17527a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 175357dacad5SJay Sternberg 1754c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 175557dacad5SJay Sternberg if (result) 1756d4875622SKeith Busch return result; 175757dacad5SJay Sternberg 175857dacad5SJay Sternberg nvmeq->cq_vector = 0; 1759161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1760dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 176157dacad5SJay Sternberg if (result) { 17627c349ddeSKeith Busch dev->online_queues--; 1763d4875622SKeith Busch return result; 176457dacad5SJay Sternberg } 176557dacad5SJay Sternberg 17664e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 176757dacad5SJay Sternberg return result; 176857dacad5SJay Sternberg } 176957dacad5SJay Sternberg 1770749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 177157dacad5SJay Sternberg { 17724b04cc6aSJens Axboe unsigned i, max, rw_queues; 1773749941f2SChristoph Hellwig int ret = 0; 177457dacad5SJay Sternberg 1775d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1776a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1777749941f2SChristoph Hellwig ret = -ENOMEM; 177857dacad5SJay Sternberg break; 1779749941f2SChristoph Hellwig } 1780749941f2SChristoph Hellwig } 178157dacad5SJay Sternberg 1782d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1783e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1784e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1785e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17864b04cc6aSJens Axboe } else { 17874b04cc6aSJens Axboe rw_queues = max; 17884b04cc6aSJens Axboe } 17894b04cc6aSJens Axboe 1790949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17914b04cc6aSJens Axboe bool polled = i > rw_queues; 17924b04cc6aSJens Axboe 17934b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1794d4875622SKeith Busch if (ret) 179557dacad5SJay Sternberg break; 179657dacad5SJay Sternberg } 179757dacad5SJay Sternberg 1798749941f2SChristoph Hellwig /* 1799749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18008adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18018adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1802749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1803749941f2SChristoph Hellwig */ 1804749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 180557dacad5SJay Sternberg } 180657dacad5SJay Sternberg 1807202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1808202021c1SStephen Bates struct device_attribute *attr, 1809202021c1SStephen Bates char *buf) 1810202021c1SStephen Bates { 1811202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1812202021c1SStephen Bates 1813c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1814202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1815202021c1SStephen Bates } 1816202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1817202021c1SStephen Bates 181888de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 181957dacad5SJay Sternberg { 182088de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 182188de4598SChristoph Hellwig 182288de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 182388de4598SChristoph Hellwig } 182488de4598SChristoph Hellwig 182588de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 182688de4598SChristoph Hellwig { 182788de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 182888de4598SChristoph Hellwig } 182988de4598SChristoph Hellwig 1830f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 183157dacad5SJay Sternberg { 183288de4598SChristoph Hellwig u64 size, offset; 183357dacad5SJay Sternberg resource_size_t bar_size; 183457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 18358969f1f8SChristoph Hellwig int bar; 183657dacad5SJay Sternberg 18379fe5c59fSKeith Busch if (dev->cmb_size) 18389fe5c59fSKeith Busch return; 18399fe5c59fSKeith Busch 184020d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 184120d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 184220d3bb92SKlaus Jensen 18437a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1844f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1845f65efd6dSChristoph Hellwig return; 1846202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 184757dacad5SJay Sternberg 184888de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 184988de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18508969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18518969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 185257dacad5SJay Sternberg 185357dacad5SJay Sternberg if (offset > bar_size) 1854f65efd6dSChristoph Hellwig return; 185557dacad5SJay Sternberg 185657dacad5SJay Sternberg /* 185720d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 185820d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 185920d3bb92SKlaus Jensen */ 186020d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 186120d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 186220d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 186320d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 186420d3bb92SKlaus Jensen } 186520d3bb92SKlaus Jensen 186620d3bb92SKlaus Jensen /* 186757dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 186857dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 186957dacad5SJay Sternberg * the reported size of the BAR 187057dacad5SJay Sternberg */ 187157dacad5SJay Sternberg if (size > bar_size - offset) 187257dacad5SJay Sternberg size = bar_size - offset; 187357dacad5SJay Sternberg 18740f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18750f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18760f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1877f65efd6dSChristoph Hellwig return; 18780f238ff5SLogan Gunthorpe } 18790f238ff5SLogan Gunthorpe 188057dacad5SJay Sternberg dev->cmb_size = size; 18810f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18820f238ff5SLogan Gunthorpe 18830f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18840f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18850f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1886f65efd6dSChristoph Hellwig 1887f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1888f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1889f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1890f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 189157dacad5SJay Sternberg } 189257dacad5SJay Sternberg 189357dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 189457dacad5SJay Sternberg { 18950f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1896f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1897f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18980f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1899f63572dfSJon Derrick } 190057dacad5SJay Sternberg } 190157dacad5SJay Sternberg 190287ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 190357dacad5SJay Sternberg { 19046c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19054033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1906f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 190787ad72a5SChristoph Hellwig int ret; 190887ad72a5SChristoph Hellwig 190987ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 191087ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 191187ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19126c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 191387ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 191487ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 191587ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 191687ad72a5SChristoph Hellwig 191787ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 191887ad72a5SChristoph Hellwig if (ret) { 191987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 192087ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 192187ad72a5SChristoph Hellwig ret, bits); 192287ad72a5SChristoph Hellwig } 192387ad72a5SChristoph Hellwig return ret; 192487ad72a5SChristoph Hellwig } 192587ad72a5SChristoph Hellwig 192687ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 192787ad72a5SChristoph Hellwig { 192887ad72a5SChristoph Hellwig int i; 192987ad72a5SChristoph Hellwig 193087ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 193187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19326c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 193387ad72a5SChristoph Hellwig 1934cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1935cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1936cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 193787ad72a5SChristoph Hellwig } 193887ad72a5SChristoph Hellwig 193987ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 194087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19414033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 19424033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 19434033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 194487ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 19457e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 194687ad72a5SChristoph Hellwig } 194787ad72a5SChristoph Hellwig 194892dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 194992dc6895SChristoph Hellwig u32 chunk_size) 195087ad72a5SChristoph Hellwig { 195187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 195292dc6895SChristoph Hellwig u32 max_entries, len; 19534033f35dSChristoph Hellwig dma_addr_t descs_dma; 19542ee0e4edSDan Carpenter int i = 0; 195587ad72a5SChristoph Hellwig void **bufs; 19566fbcde66SMinwoo Im u64 size, tmp; 195787ad72a5SChristoph Hellwig 195887ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 195987ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 196087ad72a5SChristoph Hellwig max_entries = tmp; 1961044a9df1SChristoph Hellwig 1962044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1963044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1964044a9df1SChristoph Hellwig 1965750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19664033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 196787ad72a5SChristoph Hellwig if (!descs) 196887ad72a5SChristoph Hellwig goto out; 196987ad72a5SChristoph Hellwig 197087ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 197187ad72a5SChristoph Hellwig if (!bufs) 197287ad72a5SChristoph Hellwig goto out_free_descs; 197387ad72a5SChristoph Hellwig 1974244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 197587ad72a5SChristoph Hellwig dma_addr_t dma_addr; 197687ad72a5SChristoph Hellwig 197750cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 197887ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 197987ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 198087ad72a5SChristoph Hellwig if (!bufs[i]) 198187ad72a5SChristoph Hellwig break; 198287ad72a5SChristoph Hellwig 198387ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 19846c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 198587ad72a5SChristoph Hellwig i++; 198687ad72a5SChristoph Hellwig } 198787ad72a5SChristoph Hellwig 198892dc6895SChristoph Hellwig if (!size) 198987ad72a5SChristoph Hellwig goto out_free_bufs; 199087ad72a5SChristoph Hellwig 199187ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 199287ad72a5SChristoph Hellwig dev->host_mem_size = size; 199387ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19944033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 199587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 199687ad72a5SChristoph Hellwig return 0; 199787ad72a5SChristoph Hellwig 199887ad72a5SChristoph Hellwig out_free_bufs: 199987ad72a5SChristoph Hellwig while (--i >= 0) { 20006c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 200187ad72a5SChristoph Hellwig 2002cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2003cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2004cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 200587ad72a5SChristoph Hellwig } 200687ad72a5SChristoph Hellwig 200787ad72a5SChristoph Hellwig kfree(bufs); 200887ad72a5SChristoph Hellwig out_free_descs: 20094033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20104033f35dSChristoph Hellwig descs_dma); 201187ad72a5SChristoph Hellwig out: 201287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 201387ad72a5SChristoph Hellwig return -ENOMEM; 201487ad72a5SChristoph Hellwig } 201587ad72a5SChristoph Hellwig 201692dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 201792dc6895SChristoph Hellwig { 20189dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20199dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20209dc54a0dSChaitanya Kulkarni u64 chunk_size; 202192dc6895SChristoph Hellwig 202292dc6895SChristoph Hellwig /* start big and work our way down */ 20239dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 202492dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 202592dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 202692dc6895SChristoph Hellwig return 0; 202792dc6895SChristoph Hellwig nvme_free_host_mem(dev); 202892dc6895SChristoph Hellwig } 202992dc6895SChristoph Hellwig } 203092dc6895SChristoph Hellwig 203192dc6895SChristoph Hellwig return -ENOMEM; 203292dc6895SChristoph Hellwig } 203392dc6895SChristoph Hellwig 20349620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 203587ad72a5SChristoph Hellwig { 203687ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 203787ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 203887ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 203987ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20406fbcde66SMinwoo Im int ret; 204187ad72a5SChristoph Hellwig 204287ad72a5SChristoph Hellwig preferred = min(preferred, max); 204387ad72a5SChristoph Hellwig if (min > max) { 204487ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 204587ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 204687ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 204787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20489620cfbaSChristoph Hellwig return 0; 204987ad72a5SChristoph Hellwig } 205087ad72a5SChristoph Hellwig 205187ad72a5SChristoph Hellwig /* 205287ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 205387ad72a5SChristoph Hellwig */ 205487ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 205587ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 205687ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 205787ad72a5SChristoph Hellwig else 205887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 205987ad72a5SChristoph Hellwig } 206087ad72a5SChristoph Hellwig 206187ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 206292dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 206392dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 206492dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20659620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 206687ad72a5SChristoph Hellwig } 206787ad72a5SChristoph Hellwig 206892dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 206992dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 207092dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 207192dc6895SChristoph Hellwig } 207292dc6895SChristoph Hellwig 20739620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20749620cfbaSChristoph Hellwig if (ret) 207587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20769620cfbaSChristoph Hellwig return ret; 207757dacad5SJay Sternberg } 207857dacad5SJay Sternberg 2079612b7286SMing Lei /* 2080612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2081612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2082612b7286SMing Lei */ 2083612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20843b6592f7SJens Axboe { 2085612b7286SMing Lei struct nvme_dev *dev = affd->priv; 20862a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2087c45b1fa2SMing Lei 20883b6592f7SJens Axboe /* 2089ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2090612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2091612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2092612b7286SMing Lei * 2093612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2094612b7286SMing Lei * write and read queues. 2095612b7286SMing Lei * 2096612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2097612b7286SMing Lei * queue. 20983b6592f7SJens Axboe */ 2099612b7286SMing Lei if (!nrirqs) { 2100612b7286SMing Lei nrirqs = 1; 2101612b7286SMing Lei nr_read_queues = 0; 21022a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2103612b7286SMing Lei nr_read_queues = 0; 21042a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2105612b7286SMing Lei nr_read_queues = 1; 21063b6592f7SJens Axboe } else { 21072a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 21083b6592f7SJens Axboe } 2109612b7286SMing Lei 2110612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2111612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2112612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2113612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2114612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 21153b6592f7SJens Axboe } 21163b6592f7SJens Axboe 21176451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 21183b6592f7SJens Axboe { 21193b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 21203b6592f7SJens Axboe struct irq_affinity affd = { 21213b6592f7SJens Axboe .pre_vectors = 1, 2122612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2123612b7286SMing Lei .priv = dev, 21243b6592f7SJens Axboe }; 212521cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 21266451fe73SJens Axboe 21276451fe73SJens Axboe /* 212821cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 212921cc2f3fSJeffle Xu * left over for non-polled I/O. 21306451fe73SJens Axboe */ 213121cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 213221cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 21333b6592f7SJens Axboe 213421cc2f3fSJeffle Xu /* 213521cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 213621cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 213721cc2f3fSJeffle Xu */ 2138612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2139612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 21403b6592f7SJens Axboe 214166341331SBenjamin Herrenschmidt /* 214221cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 214321cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 214421cc2f3fSJeffle Xu * vector. 214566341331SBenjamin Herrenschmidt */ 214666341331SBenjamin Herrenschmidt irq_queues = 1; 214721cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 214821cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2149612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 21503b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 21513b6592f7SJens Axboe } 21523b6592f7SJens Axboe 21538fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 21548fae268bSKeith Busch { 21558fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 21568fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 21578fae268bSKeith Busch } 21588fae268bSKeith Busch 21592a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 21602a5bcfddSWeiping Zhang { 2161e3aef095SNiklas Schnelle /* 2162e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2163e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2164e3aef095SNiklas Schnelle */ 2165e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2166e3aef095SNiklas Schnelle return 1; 21672a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 21682a5bcfddSWeiping Zhang } 21692a5bcfddSWeiping Zhang 217057dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 217157dacad5SJay Sternberg { 2172147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 217357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 21742a5bcfddSWeiping Zhang unsigned int nr_io_queues; 217597f6ef64SXu Yu unsigned long size; 21762a5bcfddSWeiping Zhang int result; 217757dacad5SJay Sternberg 21782a5bcfddSWeiping Zhang /* 21792a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 21802a5bcfddSWeiping Zhang * stable values to work with. 21812a5bcfddSWeiping Zhang */ 21822a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 21832a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2184d38e9f04SBenjamin Herrenschmidt 2185ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 21869a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21879a0be7abSChristoph Hellwig if (result < 0) 218857dacad5SJay Sternberg return result; 21899a0be7abSChristoph Hellwig 2190f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2191a5229050SKeith Busch return 0; 219257dacad5SJay Sternberg 2193e4b9852aSCasey Chen /* 2194e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2195e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2196e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2197e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2198e4b9852aSCasey Chen * nvme_dev_disable() path. 2199e4b9852aSCasey Chen */ 2200e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2201e4b9852aSCasey Chen if (result) 2202e4b9852aSCasey Chen return result; 2203e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2204e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 22054e224106SChristoph Hellwig 22060f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 220757dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 220857dacad5SJay Sternberg sizeof(struct nvme_command)); 220957dacad5SJay Sternberg if (result > 0) 221057dacad5SJay Sternberg dev->q_depth = result; 221157dacad5SJay Sternberg else 22120f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 221357dacad5SJay Sternberg } 221457dacad5SJay Sternberg 221557dacad5SJay Sternberg do { 221697f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 221797f6ef64SXu Yu result = nvme_remap_bar(dev, size); 221897f6ef64SXu Yu if (!result) 221957dacad5SJay Sternberg break; 2220e4b9852aSCasey Chen if (!--nr_io_queues) { 2221e4b9852aSCasey Chen result = -ENOMEM; 2222e4b9852aSCasey Chen goto out_unlock; 2223e4b9852aSCasey Chen } 222457dacad5SJay Sternberg } while (1); 222557dacad5SJay Sternberg adminq->q_db = dev->dbs; 222657dacad5SJay Sternberg 22278fae268bSKeith Busch retry: 222857dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2229e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 22300ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 223157dacad5SJay Sternberg 223257dacad5SJay Sternberg /* 223357dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 223457dacad5SJay Sternberg * setting up the full range we need. 223557dacad5SJay Sternberg */ 2236dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 22373b6592f7SJens Axboe 22383b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2239e4b9852aSCasey Chen if (result <= 0) { 2240e4b9852aSCasey Chen result = -EIO; 2241e4b9852aSCasey Chen goto out_unlock; 2242e4b9852aSCasey Chen } 22433b6592f7SJens Axboe 224422b55601SKeith Busch dev->num_vecs = result; 22454b04cc6aSJens Axboe result = max(result - 1, 1); 2246e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 224757dacad5SJay Sternberg 224857dacad5SJay Sternberg /* 224957dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 225057dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 225157dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 225257dacad5SJay Sternberg * number of interrupts. 225357dacad5SJay Sternberg */ 2254dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 22557c349ddeSKeith Busch if (result) 2256e4b9852aSCasey Chen goto out_unlock; 22574e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2258e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 22598fae268bSKeith Busch 22608fae268bSKeith Busch result = nvme_create_io_queues(dev); 22618fae268bSKeith Busch if (result || dev->online_queues < 2) 22628fae268bSKeith Busch return result; 22638fae268bSKeith Busch 22648fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 22658fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 22668fae268bSKeith Busch nvme_disable_io_queues(dev); 2267e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2268e4b9852aSCasey Chen if (result) 2269e4b9852aSCasey Chen return result; 22708fae268bSKeith Busch nvme_suspend_io_queues(dev); 22718fae268bSKeith Busch goto retry; 22728fae268bSKeith Busch } 22738fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 22748fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 22758fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 22768fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 22778fae268bSKeith Busch return 0; 2278e4b9852aSCasey Chen out_unlock: 2279e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2280e4b9852aSCasey Chen return result; 228157dacad5SJay Sternberg } 228257dacad5SJay Sternberg 22832a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2284db3cbfffSKeith Busch { 2285db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2286db3cbfffSKeith Busch 2287db3cbfffSKeith Busch blk_mq_free_request(req); 2288d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2289db3cbfffSKeith Busch } 2290db3cbfffSKeith Busch 22912a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2292db3cbfffSKeith Busch { 2293db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2294db3cbfffSKeith Busch 2295d1ed6aa1SChristoph Hellwig if (error) 2296d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2297db3cbfffSKeith Busch 2298db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2299db3cbfffSKeith Busch } 2300db3cbfffSKeith Busch 2301db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2302db3cbfffSKeith Busch { 2303db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2304db3cbfffSKeith Busch struct request *req; 2305f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2306db3cbfffSKeith Busch 2307db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2308db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2309db3cbfffSKeith Busch 231039dfe844SChaitanya Kulkarni req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); 2311db3cbfffSKeith Busch if (IS_ERR(req)) 2312db3cbfffSKeith Busch return PTR_ERR(req); 2313db3cbfffSKeith Busch 2314db3cbfffSKeith Busch req->end_io_data = nvmeq; 2315db3cbfffSKeith Busch 2316d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 23178eeed0b5SGuoqing Jiang blk_execute_rq_nowait(NULL, req, false, 2318db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2319db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2320db3cbfffSKeith Busch return 0; 2321db3cbfffSKeith Busch } 2322db3cbfffSKeith Busch 23238fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2324db3cbfffSKeith Busch { 23255271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2326db3cbfffSKeith Busch unsigned long timeout; 2327db3cbfffSKeith Busch 2328db3cbfffSKeith Busch retry: 2329dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 23305271edd4SChristoph Hellwig while (nr_queues > 0) { 23315271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2332db3cbfffSKeith Busch break; 23335271edd4SChristoph Hellwig nr_queues--; 23345271edd4SChristoph Hellwig sent++; 23355271edd4SChristoph Hellwig } 2336d1ed6aa1SChristoph Hellwig while (sent) { 2337d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2338d1ed6aa1SChristoph Hellwig 2339d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 23405271edd4SChristoph Hellwig timeout); 2341db3cbfffSKeith Busch if (timeout == 0) 23425271edd4SChristoph Hellwig return false; 2343d1ed6aa1SChristoph Hellwig 2344d1ed6aa1SChristoph Hellwig sent--; 23455271edd4SChristoph Hellwig if (nr_queues) 2346db3cbfffSKeith Busch goto retry; 2347db3cbfffSKeith Busch } 23485271edd4SChristoph Hellwig return true; 2349db3cbfffSKeith Busch } 2350db3cbfffSKeith Busch 23515d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 235257dacad5SJay Sternberg { 23532b1b7e78SJianchao Wang int ret; 23542b1b7e78SJianchao Wang 23555bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2356c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 235757dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 23588fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2359ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2360ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 236157dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2362d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 236361f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 236461f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2365d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 236657dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 236757dacad5SJay Sternberg dev->tagset.driver_data = dev; 236857dacad5SJay Sternberg 2369d38e9f04SBenjamin Herrenschmidt /* 2370d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2371d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2372d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2373d38e9f04SBenjamin Herrenschmidt */ 2374d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2375d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2376d38e9f04SBenjamin Herrenschmidt 23772b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 23782b1b7e78SJianchao Wang if (ret) { 23792b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23802b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 23815d02a5c1SKeith Busch return; 23822b1b7e78SJianchao Wang } 23835bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2384949928c1SKeith Busch } else { 2385949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2386949928c1SKeith Busch 2387949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2388949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 238957dacad5SJay Sternberg } 2390949928c1SKeith Busch 2391e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 239257dacad5SJay Sternberg } 239357dacad5SJay Sternberg 2394b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 239557dacad5SJay Sternberg { 2396b00a726aSKeith Busch int result = -ENOMEM; 239757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 23984bdf2603SFilippo Sironi int dma_address_bits = 64; 239957dacad5SJay Sternberg 240057dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 240157dacad5SJay Sternberg return result; 240257dacad5SJay Sternberg 240357dacad5SJay Sternberg pci_set_master(pdev); 240457dacad5SJay Sternberg 24054bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 24064bdf2603SFilippo Sironi dma_address_bits = 48; 24074bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 240857dacad5SJay Sternberg goto disable; 240957dacad5SJay Sternberg 24107a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 241157dacad5SJay Sternberg result = -ENODEV; 2412b00a726aSKeith Busch goto disable; 241357dacad5SJay Sternberg } 241457dacad5SJay Sternberg 241557dacad5SJay Sternberg /* 2416a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2417a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2418a5229050SKeith Busch * adjust this later. 241957dacad5SJay Sternberg */ 2420dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2421dca51e78SChristoph Hellwig if (result < 0) 2422dca51e78SChristoph Hellwig return result; 242357dacad5SJay Sternberg 242420d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 24257a67cbeaSChristoph Hellwig 24267442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2427b27c1e68Sweiping zhang io_queue_depth); 2428aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 242920d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 24307a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 24311f390c1fSStephan Günther 24321f390c1fSStephan Günther /* 243366341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 243466341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 243566341331SBenjamin Herrenschmidt * so we don't bother updating it here. 243666341331SBenjamin Herrenschmidt */ 243766341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 243866341331SBenjamin Herrenschmidt dev->io_sqes = 7; 243966341331SBenjamin Herrenschmidt else 2440c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 24411f390c1fSStephan Günther 24421f390c1fSStephan Günther /* 24431f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 24441f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 24451f390c1fSStephan Günther */ 24461f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 24471f390c1fSStephan Günther dev->q_depth = 2; 24489bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 24499bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 24501f390c1fSStephan Günther dev->q_depth); 2451d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2452d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 245320d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2454d554b5e1SMartin K. Petersen dev->q_depth = 64; 2455d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2456d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 24571f390c1fSStephan Günther } 24581f390c1fSStephan Günther 2459d38e9f04SBenjamin Herrenschmidt /* 2460d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2461d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2462d38e9f04SBenjamin Herrenschmidt */ 2463d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2464d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2465d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2466d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2467d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2468d38e9f04SBenjamin Herrenschmidt } 2469d38e9f04SBenjamin Herrenschmidt 2470d38e9f04SBenjamin Herrenschmidt 2471f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2472202021c1SStephen Bates 2473a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2474a0a3408eSKeith Busch pci_save_state(pdev); 247557dacad5SJay Sternberg return 0; 247657dacad5SJay Sternberg 247757dacad5SJay Sternberg disable: 247857dacad5SJay Sternberg pci_disable_device(pdev); 247957dacad5SJay Sternberg return result; 248057dacad5SJay Sternberg } 248157dacad5SJay Sternberg 248257dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 248357dacad5SJay Sternberg { 2484b00a726aSKeith Busch if (dev->bar) 2485b00a726aSKeith Busch iounmap(dev->bar); 2486a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2487b00a726aSKeith Busch } 2488b00a726aSKeith Busch 2489b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2490b00a726aSKeith Busch { 249157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 249257dacad5SJay Sternberg 2493dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 249457dacad5SJay Sternberg 2495a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2496a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 249757dacad5SJay Sternberg pci_disable_device(pdev); 249857dacad5SJay Sternberg } 2499a0a3408eSKeith Busch } 250057dacad5SJay Sternberg 2501a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 250257dacad5SJay Sternberg { 2503e43269e6SKeith Busch bool dead = true, freeze = false; 2504302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 250557dacad5SJay Sternberg 250677bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2507302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2508302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2509302ad8ccSKeith Busch 2510ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2511e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2512e43269e6SKeith Busch freeze = true; 2513302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2514e43269e6SKeith Busch } 2515302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2516302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 251757dacad5SJay Sternberg } 2518c21377f8SGabriel Krisman Bertazi 2519302ad8ccSKeith Busch /* 2520302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2521302ad8ccSKeith Busch * doing a safe shutdown. 2522302ad8ccSKeith Busch */ 2523e43269e6SKeith Busch if (!dead && shutdown && freeze) 2524302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 252587ad72a5SChristoph Hellwig 25269a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 25279a915a5bSJianchao Wang 252864ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 25298fae268bSKeith Busch nvme_disable_io_queues(dev); 2530a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 253157dacad5SJay Sternberg } 25328fae268bSKeith Busch nvme_suspend_io_queues(dev); 25338fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2534b00a726aSKeith Busch nvme_pci_disable(dev); 2535fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 253657dacad5SJay Sternberg 2537e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2538e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2539622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2540622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2541302ad8ccSKeith Busch 2542302ad8ccSKeith Busch /* 2543302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2544302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2545302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2546302ad8ccSKeith Busch */ 2547c8e9e9b7SKeith Busch if (shutdown) { 2548302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2549c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2550c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2551c8e9e9b7SKeith Busch } 255277bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 255357dacad5SJay Sternberg } 255457dacad5SJay Sternberg 2555c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2556c1ac9a4bSKeith Busch { 2557c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2558c1ac9a4bSKeith Busch return -EBUSY; 2559c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2560c1ac9a4bSKeith Busch return 0; 2561c1ac9a4bSKeith Busch } 2562c1ac9a4bSKeith Busch 256357dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 256457dacad5SJay Sternberg { 256557dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2566c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2567c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 256857dacad5SJay Sternberg if (!dev->prp_page_pool) 256957dacad5SJay Sternberg return -ENOMEM; 257057dacad5SJay Sternberg 257157dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 257257dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 257357dacad5SJay Sternberg 256, 256, 0); 257457dacad5SJay Sternberg if (!dev->prp_small_pool) { 257557dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 257657dacad5SJay Sternberg return -ENOMEM; 257757dacad5SJay Sternberg } 257857dacad5SJay Sternberg return 0; 257957dacad5SJay Sternberg } 258057dacad5SJay Sternberg 258157dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 258257dacad5SJay Sternberg { 258357dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 258457dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 258557dacad5SJay Sternberg } 258657dacad5SJay Sternberg 2587770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2588770597ecSKeith Busch { 2589770597ecSKeith Busch if (dev->tagset.tags) 2590770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2591770597ecSKeith Busch dev->ctrl.tagset = NULL; 2592770597ecSKeith Busch } 2593770597ecSKeith Busch 25941673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 259557dacad5SJay Sternberg { 25961673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 259757dacad5SJay Sternberg 2598f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2599770597ecSKeith Busch nvme_free_tagset(dev); 26001c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 26011c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2602e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2603943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2604253fd4acSIsrael Rukshin put_device(dev->dev); 2605253fd4acSIsrael Rukshin kfree(dev->queues); 260657dacad5SJay Sternberg kfree(dev); 260757dacad5SJay Sternberg } 260857dacad5SJay Sternberg 26097c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2610f58944e2SKeith Busch { 2611c1ac9a4bSKeith Busch /* 2612c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2613c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2614c1ac9a4bSKeith Busch */ 2615c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2616d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 261769d9a99cSKeith Busch nvme_dev_disable(dev, false); 26189f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 261903e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2620f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2621f58944e2SKeith Busch } 2622f58944e2SKeith Busch 2623fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 262457dacad5SJay Sternberg { 2625d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2626d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2627a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2628e71afda4SChaitanya Kulkarni int result; 262957dacad5SJay Sternberg 26307764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 26317764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 26327764656bSZhihao Cheng dev->ctrl.state); 2633e71afda4SChaitanya Kulkarni result = -ENODEV; 2634fd634f41SChristoph Hellwig goto out; 2635e71afda4SChaitanya Kulkarni } 2636fd634f41SChristoph Hellwig 2637fd634f41SChristoph Hellwig /* 2638fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2639fd634f41SChristoph Hellwig * moving on. 2640fd634f41SChristoph Hellwig */ 2641b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2642a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2643d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2644fd634f41SChristoph Hellwig 26455c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2646b00a726aSKeith Busch result = nvme_pci_enable(dev); 264757dacad5SJay Sternberg if (result) 26484726bcf3SKeith Busch goto out_unlock; 264957dacad5SJay Sternberg 265001ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 265157dacad5SJay Sternberg if (result) 26524726bcf3SKeith Busch goto out_unlock; 265357dacad5SJay Sternberg 265457dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 265557dacad5SJay Sternberg if (result) 26564726bcf3SKeith Busch goto out_unlock; 265757dacad5SJay Sternberg 2658943e942eSJens Axboe /* 2659943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2660943e942eSJens Axboe * over a single page. 2661943e942eSJens Axboe */ 26627637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 26637637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2664943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2665a48bc520SChristoph Hellwig 2666a48bc520SChristoph Hellwig /* 2667a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2668a48bc520SChristoph Hellwig */ 2669a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 26703d2d861eSJianxiong Gao dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2671a48bc520SChristoph Hellwig 26725c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 26735c959d73SKeith Busch 26745c959d73SKeith Busch /* 26755c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 26765c959d73SKeith Busch * initializing procedure here. 26775c959d73SKeith Busch */ 26785c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 26795c959d73SKeith Busch dev_warn(dev->ctrl.device, 26805c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2681cee6c269SMinwoo Im result = -EBUSY; 26825c959d73SKeith Busch goto out; 26835c959d73SKeith Busch } 2684943e942eSJens Axboe 268595093350SMax Gurtovoy /* 268695093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 268795093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 268895093350SMax Gurtovoy */ 268995093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 269095093350SMax Gurtovoy 2691f21c4769SChaitanya Kulkarni result = nvme_init_ctrl_finish(&dev->ctrl); 2692ce4541f4SChristoph Hellwig if (result) 2693f58944e2SKeith Busch goto out; 2694ce4541f4SChristoph Hellwig 2695e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2696e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 26974f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 26984f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2699e286bcfcSScott Bauer else if (was_suspend) 27004f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2701e286bcfcSScott Bauer } else { 2702e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2703e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2704e286bcfcSScott Bauer } 2705a98e58e5SScott Bauer 2706f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2707f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2708f9f38e33SHelen Koike if (result) 2709f9f38e33SHelen Koike dev_warn(dev->dev, 2710f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2711f9f38e33SHelen Koike } 2712f9f38e33SHelen Koike 27139620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 27149620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 27159620cfbaSChristoph Hellwig if (result < 0) 27169620cfbaSChristoph Hellwig goto out; 27179620cfbaSChristoph Hellwig } 271887ad72a5SChristoph Hellwig 271957dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 272057dacad5SJay Sternberg if (result) 2721f58944e2SKeith Busch goto out; 272257dacad5SJay Sternberg 272321f033f7SKeith Busch /* 272457dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 272557dacad5SJay Sternberg * any working I/O queue. 272657dacad5SJay Sternberg */ 272757dacad5SJay Sternberg if (dev->online_queues < 2) { 27281b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 27293b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 27305bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2731770597ecSKeith Busch nvme_free_tagset(dev); 273257dacad5SJay Sternberg } else { 273325646264SKeith Busch nvme_start_queues(&dev->ctrl); 2734302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 27355d02a5c1SKeith Busch nvme_dev_add(dev); 2736302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 273757dacad5SJay Sternberg } 273857dacad5SJay Sternberg 27392b1b7e78SJianchao Wang /* 27402b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 27412b1b7e78SJianchao Wang * recovery. 27422b1b7e78SJianchao Wang */ 27435d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 27442b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 27455d02a5c1SKeith Busch "failed to mark controller live state\n"); 2746e71afda4SChaitanya Kulkarni result = -ENODEV; 2747bb8d261eSChristoph Hellwig goto out; 2748bb8d261eSChristoph Hellwig } 274992911a55SChristoph Hellwig 2750d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 275157dacad5SJay Sternberg return; 275257dacad5SJay Sternberg 27534726bcf3SKeith Busch out_unlock: 27544726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 275557dacad5SJay Sternberg out: 27567c1ce408SChaitanya Kulkarni if (result) 27577c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 27587c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 27597c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 276057dacad5SJay Sternberg } 276157dacad5SJay Sternberg 27625c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 276357dacad5SJay Sternberg { 27645c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 276557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 276657dacad5SJay Sternberg 276757dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2768921920abSKeith Busch device_release_driver(&pdev->dev); 27691673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 277057dacad5SJay Sternberg } 277157dacad5SJay Sternberg 27721c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 277357dacad5SJay Sternberg { 27741c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 27751c63dc66SChristoph Hellwig return 0; 277657dacad5SJay Sternberg } 27771c63dc66SChristoph Hellwig 27785fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 27795fd4ce1bSChristoph Hellwig { 27805fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 27815fd4ce1bSChristoph Hellwig return 0; 27825fd4ce1bSChristoph Hellwig } 27835fd4ce1bSChristoph Hellwig 27847fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 27857fd8930fSChristoph Hellwig { 27863a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 27877fd8930fSChristoph Hellwig return 0; 27887fd8930fSChristoph Hellwig } 27897fd8930fSChristoph Hellwig 279097c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 279197c12223SKeith Busch { 279297c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 279397c12223SKeith Busch 27942db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 279597c12223SKeith Busch } 279697c12223SKeith Busch 27971c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 27981a353d85SMing Lin .name = "pcie", 2799e439bb12SSagi Grimberg .module = THIS_MODULE, 2800e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2801e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 28021c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 28035fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 28047fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 28051673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2806f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 280797c12223SKeith Busch .get_address = nvme_pci_get_address, 28081c63dc66SChristoph Hellwig }; 280957dacad5SJay Sternberg 2810b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2811b00a726aSKeith Busch { 2812b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2813b00a726aSKeith Busch 2814a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2815b00a726aSKeith Busch return -ENODEV; 2816b00a726aSKeith Busch 281797f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2818b00a726aSKeith Busch goto release; 2819b00a726aSKeith Busch 2820b00a726aSKeith Busch return 0; 2821b00a726aSKeith Busch release: 2822a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2823b00a726aSKeith Busch return -ENODEV; 2824b00a726aSKeith Busch } 2825b00a726aSKeith Busch 28268427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2827ff5350a8SAndy Lutomirski { 2828ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2829ff5350a8SAndy Lutomirski /* 2830ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2831ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2832ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2833ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2834ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2835ff5350a8SAndy Lutomirski * laptops. 2836ff5350a8SAndy Lutomirski */ 2837ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2838ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2839ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2840ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 28418427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 28428427bbc2SKai-Heng Feng /* 28438427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2844467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2845467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2846467c77d4SJarosław Janik * ASUS PRIME Z370-A 28478427bbc2SKai-Heng Feng */ 28488427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2849467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2850467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 28518427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 28521fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 28531fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 28541fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 28551fae37acSShyjumon N /* 28561fae37acSShyjumon N * Forcing to use host managed nvme power settings for 28571fae37acSShyjumon N * lowest idle power with quick resume latency on 28581fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 28591fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 28601fae37acSShyjumon N */ 28611fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 28621fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 28631fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2864ff5350a8SAndy Lutomirski } 2865ff5350a8SAndy Lutomirski 2866ff5350a8SAndy Lutomirski return 0; 2867ff5350a8SAndy Lutomirski } 2868ff5350a8SAndy Lutomirski 286918119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 287018119775SKeith Busch { 287118119775SKeith Busch struct nvme_dev *dev = data; 287280f513b5SKeith Busch 2873bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 287418119775SKeith Busch flush_work(&dev->ctrl.scan_work); 287580f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 287618119775SKeith Busch } 287718119775SKeith Busch 287857dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 287957dacad5SJay Sternberg { 288057dacad5SJay Sternberg int node, result = -ENOMEM; 288157dacad5SJay Sternberg struct nvme_dev *dev; 2882ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2883943e942eSJens Axboe size_t alloc_size; 288457dacad5SJay Sternberg 288557dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 288657dacad5SJay Sternberg if (node == NUMA_NO_NODE) 28872fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 288857dacad5SJay Sternberg 288957dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 289057dacad5SJay Sternberg if (!dev) 289157dacad5SJay Sternberg return -ENOMEM; 2892147b27e4SSagi Grimberg 28932a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 28942a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 28952a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 28962a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 28972a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 289857dacad5SJay Sternberg if (!dev->queues) 289957dacad5SJay Sternberg goto free; 290057dacad5SJay Sternberg 290157dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 290257dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 290357dacad5SJay Sternberg 2904b00a726aSKeith Busch result = nvme_dev_map(dev); 2905b00a726aSKeith Busch if (result) 2906b00c9b7aSChristophe JAILLET goto put_pci; 2907b00a726aSKeith Busch 2908d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 29095c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 291077bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2911f3ca80fcSChristoph Hellwig 2912f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2913f3ca80fcSChristoph Hellwig if (result) 2914b00c9b7aSChristophe JAILLET goto unmap; 2915f3ca80fcSChristoph Hellwig 29168427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2917ff5350a8SAndy Lutomirski 29182744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 2919df4f9bc4SDavid E. Box /* 2920df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 2921df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 2922df4f9bc4SDavid E. Box */ 2923df4f9bc4SDavid E. Box dev_info(&pdev->dev, 2924df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 2925df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 2926df4f9bc4SDavid E. Box } 2927df4f9bc4SDavid E. Box 2928943e942eSJens Axboe /* 2929943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2930943e942eSJens Axboe * command we support. 2931943e942eSJens Axboe */ 2932b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 2933943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2934943e942eSJens Axboe 2935943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2936943e942eSJens Axboe mempool_kfree, 2937943e942eSJens Axboe (void *) alloc_size, 2938943e942eSJens Axboe GFP_KERNEL, node); 2939943e942eSJens Axboe if (!dev->iod_mempool) { 2940943e942eSJens Axboe result = -ENOMEM; 2941943e942eSJens Axboe goto release_pools; 2942943e942eSJens Axboe } 2943943e942eSJens Axboe 2944b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2945b6e44b4cSKeith Busch quirks); 2946b6e44b4cSKeith Busch if (result) 2947b6e44b4cSKeith Busch goto release_mempool; 2948b6e44b4cSKeith Busch 29491b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 29501b3c47c1SSagi Grimberg 2951bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 295218119775SKeith Busch async_schedule(nvme_async_probe, dev); 29534caff8fcSSagi Grimberg 295457dacad5SJay Sternberg return 0; 295557dacad5SJay Sternberg 2956b6e44b4cSKeith Busch release_mempool: 2957b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 295857dacad5SJay Sternberg release_pools: 295957dacad5SJay Sternberg nvme_release_prp_pools(dev); 2960b00c9b7aSChristophe JAILLET unmap: 2961b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 296257dacad5SJay Sternberg put_pci: 296357dacad5SJay Sternberg put_device(dev->dev); 296457dacad5SJay Sternberg free: 296557dacad5SJay Sternberg kfree(dev->queues); 296657dacad5SJay Sternberg kfree(dev); 296757dacad5SJay Sternberg return result; 296857dacad5SJay Sternberg } 296957dacad5SJay Sternberg 2970775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 297157dacad5SJay Sternberg { 297257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2973c1ac9a4bSKeith Busch 2974c1ac9a4bSKeith Busch /* 2975c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 2976c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 2977c1ac9a4bSKeith Busch * with ->remove(). 2978c1ac9a4bSKeith Busch */ 2979c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 2980c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 2981775755edSChristoph Hellwig } 298257dacad5SJay Sternberg 2983775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2984775755edSChristoph Hellwig { 2985f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2986c1ac9a4bSKeith Busch 2987c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 2988c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 298957dacad5SJay Sternberg } 299057dacad5SJay Sternberg 299157dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 299257dacad5SJay Sternberg { 299357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 29944e523547SBaolin Wang 2995c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 299657dacad5SJay Sternberg } 299757dacad5SJay Sternberg 2998f58944e2SKeith Busch /* 2999f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3000f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3001f58944e2SKeith Busch * order to proceed. 3002f58944e2SKeith Busch */ 300357dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 300457dacad5SJay Sternberg { 300557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 300657dacad5SJay Sternberg 3007bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 300857dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 30090ff9d4e1SKeith Busch 30106db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 30110ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 30121d39e692SKeith Busch nvme_dev_disable(dev, true); 30136db28edaSKeith Busch } 30140ff9d4e1SKeith Busch 3015d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3016d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3017d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3018a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 30199fe5c59fSKeith Busch nvme_release_cmb(dev); 302087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 302157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 302257dacad5SJay Sternberg nvme_free_queues(dev, 0); 302357dacad5SJay Sternberg nvme_release_prp_pools(dev); 3024b00a726aSKeith Busch nvme_dev_unmap(dev); 3025726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 302657dacad5SJay Sternberg } 302757dacad5SJay Sternberg 302857dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3029d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3030d916b1beSKeith Busch { 3031d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3032d916b1beSKeith Busch } 3033d916b1beSKeith Busch 3034d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3035d916b1beSKeith Busch { 3036d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3037d916b1beSKeith Busch } 3038d916b1beSKeith Busch 3039d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3040d916b1beSKeith Busch { 3041d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3042d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3043d916b1beSKeith Busch 30444eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3045d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3046c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 3047d916b1beSKeith Busch return 0; 3048d916b1beSKeith Busch } 3049d916b1beSKeith Busch 305057dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 305157dacad5SJay Sternberg { 305257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 305357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3054d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3055d916b1beSKeith Busch int ret = -EBUSY; 3056d916b1beSKeith Busch 30574eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 30584eaefe8cSRafael J. Wysocki 3059d916b1beSKeith Busch /* 3060d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3061d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3062d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3063d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3064d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3065d916b1beSKeith Busch * device fully. 30664eaefe8cSRafael J. Wysocki * 30674eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 30684eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 30694eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 30704eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3071b97120b1SChristoph Hellwig * 3072b97120b1SChristoph Hellwig * If a host memory buffer is enabled, shut down the device as the NVMe 3073b97120b1SChristoph Hellwig * specification allows the device to access the host memory buffer in 3074b97120b1SChristoph Hellwig * host DRAM from all power states, but hosts will fail access to DRAM 3075b97120b1SChristoph Hellwig * during S3. 3076d916b1beSKeith Busch */ 30774eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3078cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3079b97120b1SChristoph Hellwig ndev->nr_host_mem_descs || 3080c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3081c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3082d916b1beSKeith Busch 3083d916b1beSKeith Busch nvme_start_freeze(ctrl); 3084d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3085d916b1beSKeith Busch nvme_sync_queues(ctrl); 3086d916b1beSKeith Busch 30875d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3088d916b1beSKeith Busch goto unfreeze; 3089d916b1beSKeith Busch 3090d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3091d916b1beSKeith Busch if (ret < 0) 3092d916b1beSKeith Busch goto unfreeze; 3093d916b1beSKeith Busch 30947cbb5c6fSMario Limonciello /* 30957cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 30967cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 30977cbb5c6fSMario Limonciello * want pci interfering. 30987cbb5c6fSMario Limonciello */ 30997cbb5c6fSMario Limonciello pci_save_state(pdev); 31007cbb5c6fSMario Limonciello 3101d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3102d916b1beSKeith Busch if (ret < 0) 3103d916b1beSKeith Busch goto unfreeze; 3104d916b1beSKeith Busch 3105d916b1beSKeith Busch if (ret) { 31067cbb5c6fSMario Limonciello /* discard the saved state */ 31077cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 31087cbb5c6fSMario Limonciello 3109d916b1beSKeith Busch /* 3110d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 311105d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3112d916b1beSKeith Busch */ 3113c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3114d916b1beSKeith Busch ctrl->npss = 0; 3115d916b1beSKeith Busch } 3116d916b1beSKeith Busch unfreeze: 3117d916b1beSKeith Busch nvme_unfreeze(ctrl); 3118d916b1beSKeith Busch return ret; 3119d916b1beSKeith Busch } 3120d916b1beSKeith Busch 3121d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3122d916b1beSKeith Busch { 3123d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 31244e523547SBaolin Wang 3125c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 312657dacad5SJay Sternberg } 312757dacad5SJay Sternberg 3128d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 312957dacad5SJay Sternberg { 313057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 313157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 313257dacad5SJay Sternberg 3133c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 313457dacad5SJay Sternberg } 313557dacad5SJay Sternberg 313621774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3137d916b1beSKeith Busch .suspend = nvme_suspend, 3138d916b1beSKeith Busch .resume = nvme_resume, 3139d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3140d916b1beSKeith Busch .thaw = nvme_simple_resume, 3141d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3142d916b1beSKeith Busch .restore = nvme_simple_resume, 3143d916b1beSKeith Busch }; 3144d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 314557dacad5SJay Sternberg 3146a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3147a0a3408eSKeith Busch pci_channel_state_t state) 3148a0a3408eSKeith Busch { 3149a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3150a0a3408eSKeith Busch 3151a0a3408eSKeith Busch /* 3152a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3153a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3154a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3155a0a3408eSKeith Busch */ 3156a0a3408eSKeith Busch switch (state) { 3157a0a3408eSKeith Busch case pci_channel_io_normal: 3158a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3159a0a3408eSKeith Busch case pci_channel_io_frozen: 3160d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3161d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3162a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3163a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3164a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3165d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3166d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3167a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3168a0a3408eSKeith Busch } 3169a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3170a0a3408eSKeith Busch } 3171a0a3408eSKeith Busch 3172a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3173a0a3408eSKeith Busch { 3174a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3175a0a3408eSKeith Busch 31761b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3177a0a3408eSKeith Busch pci_restore_state(pdev); 3178d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3179a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3180a0a3408eSKeith Busch } 3181a0a3408eSKeith Busch 3182a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3183a0a3408eSKeith Busch { 318472cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 318572cd4cc2SKeith Busch 318672cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3187a0a3408eSKeith Busch } 3188a0a3408eSKeith Busch 318957dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 319057dacad5SJay Sternberg .error_detected = nvme_error_detected, 319157dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 319257dacad5SJay Sternberg .resume = nvme_error_resume, 3193775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3194775755edSChristoph Hellwig .reset_done = nvme_reset_done, 319557dacad5SJay Sternberg }; 319657dacad5SJay Sternberg 319757dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3198972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 319908095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3200e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3201972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 320299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3203e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3204972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 320599466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3206e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3207972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3208f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3209f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 321050af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 32119abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 32126c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3213ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3214ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 32156299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 32166299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3217540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 32187b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 32197b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 32205bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 32215bedd3afSChristoph Hellwig .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 32220302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 32235e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 32245e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 322554adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 322654adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 32278c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 32288c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3229015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3230015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3231d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3232d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3233d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 32347ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3235abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 32367ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3237c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3238c9e95c39SClaus Stovgaard .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 32396e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 32406e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 32416e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 324208b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 324308b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3244f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3245f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3246f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 32475611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 32485611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 324902ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 325002ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 325189919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 325289919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3253dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3254dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3255538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3256538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 32574bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 32584bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 32594bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 32604bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 32614bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 32624bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 32634bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 32644bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 32654bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 32664bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 32674bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 32684bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 326998f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 327098f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3271124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 327266341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 327366341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3274d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3275d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_SHARED_TAGS }, 32760b85f59dSAndy Shevchenko 32770b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 327857dacad5SJay Sternberg { 0, } 327957dacad5SJay Sternberg }; 328057dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 328157dacad5SJay Sternberg 328257dacad5SJay Sternberg static struct pci_driver nvme_driver = { 328357dacad5SJay Sternberg .name = "nvme", 328457dacad5SJay Sternberg .id_table = nvme_id_table, 328557dacad5SJay Sternberg .probe = nvme_probe, 328657dacad5SJay Sternberg .remove = nvme_remove, 328757dacad5SJay Sternberg .shutdown = nvme_shutdown, 3288d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 328957dacad5SJay Sternberg .driver = { 329057dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 329157dacad5SJay Sternberg }, 3292d916b1beSKeith Busch #endif 329374d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 329457dacad5SJay Sternberg .err_handler = &nvme_err_handler, 329557dacad5SJay Sternberg }; 329657dacad5SJay Sternberg 329757dacad5SJay Sternberg static int __init nvme_init(void) 329857dacad5SJay Sternberg { 329981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 330081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 330181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3302612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 330317c33167SKeith Busch 33049a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 330557dacad5SJay Sternberg } 330657dacad5SJay Sternberg 330757dacad5SJay Sternberg static void __exit nvme_exit(void) 330857dacad5SJay Sternberg { 330957dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 331003e0f3a6SMing Lei flush_workqueue(nvme_wq); 331157dacad5SJay Sternberg } 331257dacad5SJay Sternberg 331357dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 331457dacad5SJay Sternberg MODULE_LICENSE("GPL"); 331557dacad5SJay Sternberg MODULE_VERSION("1.0"); 331657dacad5SJay Sternberg module_init(nvme_init); 331757dacad5SJay Sternberg module_exit(nvme_exit); 3318