15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 18dc90f084SChristoph Hellwig #include <linux/memremap.h> 1957dacad5SJay Sternberg #include <linux/mm.h> 2057dacad5SJay Sternberg #include <linux/module.h> 2177bf25eaSKeith Busch #include <linux/mutex.h> 22d0877473SKeith Busch #include <linux/once.h> 2357dacad5SJay Sternberg #include <linux/pci.h> 24d916b1beSKeith Busch #include <linux/suspend.h> 2557dacad5SJay Sternberg #include <linux/t10-pi.h> 2657dacad5SJay Sternberg #include <linux/types.h> 279cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2820d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 29a98e58e5SScott Bauer #include <linux/sed-opal.h> 300f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3157dacad5SJay Sternberg 32604c01d5Syupeng #include "trace.h" 3357dacad5SJay Sternberg #include "nvme.h" 3457dacad5SJay Sternberg 35c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 368a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3757dacad5SJay Sternberg 38a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39adf68f21SChristoph Hellwig 40943e942eSJens Axboe /* 41943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 42943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 43943e942eSJens Axboe */ 44943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 45943e942eSJens Axboe #define NVME_MAX_SEGS 127 46943e942eSJens Axboe 4757dacad5SJay Sternberg static int use_threaded_interrupts; 482e21e445SXin Hao module_param(use_threaded_interrupts, int, 0444); 4957dacad5SJay Sternberg 5057dacad5SJay Sternberg static bool use_cmb_sqes = true; 5169f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5257dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5357dacad5SJay Sternberg 5487ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5587ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5687ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5787ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5857dacad5SJay Sternberg 59a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 60a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 61a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 62a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 63a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 64a7a7cbe3SChaitanya Kulkarni 6527453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6627453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 7061f3b896SChaitanya Kulkarni .get = param_get_uint, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 7361f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7527453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 76b27c1e68Sweiping zhang 779c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 789c9e76d5SWeiping Zhang { 799c9e76d5SWeiping Zhang unsigned int n; 809c9e76d5SWeiping Zhang int ret; 819c9e76d5SWeiping Zhang 829c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 839c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 849c9e76d5SWeiping Zhang return -EINVAL; 859c9e76d5SWeiping Zhang return param_set_uint(val, kp); 869c9e76d5SWeiping Zhang } 879c9e76d5SWeiping Zhang 889c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 899c9e76d5SWeiping Zhang .set = io_queue_count_set, 909c9e76d5SWeiping Zhang .get = param_get_uint, 919c9e76d5SWeiping Zhang }; 929c9e76d5SWeiping Zhang 933f68baf7SKeith Busch static unsigned int write_queues; 949c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 953b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 963b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 973b6592f7SJens Axboe "will share a queue set."); 983b6592f7SJens Axboe 993f68baf7SKeith Busch static unsigned int poll_queues; 1009c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1014b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1024b04cc6aSJens Axboe 103df4f9bc4SDavid E. Box static bool noacpi; 104df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 105df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 106df4f9bc4SDavid E. Box 1071c63dc66SChristoph Hellwig struct nvme_dev; 1081c63dc66SChristoph Hellwig struct nvme_queue; 10957dacad5SJay Sternberg 110a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1118fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11257dacad5SJay Sternberg 11357dacad5SJay Sternberg /* 1141c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1151c63dc66SChristoph Hellwig */ 1161c63dc66SChristoph Hellwig struct nvme_dev { 117147b27e4SSagi Grimberg struct nvme_queue *queues; 1181c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1191c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1201c63dc66SChristoph Hellwig u32 __iomem *dbs; 1211c63dc66SChristoph Hellwig struct device *dev; 1221c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1231c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1241c63dc66SChristoph Hellwig unsigned online_queues; 1251c63dc66SChristoph Hellwig unsigned max_qid; 126e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12722b55601SKeith Busch unsigned int num_vecs; 1287442ddceSJohn Garry u32 q_depth; 129c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1301c63dc66SChristoph Hellwig u32 db_stride; 1311c63dc66SChristoph Hellwig void __iomem *bar; 13297f6ef64SXu Yu unsigned long bar_mapped_size; 1335c8809e6SChristoph Hellwig struct work_struct remove_work; 13477bf25eaSKeith Busch struct mutex shutdown_lock; 1351c63dc66SChristoph Hellwig bool subsystem; 1361c63dc66SChristoph Hellwig u64 cmb_size; 1370f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1381c63dc66SChristoph Hellwig u32 cmbsz; 139202021c1SStephen Bates u32 cmbloc; 1401c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 141d916b1beSKeith Busch u32 last_ps; 142a5df5e79SKeith Busch bool hmb; 14387ad72a5SChristoph Hellwig 144943e942eSJens Axboe mempool_t *iod_mempool; 145943e942eSJens Axboe 14687ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 147f9f38e33SHelen Koike u32 *dbbuf_dbs; 148f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 149f9f38e33SHelen Koike u32 *dbbuf_eis; 150f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15187ad72a5SChristoph Hellwig 15287ad72a5SChristoph Hellwig /* host memory buffer support: */ 15387ad72a5SChristoph Hellwig u64 host_mem_size; 15487ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1554033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15787ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1582a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1592a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1602a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 1610521905eSKeith Busch 1620521905eSKeith Busch bool attrs_added; 16357dacad5SJay Sternberg }; 16457dacad5SJay Sternberg 165b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 166b27c1e68Sweiping zhang { 16727453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16827453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 169b27c1e68Sweiping zhang } 170b27c1e68Sweiping zhang 171f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 172f9f38e33SHelen Koike { 173f9f38e33SHelen Koike return qid * 2 * stride; 174f9f38e33SHelen Koike } 175f9f38e33SHelen Koike 176f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 177f9f38e33SHelen Koike { 178f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 179f9f38e33SHelen Koike } 180f9f38e33SHelen Koike 1811c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1821c63dc66SChristoph Hellwig { 1831c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1841c63dc66SChristoph Hellwig } 1851c63dc66SChristoph Hellwig 18657dacad5SJay Sternberg /* 18757dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18857dacad5SJay Sternberg * commands and one for I/O commands). 18957dacad5SJay Sternberg */ 19057dacad5SJay Sternberg struct nvme_queue { 19157dacad5SJay Sternberg struct nvme_dev *dev; 1921ab0cd69SJens Axboe spinlock_t sq_lock; 193c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1943a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1953a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19674943d45SKeith Busch struct nvme_completion *cqes; 19757dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19857dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19957dacad5SJay Sternberg u32 __iomem *q_db; 2007442ddceSJohn Garry u32 q_depth; 2017c349ddeSKeith Busch u16 cq_vector; 20257dacad5SJay Sternberg u16 sq_tail; 20338210800SKeith Busch u16 last_sq_tail; 20457dacad5SJay Sternberg u16 cq_head; 20557dacad5SJay Sternberg u16 qid; 20657dacad5SJay Sternberg u8 cq_phase; 207c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2084e224106SChristoph Hellwig unsigned long flags; 2094e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 21063223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 211d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2127c349ddeSKeith Busch #define NVMEQ_POLLED 3 213f9f38e33SHelen Koike u32 *dbbuf_sq_db; 214f9f38e33SHelen Koike u32 *dbbuf_cq_db; 215f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 216f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 217d1ed6aa1SChristoph Hellwig struct completion delete_done; 21857dacad5SJay Sternberg }; 21957dacad5SJay Sternberg 22057dacad5SJay Sternberg /* 2219b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2229b048119SChristoph Hellwig * 2239b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2249b048119SChristoph Hellwig * to the actual struct scatterlist. 22571bd150cSChristoph Hellwig */ 22671bd150cSChristoph Hellwig struct nvme_iod { 227d49187e9SChristoph Hellwig struct nvme_request req; 228af7fae85SKeith Busch struct nvme_command cmd; 229f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 230a7a7cbe3SChaitanya Kulkarni bool use_sgl; 231f4800d6dSChristoph Hellwig int aborted; 23271bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 23371bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 23471bd150cSChristoph Hellwig dma_addr_t first_dma; 235dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 236783b94bdSChristoph Hellwig dma_addr_t meta_dma; 237f4800d6dSChristoph Hellwig struct scatterlist *sg; 23857dacad5SJay Sternberg }; 23957dacad5SJay Sternberg 2402a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2413b6592f7SJens Axboe { 2422a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 243f9f38e33SHelen Koike } 244f9f38e33SHelen Koike 245f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 246f9f38e33SHelen Koike { 2472a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 248f9f38e33SHelen Koike 24958847f12SKeith Busch if (dev->dbbuf_dbs) { 25058847f12SKeith Busch /* 25158847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25258847f12SKeith Busch * values from the previous instantiation. 25358847f12SKeith Busch */ 25458847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 25558847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 256f9f38e33SHelen Koike return 0; 25758847f12SKeith Busch } 258f9f38e33SHelen Koike 259f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 260f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 261f9f38e33SHelen Koike GFP_KERNEL); 262f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 263f9f38e33SHelen Koike return -ENOMEM; 264f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 265f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 266f9f38e33SHelen Koike GFP_KERNEL); 267f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 268f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 269f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 270f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 271f9f38e33SHelen Koike return -ENOMEM; 272f9f38e33SHelen Koike } 273f9f38e33SHelen Koike 274f9f38e33SHelen Koike return 0; 275f9f38e33SHelen Koike } 276f9f38e33SHelen Koike 277f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 278f9f38e33SHelen Koike { 2792a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 280f9f38e33SHelen Koike 281f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 282f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 283f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 284f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike if (dev->dbbuf_eis) { 287f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 288f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 289f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 290f9f38e33SHelen Koike } 291f9f38e33SHelen Koike } 292f9f38e33SHelen Koike 293f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 294f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 295f9f38e33SHelen Koike { 296f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 297f9f38e33SHelen Koike return; 298f9f38e33SHelen Koike 299f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 300f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 301f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 302f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike 3050f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3060f0d2c87SMinwoo Im { 3070f0d2c87SMinwoo Im if (!nvmeq->qid) 3080f0d2c87SMinwoo Im return; 3090f0d2c87SMinwoo Im 3100f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3110f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3120f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3130f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3140f0d2c87SMinwoo Im } 3150f0d2c87SMinwoo Im 316f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 317f9f38e33SHelen Koike { 318f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3190f0d2c87SMinwoo Im unsigned int i; 320f9f38e33SHelen Koike 321f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 322f9f38e33SHelen Koike return; 323f9f38e33SHelen Koike 324f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 325f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 326f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 327f9f38e33SHelen Koike 328f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3299bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 330f9f38e33SHelen Koike /* Free memory and continue on */ 331f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3320f0d2c87SMinwoo Im 3330f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3340f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 335f9f38e33SHelen Koike } 336f9f38e33SHelen Koike } 337f9f38e33SHelen Koike 338f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 339f9f38e33SHelen Koike { 340f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 341f9f38e33SHelen Koike } 342f9f38e33SHelen Koike 343f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 344f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 345f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 346f9f38e33SHelen Koike { 347f9f38e33SHelen Koike if (dbbuf_db) { 348f9f38e33SHelen Koike u16 old_value; 349f9f38e33SHelen Koike 350f9f38e33SHelen Koike /* 351f9f38e33SHelen Koike * Ensure that the queue is written before updating 352f9f38e33SHelen Koike * the doorbell in memory 353f9f38e33SHelen Koike */ 354f9f38e33SHelen Koike wmb(); 355f9f38e33SHelen Koike 356f9f38e33SHelen Koike old_value = *dbbuf_db; 357f9f38e33SHelen Koike *dbbuf_db = value; 358f9f38e33SHelen Koike 359f1ed3df2SMichal Wnukowski /* 360f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 361f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 362f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 363f1ed3df2SMichal Wnukowski * the doorbell. 364f1ed3df2SMichal Wnukowski */ 365f1ed3df2SMichal Wnukowski mb(); 366f1ed3df2SMichal Wnukowski 367f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 368f9f38e33SHelen Koike return false; 369f9f38e33SHelen Koike } 370f9f38e33SHelen Koike 371f9f38e33SHelen Koike return true; 37257dacad5SJay Sternberg } 37357dacad5SJay Sternberg 37457dacad5SJay Sternberg /* 37557dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37657dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37757dacad5SJay Sternberg * the I/O. 37857dacad5SJay Sternberg */ 379b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 38057dacad5SJay Sternberg { 381b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3826c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 38357dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38457dacad5SJay Sternberg } 38557dacad5SJay Sternberg 386a7a7cbe3SChaitanya Kulkarni /* 387a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 388a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 389a7a7cbe3SChaitanya Kulkarni */ 390b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 391f4800d6dSChristoph Hellwig { 392b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 393b13c6393SChaitanya Kulkarni PAGE_SIZE); 394f4800d6dSChristoph Hellwig } 395f4800d6dSChristoph Hellwig 396b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 39757dacad5SJay Sternberg { 398b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 399a7a7cbe3SChaitanya Kulkarni 400b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 401b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 402a7a7cbe3SChaitanya Kulkarni } 403a7a7cbe3SChaitanya Kulkarni 40457dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40557dacad5SJay Sternberg unsigned int hctx_idx) 40657dacad5SJay Sternberg { 40757dacad5SJay Sternberg struct nvme_dev *dev = data; 408147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40957dacad5SJay Sternberg 41057dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 41157dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 41257dacad5SJay Sternberg 41357dacad5SJay Sternberg hctx->driver_data = nvmeq; 41457dacad5SJay Sternberg return 0; 41557dacad5SJay Sternberg } 41657dacad5SJay Sternberg 41757dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41857dacad5SJay Sternberg unsigned int hctx_idx) 41957dacad5SJay Sternberg { 42057dacad5SJay Sternberg struct nvme_dev *dev = data; 421147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 42257dacad5SJay Sternberg 42357dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 42457dacad5SJay Sternberg hctx->driver_data = nvmeq; 42557dacad5SJay Sternberg return 0; 42657dacad5SJay Sternberg } 42757dacad5SJay Sternberg 428e559398fSChristoph Hellwig static int nvme_pci_init_request(struct blk_mq_tag_set *set, 429e559398fSChristoph Hellwig struct request *req, unsigned int hctx_idx, 430e559398fSChristoph Hellwig unsigned int numa_node) 43157dacad5SJay Sternberg { 432d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 433f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4340350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 435147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 43657dacad5SJay Sternberg 43757dacad5SJay Sternberg BUG_ON(!nvmeq); 438f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 43959e29ce6SSagi Grimberg 44059e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 441f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 44257dacad5SJay Sternberg return 0; 44357dacad5SJay Sternberg } 44457dacad5SJay Sternberg 4453b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4463b6592f7SJens Axboe { 4473b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4483b6592f7SJens Axboe if (dev->num_vecs > 1) 4493b6592f7SJens Axboe return 1; 4503b6592f7SJens Axboe 4513b6592f7SJens Axboe return 0; 4523b6592f7SJens Axboe } 4533b6592f7SJens Axboe 454dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 455dca51e78SChristoph Hellwig { 456dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4573b6592f7SJens Axboe int i, qoff, offset; 458dca51e78SChristoph Hellwig 4593b6592f7SJens Axboe offset = queue_irq_offset(dev); 4603b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4613b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4623b6592f7SJens Axboe 4633b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4643b6592f7SJens Axboe if (!map->nr_queues) { 465e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4667e849dd9SChristoph Hellwig continue; 4673b6592f7SJens Axboe } 4683b6592f7SJens Axboe 4694b04cc6aSJens Axboe /* 4704b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4714b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4724b04cc6aSJens Axboe */ 4733b6592f7SJens Axboe map->queue_offset = qoff; 474cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4753b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4764b04cc6aSJens Axboe else 4774b04cc6aSJens Axboe blk_mq_map_queues(map); 4783b6592f7SJens Axboe qoff += map->nr_queues; 4793b6592f7SJens Axboe offset += map->nr_queues; 4803b6592f7SJens Axboe } 4813b6592f7SJens Axboe 4823b6592f7SJens Axboe return 0; 483dca51e78SChristoph Hellwig } 484dca51e78SChristoph Hellwig 48538210800SKeith Busch /* 48638210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 48738210800SKeith Busch */ 48838210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 48904f3eafdSJens Axboe { 49038210800SKeith Busch if (!write_sq) { 49138210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 49238210800SKeith Busch 49338210800SKeith Busch if (next_tail == nvmeq->q_depth) 49438210800SKeith Busch next_tail = 0; 49538210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 49638210800SKeith Busch return; 49738210800SKeith Busch } 49838210800SKeith Busch 49904f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 50004f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 50104f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 50238210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 50304f3eafdSJens Axboe } 50404f3eafdSJens Axboe 5053233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 5063233b94cSJens Axboe struct nvme_command *cmd) 50757dacad5SJay Sternberg { 508c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 5093233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 51090ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 51190ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 51204f3eafdSJens Axboe } 51304f3eafdSJens Axboe 51404f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 51504f3eafdSJens Axboe { 51604f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 51704f3eafdSJens Axboe 51804f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 51938210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 52038210800SKeith Busch nvme_write_sq_db(nvmeq, true); 52190ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 52257dacad5SJay Sternberg } 52357dacad5SJay Sternberg 524a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 52557dacad5SJay Sternberg { 526f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 527a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 52857dacad5SJay Sternberg } 52957dacad5SJay Sternberg 530955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 531955b1b5aSMinwoo Im { 532955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 53320469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 534955b1b5aSMinwoo Im unsigned int avg_seg_size; 535955b1b5aSMinwoo Im 53620469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 537955b1b5aSMinwoo Im 538253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 539955b1b5aSMinwoo Im return false; 540955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 541955b1b5aSMinwoo Im return false; 542955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 543955b1b5aSMinwoo Im return false; 544955b1b5aSMinwoo Im return true; 545955b1b5aSMinwoo Im } 546955b1b5aSMinwoo Im 5479275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 54857dacad5SJay Sternberg { 5496c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5509275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5519275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 55257dacad5SJay Sternberg int i; 55357dacad5SJay Sternberg 5549275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5559275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5569275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5579275c206SChristoph Hellwig 5589275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5599275c206SChristoph Hellwig dma_addr = next_dma_addr; 560dff824b2SChristoph Hellwig } 5619275c206SChristoph Hellwig } 5629275c206SChristoph Hellwig 5639275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5649275c206SChristoph Hellwig { 5659275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5669275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5679275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5689275c206SChristoph Hellwig int i; 5699275c206SChristoph Hellwig 5709275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5719275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5729275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5739275c206SChristoph Hellwig 5749275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5759275c206SChristoph Hellwig dma_addr = next_dma_addr; 5769275c206SChristoph Hellwig } 5779275c206SChristoph Hellwig } 5789275c206SChristoph Hellwig 5799275c206SChristoph Hellwig static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 5809275c206SChristoph Hellwig { 5819275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 582dff824b2SChristoph Hellwig 5837f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5847f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5857f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5867f73eac3SLogan Gunthorpe else 587dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5889275c206SChristoph Hellwig } 5897fe07d14SChristoph Hellwig 5909275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5919275c206SChristoph Hellwig { 5929275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5937fe07d14SChristoph Hellwig 5949275c206SChristoph Hellwig if (iod->dma_len) { 5959275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5969275c206SChristoph Hellwig rq_dma_dir(req)); 5979275c206SChristoph Hellwig return; 5989275c206SChristoph Hellwig } 5999275c206SChristoph Hellwig 6009275c206SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 6019275c206SChristoph Hellwig 6029275c206SChristoph Hellwig nvme_unmap_sg(dev, req); 60357dacad5SJay Sternberg if (iod->npages == 0) 604a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 6059275c206SChristoph Hellwig iod->first_dma); 6069275c206SChristoph Hellwig else if (iod->use_sgl) 6079275c206SChristoph Hellwig nvme_free_sgls(dev, req); 6089275c206SChristoph Hellwig else 6099275c206SChristoph Hellwig nvme_free_prps(dev, req); 610943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 61157dacad5SJay Sternberg } 61257dacad5SJay Sternberg 613d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 614d0877473SKeith Busch { 615d0877473SKeith Busch int i; 616d0877473SKeith Busch struct scatterlist *sg; 617d0877473SKeith Busch 618d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 619d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 620d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 621d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 622d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 623d0877473SKeith Busch sg_dma_len(sg)); 624d0877473SKeith Busch } 625d0877473SKeith Busch } 626d0877473SKeith Busch 627a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 628a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 62957dacad5SJay Sternberg { 630f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 63157dacad5SJay Sternberg struct dma_pool *pool; 632b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 63357dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 63457dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 63557dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6366c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 63757dacad5SJay Sternberg __le64 *prp_list; 638a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 63957dacad5SJay Sternberg dma_addr_t prp_dma; 64057dacad5SJay Sternberg int nprps, i; 64157dacad5SJay Sternberg 6426c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6435228b328SJan H. Schönherr if (length <= 0) { 6445228b328SJan H. Schönherr iod->first_dma = 0; 645a7a7cbe3SChaitanya Kulkarni goto done; 6465228b328SJan H. Schönherr } 64757dacad5SJay Sternberg 6486c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 64957dacad5SJay Sternberg if (dma_len) { 6506c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 65157dacad5SJay Sternberg } else { 65257dacad5SJay Sternberg sg = sg_next(sg); 65357dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65457dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65557dacad5SJay Sternberg } 65657dacad5SJay Sternberg 6576c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 65857dacad5SJay Sternberg iod->first_dma = dma_addr; 659a7a7cbe3SChaitanya Kulkarni goto done; 66057dacad5SJay Sternberg } 66157dacad5SJay Sternberg 6626c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 66357dacad5SJay Sternberg if (nprps <= (256 / 8)) { 66457dacad5SJay Sternberg pool = dev->prp_small_pool; 66557dacad5SJay Sternberg iod->npages = 0; 66657dacad5SJay Sternberg } else { 66757dacad5SJay Sternberg pool = dev->prp_page_pool; 66857dacad5SJay Sternberg iod->npages = 1; 66957dacad5SJay Sternberg } 67057dacad5SJay Sternberg 67169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67257dacad5SJay Sternberg if (!prp_list) { 67357dacad5SJay Sternberg iod->first_dma = dma_addr; 67457dacad5SJay Sternberg iod->npages = -1; 67586eea289SKeith Busch return BLK_STS_RESOURCE; 67657dacad5SJay Sternberg } 67757dacad5SJay Sternberg list[0] = prp_list; 67857dacad5SJay Sternberg iod->first_dma = prp_dma; 67957dacad5SJay Sternberg i = 0; 68057dacad5SJay Sternberg for (;;) { 6816c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 68257dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 68369d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68457dacad5SJay Sternberg if (!prp_list) 685fa073216SChristoph Hellwig goto free_prps; 68657dacad5SJay Sternberg list[iod->npages++] = prp_list; 68757dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 68857dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 68957dacad5SJay Sternberg i = 1; 69057dacad5SJay Sternberg } 69157dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6926c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6936c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6946c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 69557dacad5SJay Sternberg if (length <= 0) 69657dacad5SJay Sternberg break; 69757dacad5SJay Sternberg if (dma_len > 0) 69857dacad5SJay Sternberg continue; 69986eea289SKeith Busch if (unlikely(dma_len < 0)) 70086eea289SKeith Busch goto bad_sgl; 70157dacad5SJay Sternberg sg = sg_next(sg); 70257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 70357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 70457dacad5SJay Sternberg } 705a7a7cbe3SChaitanya Kulkarni done: 706a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 707a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 70886eea289SKeith Busch return BLK_STS_OK; 709fa073216SChristoph Hellwig free_prps: 710fa073216SChristoph Hellwig nvme_free_prps(dev, req); 711fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 71286eea289SKeith Busch bad_sgl: 713d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 714d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 715d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 71686eea289SKeith Busch return BLK_STS_IOERR; 71757dacad5SJay Sternberg } 71857dacad5SJay Sternberg 719a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 720a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 721a7a7cbe3SChaitanya Kulkarni { 722a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 723a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 724a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 725a7a7cbe3SChaitanya Kulkarni } 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 728a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 729a7a7cbe3SChaitanya Kulkarni { 730a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 731a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 732a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 733a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 734a7a7cbe3SChaitanya Kulkarni } else { 735a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 736a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 737a7a7cbe3SChaitanya Kulkarni } 738a7a7cbe3SChaitanya Kulkarni } 739a7a7cbe3SChaitanya Kulkarni 740a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 741b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 742a7a7cbe3SChaitanya Kulkarni { 743a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 744a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 745a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 746a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 747a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 748b0f2853bSChristoph Hellwig int i = 0; 749a7a7cbe3SChaitanya Kulkarni 750a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 751a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 752a7a7cbe3SChaitanya Kulkarni 753b0f2853bSChristoph Hellwig if (entries == 1) { 754a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 755a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 756a7a7cbe3SChaitanya Kulkarni } 757a7a7cbe3SChaitanya Kulkarni 758a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 759a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 760a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 761a7a7cbe3SChaitanya Kulkarni } else { 762a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 763a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 764a7a7cbe3SChaitanya Kulkarni } 765a7a7cbe3SChaitanya Kulkarni 766a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 767a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 768a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 769a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 770a7a7cbe3SChaitanya Kulkarni } 771a7a7cbe3SChaitanya Kulkarni 772a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 773a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 774a7a7cbe3SChaitanya Kulkarni 775a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 776a7a7cbe3SChaitanya Kulkarni 777a7a7cbe3SChaitanya Kulkarni do { 778a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 779a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 780a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 781a7a7cbe3SChaitanya Kulkarni 782a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 783a7a7cbe3SChaitanya Kulkarni if (!sg_list) 784fa073216SChristoph Hellwig goto free_sgls; 785a7a7cbe3SChaitanya Kulkarni 786a7a7cbe3SChaitanya Kulkarni i = 0; 787a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 788a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 789a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 790a7a7cbe3SChaitanya Kulkarni } 791a7a7cbe3SChaitanya Kulkarni 792a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 793a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 794b0f2853bSChristoph Hellwig } while (--entries > 0); 795a7a7cbe3SChaitanya Kulkarni 796a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 797fa073216SChristoph Hellwig free_sgls: 798fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 799fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 800a7a7cbe3SChaitanya Kulkarni } 801a7a7cbe3SChaitanya Kulkarni 802dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 803dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 804dff824b2SChristoph Hellwig struct bio_vec *bv) 805dff824b2SChristoph Hellwig { 806dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8076c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 8086c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 809dff824b2SChristoph Hellwig 810dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 811dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 812dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 813dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 814dff824b2SChristoph Hellwig 815dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 816dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 817dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 818359c1f88SBaolin Wang return BLK_STS_OK; 819dff824b2SChristoph Hellwig } 820dff824b2SChristoph Hellwig 82129791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 82229791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 82329791057SChristoph Hellwig struct bio_vec *bv) 82429791057SChristoph Hellwig { 82529791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82629791057SChristoph Hellwig 82729791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 82829791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 82929791057SChristoph Hellwig return BLK_STS_RESOURCE; 83029791057SChristoph Hellwig iod->dma_len = bv->bv_len; 83129791057SChristoph Hellwig 832049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 83329791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 83429791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 83529791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 836359c1f88SBaolin Wang return BLK_STS_OK; 83729791057SChristoph Hellwig } 83829791057SChristoph Hellwig 839fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 840b131c61dSChristoph Hellwig struct nvme_command *cmnd) 84157dacad5SJay Sternberg { 842f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 84370479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 844b0f2853bSChristoph Hellwig int nr_mapped; 84557dacad5SJay Sternberg 846dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 847dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 848dff824b2SChristoph Hellwig 849dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8506c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 851dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 852dff824b2SChristoph Hellwig &cmnd->rw, &bv); 85329791057SChristoph Hellwig 854e51183beSNiklas Cassel if (iod->nvmeq->qid && sgl_threshold && 855253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 85629791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 85729791057SChristoph Hellwig &cmnd->rw, &bv); 858dff824b2SChristoph Hellwig } 859dff824b2SChristoph Hellwig } 860dff824b2SChristoph Hellwig 861dff824b2SChristoph Hellwig iod->dma_len = 0; 8629b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8639b048119SChristoph Hellwig if (!iod->sg) 8649b048119SChristoph Hellwig return BLK_STS_RESOURCE; 865f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 86670479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 867ba1ca37eSChristoph Hellwig if (!iod->nents) 868fa073216SChristoph Hellwig goto out_free_sg; 869ba1ca37eSChristoph Hellwig 870e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8712b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8722b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 873e0596ab2SLogan Gunthorpe else 874e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 87570479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 876b0f2853bSChristoph Hellwig if (!nr_mapped) 877fa073216SChristoph Hellwig goto out_free_sg; 878ba1ca37eSChristoph Hellwig 87970479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 880955b1b5aSMinwoo Im if (iod->use_sgl) 881b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 882a7a7cbe3SChaitanya Kulkarni else 883a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8844aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 885fa073216SChristoph Hellwig goto out_unmap_sg; 886fa073216SChristoph Hellwig return BLK_STS_OK; 887fa073216SChristoph Hellwig 888fa073216SChristoph Hellwig out_unmap_sg: 889fa073216SChristoph Hellwig nvme_unmap_sg(dev, req); 890fa073216SChristoph Hellwig out_free_sg: 891fa073216SChristoph Hellwig mempool_free(iod->sg, dev->iod_mempool); 892ba1ca37eSChristoph Hellwig return ret; 89357dacad5SJay Sternberg } 89457dacad5SJay Sternberg 8954aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8964aedb705SChristoph Hellwig struct nvme_command *cmnd) 8974aedb705SChristoph Hellwig { 8984aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8994aedb705SChristoph Hellwig 9004aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 9014aedb705SChristoph Hellwig rq_dma_dir(req), 0); 9024aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 9034aedb705SChristoph Hellwig return BLK_STS_IOERR; 9044aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 905359c1f88SBaolin Wang return BLK_STS_OK; 9064aedb705SChristoph Hellwig } 9074aedb705SChristoph Hellwig 90862451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 90962451a2bSJens Axboe { 91062451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 91162451a2bSJens Axboe blk_status_t ret; 91262451a2bSJens Axboe 91362451a2bSJens Axboe iod->aborted = 0; 91462451a2bSJens Axboe iod->npages = -1; 91562451a2bSJens Axboe iod->nents = 0; 91662451a2bSJens Axboe 91762451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 91862451a2bSJens Axboe if (ret) 91962451a2bSJens Axboe return ret; 92062451a2bSJens Axboe 92162451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 92262451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 92362451a2bSJens Axboe if (ret) 92462451a2bSJens Axboe goto out_free_cmd; 92562451a2bSJens Axboe } 92662451a2bSJens Axboe 92762451a2bSJens Axboe if (blk_integrity_rq(req)) { 92862451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 92962451a2bSJens Axboe if (ret) 93062451a2bSJens Axboe goto out_unmap_data; 93162451a2bSJens Axboe } 93262451a2bSJens Axboe 93362451a2bSJens Axboe blk_mq_start_request(req); 93462451a2bSJens Axboe return BLK_STS_OK; 93562451a2bSJens Axboe out_unmap_data: 93662451a2bSJens Axboe nvme_unmap_data(dev, req); 93762451a2bSJens Axboe out_free_cmd: 93862451a2bSJens Axboe nvme_cleanup_cmd(req); 93962451a2bSJens Axboe return ret; 94062451a2bSJens Axboe } 94162451a2bSJens Axboe 94257dacad5SJay Sternberg /* 94357dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 94457dacad5SJay Sternberg */ 945fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 94657dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 94757dacad5SJay Sternberg { 94857dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 94957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 95057dacad5SJay Sternberg struct request *req = bd->rq; 9519b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 952ebe6d874SChristoph Hellwig blk_status_t ret; 95357dacad5SJay Sternberg 954d1f06f4aSJens Axboe /* 955d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 956d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 957d1f06f4aSJens Axboe */ 9584e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 959d1f06f4aSJens Axboe return BLK_STS_IOERR; 960d1f06f4aSJens Axboe 96162451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 962d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 963d4060d2bSTao Chiu 96462451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 96562451a2bSJens Axboe if (unlikely(ret)) 966f4800d6dSChristoph Hellwig return ret; 9673233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 9683233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 9693233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 9703233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 971fc17b653SChristoph Hellwig return BLK_STS_OK; 97257dacad5SJay Sternberg } 97357dacad5SJay Sternberg 974d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 975d62cbcf6SJens Axboe { 976d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 977d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 978d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 979d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 980d62cbcf6SJens Axboe 981d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 982d62cbcf6SJens Axboe } 983d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 984d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 985d62cbcf6SJens Axboe } 986d62cbcf6SJens Axboe 987d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 988d62cbcf6SJens Axboe { 989d62cbcf6SJens Axboe /* 990d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 991d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 992d62cbcf6SJens Axboe */ 993d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 994d62cbcf6SJens Axboe return false; 995d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 996d62cbcf6SJens Axboe return false; 997d62cbcf6SJens Axboe 998d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 999d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 1000d62cbcf6SJens Axboe } 1001d62cbcf6SJens Axboe 1002d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 1003d62cbcf6SJens Axboe { 10046bfec799SKeith Busch struct request *req, *next, *prev = NULL; 1005d62cbcf6SJens Axboe struct request *requeue_list = NULL; 1006d62cbcf6SJens Axboe 10076bfec799SKeith Busch rq_list_for_each_safe(rqlist, req, next) { 1008d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1009d62cbcf6SJens Axboe 1010d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 1011d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 10126bfec799SKeith Busch rq_list_move(rqlist, &requeue_list, req, prev); 10136bfec799SKeith Busch 10146bfec799SKeith Busch req = prev; 10156bfec799SKeith Busch if (!req) 10166bfec799SKeith Busch continue; 1017d62cbcf6SJens Axboe } 1018d62cbcf6SJens Axboe 10196bfec799SKeith Busch if (!next || req->mq_hctx != next->mq_hctx) { 1020d62cbcf6SJens Axboe /* detach rest of list, and submit */ 10216bfec799SKeith Busch req->rq_next = NULL; 1022d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 10236bfec799SKeith Busch *rqlist = next; 10246bfec799SKeith Busch prev = NULL; 10256bfec799SKeith Busch } else 10266bfec799SKeith Busch prev = req; 1027d62cbcf6SJens Axboe } 1028d62cbcf6SJens Axboe 1029d62cbcf6SJens Axboe *rqlist = requeue_list; 1030d62cbcf6SJens Axboe } 1031d62cbcf6SJens Axboe 1032c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 1033eee417b0SChristoph Hellwig { 1034f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 10354aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 1036eee417b0SChristoph Hellwig 10374aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 10384aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 10394aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1040b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 10414aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 1042c234a653SJens Axboe } 1043c234a653SJens Axboe 1044c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 1045c234a653SJens Axboe { 1046c234a653SJens Axboe nvme_pci_unmap_rq(req); 104777f02a7aSChristoph Hellwig nvme_complete_rq(req); 104857dacad5SJay Sternberg } 104957dacad5SJay Sternberg 1050c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1051c234a653SJens Axboe { 1052c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 1053c234a653SJens Axboe } 1054c234a653SJens Axboe 1055d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 1056750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1057d783e0bdSMarta Rybczynska { 105874943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 105974943d45SKeith Busch 106074943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1061d783e0bdSMarta Rybczynska } 1062d783e0bdSMarta Rybczynska 1063eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 106457dacad5SJay Sternberg { 1065eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 106657dacad5SJay Sternberg 1067eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1068eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1069eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1070eb281c82SSagi Grimberg } 1071adf68f21SChristoph Hellwig 1072cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1073cfa27356SChristoph Hellwig { 1074cfa27356SChristoph Hellwig if (!nvmeq->qid) 1075cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1076cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1077cfa27356SChristoph Hellwig } 1078cfa27356SChristoph Hellwig 1079c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1080c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 108157dacad5SJay Sternberg { 108274943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 108362df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 108457dacad5SJay Sternberg struct request *req; 1085adf68f21SChristoph Hellwig 1086adf68f21SChristoph Hellwig /* 1087adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1088adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1089adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1090adf68f21SChristoph Hellwig * for them but rather special case them here. 1091adf68f21SChristoph Hellwig */ 109262df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10937bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 109483a12fb7SSagi Grimberg cqe->status, &cqe->result); 1095a0fa9647SJens Axboe return; 109657dacad5SJay Sternberg } 109757dacad5SJay Sternberg 1098e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 109950b7c243SXianting Tian if (unlikely(!req)) { 110050b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 110150b7c243SXianting Tian "invalid id %d completed on queue %d\n", 110262df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 110350b7c243SXianting Tian return; 110450b7c243SXianting Tian } 110550b7c243SXianting Tian 1106604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1107c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1108c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1109c234a653SJens Axboe nvme_pci_complete_batch)) 1110ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 111183a12fb7SSagi Grimberg } 111257dacad5SJay Sternberg 11135cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 11145cb525c8SJens Axboe { 1115a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1116a8de6639SAlexey Dobriyan 1117a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1118920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1119e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1120a8de6639SAlexey Dobriyan } else { 1121a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1122920d13a8SSagi Grimberg } 1123a0fa9647SJens Axboe } 1124a0fa9647SJens Axboe 1125c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1126c234a653SJens Axboe struct io_comp_batch *iob) 1127a0fa9647SJens Axboe { 11281052b8acSJens Axboe int found = 0; 112983a12fb7SSagi Grimberg 11301052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 11311052b8acSJens Axboe found++; 1132b69e2ef2SKeith Busch /* 1133b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1134b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1135b69e2ef2SKeith Busch */ 1136b69e2ef2SKeith Busch dma_rmb(); 1137c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 11385cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 113957dacad5SJay Sternberg } 114057dacad5SJay Sternberg 1141324b494cSKeith Busch if (found) 1142eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 11435cb525c8SJens Axboe return found; 114457dacad5SJay Sternberg } 114557dacad5SJay Sternberg 114657dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 114757dacad5SJay Sternberg { 114857dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11494f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 11505cb525c8SJens Axboe 11514f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 11524f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 11534f502245SJens Axboe nvme_pci_complete_batch(&iob); 115405fae499SChaitanya Kulkarni return IRQ_HANDLED; 11554f502245SJens Axboe } 115605fae499SChaitanya Kulkarni return IRQ_NONE; 115757dacad5SJay Sternberg } 115857dacad5SJay Sternberg 115957dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 116057dacad5SJay Sternberg { 116157dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11624e523547SBaolin Wang 1163750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 116457dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1165d783e0bdSMarta Rybczynska return IRQ_NONE; 116657dacad5SJay Sternberg } 116757dacad5SJay Sternberg 11680b2a8a9fSChristoph Hellwig /* 1169fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11700b2a8a9fSChristoph Hellwig * Can be called from any context. 11710b2a8a9fSChristoph Hellwig */ 1172fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1173a0fa9647SJens Axboe { 11743a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1175a0fa9647SJens Axboe 1176fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1177fa059b85SKeith Busch 11783a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1179c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11803a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 118191a509f8SChristoph Hellwig } 1182442e19b7SSagi Grimberg 11835a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11847776db1cSKeith Busch { 11857776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1186dabcefabSJens Axboe bool found; 1187dabcefabSJens Axboe 1188dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1189dabcefabSJens Axboe return 0; 1190dabcefabSJens Axboe 11913a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1192c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11933a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1194dabcefabSJens Axboe 1195dabcefabSJens Axboe return found; 1196dabcefabSJens Axboe } 1197dabcefabSJens Axboe 1198ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 119957dacad5SJay Sternberg { 1200f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1201147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1202f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 120357dacad5SJay Sternberg 120457dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1205ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 12063233b94cSJens Axboe 12073233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 12083233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 12093233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 12103233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 121157dacad5SJay Sternberg } 121257dacad5SJay Sternberg 121357dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 121457dacad5SJay Sternberg { 1215f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 121657dacad5SJay Sternberg 121757dacad5SJay Sternberg c.delete_queue.opcode = opcode; 121857dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 121957dacad5SJay Sternberg 12201c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 122157dacad5SJay Sternberg } 122257dacad5SJay Sternberg 122357dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1224a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 122557dacad5SJay Sternberg { 1226f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 12274b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 12284b04cc6aSJens Axboe 12297c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 12304b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 123157dacad5SJay Sternberg 123257dacad5SJay Sternberg /* 123316772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 123457dacad5SJay Sternberg * is attached to the request. 123557dacad5SJay Sternberg */ 123657dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 123757dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 123857dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 123957dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 124057dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1241a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 124257dacad5SJay Sternberg 12431c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 124457dacad5SJay Sternberg } 124557dacad5SJay Sternberg 124657dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 124757dacad5SJay Sternberg struct nvme_queue *nvmeq) 124857dacad5SJay Sternberg { 12499abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1250f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 125181c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 125257dacad5SJay Sternberg 125357dacad5SJay Sternberg /* 12549abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 12559abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 12569abd68efSJens Axboe * URGENT. 12579abd68efSJens Axboe */ 12589abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 12599abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 12609abd68efSJens Axboe 12619abd68efSJens Axboe /* 126216772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 126357dacad5SJay Sternberg * is attached to the request. 126457dacad5SJay Sternberg */ 126557dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 126657dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 126757dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 126857dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 126957dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 127057dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 127157dacad5SJay Sternberg 12721c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 127357dacad5SJay Sternberg } 127457dacad5SJay Sternberg 127557dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 127657dacad5SJay Sternberg { 127757dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 127857dacad5SJay Sternberg } 127957dacad5SJay Sternberg 128057dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 128157dacad5SJay Sternberg { 128257dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 128357dacad5SJay Sternberg } 128457dacad5SJay Sternberg 12852a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 128657dacad5SJay Sternberg { 1287f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1288f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 128957dacad5SJay Sternberg 129027fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 129127fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1292e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1293e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 129457dacad5SJay Sternberg } 129557dacad5SJay Sternberg 1296b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1297b2a0eb1aSKeith Busch { 1298b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1299b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1300b2a0eb1aSKeith Busch */ 1301b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1302b2a0eb1aSKeith Busch 1303ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1304ad70062cSJianchao Wang switch (dev->ctrl.state) { 1305ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1306ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1307b2a0eb1aSKeith Busch return false; 1308ad70062cSJianchao Wang default: 1309ad70062cSJianchao Wang break; 1310ad70062cSJianchao Wang } 1311b2a0eb1aSKeith Busch 1312b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1313b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1314b2a0eb1aSKeith Busch */ 1315b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1316b2a0eb1aSKeith Busch return false; 1317b2a0eb1aSKeith Busch 1318b2a0eb1aSKeith Busch return true; 1319b2a0eb1aSKeith Busch } 1320b2a0eb1aSKeith Busch 1321b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1322b2a0eb1aSKeith Busch { 1323b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1324b2a0eb1aSKeith Busch u16 pci_status; 1325b2a0eb1aSKeith Busch int result; 1326b2a0eb1aSKeith Busch 1327b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1328b2a0eb1aSKeith Busch &pci_status); 1329b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1330b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1331b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1332b2a0eb1aSKeith Busch csts, pci_status); 1333b2a0eb1aSKeith Busch else 1334b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1335b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1336b2a0eb1aSKeith Busch csts, result); 13374641a8e6SKeith Busch 13384641a8e6SKeith Busch if (csts != ~0) 13394641a8e6SKeith Busch return; 13404641a8e6SKeith Busch 13414641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13424641a8e6SKeith Busch "Does your device have a faulty power saving mode enabled?\n"); 13434641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13444641a8e6SKeith Busch "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1345b2a0eb1aSKeith Busch } 1346b2a0eb1aSKeith Busch 13479bdb4833SJohn Garry static enum blk_eh_timer_return nvme_timeout(struct request *req) 134857dacad5SJay Sternberg { 1349f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1350f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 135157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 135257dacad5SJay Sternberg struct request *abort_req; 1353f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1354b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1355b2a0eb1aSKeith Busch 1356651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1357651438bbSWen Xiong * the recovery mechanism will surely fail. 1358651438bbSWen Xiong */ 1359651438bbSWen Xiong mb(); 1360651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1361651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1362651438bbSWen Xiong 1363b2a0eb1aSKeith Busch /* 1364b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1365b2a0eb1aSKeith Busch */ 1366b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1367b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1368b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1369d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1370db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1371b2a0eb1aSKeith Busch } 137257dacad5SJay Sternberg 137331c7c7d2SChristoph Hellwig /* 13747776db1cSKeith Busch * Did we miss an interrupt? 13757776db1cSKeith Busch */ 1376fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13775a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1378fa059b85SKeith Busch else 1379bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1380fa059b85SKeith Busch 1381bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 13827776db1cSKeith Busch dev_warn(dev->ctrl.device, 13837776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13847776db1cSKeith Busch req->tag, nvmeq->qid); 1385db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13867776db1cSKeith Busch } 13877776db1cSKeith Busch 13887776db1cSKeith Busch /* 1389fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1390fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1391fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1392db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1393fd634f41SChristoph Hellwig */ 13944244140dSKeith Busch switch (dev->ctrl.state) { 13954244140dSKeith Busch case NVME_CTRL_CONNECTING: 13962036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1397df561f66SGustavo A. R. Silva fallthrough; 13982036f726SKeith Busch case NVME_CTRL_DELETING: 1399b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1400fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1401fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 140227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 14037ad92f65STong Zhang nvme_dev_disable(dev, true); 1404db8c48e4SChristoph Hellwig return BLK_EH_DONE; 140539a9dd81SKeith Busch case NVME_CTRL_RESETTING: 140639a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 14074244140dSKeith Busch default: 14084244140dSKeith Busch break; 1409fd634f41SChristoph Hellwig } 1410fd634f41SChristoph Hellwig 1411fd634f41SChristoph Hellwig /* 1412e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1413e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1414e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 141531c7c7d2SChristoph Hellwig */ 1416f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 14171b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 141857dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 141957dacad5SJay Sternberg req->tag, nvmeq->qid); 14207ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1421a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1422d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1423e1569a16SKeith Busch 1424db8c48e4SChristoph Hellwig return BLK_EH_DONE; 142557dacad5SJay Sternberg } 142657dacad5SJay Sternberg 1427e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1428e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1429e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1430e7a2a87dSChristoph Hellwig } 14317bf7d778SKeith Busch iod->aborted = 1; 143257dacad5SJay Sternberg 143357dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 143485f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 143557dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 143657dacad5SJay Sternberg 14371b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 14381b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 143957dacad5SJay Sternberg req->tag, nvmeq->qid); 1440e7a2a87dSChristoph Hellwig 1441e559398fSChristoph Hellwig abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 144239dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 14436bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 14446bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 144531c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 144657dacad5SJay Sternberg } 1447e559398fSChristoph Hellwig nvme_init_request(abort_req, &cmd); 144857dacad5SJay Sternberg 1449e2e53086SChristoph Hellwig abort_req->end_io = abort_endio; 1450e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1451128126a7SChaitanya Kulkarni abort_req->rq_flags |= RQF_QUIET; 1452e2e53086SChristoph Hellwig blk_execute_rq_nowait(abort_req, false); 145357dacad5SJay Sternberg 145457dacad5SJay Sternberg /* 145557dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 145657dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 145757dacad5SJay Sternberg * as the device then is in a faulty state. 145857dacad5SJay Sternberg */ 145957dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 146057dacad5SJay Sternberg } 146157dacad5SJay Sternberg 146257dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 146357dacad5SJay Sternberg { 14648a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 146557dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 146663223078SChristoph Hellwig if (!nvmeq->sq_cmds) 146763223078SChristoph Hellwig return; 14680f238ff5SLogan Gunthorpe 146963223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 147088a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14718a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 147263223078SChristoph Hellwig } else { 14738a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 147463223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14750f238ff5SLogan Gunthorpe } 147657dacad5SJay Sternberg } 147757dacad5SJay Sternberg 147857dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 147957dacad5SJay Sternberg { 148057dacad5SJay Sternberg int i; 148157dacad5SJay Sternberg 1482d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1483d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1484147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 148557dacad5SJay Sternberg } 148657dacad5SJay Sternberg } 148757dacad5SJay Sternberg 148857dacad5SJay Sternberg /** 148957dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 149040581d1aSBart Van Assche * @nvmeq: queue to suspend 149157dacad5SJay Sternberg */ 149257dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 149357dacad5SJay Sternberg { 14944e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 149557dacad5SJay Sternberg return 1; 149657dacad5SJay Sternberg 14974e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1498d1f06f4aSJens Axboe mb(); 149957dacad5SJay Sternberg 15004e224106SChristoph Hellwig nvmeq->dev->online_queues--; 15011c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 15026ca1d902SMing Lei nvme_stop_admin_queue(&nvmeq->dev->ctrl); 15037c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 15044e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 150557dacad5SJay Sternberg return 0; 150657dacad5SJay Sternberg } 150757dacad5SJay Sternberg 15088fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 15098fae268bSKeith Busch { 15108fae268bSKeith Busch int i; 15118fae268bSKeith Busch 15128fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 15138fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 15148fae268bSKeith Busch } 15158fae268bSKeith Busch 1516a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 151757dacad5SJay Sternberg { 1518147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 151957dacad5SJay Sternberg 1520a5cdb68cSKeith Busch if (shutdown) 1521a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1522a5cdb68cSKeith Busch else 1523b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 152457dacad5SJay Sternberg 1525bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 152657dacad5SJay Sternberg } 152757dacad5SJay Sternberg 1528fa46c6fbSKeith Busch /* 1529fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 15309210c075SDongli Zhang * that can check this device's completion queues have synced, except 15319210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 15329210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1533fa46c6fbSKeith Busch */ 1534fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1535fa46c6fbSKeith Busch { 1536fa46c6fbSKeith Busch int i; 1537fa46c6fbSKeith Busch 15389210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 15399210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1540c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 15419210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 15429210c075SDongli Zhang } 1543fa46c6fbSKeith Busch } 1544fa46c6fbSKeith Busch 154557dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 154657dacad5SJay Sternberg int entry_size) 154757dacad5SJay Sternberg { 154857dacad5SJay Sternberg int q_depth = dev->q_depth; 15495fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 15506c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 155157dacad5SJay Sternberg 155257dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 155357dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 15544e523547SBaolin Wang 15556c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 155657dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 155757dacad5SJay Sternberg 155857dacad5SJay Sternberg /* 155957dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 156057dacad5SJay Sternberg * would be better to map queues in system memory with the 156157dacad5SJay Sternberg * original depth 156257dacad5SJay Sternberg */ 156357dacad5SJay Sternberg if (q_depth < 64) 156457dacad5SJay Sternberg return -ENOMEM; 156557dacad5SJay Sternberg } 156657dacad5SJay Sternberg 156757dacad5SJay Sternberg return q_depth; 156857dacad5SJay Sternberg } 156957dacad5SJay Sternberg 157057dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 15718a1d09a6SBenjamin Herrenschmidt int qid) 157257dacad5SJay Sternberg { 15730f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1574815c6704SKeith Busch 15750f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 15768a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1577bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15780f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15790f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 158063223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 158163223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 158263223078SChristoph Hellwig return 0; 158363223078SChristoph Hellwig } 1584bfac8e9fSAlan Mikhak 15858a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1586bfac8e9fSAlan Mikhak } 15870f238ff5SLogan Gunthorpe } 15880f238ff5SLogan Gunthorpe 15898a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 159057dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 159157dacad5SJay Sternberg if (!nvmeq->sq_cmds) 159257dacad5SJay Sternberg return -ENOMEM; 159357dacad5SJay Sternberg return 0; 159457dacad5SJay Sternberg } 159557dacad5SJay Sternberg 1596a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 159757dacad5SJay Sternberg { 1598147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 159957dacad5SJay Sternberg 160062314e40SKeith Busch if (dev->ctrl.queue_count > qid) 160162314e40SKeith Busch return 0; 160257dacad5SJay Sternberg 1603c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 16048a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 16058a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 160657dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 160757dacad5SJay Sternberg if (!nvmeq->cqes) 160857dacad5SJay Sternberg goto free_nvmeq; 160957dacad5SJay Sternberg 16108a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 161157dacad5SJay Sternberg goto free_cqdma; 161257dacad5SJay Sternberg 161357dacad5SJay Sternberg nvmeq->dev = dev; 16141ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 16153a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 161657dacad5SJay Sternberg nvmeq->cq_head = 0; 161757dacad5SJay Sternberg nvmeq->cq_phase = 1; 161857dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 161957dacad5SJay Sternberg nvmeq->qid = qid; 1620d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 162157dacad5SJay Sternberg 1622147b27e4SSagi Grimberg return 0; 162357dacad5SJay Sternberg 162457dacad5SJay Sternberg free_cqdma: 16258a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 162657dacad5SJay Sternberg nvmeq->cq_dma_addr); 162757dacad5SJay Sternberg free_nvmeq: 1628147b27e4SSagi Grimberg return -ENOMEM; 162957dacad5SJay Sternberg } 163057dacad5SJay Sternberg 1631dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 163257dacad5SJay Sternberg { 16330ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 16340ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 16350ff199cbSChristoph Hellwig 16360ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 16370ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 16380ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16390ff199cbSChristoph Hellwig } else { 16400ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 16410ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16420ff199cbSChristoph Hellwig } 164357dacad5SJay Sternberg } 164457dacad5SJay Sternberg 164557dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 164657dacad5SJay Sternberg { 164757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 164857dacad5SJay Sternberg 164957dacad5SJay Sternberg nvmeq->sq_tail = 0; 165038210800SKeith Busch nvmeq->last_sq_tail = 0; 165157dacad5SJay Sternberg nvmeq->cq_head = 0; 165257dacad5SJay Sternberg nvmeq->cq_phase = 1; 165357dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 16548a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1655f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 165657dacad5SJay Sternberg dev->online_queues++; 16573a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 165857dacad5SJay Sternberg } 165957dacad5SJay Sternberg 1660e4b9852aSCasey Chen /* 1661e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1662e4b9852aSCasey Chen */ 1663e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1664e4b9852aSCasey Chen { 1665e4b9852aSCasey Chen /* 1666e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1667e4b9852aSCasey Chen */ 1668e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1669e4b9852aSCasey Chen return -ENODEV; 1670e4b9852aSCasey Chen 1671e4b9852aSCasey Chen /* 1672e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1673e4b9852aSCasey Chen */ 1674e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1675e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1676e4b9852aSCasey Chen return -ENODEV; 1677e4b9852aSCasey Chen } 1678e4b9852aSCasey Chen 1679e4b9852aSCasey Chen return 0; 1680e4b9852aSCasey Chen } 1681e4b9852aSCasey Chen 16824b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 168357dacad5SJay Sternberg { 168457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 168557dacad5SJay Sternberg int result; 16867c349ddeSKeith Busch u16 vector = 0; 168757dacad5SJay Sternberg 1688d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1689d1ed6aa1SChristoph Hellwig 169022b55601SKeith Busch /* 169122b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 169222b55601SKeith Busch * has only one vector available. 169322b55601SKeith Busch */ 16944b04cc6aSJens Axboe if (!polled) 1695a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16964b04cc6aSJens Axboe else 16977c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16984b04cc6aSJens Axboe 1699a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1700ded45505SKeith Busch if (result) 1701ded45505SKeith Busch return result; 170257dacad5SJay Sternberg 170357dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 170457dacad5SJay Sternberg if (result < 0) 1705ded45505SKeith Busch return result; 1706c80b36cdSEdmund Nadolski if (result) 170757dacad5SJay Sternberg goto release_cq; 170857dacad5SJay Sternberg 1709a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 17104b04cc6aSJens Axboe 1711e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1712e4b9852aSCasey Chen if (result) 1713e4b9852aSCasey Chen return result; 1714e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 17157c349ddeSKeith Busch if (!polled) { 1716dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 171757dacad5SJay Sternberg if (result < 0) 171857dacad5SJay Sternberg goto release_sq; 17194b04cc6aSJens Axboe } 172057dacad5SJay Sternberg 17214e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1722e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 172357dacad5SJay Sternberg return result; 172457dacad5SJay Sternberg 172557dacad5SJay Sternberg release_sq: 1726f25a2dfcSJianchao Wang dev->online_queues--; 1727e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 172857dacad5SJay Sternberg adapter_delete_sq(dev, qid); 172957dacad5SJay Sternberg release_cq: 173057dacad5SJay Sternberg adapter_delete_cq(dev, qid); 173157dacad5SJay Sternberg return result; 173257dacad5SJay Sternberg } 173357dacad5SJay Sternberg 1734f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 173557dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 173677f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 173757dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 1738e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 173957dacad5SJay Sternberg .timeout = nvme_timeout, 174057dacad5SJay Sternberg }; 174157dacad5SJay Sternberg 1742f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1743376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1744d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1745376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1746376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1747376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1748e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 1749376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1750376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1751c6d962aeSChristoph Hellwig .poll = nvme_poll, 1752dabcefabSJens Axboe }; 1753dabcefabSJens Axboe 175457dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 175557dacad5SJay Sternberg { 17561c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 175769d9a99cSKeith Busch /* 175869d9a99cSKeith Busch * If the controller was reset during removal, it's possible 175969d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 176069d9a99cSKeith Busch * queue to flush these to completion. 176169d9a99cSKeith Busch */ 17626ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 17636f8191fdSChristoph Hellwig blk_mq_destroy_queue(dev->ctrl.admin_q); 176457dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 176557dacad5SJay Sternberg } 176657dacad5SJay Sternberg } 176757dacad5SJay Sternberg 176857dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 176957dacad5SJay Sternberg { 17701c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 177157dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 177257dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1773e3e9d50cSKeith Busch 177438dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1775dc96f938SChaitanya Kulkarni dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; 1776d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1777d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1778d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 177957dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 178057dacad5SJay Sternberg 178157dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 178257dacad5SJay Sternberg return -ENOMEM; 178334b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 178457dacad5SJay Sternberg 17851c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 17861c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 178757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 1788da427611SSmith, Kyle Miller (Nimble Kernel) dev->ctrl.admin_q = NULL; 178957dacad5SJay Sternberg return -ENOMEM; 179057dacad5SJay Sternberg } 17911c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 179257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 17931c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 179457dacad5SJay Sternberg return -ENODEV; 179557dacad5SJay Sternberg } 179657dacad5SJay Sternberg } else 17976ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 179857dacad5SJay Sternberg 179957dacad5SJay Sternberg return 0; 180057dacad5SJay Sternberg } 180157dacad5SJay Sternberg 180297f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 180397f6ef64SXu Yu { 180497f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 180597f6ef64SXu Yu } 180697f6ef64SXu Yu 180797f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 180897f6ef64SXu Yu { 180997f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 181097f6ef64SXu Yu 181197f6ef64SXu Yu if (size <= dev->bar_mapped_size) 181297f6ef64SXu Yu return 0; 181397f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 181497f6ef64SXu Yu return -ENOMEM; 181597f6ef64SXu Yu if (dev->bar) 181697f6ef64SXu Yu iounmap(dev->bar); 181797f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 181897f6ef64SXu Yu if (!dev->bar) { 181997f6ef64SXu Yu dev->bar_mapped_size = 0; 182097f6ef64SXu Yu return -ENOMEM; 182197f6ef64SXu Yu } 182297f6ef64SXu Yu dev->bar_mapped_size = size; 182397f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 182497f6ef64SXu Yu 182597f6ef64SXu Yu return 0; 182697f6ef64SXu Yu } 182797f6ef64SXu Yu 182801ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 182957dacad5SJay Sternberg { 183057dacad5SJay Sternberg int result; 183157dacad5SJay Sternberg u32 aqa; 183257dacad5SJay Sternberg struct nvme_queue *nvmeq; 183357dacad5SJay Sternberg 183497f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 183597f6ef64SXu Yu if (result < 0) 183697f6ef64SXu Yu return result; 183797f6ef64SXu Yu 18388ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 183920d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 184057dacad5SJay Sternberg 18417a67cbeaSChristoph Hellwig if (dev->subsystem && 18427a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 18437a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 184457dacad5SJay Sternberg 1845b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 184657dacad5SJay Sternberg if (result < 0) 184757dacad5SJay Sternberg return result; 184857dacad5SJay Sternberg 1849a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1850147b27e4SSagi Grimberg if (result) 1851147b27e4SSagi Grimberg return result; 185257dacad5SJay Sternberg 1853635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1854635333e4SMax Gurtovoy 1855147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 185657dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 185757dacad5SJay Sternberg aqa |= aqa << 16; 185857dacad5SJay Sternberg 18597a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 18607a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 18617a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 186257dacad5SJay Sternberg 1863c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 186457dacad5SJay Sternberg if (result) 1865d4875622SKeith Busch return result; 186657dacad5SJay Sternberg 186757dacad5SJay Sternberg nvmeq->cq_vector = 0; 1868161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1869dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 187057dacad5SJay Sternberg if (result) { 18717c349ddeSKeith Busch dev->online_queues--; 1872d4875622SKeith Busch return result; 187357dacad5SJay Sternberg } 187457dacad5SJay Sternberg 18754e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 187657dacad5SJay Sternberg return result; 187757dacad5SJay Sternberg } 187857dacad5SJay Sternberg 1879749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 188057dacad5SJay Sternberg { 18814b04cc6aSJens Axboe unsigned i, max, rw_queues; 1882749941f2SChristoph Hellwig int ret = 0; 188357dacad5SJay Sternberg 1884d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1885a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1886749941f2SChristoph Hellwig ret = -ENOMEM; 188757dacad5SJay Sternberg break; 1888749941f2SChristoph Hellwig } 1889749941f2SChristoph Hellwig } 189057dacad5SJay Sternberg 1891d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1892e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1893e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1894e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 18954b04cc6aSJens Axboe } else { 18964b04cc6aSJens Axboe rw_queues = max; 18974b04cc6aSJens Axboe } 18984b04cc6aSJens Axboe 1899949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 19004b04cc6aSJens Axboe bool polled = i > rw_queues; 19014b04cc6aSJens Axboe 19024b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1903d4875622SKeith Busch if (ret) 190457dacad5SJay Sternberg break; 190557dacad5SJay Sternberg } 190657dacad5SJay Sternberg 1907749941f2SChristoph Hellwig /* 1908749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 19098adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 19108adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1911749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1912749941f2SChristoph Hellwig */ 1913749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 191457dacad5SJay Sternberg } 191557dacad5SJay Sternberg 191688de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 191757dacad5SJay Sternberg { 191888de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 191988de4598SChristoph Hellwig 192088de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 192188de4598SChristoph Hellwig } 192288de4598SChristoph Hellwig 192388de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 192488de4598SChristoph Hellwig { 192588de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 192688de4598SChristoph Hellwig } 192788de4598SChristoph Hellwig 1928f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 192957dacad5SJay Sternberg { 193088de4598SChristoph Hellwig u64 size, offset; 193157dacad5SJay Sternberg resource_size_t bar_size; 193257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 19338969f1f8SChristoph Hellwig int bar; 193457dacad5SJay Sternberg 19359fe5c59fSKeith Busch if (dev->cmb_size) 19369fe5c59fSKeith Busch return; 19379fe5c59fSKeith Busch 193820d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 193920d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 194020d3bb92SKlaus Jensen 19417a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1942f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1943f65efd6dSChristoph Hellwig return; 1944202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 194557dacad5SJay Sternberg 194688de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 194788de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 19488969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 19498969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 195057dacad5SJay Sternberg 195157dacad5SJay Sternberg if (offset > bar_size) 1952f65efd6dSChristoph Hellwig return; 195357dacad5SJay Sternberg 195457dacad5SJay Sternberg /* 195520d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 195620d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 195720d3bb92SKlaus Jensen */ 195820d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 195920d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 196020d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 196120d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 196220d3bb92SKlaus Jensen } 196320d3bb92SKlaus Jensen 196420d3bb92SKlaus Jensen /* 196557dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 196657dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 196757dacad5SJay Sternberg * the reported size of the BAR 196857dacad5SJay Sternberg */ 196957dacad5SJay Sternberg if (size > bar_size - offset) 197057dacad5SJay Sternberg size = bar_size - offset; 197157dacad5SJay Sternberg 19720f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 19730f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 19740f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1975f65efd6dSChristoph Hellwig return; 19760f238ff5SLogan Gunthorpe } 19770f238ff5SLogan Gunthorpe 197857dacad5SJay Sternberg dev->cmb_size = size; 19790f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 19800f238ff5SLogan Gunthorpe 19810f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 19820f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 19830f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 198457dacad5SJay Sternberg } 198557dacad5SJay Sternberg 198687ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 198757dacad5SJay Sternberg { 19886c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19894033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1990f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 199187ad72a5SChristoph Hellwig int ret; 199287ad72a5SChristoph Hellwig 199387ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 199487ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 199587ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19966c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 199787ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 199887ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 199987ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 200087ad72a5SChristoph Hellwig 200187ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 200287ad72a5SChristoph Hellwig if (ret) { 200387ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 200487ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 200587ad72a5SChristoph Hellwig ret, bits); 2006a5df5e79SKeith Busch } else 2007a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 2008a5df5e79SKeith Busch 200987ad72a5SChristoph Hellwig return ret; 201087ad72a5SChristoph Hellwig } 201187ad72a5SChristoph Hellwig 201287ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 201387ad72a5SChristoph Hellwig { 201487ad72a5SChristoph Hellwig int i; 201587ad72a5SChristoph Hellwig 201687ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 201787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 20186c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 201987ad72a5SChristoph Hellwig 2020cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 2021cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 2022cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 202387ad72a5SChristoph Hellwig } 202487ad72a5SChristoph Hellwig 202587ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 202687ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 20274033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 20284033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 20294033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 203087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 20317e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 203287ad72a5SChristoph Hellwig } 203387ad72a5SChristoph Hellwig 203492dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 203592dc6895SChristoph Hellwig u32 chunk_size) 203687ad72a5SChristoph Hellwig { 203787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 203892dc6895SChristoph Hellwig u32 max_entries, len; 20394033f35dSChristoph Hellwig dma_addr_t descs_dma; 20402ee0e4edSDan Carpenter int i = 0; 204187ad72a5SChristoph Hellwig void **bufs; 20426fbcde66SMinwoo Im u64 size, tmp; 204387ad72a5SChristoph Hellwig 204487ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 204587ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 204687ad72a5SChristoph Hellwig max_entries = tmp; 2047044a9df1SChristoph Hellwig 2048044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2049044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 2050044a9df1SChristoph Hellwig 2051750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 20524033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 205387ad72a5SChristoph Hellwig if (!descs) 205487ad72a5SChristoph Hellwig goto out; 205587ad72a5SChristoph Hellwig 205687ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 205787ad72a5SChristoph Hellwig if (!bufs) 205887ad72a5SChristoph Hellwig goto out_free_descs; 205987ad72a5SChristoph Hellwig 2060244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 206187ad72a5SChristoph Hellwig dma_addr_t dma_addr; 206287ad72a5SChristoph Hellwig 206350cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 206487ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 206587ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 206687ad72a5SChristoph Hellwig if (!bufs[i]) 206787ad72a5SChristoph Hellwig break; 206887ad72a5SChristoph Hellwig 206987ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 20706c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 207187ad72a5SChristoph Hellwig i++; 207287ad72a5SChristoph Hellwig } 207387ad72a5SChristoph Hellwig 207492dc6895SChristoph Hellwig if (!size) 207587ad72a5SChristoph Hellwig goto out_free_bufs; 207687ad72a5SChristoph Hellwig 207787ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 207887ad72a5SChristoph Hellwig dev->host_mem_size = size; 207987ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 20804033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 208187ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 208287ad72a5SChristoph Hellwig return 0; 208387ad72a5SChristoph Hellwig 208487ad72a5SChristoph Hellwig out_free_bufs: 208587ad72a5SChristoph Hellwig while (--i >= 0) { 20866c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 208787ad72a5SChristoph Hellwig 2088cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2089cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2090cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 209187ad72a5SChristoph Hellwig } 209287ad72a5SChristoph Hellwig 209387ad72a5SChristoph Hellwig kfree(bufs); 209487ad72a5SChristoph Hellwig out_free_descs: 20954033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20964033f35dSChristoph Hellwig descs_dma); 209787ad72a5SChristoph Hellwig out: 209887ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 209987ad72a5SChristoph Hellwig return -ENOMEM; 210087ad72a5SChristoph Hellwig } 210187ad72a5SChristoph Hellwig 210292dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 210392dc6895SChristoph Hellwig { 21049dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 21059dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 21069dc54a0dSChaitanya Kulkarni u64 chunk_size; 210792dc6895SChristoph Hellwig 210892dc6895SChristoph Hellwig /* start big and work our way down */ 21099dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 211092dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 211192dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 211292dc6895SChristoph Hellwig return 0; 211392dc6895SChristoph Hellwig nvme_free_host_mem(dev); 211492dc6895SChristoph Hellwig } 211592dc6895SChristoph Hellwig } 211692dc6895SChristoph Hellwig 211792dc6895SChristoph Hellwig return -ENOMEM; 211892dc6895SChristoph Hellwig } 211992dc6895SChristoph Hellwig 21209620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 212187ad72a5SChristoph Hellwig { 212287ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 212387ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 212487ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 212587ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 21266fbcde66SMinwoo Im int ret; 212787ad72a5SChristoph Hellwig 212887ad72a5SChristoph Hellwig preferred = min(preferred, max); 212987ad72a5SChristoph Hellwig if (min > max) { 213087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 213187ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 213287ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 213387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21349620cfbaSChristoph Hellwig return 0; 213587ad72a5SChristoph Hellwig } 213687ad72a5SChristoph Hellwig 213787ad72a5SChristoph Hellwig /* 213887ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 213987ad72a5SChristoph Hellwig */ 214087ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 214187ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 214287ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 214387ad72a5SChristoph Hellwig else 214487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 214587ad72a5SChristoph Hellwig } 214687ad72a5SChristoph Hellwig 214787ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 214892dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 214992dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 215092dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 21519620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 215287ad72a5SChristoph Hellwig } 215387ad72a5SChristoph Hellwig 215492dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 215592dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 215692dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 215792dc6895SChristoph Hellwig } 215892dc6895SChristoph Hellwig 21599620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 21609620cfbaSChristoph Hellwig if (ret) 216187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21629620cfbaSChristoph Hellwig return ret; 216357dacad5SJay Sternberg } 216457dacad5SJay Sternberg 21650521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 21660521905eSKeith Busch char *buf) 21670521905eSKeith Busch { 21680521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21690521905eSKeith Busch 21700521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 21710521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 21720521905eSKeith Busch } 21730521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 21740521905eSKeith Busch 21751751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 21761751e97aSKeith Busch char *buf) 21771751e97aSKeith Busch { 21781751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21791751e97aSKeith Busch 21801751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 21811751e97aSKeith Busch } 21821751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 21831751e97aSKeith Busch 21841751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 21851751e97aSKeith Busch char *buf) 21861751e97aSKeith Busch { 21871751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21881751e97aSKeith Busch 21891751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 21901751e97aSKeith Busch } 21911751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 21921751e97aSKeith Busch 2193a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2194a5df5e79SKeith Busch char *buf) 2195a5df5e79SKeith Busch { 2196a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2197a5df5e79SKeith Busch 2198a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2199a5df5e79SKeith Busch } 2200a5df5e79SKeith Busch 2201a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2202a5df5e79SKeith Busch const char *buf, size_t count) 2203a5df5e79SKeith Busch { 2204a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2205a5df5e79SKeith Busch bool new; 2206a5df5e79SKeith Busch int ret; 2207a5df5e79SKeith Busch 2208a5df5e79SKeith Busch if (strtobool(buf, &new) < 0) 2209a5df5e79SKeith Busch return -EINVAL; 2210a5df5e79SKeith Busch 2211a5df5e79SKeith Busch if (new == ndev->hmb) 2212a5df5e79SKeith Busch return count; 2213a5df5e79SKeith Busch 2214a5df5e79SKeith Busch if (new) { 2215a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2216a5df5e79SKeith Busch } else { 2217a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2218a5df5e79SKeith Busch if (!ret) 2219a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2220a5df5e79SKeith Busch } 2221a5df5e79SKeith Busch 2222a5df5e79SKeith Busch if (ret < 0) 2223a5df5e79SKeith Busch return ret; 2224a5df5e79SKeith Busch 2225a5df5e79SKeith Busch return count; 2226a5df5e79SKeith Busch } 2227a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2228a5df5e79SKeith Busch 22290521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 22300521905eSKeith Busch struct attribute *a, int n) 22310521905eSKeith Busch { 22320521905eSKeith Busch struct nvme_ctrl *ctrl = 22330521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 22340521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 22350521905eSKeith Busch 22361751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 22371751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 22381751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 22391751e97aSKeith Busch if (!dev->cmbsz) 22400521905eSKeith Busch return 0; 22411751e97aSKeith Busch } 2242a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2243a5df5e79SKeith Busch return 0; 2244a5df5e79SKeith Busch 22450521905eSKeith Busch return a->mode; 22460521905eSKeith Busch } 22470521905eSKeith Busch 22480521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 22490521905eSKeith Busch &dev_attr_cmb.attr, 22501751e97aSKeith Busch &dev_attr_cmbloc.attr, 22511751e97aSKeith Busch &dev_attr_cmbsz.attr, 2252a5df5e79SKeith Busch &dev_attr_hmb.attr, 22530521905eSKeith Busch NULL, 22540521905eSKeith Busch }; 22550521905eSKeith Busch 22560521905eSKeith Busch static const struct attribute_group nvme_pci_attr_group = { 22570521905eSKeith Busch .attrs = nvme_pci_attrs, 22580521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 22590521905eSKeith Busch }; 22600521905eSKeith Busch 2261612b7286SMing Lei /* 2262612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2263612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2264612b7286SMing Lei */ 2265612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 22663b6592f7SJens Axboe { 2267612b7286SMing Lei struct nvme_dev *dev = affd->priv; 22682a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2269c45b1fa2SMing Lei 22703b6592f7SJens Axboe /* 2271ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2272612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2273612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2274612b7286SMing Lei * 2275612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2276612b7286SMing Lei * write and read queues. 2277612b7286SMing Lei * 2278612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2279612b7286SMing Lei * queue. 22803b6592f7SJens Axboe */ 2281612b7286SMing Lei if (!nrirqs) { 2282612b7286SMing Lei nrirqs = 1; 2283612b7286SMing Lei nr_read_queues = 0; 22842a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2285612b7286SMing Lei nr_read_queues = 0; 22862a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2287612b7286SMing Lei nr_read_queues = 1; 22883b6592f7SJens Axboe } else { 22892a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22903b6592f7SJens Axboe } 2291612b7286SMing Lei 2292612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2293612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2294612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2295612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2296612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22973b6592f7SJens Axboe } 22983b6592f7SJens Axboe 22996451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 23003b6592f7SJens Axboe { 23013b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 23023b6592f7SJens Axboe struct irq_affinity affd = { 23033b6592f7SJens Axboe .pre_vectors = 1, 2304612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2305612b7286SMing Lei .priv = dev, 23063b6592f7SJens Axboe }; 230721cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 23086451fe73SJens Axboe 23096451fe73SJens Axboe /* 231021cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 231121cc2f3fSJeffle Xu * left over for non-polled I/O. 23126451fe73SJens Axboe */ 231321cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 231421cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 23153b6592f7SJens Axboe 231621cc2f3fSJeffle Xu /* 231721cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 231821cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 231921cc2f3fSJeffle Xu */ 2320612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2321612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 23223b6592f7SJens Axboe 232366341331SBenjamin Herrenschmidt /* 232421cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 232521cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 232621cc2f3fSJeffle Xu * vector. 232766341331SBenjamin Herrenschmidt */ 232866341331SBenjamin Herrenschmidt irq_queues = 1; 232921cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 233021cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2331612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 23323b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 23333b6592f7SJens Axboe } 23343b6592f7SJens Axboe 23358fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 23368fae268bSKeith Busch { 23378fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 23388fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 23398fae268bSKeith Busch } 23408fae268bSKeith Busch 23412a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 23422a5bcfddSWeiping Zhang { 2343e3aef095SNiklas Schnelle /* 2344e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2345e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2346e3aef095SNiklas Schnelle */ 2347e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2348e3aef095SNiklas Schnelle return 1; 23492a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 23502a5bcfddSWeiping Zhang } 23512a5bcfddSWeiping Zhang 235257dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 235357dacad5SJay Sternberg { 2354147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 235557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 23562a5bcfddSWeiping Zhang unsigned int nr_io_queues; 235797f6ef64SXu Yu unsigned long size; 23582a5bcfddSWeiping Zhang int result; 235957dacad5SJay Sternberg 23602a5bcfddSWeiping Zhang /* 23612a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 23622a5bcfddSWeiping Zhang * stable values to work with. 23632a5bcfddSWeiping Zhang */ 23642a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 23652a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2366d38e9f04SBenjamin Herrenschmidt 2367ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 23689a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 23699a0be7abSChristoph Hellwig if (result < 0) 237057dacad5SJay Sternberg return result; 23719a0be7abSChristoph Hellwig 2372f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2373a5229050SKeith Busch return 0; 237457dacad5SJay Sternberg 2375e4b9852aSCasey Chen /* 2376e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2377e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2378e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2379e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2380e4b9852aSCasey Chen * nvme_dev_disable() path. 2381e4b9852aSCasey Chen */ 2382e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2383e4b9852aSCasey Chen if (result) 2384e4b9852aSCasey Chen return result; 2385e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2386e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 23874e224106SChristoph Hellwig 23880f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 238957dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 239057dacad5SJay Sternberg sizeof(struct nvme_command)); 239157dacad5SJay Sternberg if (result > 0) 239257dacad5SJay Sternberg dev->q_depth = result; 239357dacad5SJay Sternberg else 23940f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 239557dacad5SJay Sternberg } 239657dacad5SJay Sternberg 239757dacad5SJay Sternberg do { 239897f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 239997f6ef64SXu Yu result = nvme_remap_bar(dev, size); 240097f6ef64SXu Yu if (!result) 240157dacad5SJay Sternberg break; 2402e4b9852aSCasey Chen if (!--nr_io_queues) { 2403e4b9852aSCasey Chen result = -ENOMEM; 2404e4b9852aSCasey Chen goto out_unlock; 2405e4b9852aSCasey Chen } 240657dacad5SJay Sternberg } while (1); 240757dacad5SJay Sternberg adminq->q_db = dev->dbs; 240857dacad5SJay Sternberg 24098fae268bSKeith Busch retry: 241057dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2411e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 24120ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 241357dacad5SJay Sternberg 241457dacad5SJay Sternberg /* 241557dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 241657dacad5SJay Sternberg * setting up the full range we need. 241757dacad5SJay Sternberg */ 2418dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 24193b6592f7SJens Axboe 24203b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2421e4b9852aSCasey Chen if (result <= 0) { 2422e4b9852aSCasey Chen result = -EIO; 2423e4b9852aSCasey Chen goto out_unlock; 2424e4b9852aSCasey Chen } 24253b6592f7SJens Axboe 242622b55601SKeith Busch dev->num_vecs = result; 24274b04cc6aSJens Axboe result = max(result - 1, 1); 2428e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 242957dacad5SJay Sternberg 243057dacad5SJay Sternberg /* 243157dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 243257dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 243357dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 243457dacad5SJay Sternberg * number of interrupts. 243557dacad5SJay Sternberg */ 2436dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 24377c349ddeSKeith Busch if (result) 2438e4b9852aSCasey Chen goto out_unlock; 24394e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2440e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 24418fae268bSKeith Busch 24428fae268bSKeith Busch result = nvme_create_io_queues(dev); 24438fae268bSKeith Busch if (result || dev->online_queues < 2) 24448fae268bSKeith Busch return result; 24458fae268bSKeith Busch 24468fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 24478fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 24488fae268bSKeith Busch nvme_disable_io_queues(dev); 2449e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2450e4b9852aSCasey Chen if (result) 2451e4b9852aSCasey Chen return result; 24528fae268bSKeith Busch nvme_suspend_io_queues(dev); 24538fae268bSKeith Busch goto retry; 24548fae268bSKeith Busch } 24558fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 24568fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 24578fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 24588fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 24598fae268bSKeith Busch return 0; 2460e4b9852aSCasey Chen out_unlock: 2461e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2462e4b9852aSCasey Chen return result; 246357dacad5SJay Sternberg } 246457dacad5SJay Sternberg 24652a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2466db3cbfffSKeith Busch { 2467db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2468db3cbfffSKeith Busch 2469db3cbfffSKeith Busch blk_mq_free_request(req); 2470d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2471db3cbfffSKeith Busch } 2472db3cbfffSKeith Busch 24732a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2474db3cbfffSKeith Busch { 2475db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2476db3cbfffSKeith Busch 2477d1ed6aa1SChristoph Hellwig if (error) 2478d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2479db3cbfffSKeith Busch 2480db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2481db3cbfffSKeith Busch } 2482db3cbfffSKeith Busch 2483db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2484db3cbfffSKeith Busch { 2485db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2486db3cbfffSKeith Busch struct request *req; 2487f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2488db3cbfffSKeith Busch 2489db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2490db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2491db3cbfffSKeith Busch 2492e559398fSChristoph Hellwig req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2493db3cbfffSKeith Busch if (IS_ERR(req)) 2494db3cbfffSKeith Busch return PTR_ERR(req); 2495e559398fSChristoph Hellwig nvme_init_request(req, &cmd); 2496db3cbfffSKeith Busch 2497e2e53086SChristoph Hellwig if (opcode == nvme_admin_delete_cq) 2498e2e53086SChristoph Hellwig req->end_io = nvme_del_cq_end; 2499e2e53086SChristoph Hellwig else 2500e2e53086SChristoph Hellwig req->end_io = nvme_del_queue_end; 2501db3cbfffSKeith Busch req->end_io_data = nvmeq; 2502db3cbfffSKeith Busch 2503d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2504128126a7SChaitanya Kulkarni req->rq_flags |= RQF_QUIET; 2505e2e53086SChristoph Hellwig blk_execute_rq_nowait(req, false); 2506db3cbfffSKeith Busch return 0; 2507db3cbfffSKeith Busch } 2508db3cbfffSKeith Busch 25098fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2510db3cbfffSKeith Busch { 25115271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2512db3cbfffSKeith Busch unsigned long timeout; 2513db3cbfffSKeith Busch 2514db3cbfffSKeith Busch retry: 2515dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 25165271edd4SChristoph Hellwig while (nr_queues > 0) { 25175271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2518db3cbfffSKeith Busch break; 25195271edd4SChristoph Hellwig nr_queues--; 25205271edd4SChristoph Hellwig sent++; 25215271edd4SChristoph Hellwig } 2522d1ed6aa1SChristoph Hellwig while (sent) { 2523d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2524d1ed6aa1SChristoph Hellwig 2525d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 25265271edd4SChristoph Hellwig timeout); 2527db3cbfffSKeith Busch if (timeout == 0) 25285271edd4SChristoph Hellwig return false; 2529d1ed6aa1SChristoph Hellwig 2530d1ed6aa1SChristoph Hellwig sent--; 25315271edd4SChristoph Hellwig if (nr_queues) 2532db3cbfffSKeith Busch goto retry; 2533db3cbfffSKeith Busch } 25345271edd4SChristoph Hellwig return true; 2535db3cbfffSKeith Busch } 2536db3cbfffSKeith Busch 25375d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 253857dacad5SJay Sternberg { 25392b1b7e78SJianchao Wang int ret; 25402b1b7e78SJianchao Wang 25415bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2542c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 254357dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 25448fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2545ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2546ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 254757dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2548d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 254961f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 255061f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2551d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 255257dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 255357dacad5SJay Sternberg dev->tagset.driver_data = dev; 255457dacad5SJay Sternberg 2555d38e9f04SBenjamin Herrenschmidt /* 2556d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2557d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2558d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2559d38e9f04SBenjamin Herrenschmidt */ 2560d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2561d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2562d38e9f04SBenjamin Herrenschmidt 25632b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 25642b1b7e78SJianchao Wang if (ret) { 25652b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25662b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 25675d02a5c1SKeith Busch return; 25682b1b7e78SJianchao Wang } 25695bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2570949928c1SKeith Busch } else { 2571949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2572949928c1SKeith Busch 2573949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2574949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 257557dacad5SJay Sternberg } 2576949928c1SKeith Busch 2577e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 257857dacad5SJay Sternberg } 257957dacad5SJay Sternberg 2580b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 258157dacad5SJay Sternberg { 2582b00a726aSKeith Busch int result = -ENOMEM; 258357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 25844bdf2603SFilippo Sironi int dma_address_bits = 64; 258557dacad5SJay Sternberg 258657dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 258757dacad5SJay Sternberg return result; 258857dacad5SJay Sternberg 258957dacad5SJay Sternberg pci_set_master(pdev); 259057dacad5SJay Sternberg 25914bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 25924bdf2603SFilippo Sironi dma_address_bits = 48; 25934bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 259457dacad5SJay Sternberg goto disable; 259557dacad5SJay Sternberg 25967a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 259757dacad5SJay Sternberg result = -ENODEV; 2598b00a726aSKeith Busch goto disable; 259957dacad5SJay Sternberg } 260057dacad5SJay Sternberg 260157dacad5SJay Sternberg /* 2602a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2603a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2604a5229050SKeith Busch * adjust this later. 260557dacad5SJay Sternberg */ 2606dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2607dca51e78SChristoph Hellwig if (result < 0) 2608dca51e78SChristoph Hellwig return result; 260957dacad5SJay Sternberg 261020d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 26117a67cbeaSChristoph Hellwig 26127442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2613b27c1e68Sweiping zhang io_queue_depth); 2614aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 261520d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 26167a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 26171f390c1fSStephan Günther 26181f390c1fSStephan Günther /* 261966341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 262066341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 262166341331SBenjamin Herrenschmidt * so we don't bother updating it here. 262266341331SBenjamin Herrenschmidt */ 262366341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 262466341331SBenjamin Herrenschmidt dev->io_sqes = 7; 262566341331SBenjamin Herrenschmidt else 2626c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 26271f390c1fSStephan Günther 26281f390c1fSStephan Günther /* 26291f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 26301f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 26311f390c1fSStephan Günther */ 26321f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 26331f390c1fSStephan Günther dev->q_depth = 2; 26349bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 26359bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 26361f390c1fSStephan Günther dev->q_depth); 2637d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2638d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 263920d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2640d554b5e1SMartin K. Petersen dev->q_depth = 64; 2641d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2642d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 26431f390c1fSStephan Günther } 26441f390c1fSStephan Günther 2645d38e9f04SBenjamin Herrenschmidt /* 2646d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2647d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2648d38e9f04SBenjamin Herrenschmidt */ 2649d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2650d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2651d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2652d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2653d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2654d38e9f04SBenjamin Herrenschmidt } 2655d38e9f04SBenjamin Herrenschmidt 2656d38e9f04SBenjamin Herrenschmidt 2657f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2658202021c1SStephen Bates 2659a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2660a0a3408eSKeith Busch pci_save_state(pdev); 266157dacad5SJay Sternberg return 0; 266257dacad5SJay Sternberg 266357dacad5SJay Sternberg disable: 266457dacad5SJay Sternberg pci_disable_device(pdev); 266557dacad5SJay Sternberg return result; 266657dacad5SJay Sternberg } 266757dacad5SJay Sternberg 266857dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 266957dacad5SJay Sternberg { 2670b00a726aSKeith Busch if (dev->bar) 2671b00a726aSKeith Busch iounmap(dev->bar); 2672a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2673b00a726aSKeith Busch } 2674b00a726aSKeith Busch 2675b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2676b00a726aSKeith Busch { 267757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 267857dacad5SJay Sternberg 2679dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 268057dacad5SJay Sternberg 2681a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2682a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 268357dacad5SJay Sternberg pci_disable_device(pdev); 268457dacad5SJay Sternberg } 2685a0a3408eSKeith Busch } 268657dacad5SJay Sternberg 2687a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 268857dacad5SJay Sternberg { 2689e43269e6SKeith Busch bool dead = true, freeze = false; 2690302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 269157dacad5SJay Sternberg 269277bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2693081f5e75SKeith Busch if (pci_is_enabled(pdev)) { 2694081f5e75SKeith Busch u32 csts; 2695081f5e75SKeith Busch 2696081f5e75SKeith Busch if (pci_device_is_present(pdev)) 2697081f5e75SKeith Busch csts = readl(dev->bar + NVME_REG_CSTS); 2698081f5e75SKeith Busch else 2699081f5e75SKeith Busch csts = ~0; 2700302ad8ccSKeith Busch 2701ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2702e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2703e43269e6SKeith Busch freeze = true; 2704302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2705e43269e6SKeith Busch } 2706302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2707302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 270857dacad5SJay Sternberg } 2709c21377f8SGabriel Krisman Bertazi 2710302ad8ccSKeith Busch /* 2711302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2712302ad8ccSKeith Busch * doing a safe shutdown. 2713302ad8ccSKeith Busch */ 2714e43269e6SKeith Busch if (!dead && shutdown && freeze) 2715302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 271687ad72a5SChristoph Hellwig 27179a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 27189a915a5bSJianchao Wang 271964ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 27208fae268bSKeith Busch nvme_disable_io_queues(dev); 2721a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 272257dacad5SJay Sternberg } 27238fae268bSKeith Busch nvme_suspend_io_queues(dev); 27248fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2725b00a726aSKeith Busch nvme_pci_disable(dev); 2726fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 272757dacad5SJay Sternberg 2728*1fcfca78SGuixin Liu nvme_cancel_tagset(&dev->ctrl); 2729*1fcfca78SGuixin Liu nvme_cancel_admin_tagset(&dev->ctrl); 2730302ad8ccSKeith Busch 2731302ad8ccSKeith Busch /* 2732302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2733302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2734302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2735302ad8ccSKeith Busch */ 2736c8e9e9b7SKeith Busch if (shutdown) { 2737302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2738c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 27396ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 2740c8e9e9b7SKeith Busch } 274177bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 274257dacad5SJay Sternberg } 274357dacad5SJay Sternberg 2744c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2745c1ac9a4bSKeith Busch { 2746c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2747c1ac9a4bSKeith Busch return -EBUSY; 2748c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2749c1ac9a4bSKeith Busch return 0; 2750c1ac9a4bSKeith Busch } 2751c1ac9a4bSKeith Busch 275257dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 275357dacad5SJay Sternberg { 275457dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2755c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2756c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 275757dacad5SJay Sternberg if (!dev->prp_page_pool) 275857dacad5SJay Sternberg return -ENOMEM; 275957dacad5SJay Sternberg 276057dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 276157dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 276257dacad5SJay Sternberg 256, 256, 0); 276357dacad5SJay Sternberg if (!dev->prp_small_pool) { 276457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 276557dacad5SJay Sternberg return -ENOMEM; 276657dacad5SJay Sternberg } 276757dacad5SJay Sternberg return 0; 276857dacad5SJay Sternberg } 276957dacad5SJay Sternberg 277057dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 277157dacad5SJay Sternberg { 277257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 277357dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 277457dacad5SJay Sternberg } 277557dacad5SJay Sternberg 2776770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2777770597ecSKeith Busch { 2778770597ecSKeith Busch if (dev->tagset.tags) 2779770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2780770597ecSKeith Busch dev->ctrl.tagset = NULL; 2781770597ecSKeith Busch } 2782770597ecSKeith Busch 27831673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 278457dacad5SJay Sternberg { 27851673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 278657dacad5SJay Sternberg 2787f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2788770597ecSKeith Busch nvme_free_tagset(dev); 27891c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 27901c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2791e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2792943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2793253fd4acSIsrael Rukshin put_device(dev->dev); 2794253fd4acSIsrael Rukshin kfree(dev->queues); 279557dacad5SJay Sternberg kfree(dev); 279657dacad5SJay Sternberg } 279757dacad5SJay Sternberg 27987c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2799f58944e2SKeith Busch { 2800c1ac9a4bSKeith Busch /* 2801c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2802c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2803c1ac9a4bSKeith Busch */ 2804c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2805d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 280669d9a99cSKeith Busch nvme_dev_disable(dev, false); 28079f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 280803e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2809f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2810f58944e2SKeith Busch } 2811f58944e2SKeith Busch 2812fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 281357dacad5SJay Sternberg { 2814d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2815d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2816a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2817e71afda4SChaitanya Kulkarni int result; 281857dacad5SJay Sternberg 28197764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 28207764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 28217764656bSZhihao Cheng dev->ctrl.state); 2822e71afda4SChaitanya Kulkarni result = -ENODEV; 2823fd634f41SChristoph Hellwig goto out; 2824e71afda4SChaitanya Kulkarni } 2825fd634f41SChristoph Hellwig 2826fd634f41SChristoph Hellwig /* 2827fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2828fd634f41SChristoph Hellwig * moving on. 2829fd634f41SChristoph Hellwig */ 2830b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2831a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2832d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2833fd634f41SChristoph Hellwig 28345c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2835b00a726aSKeith Busch result = nvme_pci_enable(dev); 283657dacad5SJay Sternberg if (result) 28374726bcf3SKeith Busch goto out_unlock; 283857dacad5SJay Sternberg 283901ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 284057dacad5SJay Sternberg if (result) 28414726bcf3SKeith Busch goto out_unlock; 284257dacad5SJay Sternberg 284357dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 284457dacad5SJay Sternberg if (result) 28454726bcf3SKeith Busch goto out_unlock; 284657dacad5SJay Sternberg 2847943e942eSJens Axboe /* 2848943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2849943e942eSJens Axboe * over a single page. 2850943e942eSJens Axboe */ 28517637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 28527637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2853943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2854a48bc520SChristoph Hellwig 2855a48bc520SChristoph Hellwig /* 2856a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2857a48bc520SChristoph Hellwig */ 2858a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 28593d2d861eSJianxiong Gao dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2860a48bc520SChristoph Hellwig 28615c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 28625c959d73SKeith Busch 28635c959d73SKeith Busch /* 28645c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 28655c959d73SKeith Busch * initializing procedure here. 28665c959d73SKeith Busch */ 28675c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 28685c959d73SKeith Busch dev_warn(dev->ctrl.device, 28695c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2870cee6c269SMinwoo Im result = -EBUSY; 28715c959d73SKeith Busch goto out; 28725c959d73SKeith Busch } 2873943e942eSJens Axboe 287495093350SMax Gurtovoy /* 287595093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 287695093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 287795093350SMax Gurtovoy */ 287895093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 287995093350SMax Gurtovoy 2880f21c4769SChaitanya Kulkarni result = nvme_init_ctrl_finish(&dev->ctrl); 2881ce4541f4SChristoph Hellwig if (result) 2882f58944e2SKeith Busch goto out; 2883ce4541f4SChristoph Hellwig 2884e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2885e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 28864f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 28874f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2888e286bcfcSScott Bauer else if (was_suspend) 28894f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2890e286bcfcSScott Bauer } else { 2891e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2892e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2893e286bcfcSScott Bauer } 2894a98e58e5SScott Bauer 2895f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2896f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2897f9f38e33SHelen Koike if (result) 2898f9f38e33SHelen Koike dev_warn(dev->dev, 2899f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2900f9f38e33SHelen Koike } 2901f9f38e33SHelen Koike 29029620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 29039620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 29049620cfbaSChristoph Hellwig if (result < 0) 29059620cfbaSChristoph Hellwig goto out; 29069620cfbaSChristoph Hellwig } 290787ad72a5SChristoph Hellwig 290857dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 290957dacad5SJay Sternberg if (result) 2910f58944e2SKeith Busch goto out; 291157dacad5SJay Sternberg 291221f033f7SKeith Busch /* 291357dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 291457dacad5SJay Sternberg * any working I/O queue. 291557dacad5SJay Sternberg */ 291657dacad5SJay Sternberg if (dev->online_queues < 2) { 29171b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 29183b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 29195bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2920770597ecSKeith Busch nvme_free_tagset(dev); 292157dacad5SJay Sternberg } else { 292225646264SKeith Busch nvme_start_queues(&dev->ctrl); 2923302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 29245d02a5c1SKeith Busch nvme_dev_add(dev); 2925302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 292657dacad5SJay Sternberg } 292757dacad5SJay Sternberg 29282b1b7e78SJianchao Wang /* 29292b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 29302b1b7e78SJianchao Wang * recovery. 29312b1b7e78SJianchao Wang */ 29325d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 29332b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 29345d02a5c1SKeith Busch "failed to mark controller live state\n"); 2935e71afda4SChaitanya Kulkarni result = -ENODEV; 2936bb8d261eSChristoph Hellwig goto out; 2937bb8d261eSChristoph Hellwig } 293892911a55SChristoph Hellwig 29390521905eSKeith Busch if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, 29400521905eSKeith Busch &nvme_pci_attr_group)) 29410521905eSKeith Busch dev->attrs_added = true; 29420521905eSKeith Busch 2943d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 294457dacad5SJay Sternberg return; 294557dacad5SJay Sternberg 29464726bcf3SKeith Busch out_unlock: 29474726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 294857dacad5SJay Sternberg out: 29497c1ce408SChaitanya Kulkarni if (result) 29507c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 29517c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 29527c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 295357dacad5SJay Sternberg } 295457dacad5SJay Sternberg 29555c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 295657dacad5SJay Sternberg { 29575c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 295857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 295957dacad5SJay Sternberg 296057dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2961921920abSKeith Busch device_release_driver(&pdev->dev); 29621673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 296357dacad5SJay Sternberg } 296457dacad5SJay Sternberg 29651c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 296657dacad5SJay Sternberg { 29671c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 29681c63dc66SChristoph Hellwig return 0; 296957dacad5SJay Sternberg } 29701c63dc66SChristoph Hellwig 29715fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 29725fd4ce1bSChristoph Hellwig { 29735fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 29745fd4ce1bSChristoph Hellwig return 0; 29755fd4ce1bSChristoph Hellwig } 29765fd4ce1bSChristoph Hellwig 29777fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 29787fd8930fSChristoph Hellwig { 29793a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 29807fd8930fSChristoph Hellwig return 0; 29817fd8930fSChristoph Hellwig } 29827fd8930fSChristoph Hellwig 298397c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 298497c12223SKeith Busch { 298597c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 298697c12223SKeith Busch 29872db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 298897c12223SKeith Busch } 298997c12223SKeith Busch 29902f0dad17SKeith Busch 29912f0dad17SKeith Busch static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 29922f0dad17SKeith Busch { 29932f0dad17SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 29942f0dad17SKeith Busch struct nvme_subsystem *subsys = ctrl->subsys; 29952f0dad17SKeith Busch 29962f0dad17SKeith Busch dev_err(ctrl->device, 29972f0dad17SKeith Busch "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 29982f0dad17SKeith Busch pdev->vendor, pdev->device, 29992f0dad17SKeith Busch nvme_strlen(subsys->model, sizeof(subsys->model)), 30002f0dad17SKeith Busch subsys->model, nvme_strlen(subsys->firmware_rev, 30012f0dad17SKeith Busch sizeof(subsys->firmware_rev)), 30022f0dad17SKeith Busch subsys->firmware_rev); 30032f0dad17SKeith Busch } 30042f0dad17SKeith Busch 30051c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 30061a353d85SMing Lin .name = "pcie", 3007e439bb12SSagi Grimberg .module = THIS_MODULE, 3008e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 3009e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 30101c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 30115fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 30127fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 30131673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 3014f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 301597c12223SKeith Busch .get_address = nvme_pci_get_address, 30162f0dad17SKeith Busch .print_device_info = nvme_pci_print_device_info, 30171c63dc66SChristoph Hellwig }; 301857dacad5SJay Sternberg 3019b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 3020b00a726aSKeith Busch { 3021b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 3022b00a726aSKeith Busch 3023a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 3024b00a726aSKeith Busch return -ENODEV; 3025b00a726aSKeith Busch 302697f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 3027b00a726aSKeith Busch goto release; 3028b00a726aSKeith Busch 3029b00a726aSKeith Busch return 0; 3030b00a726aSKeith Busch release: 3031a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 3032b00a726aSKeith Busch return -ENODEV; 3033b00a726aSKeith Busch } 3034b00a726aSKeith Busch 30358427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 3036ff5350a8SAndy Lutomirski { 3037ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 3038ff5350a8SAndy Lutomirski /* 3039ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 3040ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 3041ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 3042ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 3043ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 3044ff5350a8SAndy Lutomirski * laptops. 3045ff5350a8SAndy Lutomirski */ 3046ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 3047ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 3048ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 3049ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 30508427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 30518427bbc2SKai-Heng Feng /* 30528427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 3053467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 3054467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 3055467c77d4SJarosław Janik * ASUS PRIME Z370-A 30568427bbc2SKai-Heng Feng */ 30578427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3058467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3059467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 30608427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 30611fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 30621fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 30631fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 30641fae37acSShyjumon N /* 30651fae37acSShyjumon N * Forcing to use host managed nvme power settings for 30661fae37acSShyjumon N * lowest idle power with quick resume latency on 30671fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 30681fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 30691fae37acSShyjumon N */ 30701fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 30711fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 30721fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 3073ff5350a8SAndy Lutomirski } 3074ff5350a8SAndy Lutomirski 3075ff5350a8SAndy Lutomirski return 0; 3076ff5350a8SAndy Lutomirski } 3077ff5350a8SAndy Lutomirski 307818119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 307918119775SKeith Busch { 308018119775SKeith Busch struct nvme_dev *dev = data; 308180f513b5SKeith Busch 3082bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 308318119775SKeith Busch flush_work(&dev->ctrl.scan_work); 308480f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 308518119775SKeith Busch } 308618119775SKeith Busch 308757dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 308857dacad5SJay Sternberg { 308957dacad5SJay Sternberg int node, result = -ENOMEM; 309057dacad5SJay Sternberg struct nvme_dev *dev; 3091ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 3092943e942eSJens Axboe size_t alloc_size; 309357dacad5SJay Sternberg 309457dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 309557dacad5SJay Sternberg if (node == NUMA_NO_NODE) 30962fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 309757dacad5SJay Sternberg 309857dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 309957dacad5SJay Sternberg if (!dev) 310057dacad5SJay Sternberg return -ENOMEM; 3101147b27e4SSagi Grimberg 31022a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 31032a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 31042a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 31052a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 31062a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 310757dacad5SJay Sternberg if (!dev->queues) 310857dacad5SJay Sternberg goto free; 310957dacad5SJay Sternberg 311057dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 311157dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 311257dacad5SJay Sternberg 3113b00a726aSKeith Busch result = nvme_dev_map(dev); 3114b00a726aSKeith Busch if (result) 3115b00c9b7aSChristophe JAILLET goto put_pci; 3116b00a726aSKeith Busch 3117d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 31185c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 311977bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 3120f3ca80fcSChristoph Hellwig 3121f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 3122f3ca80fcSChristoph Hellwig if (result) 3123b00c9b7aSChristophe JAILLET goto unmap; 3124f3ca80fcSChristoph Hellwig 31258427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 3126ff5350a8SAndy Lutomirski 31272744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3128df4f9bc4SDavid E. Box /* 3129df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3130df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3131df4f9bc4SDavid E. Box */ 3132df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3133df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3134df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3135df4f9bc4SDavid E. Box } 3136df4f9bc4SDavid E. Box 3137943e942eSJens Axboe /* 3138943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 3139943e942eSJens Axboe * command we support. 3140943e942eSJens Axboe */ 3141b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 3142943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 3143943e942eSJens Axboe 3144943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 3145943e942eSJens Axboe mempool_kfree, 3146943e942eSJens Axboe (void *) alloc_size, 3147943e942eSJens Axboe GFP_KERNEL, node); 3148943e942eSJens Axboe if (!dev->iod_mempool) { 3149943e942eSJens Axboe result = -ENOMEM; 3150943e942eSJens Axboe goto release_pools; 3151943e942eSJens Axboe } 3152943e942eSJens Axboe 3153b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3154b6e44b4cSKeith Busch quirks); 3155b6e44b4cSKeith Busch if (result) 3156b6e44b4cSKeith Busch goto release_mempool; 3157b6e44b4cSKeith Busch 31581b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 31591b3c47c1SSagi Grimberg 3160bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 316118119775SKeith Busch async_schedule(nvme_async_probe, dev); 31624caff8fcSSagi Grimberg 316357dacad5SJay Sternberg return 0; 316457dacad5SJay Sternberg 3165b6e44b4cSKeith Busch release_mempool: 3166b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 316757dacad5SJay Sternberg release_pools: 316857dacad5SJay Sternberg nvme_release_prp_pools(dev); 3169b00c9b7aSChristophe JAILLET unmap: 3170b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 317157dacad5SJay Sternberg put_pci: 317257dacad5SJay Sternberg put_device(dev->dev); 317357dacad5SJay Sternberg free: 317457dacad5SJay Sternberg kfree(dev->queues); 317557dacad5SJay Sternberg kfree(dev); 317657dacad5SJay Sternberg return result; 317757dacad5SJay Sternberg } 317857dacad5SJay Sternberg 3179775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 318057dacad5SJay Sternberg { 318157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3182c1ac9a4bSKeith Busch 3183c1ac9a4bSKeith Busch /* 3184c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3185c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3186c1ac9a4bSKeith Busch * with ->remove(). 3187c1ac9a4bSKeith Busch */ 3188c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3189c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3190775755edSChristoph Hellwig } 319157dacad5SJay Sternberg 3192775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3193775755edSChristoph Hellwig { 3194f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3195c1ac9a4bSKeith Busch 3196c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3197c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 319857dacad5SJay Sternberg } 319957dacad5SJay Sternberg 320057dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 320157dacad5SJay Sternberg { 320257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 32034e523547SBaolin Wang 3204c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 320557dacad5SJay Sternberg } 320657dacad5SJay Sternberg 32070521905eSKeith Busch static void nvme_remove_attrs(struct nvme_dev *dev) 32080521905eSKeith Busch { 32090521905eSKeith Busch if (dev->attrs_added) 32100521905eSKeith Busch sysfs_remove_group(&dev->ctrl.device->kobj, 32110521905eSKeith Busch &nvme_pci_attr_group); 32120521905eSKeith Busch } 32130521905eSKeith Busch 3214f58944e2SKeith Busch /* 3215f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3216f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3217f58944e2SKeith Busch * order to proceed. 3218f58944e2SKeith Busch */ 321957dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 322057dacad5SJay Sternberg { 322157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 322257dacad5SJay Sternberg 3223bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 322457dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 32250ff9d4e1SKeith Busch 32266db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 32270ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 32281d39e692SKeith Busch nvme_dev_disable(dev, true); 32296db28edaSKeith Busch } 32300ff9d4e1SKeith Busch 3231d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3232d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3233d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3234a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 32350521905eSKeith Busch nvme_remove_attrs(dev); 323687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 323757dacad5SJay Sternberg nvme_dev_remove_admin(dev); 323857dacad5SJay Sternberg nvme_free_queues(dev, 0); 323957dacad5SJay Sternberg nvme_release_prp_pools(dev); 3240b00a726aSKeith Busch nvme_dev_unmap(dev); 3241726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 324257dacad5SJay Sternberg } 324357dacad5SJay Sternberg 324457dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3245d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3246d916b1beSKeith Busch { 3247d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3248d916b1beSKeith Busch } 3249d916b1beSKeith Busch 3250d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3251d916b1beSKeith Busch { 3252d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3253d916b1beSKeith Busch } 3254d916b1beSKeith Busch 3255d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3256d916b1beSKeith Busch { 3257d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3258d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3259d916b1beSKeith Busch 32604eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3261d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3262e5ad96f3SKeith Busch goto reset; 3263e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3264e5ad96f3SKeith Busch goto reset; 3265e5ad96f3SKeith Busch 3266d916b1beSKeith Busch return 0; 3267e5ad96f3SKeith Busch reset: 3268e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3269d916b1beSKeith Busch } 3270d916b1beSKeith Busch 327157dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 327257dacad5SJay Sternberg { 327357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 327457dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3275d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3276d916b1beSKeith Busch int ret = -EBUSY; 3277d916b1beSKeith Busch 32784eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 32794eaefe8cSRafael J. Wysocki 3280d916b1beSKeith Busch /* 3281d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3282d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3283d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3284d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3285d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3286d916b1beSKeith Busch * device fully. 32874eaefe8cSRafael J. Wysocki * 32884eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 32894eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 32904eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 32914eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3292d916b1beSKeith Busch */ 32934eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3294cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3295c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3296c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3297d916b1beSKeith Busch 3298d916b1beSKeith Busch nvme_start_freeze(ctrl); 3299d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3300d916b1beSKeith Busch nvme_sync_queues(ctrl); 3301d916b1beSKeith Busch 33025d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3303d916b1beSKeith Busch goto unfreeze; 3304d916b1beSKeith Busch 3305e5ad96f3SKeith Busch /* 3306e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3307e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3308e5ad96f3SKeith Busch * non-operational power state. 3309e5ad96f3SKeith Busch */ 3310e5ad96f3SKeith Busch if (ndev->hmb) { 3311e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3312e5ad96f3SKeith Busch if (ret < 0) 3313e5ad96f3SKeith Busch goto unfreeze; 3314e5ad96f3SKeith Busch } 3315e5ad96f3SKeith Busch 3316d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3317d916b1beSKeith Busch if (ret < 0) 3318d916b1beSKeith Busch goto unfreeze; 3319d916b1beSKeith Busch 33207cbb5c6fSMario Limonciello /* 33217cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 33227cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 33237cbb5c6fSMario Limonciello * want pci interfering. 33247cbb5c6fSMario Limonciello */ 33257cbb5c6fSMario Limonciello pci_save_state(pdev); 33267cbb5c6fSMario Limonciello 3327d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3328d916b1beSKeith Busch if (ret < 0) 3329d916b1beSKeith Busch goto unfreeze; 3330d916b1beSKeith Busch 3331d916b1beSKeith Busch if (ret) { 33327cbb5c6fSMario Limonciello /* discard the saved state */ 33337cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 33347cbb5c6fSMario Limonciello 3335d916b1beSKeith Busch /* 3336d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 333705d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3338d916b1beSKeith Busch */ 3339c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3340d916b1beSKeith Busch ctrl->npss = 0; 3341d916b1beSKeith Busch } 3342d916b1beSKeith Busch unfreeze: 3343d916b1beSKeith Busch nvme_unfreeze(ctrl); 3344d916b1beSKeith Busch return ret; 3345d916b1beSKeith Busch } 3346d916b1beSKeith Busch 3347d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3348d916b1beSKeith Busch { 3349d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 33504e523547SBaolin Wang 3351c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 335257dacad5SJay Sternberg } 335357dacad5SJay Sternberg 3354d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 335557dacad5SJay Sternberg { 335657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 335757dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 335857dacad5SJay Sternberg 3359c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 336057dacad5SJay Sternberg } 336157dacad5SJay Sternberg 336221774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3363d916b1beSKeith Busch .suspend = nvme_suspend, 3364d916b1beSKeith Busch .resume = nvme_resume, 3365d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3366d916b1beSKeith Busch .thaw = nvme_simple_resume, 3367d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3368d916b1beSKeith Busch .restore = nvme_simple_resume, 3369d916b1beSKeith Busch }; 3370d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 337157dacad5SJay Sternberg 3372a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3373a0a3408eSKeith Busch pci_channel_state_t state) 3374a0a3408eSKeith Busch { 3375a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3376a0a3408eSKeith Busch 3377a0a3408eSKeith Busch /* 3378a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3379a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3380a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3381a0a3408eSKeith Busch */ 3382a0a3408eSKeith Busch switch (state) { 3383a0a3408eSKeith Busch case pci_channel_io_normal: 3384a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3385a0a3408eSKeith Busch case pci_channel_io_frozen: 3386d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3387d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3388a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3389a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3390a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3391d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3392d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3393a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3394a0a3408eSKeith Busch } 3395a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3396a0a3408eSKeith Busch } 3397a0a3408eSKeith Busch 3398a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3399a0a3408eSKeith Busch { 3400a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3401a0a3408eSKeith Busch 34021b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3403a0a3408eSKeith Busch pci_restore_state(pdev); 3404d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3405a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3406a0a3408eSKeith Busch } 3407a0a3408eSKeith Busch 3408a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3409a0a3408eSKeith Busch { 341072cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 341172cd4cc2SKeith Busch 341272cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3413a0a3408eSKeith Busch } 3414a0a3408eSKeith Busch 341557dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 341657dacad5SJay Sternberg .error_detected = nvme_error_detected, 341757dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 341857dacad5SJay Sternberg .resume = nvme_error_resume, 3419775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3420775755edSChristoph Hellwig .reset_done = nvme_reset_done, 342157dacad5SJay Sternberg }; 342257dacad5SJay Sternberg 342357dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3424972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 342508095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3426e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3427972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 342899466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3429e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3430972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 343199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 343225e58af4SWu Zheng NVME_QUIRK_DEALLOCATE_ZEROES | 343325e58af4SWu Zheng NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3434972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3435f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3436f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 343750af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 34389abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 34396c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3440ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3441ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34426299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 34436299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3444540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 34457b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 344666dd346bSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES | 344766dd346bSChristoph Hellwig NVME_QUIRK_BOGUS_NID, }, 344866dd346bSChristoph Hellwig { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 344966dd346bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 34505bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3451c98a8793SKeith Busch .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3452c98a8793SKeith Busch NVME_QUIRK_BOGUS_NID, }, 34530302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 34545e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 34555e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 345654adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 345754adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 34588c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 34598c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3460015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3461015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3462d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3463d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3464d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 34657ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3466abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 34677ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34682cf7a77eSKeith Busch { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 34692cf7a77eSKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 3470c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 347173029c9bSKeith Busch .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 347273029c9bSKeith Busch NVME_QUIRK_BOGUS_NID, }, 34736e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 34746e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 34756e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3476e1c70d79SLamarque Vieira Souza { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3477e1c70d79SLamarque Vieira Souza .driver_data = NVME_QUIRK_BOGUS_NID, }, 347808b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 34791629de0eSPablo Greco .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 34801629de0eSPablo Greco NVME_QUIRK_BOGUS_NID, }, 3481f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3482f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3483f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 348441f38043SLeo Savernik { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 348541f38043SLeo Savernik .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 34865611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 34875611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3488c4f01a77SKeith Busch { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3489c4f01a77SKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 349002ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 349102ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349289919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 349389919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349443047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 349543047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349643047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 349743047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349843047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 349943047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 350043047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 350143047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3502dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3503dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3504538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3505538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 350670ce3455SChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 350770ce3455SChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3508a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3509a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3510a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3511a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 35123765fad5SStefan Reiter { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 35133765fad5SStefan Reiter .driver_data = NVME_QUIRK_BOGUS_NID, }, 35146b961bceSNing Wang { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 35156b961bceSNing Wang .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3516d6c52fa3STobias Gruetzmacher { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3517d6c52fa3STobias Gruetzmacher .driver_data = NVME_QUIRK_BOGUS_NID, }, 35184bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 35194bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35204bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 35214bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35224bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 35234bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35244bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 35254bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35264bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 35274bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35284bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 35294bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 353098f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 353198f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3532124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 353366341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 353466341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3535d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3536a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3537a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 35380b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 353957dacad5SJay Sternberg { 0, } 354057dacad5SJay Sternberg }; 354157dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 354257dacad5SJay Sternberg 354357dacad5SJay Sternberg static struct pci_driver nvme_driver = { 354457dacad5SJay Sternberg .name = "nvme", 354557dacad5SJay Sternberg .id_table = nvme_id_table, 354657dacad5SJay Sternberg .probe = nvme_probe, 354757dacad5SJay Sternberg .remove = nvme_remove, 354857dacad5SJay Sternberg .shutdown = nvme_shutdown, 3549d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 355057dacad5SJay Sternberg .driver = { 355157dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 355257dacad5SJay Sternberg }, 3553d916b1beSKeith Busch #endif 355474d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 355557dacad5SJay Sternberg .err_handler = &nvme_err_handler, 355657dacad5SJay Sternberg }; 355757dacad5SJay Sternberg 355857dacad5SJay Sternberg static int __init nvme_init(void) 355957dacad5SJay Sternberg { 356081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 356181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 356281101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3563612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 356417c33167SKeith Busch 35659a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 356657dacad5SJay Sternberg } 356757dacad5SJay Sternberg 356857dacad5SJay Sternberg static void __exit nvme_exit(void) 356957dacad5SJay Sternberg { 357057dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 357103e0f3a6SMing Lei flush_workqueue(nvme_wq); 357257dacad5SJay Sternberg } 357357dacad5SJay Sternberg 357457dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 357557dacad5SJay Sternberg MODULE_LICENSE("GPL"); 357657dacad5SJay Sternberg MODULE_VERSION("1.0"); 357757dacad5SJay Sternberg module_init(nvme_init); 357857dacad5SJay Sternberg module_exit(nvme_exit); 3579