157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1657dacad5SJay Sternberg #include <linux/bitops.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 2757dacad5SJay Sternberg #include <linux/pci.h> 2857dacad5SJay Sternberg #include <linux/poison.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 302d55cd5fSChristoph Hellwig #include <linux/timer.h> 3157dacad5SJay Sternberg #include <linux/types.h> 329cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 331d277a63SKeith Busch #include <asm/unaligned.h> 34a98e58e5SScott Bauer #include <linux/sed-opal.h> 3557dacad5SJay Sternberg 3657dacad5SJay Sternberg #include "nvme.h" 3757dacad5SJay Sternberg 3857dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3957dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 4057dacad5SJay Sternberg 41adf68f21SChristoph Hellwig /* 42adf68f21SChristoph Hellwig * We handle AEN commands ourselves and don't even let the 43adf68f21SChristoph Hellwig * block layer know about them. 44adf68f21SChristoph Hellwig */ 45f866fc42SChristoph Hellwig #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) 46adf68f21SChristoph Hellwig 4757dacad5SJay Sternberg static int use_threaded_interrupts; 4857dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4957dacad5SJay Sternberg 5057dacad5SJay Sternberg static bool use_cmb_sqes = true; 5157dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 5257dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5357dacad5SJay Sternberg 5487ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5587ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5687ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5787ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5857dacad5SJay Sternberg 59b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 60b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 61b27c1e68Sweiping zhang .set = io_queue_depth_set, 62b27c1e68Sweiping zhang .get = param_get_int, 63b27c1e68Sweiping zhang }; 64b27c1e68Sweiping zhang 65b27c1e68Sweiping zhang static int io_queue_depth = 1024; 66b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 67b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 68b27c1e68Sweiping zhang 691c63dc66SChristoph Hellwig struct nvme_dev; 701c63dc66SChristoph Hellwig struct nvme_queue; 7157dacad5SJay Sternberg 72a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq); 73a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 7457dacad5SJay Sternberg 7557dacad5SJay Sternberg /* 761c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 771c63dc66SChristoph Hellwig */ 781c63dc66SChristoph Hellwig struct nvme_dev { 791c63dc66SChristoph Hellwig struct nvme_queue **queues; 801c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 811c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 821c63dc66SChristoph Hellwig u32 __iomem *dbs; 831c63dc66SChristoph Hellwig struct device *dev; 841c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 851c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 861c63dc66SChristoph Hellwig unsigned online_queues; 871c63dc66SChristoph Hellwig unsigned max_qid; 881c63dc66SChristoph Hellwig int q_depth; 891c63dc66SChristoph Hellwig u32 db_stride; 901c63dc66SChristoph Hellwig void __iomem *bar; 9197f6ef64SXu Yu unsigned long bar_mapped_size; 925c8809e6SChristoph Hellwig struct work_struct remove_work; 9377bf25eaSKeith Busch struct mutex shutdown_lock; 941c63dc66SChristoph Hellwig bool subsystem; 951c63dc66SChristoph Hellwig void __iomem *cmb; 961c63dc66SChristoph Hellwig dma_addr_t cmb_dma_addr; 971c63dc66SChristoph Hellwig u64 cmb_size; 981c63dc66SChristoph Hellwig u32 cmbsz; 99202021c1SStephen Bates u32 cmbloc; 1001c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 101db3cbfffSKeith Busch struct completion ioq_wait; 10287ad72a5SChristoph Hellwig 10387ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 104f9f38e33SHelen Koike u32 *dbbuf_dbs; 105f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 106f9f38e33SHelen Koike u32 *dbbuf_eis; 107f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 10887ad72a5SChristoph Hellwig 10987ad72a5SChristoph Hellwig /* host memory buffer support: */ 11087ad72a5SChristoph Hellwig u64 host_mem_size; 11187ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1124033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 11387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 11487ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 11557dacad5SJay Sternberg }; 11657dacad5SJay Sternberg 117b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 118b27c1e68Sweiping zhang { 119b27c1e68Sweiping zhang int n = 0, ret; 120b27c1e68Sweiping zhang 121b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 122b27c1e68Sweiping zhang if (ret != 0 || n < 2) 123b27c1e68Sweiping zhang return -EINVAL; 124b27c1e68Sweiping zhang 125b27c1e68Sweiping zhang return param_set_int(val, kp); 126b27c1e68Sweiping zhang } 127b27c1e68Sweiping zhang 128f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 129f9f38e33SHelen Koike { 130f9f38e33SHelen Koike return qid * 2 * stride; 131f9f38e33SHelen Koike } 132f9f38e33SHelen Koike 133f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 134f9f38e33SHelen Koike { 135f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 136f9f38e33SHelen Koike } 137f9f38e33SHelen Koike 1381c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1391c63dc66SChristoph Hellwig { 1401c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1411c63dc66SChristoph Hellwig } 1421c63dc66SChristoph Hellwig 14357dacad5SJay Sternberg /* 14457dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14557dacad5SJay Sternberg * commands and one for I/O commands). 14657dacad5SJay Sternberg */ 14757dacad5SJay Sternberg struct nvme_queue { 14857dacad5SJay Sternberg struct device *q_dmadev; 14957dacad5SJay Sternberg struct nvme_dev *dev; 15057dacad5SJay Sternberg spinlock_t q_lock; 15157dacad5SJay Sternberg struct nvme_command *sq_cmds; 15257dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 15357dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15457dacad5SJay Sternberg struct blk_mq_tags **tags; 15557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15757dacad5SJay Sternberg u32 __iomem *q_db; 15857dacad5SJay Sternberg u16 q_depth; 15957dacad5SJay Sternberg s16 cq_vector; 16057dacad5SJay Sternberg u16 sq_tail; 16157dacad5SJay Sternberg u16 cq_head; 16257dacad5SJay Sternberg u16 qid; 16357dacad5SJay Sternberg u8 cq_phase; 16457dacad5SJay Sternberg u8 cqe_seen; 165f9f38e33SHelen Koike u32 *dbbuf_sq_db; 166f9f38e33SHelen Koike u32 *dbbuf_cq_db; 167f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 168f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 16957dacad5SJay Sternberg }; 17057dacad5SJay Sternberg 17157dacad5SJay Sternberg /* 17271bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 17371bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 174f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17571bd150cSChristoph Hellwig * allocated to store the PRP list. 17671bd150cSChristoph Hellwig */ 17771bd150cSChristoph Hellwig struct nvme_iod { 178d49187e9SChristoph Hellwig struct nvme_request req; 179f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 180f4800d6dSChristoph Hellwig int aborted; 18171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 18271bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 18371bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18471bd150cSChristoph Hellwig dma_addr_t first_dma; 185bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 186f4800d6dSChristoph Hellwig struct scatterlist *sg; 187f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 18857dacad5SJay Sternberg }; 18957dacad5SJay Sternberg 19057dacad5SJay Sternberg /* 19157dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 19257dacad5SJay Sternberg */ 19357dacad5SJay Sternberg static inline void _nvme_check_size(void) 19457dacad5SJay Sternberg { 19557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 20257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2030add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2040add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 20557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 207f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 208f9f38e33SHelen Koike } 209f9f38e33SHelen Koike 210f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 211f9f38e33SHelen Koike { 212f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 213f9f38e33SHelen Koike } 214f9f38e33SHelen Koike 215f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 216f9f38e33SHelen Koike { 217f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 218f9f38e33SHelen Koike 219f9f38e33SHelen Koike if (dev->dbbuf_dbs) 220f9f38e33SHelen Koike return 0; 221f9f38e33SHelen Koike 222f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 223f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 224f9f38e33SHelen Koike GFP_KERNEL); 225f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 226f9f38e33SHelen Koike return -ENOMEM; 227f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 228f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 229f9f38e33SHelen Koike GFP_KERNEL); 230f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 231f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 232f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 233f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 234f9f38e33SHelen Koike return -ENOMEM; 235f9f38e33SHelen Koike } 236f9f38e33SHelen Koike 237f9f38e33SHelen Koike return 0; 238f9f38e33SHelen Koike } 239f9f38e33SHelen Koike 240f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 241f9f38e33SHelen Koike { 242f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 243f9f38e33SHelen Koike 244f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 245f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 246f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 247f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 248f9f38e33SHelen Koike } 249f9f38e33SHelen Koike if (dev->dbbuf_eis) { 250f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 251f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 252f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 253f9f38e33SHelen Koike } 254f9f38e33SHelen Koike } 255f9f38e33SHelen Koike 256f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 257f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 258f9f38e33SHelen Koike { 259f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 260f9f38e33SHelen Koike return; 261f9f38e33SHelen Koike 262f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 263f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 264f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 265f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 266f9f38e33SHelen Koike } 267f9f38e33SHelen Koike 268f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 269f9f38e33SHelen Koike { 270f9f38e33SHelen Koike struct nvme_command c; 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 273f9f38e33SHelen Koike return; 274f9f38e33SHelen Koike 275f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 276f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 277f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 278f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 279f9f38e33SHelen Koike 280f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2819bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 282f9f38e33SHelen Koike /* Free memory and continue on */ 283f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 284f9f38e33SHelen Koike } 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike 287f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 288f9f38e33SHelen Koike { 289f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 290f9f38e33SHelen Koike } 291f9f38e33SHelen Koike 292f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 293f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 294f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 295f9f38e33SHelen Koike { 296f9f38e33SHelen Koike if (dbbuf_db) { 297f9f38e33SHelen Koike u16 old_value; 298f9f38e33SHelen Koike 299f9f38e33SHelen Koike /* 300f9f38e33SHelen Koike * Ensure that the queue is written before updating 301f9f38e33SHelen Koike * the doorbell in memory 302f9f38e33SHelen Koike */ 303f9f38e33SHelen Koike wmb(); 304f9f38e33SHelen Koike 305f9f38e33SHelen Koike old_value = *dbbuf_db; 306f9f38e33SHelen Koike *dbbuf_db = value; 307f9f38e33SHelen Koike 308f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 309f9f38e33SHelen Koike return false; 310f9f38e33SHelen Koike } 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike return true; 31357dacad5SJay Sternberg } 31457dacad5SJay Sternberg 31557dacad5SJay Sternberg /* 31657dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31757dacad5SJay Sternberg */ 31857dacad5SJay Sternberg #define NVME_INT_PAGES 2 3195fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 32057dacad5SJay Sternberg 32157dacad5SJay Sternberg /* 32257dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 32357dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32457dacad5SJay Sternberg * the I/O. 32557dacad5SJay Sternberg */ 32657dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32757dacad5SJay Sternberg { 3285fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3295fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 33057dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 33157dacad5SJay Sternberg } 33257dacad5SJay Sternberg 333f4800d6dSChristoph Hellwig static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, 334f4800d6dSChristoph Hellwig unsigned int size, unsigned int nseg) 335f4800d6dSChristoph Hellwig { 336f4800d6dSChristoph Hellwig return sizeof(__le64 *) * nvme_npages(size, dev) + 337f4800d6dSChristoph Hellwig sizeof(struct scatterlist) * nseg; 338f4800d6dSChristoph Hellwig } 339f4800d6dSChristoph Hellwig 34057dacad5SJay Sternberg static unsigned int nvme_cmd_size(struct nvme_dev *dev) 34157dacad5SJay Sternberg { 342f4800d6dSChristoph Hellwig return sizeof(struct nvme_iod) + 343f4800d6dSChristoph Hellwig nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); 34457dacad5SJay Sternberg } 34557dacad5SJay Sternberg 34657dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 34757dacad5SJay Sternberg unsigned int hctx_idx) 34857dacad5SJay Sternberg { 34957dacad5SJay Sternberg struct nvme_dev *dev = data; 35057dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[0]; 35157dacad5SJay Sternberg 35257dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 35357dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 35457dacad5SJay Sternberg WARN_ON(nvmeq->tags); 35557dacad5SJay Sternberg 35657dacad5SJay Sternberg hctx->driver_data = nvmeq; 35757dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 35857dacad5SJay Sternberg return 0; 35957dacad5SJay Sternberg } 36057dacad5SJay Sternberg 36157dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 36257dacad5SJay Sternberg { 36357dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 36457dacad5SJay Sternberg 36557dacad5SJay Sternberg nvmeq->tags = NULL; 36657dacad5SJay Sternberg } 36757dacad5SJay Sternberg 36857dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 36957dacad5SJay Sternberg unsigned int hctx_idx) 37057dacad5SJay Sternberg { 37157dacad5SJay Sternberg struct nvme_dev *dev = data; 37257dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 37357dacad5SJay Sternberg 37457dacad5SJay Sternberg if (!nvmeq->tags) 37557dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 37657dacad5SJay Sternberg 37757dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 37857dacad5SJay Sternberg hctx->driver_data = nvmeq; 37957dacad5SJay Sternberg return 0; 38057dacad5SJay Sternberg } 38157dacad5SJay Sternberg 382d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 383d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 38457dacad5SJay Sternberg { 385d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 386f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 3870350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 3880350815aSChristoph Hellwig struct nvme_queue *nvmeq = dev->queues[queue_idx]; 38957dacad5SJay Sternberg 39057dacad5SJay Sternberg BUG_ON(!nvmeq); 391f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 39257dacad5SJay Sternberg return 0; 39357dacad5SJay Sternberg } 39457dacad5SJay Sternberg 395dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 396dca51e78SChristoph Hellwig { 397dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 398dca51e78SChristoph Hellwig 399dca51e78SChristoph Hellwig return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); 400dca51e78SChristoph Hellwig } 401dca51e78SChristoph Hellwig 40257dacad5SJay Sternberg /** 403adf68f21SChristoph Hellwig * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 40457dacad5SJay Sternberg * @nvmeq: The queue to use 40557dacad5SJay Sternberg * @cmd: The command to send 40657dacad5SJay Sternberg * 40757dacad5SJay Sternberg * Safe to use from interrupt context 40857dacad5SJay Sternberg */ 40957dacad5SJay Sternberg static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 41057dacad5SJay Sternberg struct nvme_command *cmd) 41157dacad5SJay Sternberg { 41257dacad5SJay Sternberg u16 tail = nvmeq->sq_tail; 41357dacad5SJay Sternberg 41457dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 41557dacad5SJay Sternberg memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 41657dacad5SJay Sternberg else 41757dacad5SJay Sternberg memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 41857dacad5SJay Sternberg 41957dacad5SJay Sternberg if (++tail == nvmeq->q_depth) 42057dacad5SJay Sternberg tail = 0; 421f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 422f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei)) 42357dacad5SJay Sternberg writel(tail, nvmeq->q_db); 42457dacad5SJay Sternberg nvmeq->sq_tail = tail; 42557dacad5SJay Sternberg } 42657dacad5SJay Sternberg 427f4800d6dSChristoph Hellwig static __le64 **iod_list(struct request *req) 42857dacad5SJay Sternberg { 429f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 430f9d03f96SChristoph Hellwig return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); 43157dacad5SJay Sternberg } 43257dacad5SJay Sternberg 433fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 43457dacad5SJay Sternberg { 435f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 436f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 437b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 438f4800d6dSChristoph Hellwig 439f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 440f4800d6dSChristoph Hellwig iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); 441f4800d6dSChristoph Hellwig if (!iod->sg) 442fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 443f4800d6dSChristoph Hellwig } else { 444f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 44557dacad5SJay Sternberg } 44657dacad5SJay Sternberg 447f4800d6dSChristoph Hellwig iod->aborted = 0; 44857dacad5SJay Sternberg iod->npages = -1; 44957dacad5SJay Sternberg iod->nents = 0; 450f4800d6dSChristoph Hellwig iod->length = size; 451f80ec966SKeith Busch 452fc17b653SChristoph Hellwig return BLK_STS_OK; 45357dacad5SJay Sternberg } 45457dacad5SJay Sternberg 455f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 45657dacad5SJay Sternberg { 457f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4585fd4ce1bSChristoph Hellwig const int last_prp = dev->ctrl.page_size / 8 - 1; 45957dacad5SJay Sternberg int i; 460f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 46157dacad5SJay Sternberg dma_addr_t prp_dma = iod->first_dma; 46257dacad5SJay Sternberg 46357dacad5SJay Sternberg if (iod->npages == 0) 46457dacad5SJay Sternberg dma_pool_free(dev->prp_small_pool, list[0], prp_dma); 46557dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 46657dacad5SJay Sternberg __le64 *prp_list = list[i]; 46757dacad5SJay Sternberg dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); 46857dacad5SJay Sternberg dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); 46957dacad5SJay Sternberg prp_dma = next_prp_dma; 47057dacad5SJay Sternberg } 47157dacad5SJay Sternberg 472f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 473f4800d6dSChristoph Hellwig kfree(iod->sg); 47457dacad5SJay Sternberg } 47557dacad5SJay Sternberg 47657dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 47757dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 47857dacad5SJay Sternberg { 47957dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 48057dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 48157dacad5SJay Sternberg } 48257dacad5SJay Sternberg 48357dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 48457dacad5SJay Sternberg { 48557dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 48657dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 48757dacad5SJay Sternberg } 48857dacad5SJay Sternberg 48957dacad5SJay Sternberg /** 49057dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 49157dacad5SJay Sternberg * 49257dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 49357dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 49457dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 49557dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 49657dacad5SJay Sternberg * 49757dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 49857dacad5SJay Sternberg */ 49957dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 50057dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 50157dacad5SJay Sternberg { 50257dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 50357dacad5SJay Sternberg struct bio_integrity_payload *bip; 50457dacad5SJay Sternberg struct t10_pi_tuple *pi; 50557dacad5SJay Sternberg void *p, *pmap; 50657dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 50757dacad5SJay Sternberg 50857dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 50957dacad5SJay Sternberg return; 51057dacad5SJay Sternberg 51157dacad5SJay Sternberg bip = bio_integrity(req->bio); 51257dacad5SJay Sternberg if (!bip) 51357dacad5SJay Sternberg return; 51457dacad5SJay Sternberg 51557dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 51657dacad5SJay Sternberg 51757dacad5SJay Sternberg p = pmap; 51857dacad5SJay Sternberg virt = bip_get_seed(bip); 51957dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 52057dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 521ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 52257dacad5SJay Sternberg 52357dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 52457dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 52557dacad5SJay Sternberg dif_swap(phys, virt, pi); 52657dacad5SJay Sternberg p += ts; 52757dacad5SJay Sternberg } 52857dacad5SJay Sternberg kunmap_atomic(pmap); 52957dacad5SJay Sternberg } 53057dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 53157dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 53257dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 53357dacad5SJay Sternberg { 53457dacad5SJay Sternberg } 53557dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 53657dacad5SJay Sternberg { 53757dacad5SJay Sternberg } 53857dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 53957dacad5SJay Sternberg { 54057dacad5SJay Sternberg } 54157dacad5SJay Sternberg #endif 54257dacad5SJay Sternberg 54386eea289SKeith Busch static blk_status_t nvme_setup_prps(struct nvme_dev *dev, struct request *req) 54457dacad5SJay Sternberg { 545f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 54657dacad5SJay Sternberg struct dma_pool *pool; 547b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 54857dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 54957dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 55057dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5515fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 55257dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 55357dacad5SJay Sternberg __le64 *prp_list; 554f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 55557dacad5SJay Sternberg dma_addr_t prp_dma; 55657dacad5SJay Sternberg int nprps, i; 55757dacad5SJay Sternberg 55857dacad5SJay Sternberg length -= (page_size - offset); 5595228b328SJan H. Schönherr if (length <= 0) { 5605228b328SJan H. Schönherr iod->first_dma = 0; 56186eea289SKeith Busch return BLK_STS_OK; 5625228b328SJan H. Schönherr } 56357dacad5SJay Sternberg 56457dacad5SJay Sternberg dma_len -= (page_size - offset); 56557dacad5SJay Sternberg if (dma_len) { 56657dacad5SJay Sternberg dma_addr += (page_size - offset); 56757dacad5SJay Sternberg } else { 56857dacad5SJay Sternberg sg = sg_next(sg); 56957dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 57057dacad5SJay Sternberg dma_len = sg_dma_len(sg); 57157dacad5SJay Sternberg } 57257dacad5SJay Sternberg 57357dacad5SJay Sternberg if (length <= page_size) { 57457dacad5SJay Sternberg iod->first_dma = dma_addr; 57586eea289SKeith Busch return BLK_STS_OK; 57657dacad5SJay Sternberg } 57757dacad5SJay Sternberg 57857dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 57957dacad5SJay Sternberg if (nprps <= (256 / 8)) { 58057dacad5SJay Sternberg pool = dev->prp_small_pool; 58157dacad5SJay Sternberg iod->npages = 0; 58257dacad5SJay Sternberg } else { 58357dacad5SJay Sternberg pool = dev->prp_page_pool; 58457dacad5SJay Sternberg iod->npages = 1; 58557dacad5SJay Sternberg } 58657dacad5SJay Sternberg 58769d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 58857dacad5SJay Sternberg if (!prp_list) { 58957dacad5SJay Sternberg iod->first_dma = dma_addr; 59057dacad5SJay Sternberg iod->npages = -1; 59186eea289SKeith Busch return BLK_STS_RESOURCE; 59257dacad5SJay Sternberg } 59357dacad5SJay Sternberg list[0] = prp_list; 59457dacad5SJay Sternberg iod->first_dma = prp_dma; 59557dacad5SJay Sternberg i = 0; 59657dacad5SJay Sternberg for (;;) { 59757dacad5SJay Sternberg if (i == page_size >> 3) { 59857dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 59969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 60057dacad5SJay Sternberg if (!prp_list) 60186eea289SKeith Busch return BLK_STS_RESOURCE; 60257dacad5SJay Sternberg list[iod->npages++] = prp_list; 60357dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 60457dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 60557dacad5SJay Sternberg i = 1; 60657dacad5SJay Sternberg } 60757dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 60857dacad5SJay Sternberg dma_len -= page_size; 60957dacad5SJay Sternberg dma_addr += page_size; 61057dacad5SJay Sternberg length -= page_size; 61157dacad5SJay Sternberg if (length <= 0) 61257dacad5SJay Sternberg break; 61357dacad5SJay Sternberg if (dma_len > 0) 61457dacad5SJay Sternberg continue; 61586eea289SKeith Busch if (unlikely(dma_len < 0)) 61686eea289SKeith Busch goto bad_sgl; 61757dacad5SJay Sternberg sg = sg_next(sg); 61857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 61957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 62057dacad5SJay Sternberg } 62157dacad5SJay Sternberg 62286eea289SKeith Busch return BLK_STS_OK; 62386eea289SKeith Busch 62486eea289SKeith Busch bad_sgl: 62586eea289SKeith Busch if (WARN_ONCE(1, "Invalid SGL for payload:%d nents:%d\n", 62686eea289SKeith Busch blk_rq_payload_bytes(req), iod->nents)) { 62786eea289SKeith Busch for_each_sg(iod->sg, sg, iod->nents, i) { 62886eea289SKeith Busch dma_addr_t phys = sg_phys(sg); 62986eea289SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 63086eea289SKeith Busch "dma_address:%pad dma_length:%d\n", i, &phys, 63186eea289SKeith Busch sg->offset, sg->length, 63286eea289SKeith Busch &sg_dma_address(sg), 63386eea289SKeith Busch sg_dma_len(sg)); 63486eea289SKeith Busch } 63586eea289SKeith Busch } 63686eea289SKeith Busch return BLK_STS_IOERR; 63786eea289SKeith Busch 63857dacad5SJay Sternberg } 63957dacad5SJay Sternberg 640fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 641b131c61dSChristoph Hellwig struct nvme_command *cmnd) 64257dacad5SJay Sternberg { 643f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 644ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 645ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 646ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 647fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 64857dacad5SJay Sternberg 649f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 650ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 651ba1ca37eSChristoph Hellwig if (!iod->nents) 652ba1ca37eSChristoph Hellwig goto out; 653ba1ca37eSChristoph Hellwig 654fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 6552b6b535dSMauricio Faria de Oliveira if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 6562b6b535dSMauricio Faria de Oliveira DMA_ATTR_NO_WARN)) 657ba1ca37eSChristoph Hellwig goto out; 658ba1ca37eSChristoph Hellwig 65986eea289SKeith Busch ret = nvme_setup_prps(dev, req); 66086eea289SKeith Busch if (ret != BLK_STS_OK) 661ba1ca37eSChristoph Hellwig goto out_unmap; 662ba1ca37eSChristoph Hellwig 663fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 664ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 665ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 666ba1ca37eSChristoph Hellwig goto out_unmap; 667ba1ca37eSChristoph Hellwig 668bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 669bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 670ba1ca37eSChristoph Hellwig goto out_unmap; 671ba1ca37eSChristoph Hellwig 672b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_WRITE) 673ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 674ba1ca37eSChristoph Hellwig 675bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 676ba1ca37eSChristoph Hellwig goto out_unmap; 67757dacad5SJay Sternberg } 67857dacad5SJay Sternberg 679eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 680eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); 681ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 682bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 683fc17b653SChristoph Hellwig return BLK_STS_OK; 684ba1ca37eSChristoph Hellwig 685ba1ca37eSChristoph Hellwig out_unmap: 686ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 687ba1ca37eSChristoph Hellwig out: 688ba1ca37eSChristoph Hellwig return ret; 68957dacad5SJay Sternberg } 69057dacad5SJay Sternberg 691f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 692d4f6c3abSChristoph Hellwig { 693f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 694d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 695d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 696d4f6c3abSChristoph Hellwig 697d4f6c3abSChristoph Hellwig if (iod->nents) { 698d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 699d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 700b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_READ) 701d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 702bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 703d4f6c3abSChristoph Hellwig } 704d4f6c3abSChristoph Hellwig } 705d4f6c3abSChristoph Hellwig 706f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 707f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 70857dacad5SJay Sternberg } 70957dacad5SJay Sternberg 71057dacad5SJay Sternberg /* 71157dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 71257dacad5SJay Sternberg */ 713fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 71457dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 71557dacad5SJay Sternberg { 71657dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 71757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 71857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 71957dacad5SJay Sternberg struct request *req = bd->rq; 720ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 721ebe6d874SChristoph Hellwig blk_status_t ret; 72257dacad5SJay Sternberg 723f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 724fc17b653SChristoph Hellwig if (ret) 725f4800d6dSChristoph Hellwig return ret; 72657dacad5SJay Sternberg 727b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 728fc17b653SChristoph Hellwig if (ret) 729f9d03f96SChristoph Hellwig goto out_free_cmd; 73057dacad5SJay Sternberg 731fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 732b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 733fc17b653SChristoph Hellwig if (ret) 734f9d03f96SChristoph Hellwig goto out_cleanup_iod; 735fc17b653SChristoph Hellwig } 736ba1ca37eSChristoph Hellwig 737aae239e1SChristoph Hellwig blk_mq_start_request(req); 738ba1ca37eSChristoph Hellwig 739ba1ca37eSChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 740ae1fba20SKeith Busch if (unlikely(nvmeq->cq_vector < 0)) { 741fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 742ae1fba20SKeith Busch spin_unlock_irq(&nvmeq->q_lock); 743f9d03f96SChristoph Hellwig goto out_cleanup_iod; 744ae1fba20SKeith Busch } 745ba1ca37eSChristoph Hellwig __nvme_submit_cmd(nvmeq, &cmnd); 74657dacad5SJay Sternberg nvme_process_cq(nvmeq); 74757dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 748fc17b653SChristoph Hellwig return BLK_STS_OK; 749f9d03f96SChristoph Hellwig out_cleanup_iod: 750f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 751f9d03f96SChristoph Hellwig out_free_cmd: 752f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 753ba1ca37eSChristoph Hellwig return ret; 75457dacad5SJay Sternberg } 75557dacad5SJay Sternberg 75677f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 757eee417b0SChristoph Hellwig { 758f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 759eee417b0SChristoph Hellwig 76077f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 76177f02a7aSChristoph Hellwig nvme_complete_rq(req); 76257dacad5SJay Sternberg } 76357dacad5SJay Sternberg 764d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 765d783e0bdSMarta Rybczynska static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, 766d783e0bdSMarta Rybczynska u16 phase) 767d783e0bdSMarta Rybczynska { 768d783e0bdSMarta Rybczynska return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; 769d783e0bdSMarta Rybczynska } 770d783e0bdSMarta Rybczynska 771eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 77257dacad5SJay Sternberg { 773eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 77457dacad5SJay Sternberg 775eb281c82SSagi Grimberg if (likely(nvmeq->cq_vector >= 0)) { 776eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 777eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 778eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 779eb281c82SSagi Grimberg } 78057dacad5SJay Sternberg } 781adf68f21SChristoph Hellwig 78283a12fb7SSagi Grimberg static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 78383a12fb7SSagi Grimberg struct nvme_completion *cqe) 78457dacad5SJay Sternberg { 78557dacad5SJay Sternberg struct request *req; 786adf68f21SChristoph Hellwig 78783a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 7881b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 789aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 79083a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 79183a12fb7SSagi Grimberg return; 792aae239e1SChristoph Hellwig } 793aae239e1SChristoph Hellwig 794adf68f21SChristoph Hellwig /* 795adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 796adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 797adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 798adf68f21SChristoph Hellwig * for them but rather special case them here. 799adf68f21SChristoph Hellwig */ 800adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 80183a12fb7SSagi Grimberg cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) { 8027bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 80383a12fb7SSagi Grimberg cqe->status, &cqe->result); 804a0fa9647SJens Axboe return; 80557dacad5SJay Sternberg } 80657dacad5SJay Sternberg 807e9d8a0fdSKeith Busch nvmeq->cqe_seen = 1; 80883a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 80983a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 81083a12fb7SSagi Grimberg } 81157dacad5SJay Sternberg 812920d13a8SSagi Grimberg static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, 813920d13a8SSagi Grimberg struct nvme_completion *cqe) 81483a12fb7SSagi Grimberg { 815920d13a8SSagi Grimberg if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { 816920d13a8SSagi Grimberg *cqe = nvmeq->cqes[nvmeq->cq_head]; 81783a12fb7SSagi Grimberg 818920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 819920d13a8SSagi Grimberg nvmeq->cq_head = 0; 820920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 821920d13a8SSagi Grimberg } 822920d13a8SSagi Grimberg return true; 823920d13a8SSagi Grimberg } 824920d13a8SSagi Grimberg return false; 825a0fa9647SJens Axboe } 826a0fa9647SJens Axboe 827a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq) 828a0fa9647SJens Axboe { 829920d13a8SSagi Grimberg struct nvme_completion cqe; 830920d13a8SSagi Grimberg int consumed = 0; 83183a12fb7SSagi Grimberg 832920d13a8SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 83383a12fb7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 834920d13a8SSagi Grimberg consumed++; 83557dacad5SJay Sternberg } 83657dacad5SJay Sternberg 837e9d8a0fdSKeith Busch if (consumed) 838eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 83957dacad5SJay Sternberg } 84057dacad5SJay Sternberg 84157dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 84257dacad5SJay Sternberg { 84357dacad5SJay Sternberg irqreturn_t result; 84457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 84557dacad5SJay Sternberg spin_lock(&nvmeq->q_lock); 84657dacad5SJay Sternberg nvme_process_cq(nvmeq); 84757dacad5SJay Sternberg result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 84857dacad5SJay Sternberg nvmeq->cqe_seen = 0; 84957dacad5SJay Sternberg spin_unlock(&nvmeq->q_lock); 85057dacad5SJay Sternberg return result; 85157dacad5SJay Sternberg } 85257dacad5SJay Sternberg 85357dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 85457dacad5SJay Sternberg { 85557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 856d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 85757dacad5SJay Sternberg return IRQ_WAKE_THREAD; 858d783e0bdSMarta Rybczynska return IRQ_NONE; 85957dacad5SJay Sternberg } 86057dacad5SJay Sternberg 8617776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 862a0fa9647SJens Axboe { 863442e19b7SSagi Grimberg struct nvme_completion cqe; 864442e19b7SSagi Grimberg int found = 0, consumed = 0; 865a0fa9647SJens Axboe 866442e19b7SSagi Grimberg if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 867442e19b7SSagi Grimberg return 0; 868442e19b7SSagi Grimberg 869442e19b7SSagi Grimberg spin_lock_irq(&nvmeq->q_lock); 870442e19b7SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 871442e19b7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 872442e19b7SSagi Grimberg consumed++; 873442e19b7SSagi Grimberg 874442e19b7SSagi Grimberg if (tag == cqe.command_id) { 875442e19b7SSagi Grimberg found = 1; 876442e19b7SSagi Grimberg break; 877442e19b7SSagi Grimberg } 878a0fa9647SJens Axboe } 879a0fa9647SJens Axboe 880442e19b7SSagi Grimberg if (consumed) 881442e19b7SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 882442e19b7SSagi Grimberg spin_unlock_irq(&nvmeq->q_lock); 883442e19b7SSagi Grimberg 884442e19b7SSagi Grimberg return found; 885a0fa9647SJens Axboe } 886a0fa9647SJens Axboe 8877776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 8887776db1cSKeith Busch { 8897776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 8907776db1cSKeith Busch 8917776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 8927776db1cSKeith Busch } 8937776db1cSKeith Busch 894f866fc42SChristoph Hellwig static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) 89557dacad5SJay Sternberg { 896f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 8979396dec9SChristoph Hellwig struct nvme_queue *nvmeq = dev->queues[0]; 89857dacad5SJay Sternberg struct nvme_command c; 89957dacad5SJay Sternberg 90057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 90157dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 902f866fc42SChristoph Hellwig c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; 90357dacad5SJay Sternberg 9049396dec9SChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 9059396dec9SChristoph Hellwig __nvme_submit_cmd(nvmeq, &c); 9069396dec9SChristoph Hellwig spin_unlock_irq(&nvmeq->q_lock); 90757dacad5SJay Sternberg } 90857dacad5SJay Sternberg 90957dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 91057dacad5SJay Sternberg { 91157dacad5SJay Sternberg struct nvme_command c; 91257dacad5SJay Sternberg 91357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 91457dacad5SJay Sternberg c.delete_queue.opcode = opcode; 91557dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 91657dacad5SJay Sternberg 9171c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 91857dacad5SJay Sternberg } 91957dacad5SJay Sternberg 92057dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 92157dacad5SJay Sternberg struct nvme_queue *nvmeq) 92257dacad5SJay Sternberg { 92357dacad5SJay Sternberg struct nvme_command c; 92457dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 92557dacad5SJay Sternberg 92657dacad5SJay Sternberg /* 92757dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 92857dacad5SJay Sternberg * is attached to the request. 92957dacad5SJay Sternberg */ 93057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 93157dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 93257dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 93357dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 93457dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 93557dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 93657dacad5SJay Sternberg c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 93757dacad5SJay Sternberg 9381c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 93957dacad5SJay Sternberg } 94057dacad5SJay Sternberg 94157dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 94257dacad5SJay Sternberg struct nvme_queue *nvmeq) 94357dacad5SJay Sternberg { 94457dacad5SJay Sternberg struct nvme_command c; 94581c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 94657dacad5SJay Sternberg 94757dacad5SJay Sternberg /* 94857dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 94957dacad5SJay Sternberg * is attached to the request. 95057dacad5SJay Sternberg */ 95157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 95257dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 95357dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 95457dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 95557dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 95657dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 95757dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 95857dacad5SJay Sternberg 9591c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 96057dacad5SJay Sternberg } 96157dacad5SJay Sternberg 96257dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 96357dacad5SJay Sternberg { 96457dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 96557dacad5SJay Sternberg } 96657dacad5SJay Sternberg 96757dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 96857dacad5SJay Sternberg { 96957dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 97057dacad5SJay Sternberg } 97157dacad5SJay Sternberg 9722a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 97357dacad5SJay Sternberg { 974f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 975f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 97657dacad5SJay Sternberg 97727fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 97827fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 979e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 980e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 98157dacad5SJay Sternberg } 98257dacad5SJay Sternberg 983b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 984b2a0eb1aSKeith Busch { 985b2a0eb1aSKeith Busch 986b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 987b2a0eb1aSKeith Busch * NVMe Subsystem reset. 988b2a0eb1aSKeith Busch */ 989b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 990b2a0eb1aSKeith Busch 991b2a0eb1aSKeith Busch /* If there is a reset ongoing, we shouldn't reset again. */ 992b2a0eb1aSKeith Busch if (dev->ctrl.state == NVME_CTRL_RESETTING) 993b2a0eb1aSKeith Busch return false; 994b2a0eb1aSKeith Busch 995b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 996b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 997b2a0eb1aSKeith Busch */ 998b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 999b2a0eb1aSKeith Busch return false; 1000b2a0eb1aSKeith Busch 1001b2a0eb1aSKeith Busch /* If PCI error recovery process is happening, we cannot reset or 1002b2a0eb1aSKeith Busch * the recovery mechanism will surely fail. 1003b2a0eb1aSKeith Busch */ 1004b2a0eb1aSKeith Busch if (pci_channel_offline(to_pci_dev(dev->dev))) 1005b2a0eb1aSKeith Busch return false; 1006b2a0eb1aSKeith Busch 1007b2a0eb1aSKeith Busch return true; 1008b2a0eb1aSKeith Busch } 1009b2a0eb1aSKeith Busch 1010b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1011b2a0eb1aSKeith Busch { 1012b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1013b2a0eb1aSKeith Busch u16 pci_status; 1014b2a0eb1aSKeith Busch int result; 1015b2a0eb1aSKeith Busch 1016b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1017b2a0eb1aSKeith Busch &pci_status); 1018b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1019b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1020b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1021b2a0eb1aSKeith Busch csts, pci_status); 1022b2a0eb1aSKeith Busch else 1023b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1024b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1025b2a0eb1aSKeith Busch csts, result); 1026b2a0eb1aSKeith Busch } 1027b2a0eb1aSKeith Busch 102831c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 102957dacad5SJay Sternberg { 1030f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1031f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 103257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 103357dacad5SJay Sternberg struct request *abort_req; 103457dacad5SJay Sternberg struct nvme_command cmd; 1035b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1036b2a0eb1aSKeith Busch 1037b2a0eb1aSKeith Busch /* 1038b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1039b2a0eb1aSKeith Busch */ 1040b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1041b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1042b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1043d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1044b2a0eb1aSKeith Busch return BLK_EH_HANDLED; 1045b2a0eb1aSKeith Busch } 104657dacad5SJay Sternberg 104731c7c7d2SChristoph Hellwig /* 10487776db1cSKeith Busch * Did we miss an interrupt? 10497776db1cSKeith Busch */ 10507776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 10517776db1cSKeith Busch dev_warn(dev->ctrl.device, 10527776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 10537776db1cSKeith Busch req->tag, nvmeq->qid); 10547776db1cSKeith Busch return BLK_EH_HANDLED; 10557776db1cSKeith Busch } 10567776db1cSKeith Busch 10577776db1cSKeith Busch /* 1058fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1059fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1060fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1061fd634f41SChristoph Hellwig * shutdown, so we return BLK_EH_HANDLED. 1062fd634f41SChristoph Hellwig */ 1063bb8d261eSChristoph Hellwig if (dev->ctrl.state == NVME_CTRL_RESETTING) { 10641b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 1065fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1066fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1067a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 106827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1069fd634f41SChristoph Hellwig return BLK_EH_HANDLED; 1070fd634f41SChristoph Hellwig } 1071fd634f41SChristoph Hellwig 1072fd634f41SChristoph Hellwig /* 1073e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1074e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1075e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 107631c7c7d2SChristoph Hellwig */ 1077f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 10781b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 107957dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 108057dacad5SJay Sternberg req->tag, nvmeq->qid); 1081a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1082d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1083e1569a16SKeith Busch 1084e1569a16SKeith Busch /* 1085e1569a16SKeith Busch * Mark the request as handled, since the inline shutdown 1086e1569a16SKeith Busch * forces all outstanding requests to complete. 1087e1569a16SKeith Busch */ 108827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1089e1569a16SKeith Busch return BLK_EH_HANDLED; 109057dacad5SJay Sternberg } 109157dacad5SJay Sternberg 1092e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1093e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1094e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1095e7a2a87dSChristoph Hellwig } 10967bf7d778SKeith Busch iod->aborted = 1; 109757dacad5SJay Sternberg 109857dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 109957dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 110057dacad5SJay Sternberg cmd.abort.cid = req->tag; 110157dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 110257dacad5SJay Sternberg 11031b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 11041b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 110557dacad5SJay Sternberg req->tag, nvmeq->qid); 1106e7a2a87dSChristoph Hellwig 1107e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1108eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 11096bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 11106bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 111131c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 111257dacad5SJay Sternberg } 111357dacad5SJay Sternberg 1114e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1115e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1116e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 111757dacad5SJay Sternberg 111857dacad5SJay Sternberg /* 111957dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 112057dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 112157dacad5SJay Sternberg * as the device then is in a faulty state. 112257dacad5SJay Sternberg */ 112357dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 112457dacad5SJay Sternberg } 112557dacad5SJay Sternberg 112657dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 112757dacad5SJay Sternberg { 112857dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 112957dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 113057dacad5SJay Sternberg if (nvmeq->sq_cmds) 113157dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 113257dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 113357dacad5SJay Sternberg kfree(nvmeq); 113457dacad5SJay Sternberg } 113557dacad5SJay Sternberg 113657dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 113757dacad5SJay Sternberg { 113857dacad5SJay Sternberg int i; 113957dacad5SJay Sternberg 1140d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 114157dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[i]; 1142d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 114357dacad5SJay Sternberg dev->queues[i] = NULL; 114457dacad5SJay Sternberg nvme_free_queue(nvmeq); 114557dacad5SJay Sternberg } 114657dacad5SJay Sternberg } 114757dacad5SJay Sternberg 114857dacad5SJay Sternberg /** 114957dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 115057dacad5SJay Sternberg * @nvmeq - queue to suspend 115157dacad5SJay Sternberg */ 115257dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 115357dacad5SJay Sternberg { 115457dacad5SJay Sternberg int vector; 115557dacad5SJay Sternberg 115657dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 115757dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 115857dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 115957dacad5SJay Sternberg return 1; 116057dacad5SJay Sternberg } 11610ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 116257dacad5SJay Sternberg nvmeq->dev->online_queues--; 116357dacad5SJay Sternberg nvmeq->cq_vector = -1; 116457dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 116557dacad5SJay Sternberg 11661c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1167c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 116857dacad5SJay Sternberg 11690ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 117057dacad5SJay Sternberg 117157dacad5SJay Sternberg return 0; 117257dacad5SJay Sternberg } 117357dacad5SJay Sternberg 1174a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 117557dacad5SJay Sternberg { 1176a5cdb68cSKeith Busch struct nvme_queue *nvmeq = dev->queues[0]; 117757dacad5SJay Sternberg 117857dacad5SJay Sternberg if (!nvmeq) 117957dacad5SJay Sternberg return; 118057dacad5SJay Sternberg if (nvme_suspend_queue(nvmeq)) 118157dacad5SJay Sternberg return; 118257dacad5SJay Sternberg 1183a5cdb68cSKeith Busch if (shutdown) 1184a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1185a5cdb68cSKeith Busch else 118620d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 118757dacad5SJay Sternberg 118857dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 118957dacad5SJay Sternberg nvme_process_cq(nvmeq); 119057dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 119157dacad5SJay Sternberg } 119257dacad5SJay Sternberg 119357dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 119457dacad5SJay Sternberg int entry_size) 119557dacad5SJay Sternberg { 119657dacad5SJay Sternberg int q_depth = dev->q_depth; 11975fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 11985fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 119957dacad5SJay Sternberg 120057dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 120157dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 12025fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 120357dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 120457dacad5SJay Sternberg 120557dacad5SJay Sternberg /* 120657dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 120757dacad5SJay Sternberg * would be better to map queues in system memory with the 120857dacad5SJay Sternberg * original depth 120957dacad5SJay Sternberg */ 121057dacad5SJay Sternberg if (q_depth < 64) 121157dacad5SJay Sternberg return -ENOMEM; 121257dacad5SJay Sternberg } 121357dacad5SJay Sternberg 121457dacad5SJay Sternberg return q_depth; 121557dacad5SJay Sternberg } 121657dacad5SJay Sternberg 121757dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 121857dacad5SJay Sternberg int qid, int depth) 121957dacad5SJay Sternberg { 122057dacad5SJay Sternberg if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 12215fd4ce1bSChristoph Hellwig unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 12225fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 122357dacad5SJay Sternberg nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; 122457dacad5SJay Sternberg nvmeq->sq_cmds_io = dev->cmb + offset; 122557dacad5SJay Sternberg } else { 122657dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 122757dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 122857dacad5SJay Sternberg if (!nvmeq->sq_cmds) 122957dacad5SJay Sternberg return -ENOMEM; 123057dacad5SJay Sternberg } 123157dacad5SJay Sternberg 123257dacad5SJay Sternberg return 0; 123357dacad5SJay Sternberg } 123457dacad5SJay Sternberg 123557dacad5SJay Sternberg static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, 1236d3af3ecdSShaohua Li int depth, int node) 123757dacad5SJay Sternberg { 1238d3af3ecdSShaohua Li struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, 1239d3af3ecdSShaohua Li node); 124057dacad5SJay Sternberg if (!nvmeq) 124157dacad5SJay Sternberg return NULL; 124257dacad5SJay Sternberg 124357dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 124457dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 124557dacad5SJay Sternberg if (!nvmeq->cqes) 124657dacad5SJay Sternberg goto free_nvmeq; 124757dacad5SJay Sternberg 124857dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 124957dacad5SJay Sternberg goto free_cqdma; 125057dacad5SJay Sternberg 125157dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 125257dacad5SJay Sternberg nvmeq->dev = dev; 125357dacad5SJay Sternberg spin_lock_init(&nvmeq->q_lock); 125457dacad5SJay Sternberg nvmeq->cq_head = 0; 125557dacad5SJay Sternberg nvmeq->cq_phase = 1; 125657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 125757dacad5SJay Sternberg nvmeq->q_depth = depth; 125857dacad5SJay Sternberg nvmeq->qid = qid; 125957dacad5SJay Sternberg nvmeq->cq_vector = -1; 126057dacad5SJay Sternberg dev->queues[qid] = nvmeq; 1261d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 126257dacad5SJay Sternberg 126357dacad5SJay Sternberg return nvmeq; 126457dacad5SJay Sternberg 126557dacad5SJay Sternberg free_cqdma: 126657dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 126757dacad5SJay Sternberg nvmeq->cq_dma_addr); 126857dacad5SJay Sternberg free_nvmeq: 126957dacad5SJay Sternberg kfree(nvmeq); 127057dacad5SJay Sternberg return NULL; 127157dacad5SJay Sternberg } 127257dacad5SJay Sternberg 1273dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 127457dacad5SJay Sternberg { 12750ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 12760ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 12770ff199cbSChristoph Hellwig 12780ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 12790ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 12800ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12810ff199cbSChristoph Hellwig } else { 12820ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 12830ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12840ff199cbSChristoph Hellwig } 128557dacad5SJay Sternberg } 128657dacad5SJay Sternberg 128757dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 128857dacad5SJay Sternberg { 128957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 129057dacad5SJay Sternberg 129157dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 129257dacad5SJay Sternberg nvmeq->sq_tail = 0; 129357dacad5SJay Sternberg nvmeq->cq_head = 0; 129457dacad5SJay Sternberg nvmeq->cq_phase = 1; 129557dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 129657dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1297f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 129857dacad5SJay Sternberg dev->online_queues++; 129957dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 130057dacad5SJay Sternberg } 130157dacad5SJay Sternberg 130257dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 130357dacad5SJay Sternberg { 130457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 130557dacad5SJay Sternberg int result; 130657dacad5SJay Sternberg 130757dacad5SJay Sternberg nvmeq->cq_vector = qid - 1; 130857dacad5SJay Sternberg result = adapter_alloc_cq(dev, qid, nvmeq); 130957dacad5SJay Sternberg if (result < 0) 131057dacad5SJay Sternberg return result; 131157dacad5SJay Sternberg 131257dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 131357dacad5SJay Sternberg if (result < 0) 131457dacad5SJay Sternberg goto release_cq; 131557dacad5SJay Sternberg 1316161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 1317dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 131857dacad5SJay Sternberg if (result < 0) 131957dacad5SJay Sternberg goto release_sq; 132057dacad5SJay Sternberg 132157dacad5SJay Sternberg return result; 132257dacad5SJay Sternberg 132357dacad5SJay Sternberg release_sq: 132457dacad5SJay Sternberg adapter_delete_sq(dev, qid); 132557dacad5SJay Sternberg release_cq: 132657dacad5SJay Sternberg adapter_delete_cq(dev, qid); 132757dacad5SJay Sternberg return result; 132857dacad5SJay Sternberg } 132957dacad5SJay Sternberg 1330f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 133157dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 133277f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 133357dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 133457dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 13350350815aSChristoph Hellwig .init_request = nvme_init_request, 133657dacad5SJay Sternberg .timeout = nvme_timeout, 133757dacad5SJay Sternberg }; 133857dacad5SJay Sternberg 1339f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 134057dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 134177f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 134257dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 134357dacad5SJay Sternberg .init_request = nvme_init_request, 1344dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 134557dacad5SJay Sternberg .timeout = nvme_timeout, 1346a0fa9647SJens Axboe .poll = nvme_poll, 134757dacad5SJay Sternberg }; 134857dacad5SJay Sternberg 134957dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 135057dacad5SJay Sternberg { 13511c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 135269d9a99cSKeith Busch /* 135369d9a99cSKeith Busch * If the controller was reset during removal, it's possible 135469d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 135569d9a99cSKeith Busch * queue to flush these to completion. 135669d9a99cSKeith Busch */ 1357c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 13581c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 135957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 136057dacad5SJay Sternberg } 136157dacad5SJay Sternberg } 136257dacad5SJay Sternberg 136357dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 136457dacad5SJay Sternberg { 13651c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 136657dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 136757dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1368e3e9d50cSKeith Busch 1369e3e9d50cSKeith Busch /* 1370e3e9d50cSKeith Busch * Subtract one to leave an empty queue entry for 'Full Queue' 1371e3e9d50cSKeith Busch * condition. See NVM-Express 1.2 specification, section 4.1.2. 1372e3e9d50cSKeith Busch */ 1373e3e9d50cSKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; 137457dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 137557dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 137657dacad5SJay Sternberg dev->admin_tagset.cmd_size = nvme_cmd_size(dev); 1377d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 137857dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 137957dacad5SJay Sternberg 138057dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 138157dacad5SJay Sternberg return -ENOMEM; 138234b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 138357dacad5SJay Sternberg 13841c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 13851c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 138657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 138757dacad5SJay Sternberg return -ENOMEM; 138857dacad5SJay Sternberg } 13891c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 139057dacad5SJay Sternberg nvme_dev_remove_admin(dev); 13911c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 139257dacad5SJay Sternberg return -ENODEV; 139357dacad5SJay Sternberg } 139457dacad5SJay Sternberg } else 1395c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 139657dacad5SJay Sternberg 139757dacad5SJay Sternberg return 0; 139857dacad5SJay Sternberg } 139957dacad5SJay Sternberg 140097f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 140197f6ef64SXu Yu { 140297f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 140397f6ef64SXu Yu } 140497f6ef64SXu Yu 140597f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 140697f6ef64SXu Yu { 140797f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 140897f6ef64SXu Yu 140997f6ef64SXu Yu if (size <= dev->bar_mapped_size) 141097f6ef64SXu Yu return 0; 141197f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 141297f6ef64SXu Yu return -ENOMEM; 141397f6ef64SXu Yu if (dev->bar) 141497f6ef64SXu Yu iounmap(dev->bar); 141597f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 141697f6ef64SXu Yu if (!dev->bar) { 141797f6ef64SXu Yu dev->bar_mapped_size = 0; 141897f6ef64SXu Yu return -ENOMEM; 141997f6ef64SXu Yu } 142097f6ef64SXu Yu dev->bar_mapped_size = size; 142197f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 142297f6ef64SXu Yu 142397f6ef64SXu Yu return 0; 142497f6ef64SXu Yu } 142597f6ef64SXu Yu 142601ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 142757dacad5SJay Sternberg { 142857dacad5SJay Sternberg int result; 142957dacad5SJay Sternberg u32 aqa; 143057dacad5SJay Sternberg struct nvme_queue *nvmeq; 143157dacad5SJay Sternberg 143297f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 143397f6ef64SXu Yu if (result < 0) 143497f6ef64SXu Yu return result; 143597f6ef64SXu Yu 14368ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 143720d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 143857dacad5SJay Sternberg 14397a67cbeaSChristoph Hellwig if (dev->subsystem && 14407a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 14417a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 144257dacad5SJay Sternberg 144320d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 144457dacad5SJay Sternberg if (result < 0) 144557dacad5SJay Sternberg return result; 144657dacad5SJay Sternberg 144757dacad5SJay Sternberg nvmeq = dev->queues[0]; 144857dacad5SJay Sternberg if (!nvmeq) { 1449d3af3ecdSShaohua Li nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 1450d3af3ecdSShaohua Li dev_to_node(dev->dev)); 145157dacad5SJay Sternberg if (!nvmeq) 145257dacad5SJay Sternberg return -ENOMEM; 145357dacad5SJay Sternberg } 145457dacad5SJay Sternberg 145557dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 145657dacad5SJay Sternberg aqa |= aqa << 16; 145757dacad5SJay Sternberg 14587a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 14597a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 14607a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 146157dacad5SJay Sternberg 146220d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 146357dacad5SJay Sternberg if (result) 1464d4875622SKeith Busch return result; 146557dacad5SJay Sternberg 146657dacad5SJay Sternberg nvmeq->cq_vector = 0; 1467161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1468dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 146957dacad5SJay Sternberg if (result) { 147057dacad5SJay Sternberg nvmeq->cq_vector = -1; 1471d4875622SKeith Busch return result; 147257dacad5SJay Sternberg } 147357dacad5SJay Sternberg 147457dacad5SJay Sternberg return result; 147557dacad5SJay Sternberg } 147657dacad5SJay Sternberg 1477749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 147857dacad5SJay Sternberg { 1479949928c1SKeith Busch unsigned i, max; 1480749941f2SChristoph Hellwig int ret = 0; 148157dacad5SJay Sternberg 1482d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1483d3af3ecdSShaohua Li /* vector == qid - 1, match nvme_create_queue */ 1484d3af3ecdSShaohua Li if (!nvme_alloc_queue(dev, i, dev->q_depth, 1485d3af3ecdSShaohua Li pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { 1486749941f2SChristoph Hellwig ret = -ENOMEM; 148757dacad5SJay Sternberg break; 1488749941f2SChristoph Hellwig } 1489749941f2SChristoph Hellwig } 149057dacad5SJay Sternberg 1491d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1492949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1493749941f2SChristoph Hellwig ret = nvme_create_queue(dev->queues[i], i); 1494d4875622SKeith Busch if (ret) 149557dacad5SJay Sternberg break; 149657dacad5SJay Sternberg } 149757dacad5SJay Sternberg 1498749941f2SChristoph Hellwig /* 1499749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 1500749941f2SChristoph Hellwig * than the desired aount of queues, and even a controller without 1501749941f2SChristoph Hellwig * I/O queues an still be used to issue admin commands. This might 1502749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1503749941f2SChristoph Hellwig */ 1504749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 150557dacad5SJay Sternberg } 150657dacad5SJay Sternberg 1507202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1508202021c1SStephen Bates struct device_attribute *attr, 1509202021c1SStephen Bates char *buf) 1510202021c1SStephen Bates { 1511202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1512202021c1SStephen Bates 1513c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1514202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1515202021c1SStephen Bates } 1516202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1517202021c1SStephen Bates 151857dacad5SJay Sternberg static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 151957dacad5SJay Sternberg { 152057dacad5SJay Sternberg u64 szu, size, offset; 152157dacad5SJay Sternberg resource_size_t bar_size; 152257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 152357dacad5SJay Sternberg void __iomem *cmb; 152457dacad5SJay Sternberg dma_addr_t dma_addr; 152557dacad5SJay Sternberg 15267a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 152757dacad5SJay Sternberg if (!(NVME_CMB_SZ(dev->cmbsz))) 152857dacad5SJay Sternberg return NULL; 1529202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 153057dacad5SJay Sternberg 1531202021c1SStephen Bates if (!use_cmb_sqes) 1532202021c1SStephen Bates return NULL; 153357dacad5SJay Sternberg 153457dacad5SJay Sternberg szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 153557dacad5SJay Sternberg size = szu * NVME_CMB_SZ(dev->cmbsz); 1536202021c1SStephen Bates offset = szu * NVME_CMB_OFST(dev->cmbloc); 1537202021c1SStephen Bates bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); 153857dacad5SJay Sternberg 153957dacad5SJay Sternberg if (offset > bar_size) 154057dacad5SJay Sternberg return NULL; 154157dacad5SJay Sternberg 154257dacad5SJay Sternberg /* 154357dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 154457dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 154557dacad5SJay Sternberg * the reported size of the BAR 154657dacad5SJay Sternberg */ 154757dacad5SJay Sternberg if (size > bar_size - offset) 154857dacad5SJay Sternberg size = bar_size - offset; 154957dacad5SJay Sternberg 1550202021c1SStephen Bates dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; 155157dacad5SJay Sternberg cmb = ioremap_wc(dma_addr, size); 155257dacad5SJay Sternberg if (!cmb) 155357dacad5SJay Sternberg return NULL; 155457dacad5SJay Sternberg 155557dacad5SJay Sternberg dev->cmb_dma_addr = dma_addr; 155657dacad5SJay Sternberg dev->cmb_size = size; 155757dacad5SJay Sternberg return cmb; 155857dacad5SJay Sternberg } 155957dacad5SJay Sternberg 156057dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 156157dacad5SJay Sternberg { 156257dacad5SJay Sternberg if (dev->cmb) { 156357dacad5SJay Sternberg iounmap(dev->cmb); 156457dacad5SJay Sternberg dev->cmb = NULL; 1565f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1566f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1567f63572dfSJon Derrick dev->cmbsz = 0; 1568f63572dfSJon Derrick } 156957dacad5SJay Sternberg } 157057dacad5SJay Sternberg 157187ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 157257dacad5SJay Sternberg { 15734033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 157487ad72a5SChristoph Hellwig struct nvme_command c; 157587ad72a5SChristoph Hellwig int ret; 157687ad72a5SChristoph Hellwig 157787ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 157887ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 157987ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 158087ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 158187ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 158287ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 158387ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 158487ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 158587ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 158687ad72a5SChristoph Hellwig 158787ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 158887ad72a5SChristoph Hellwig if (ret) { 158987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 159087ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 159187ad72a5SChristoph Hellwig ret, bits); 159287ad72a5SChristoph Hellwig } 159387ad72a5SChristoph Hellwig return ret; 159487ad72a5SChristoph Hellwig } 159587ad72a5SChristoph Hellwig 159687ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 159787ad72a5SChristoph Hellwig { 159887ad72a5SChristoph Hellwig int i; 159987ad72a5SChristoph Hellwig 160087ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 160187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 160287ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 160387ad72a5SChristoph Hellwig 160487ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 160587ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 160687ad72a5SChristoph Hellwig } 160787ad72a5SChristoph Hellwig 160887ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 160987ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 16104033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 16114033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 16124033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 161387ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 161487ad72a5SChristoph Hellwig } 161587ad72a5SChristoph Hellwig 161692dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 161792dc6895SChristoph Hellwig u32 chunk_size) 161887ad72a5SChristoph Hellwig { 161987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 162092dc6895SChristoph Hellwig u32 max_entries, len; 16214033f35dSChristoph Hellwig dma_addr_t descs_dma; 16222ee0e4edSDan Carpenter int i = 0; 162387ad72a5SChristoph Hellwig void **bufs; 16242ee0e4edSDan Carpenter u64 size = 0, tmp; 162587ad72a5SChristoph Hellwig 162687ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 162787ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 162887ad72a5SChristoph Hellwig max_entries = tmp; 1629044a9df1SChristoph Hellwig 1630044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1631044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1632044a9df1SChristoph Hellwig 16334033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 16344033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 163587ad72a5SChristoph Hellwig if (!descs) 163687ad72a5SChristoph Hellwig goto out; 163787ad72a5SChristoph Hellwig 163887ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 163987ad72a5SChristoph Hellwig if (!bufs) 164087ad72a5SChristoph Hellwig goto out_free_descs; 164187ad72a5SChristoph Hellwig 164250cdb7c6SChristoph Hellwig for (size = 0; size < preferred; size += len) { 164387ad72a5SChristoph Hellwig dma_addr_t dma_addr; 164487ad72a5SChristoph Hellwig 164550cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 164687ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 164787ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 164887ad72a5SChristoph Hellwig if (!bufs[i]) 164987ad72a5SChristoph Hellwig break; 165087ad72a5SChristoph Hellwig 165187ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 165287ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 165387ad72a5SChristoph Hellwig i++; 165487ad72a5SChristoph Hellwig } 165587ad72a5SChristoph Hellwig 165692dc6895SChristoph Hellwig if (!size) 165787ad72a5SChristoph Hellwig goto out_free_bufs; 165887ad72a5SChristoph Hellwig 165987ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 166087ad72a5SChristoph Hellwig dev->host_mem_size = size; 166187ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 16624033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 166387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 166487ad72a5SChristoph Hellwig return 0; 166587ad72a5SChristoph Hellwig 166687ad72a5SChristoph Hellwig out_free_bufs: 166787ad72a5SChristoph Hellwig while (--i >= 0) { 166887ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 166987ad72a5SChristoph Hellwig 167087ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 167187ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 167287ad72a5SChristoph Hellwig } 167387ad72a5SChristoph Hellwig 167487ad72a5SChristoph Hellwig kfree(bufs); 167587ad72a5SChristoph Hellwig out_free_descs: 16764033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 16774033f35dSChristoph Hellwig descs_dma); 167887ad72a5SChristoph Hellwig out: 167987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 168087ad72a5SChristoph Hellwig return -ENOMEM; 168187ad72a5SChristoph Hellwig } 168287ad72a5SChristoph Hellwig 168392dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 168492dc6895SChristoph Hellwig { 168592dc6895SChristoph Hellwig u32 chunk_size; 168692dc6895SChristoph Hellwig 168792dc6895SChristoph Hellwig /* start big and work our way down */ 168830f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1689044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 169092dc6895SChristoph Hellwig chunk_size /= 2) { 169192dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 169292dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 169392dc6895SChristoph Hellwig return 0; 169492dc6895SChristoph Hellwig nvme_free_host_mem(dev); 169592dc6895SChristoph Hellwig } 169692dc6895SChristoph Hellwig } 169792dc6895SChristoph Hellwig 169892dc6895SChristoph Hellwig return -ENOMEM; 169992dc6895SChristoph Hellwig } 170092dc6895SChristoph Hellwig 17019620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 170287ad72a5SChristoph Hellwig { 170387ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 170487ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 170587ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 170687ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 17079620cfbaSChristoph Hellwig int ret = 0; 170887ad72a5SChristoph Hellwig 170987ad72a5SChristoph Hellwig preferred = min(preferred, max); 171087ad72a5SChristoph Hellwig if (min > max) { 171187ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 171287ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 171387ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 171487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 17159620cfbaSChristoph Hellwig return 0; 171687ad72a5SChristoph Hellwig } 171787ad72a5SChristoph Hellwig 171887ad72a5SChristoph Hellwig /* 171987ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 172087ad72a5SChristoph Hellwig */ 172187ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 172287ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 172387ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 172487ad72a5SChristoph Hellwig else 172587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 172687ad72a5SChristoph Hellwig } 172787ad72a5SChristoph Hellwig 172887ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 172992dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 173092dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 173192dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 17329620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 173387ad72a5SChristoph Hellwig } 173487ad72a5SChristoph Hellwig 173592dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 173692dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 173792dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 173892dc6895SChristoph Hellwig } 173992dc6895SChristoph Hellwig 17409620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 17419620cfbaSChristoph Hellwig if (ret) 174287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 17439620cfbaSChristoph Hellwig return ret; 174457dacad5SJay Sternberg } 174557dacad5SJay Sternberg 174657dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 174757dacad5SJay Sternberg { 174857dacad5SJay Sternberg struct nvme_queue *adminq = dev->queues[0]; 174957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 175097f6ef64SXu Yu int result, nr_io_queues; 175197f6ef64SXu Yu unsigned long size; 175257dacad5SJay Sternberg 1753425a17cbSChristoph Hellwig nr_io_queues = num_present_cpus(); 17549a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 17559a0be7abSChristoph Hellwig if (result < 0) 175657dacad5SJay Sternberg return result; 17579a0be7abSChristoph Hellwig 1758f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1759a5229050SKeith Busch return 0; 176057dacad5SJay Sternberg 176157dacad5SJay Sternberg if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 176257dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 176357dacad5SJay Sternberg sizeof(struct nvme_command)); 176457dacad5SJay Sternberg if (result > 0) 176557dacad5SJay Sternberg dev->q_depth = result; 176657dacad5SJay Sternberg else 176757dacad5SJay Sternberg nvme_release_cmb(dev); 176857dacad5SJay Sternberg } 176957dacad5SJay Sternberg 177057dacad5SJay Sternberg do { 177197f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 177297f6ef64SXu Yu result = nvme_remap_bar(dev, size); 177397f6ef64SXu Yu if (!result) 177457dacad5SJay Sternberg break; 177557dacad5SJay Sternberg if (!--nr_io_queues) 177657dacad5SJay Sternberg return -ENOMEM; 177757dacad5SJay Sternberg } while (1); 177857dacad5SJay Sternberg adminq->q_db = dev->dbs; 177957dacad5SJay Sternberg 178057dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 17810ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 178257dacad5SJay Sternberg 178357dacad5SJay Sternberg /* 178457dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 178557dacad5SJay Sternberg * setting up the full range we need. 178657dacad5SJay Sternberg */ 1787dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 1788dca51e78SChristoph Hellwig nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, 1789dca51e78SChristoph Hellwig PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); 1790dca51e78SChristoph Hellwig if (nr_io_queues <= 0) 1791dca51e78SChristoph Hellwig return -EIO; 1792dca51e78SChristoph Hellwig dev->max_qid = nr_io_queues; 179357dacad5SJay Sternberg 179457dacad5SJay Sternberg /* 179557dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 179657dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 179757dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 179857dacad5SJay Sternberg * number of interrupts. 179957dacad5SJay Sternberg */ 180057dacad5SJay Sternberg 1801dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 180257dacad5SJay Sternberg if (result) { 180357dacad5SJay Sternberg adminq->cq_vector = -1; 1804d4875622SKeith Busch return result; 180557dacad5SJay Sternberg } 1806749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 180757dacad5SJay Sternberg } 180857dacad5SJay Sternberg 18092a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1810db3cbfffSKeith Busch { 1811db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1812db3cbfffSKeith Busch 1813db3cbfffSKeith Busch blk_mq_free_request(req); 1814db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1815db3cbfffSKeith Busch } 1816db3cbfffSKeith Busch 18172a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1818db3cbfffSKeith Busch { 1819db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1820db3cbfffSKeith Busch 1821db3cbfffSKeith Busch if (!error) { 1822db3cbfffSKeith Busch unsigned long flags; 1823db3cbfffSKeith Busch 18242e39e0f6SMing Lin /* 18252e39e0f6SMing Lin * We might be called with the AQ q_lock held 18262e39e0f6SMing Lin * and the I/O queue q_lock should always 18272e39e0f6SMing Lin * nest inside the AQ one. 18282e39e0f6SMing Lin */ 18292e39e0f6SMing Lin spin_lock_irqsave_nested(&nvmeq->q_lock, flags, 18302e39e0f6SMing Lin SINGLE_DEPTH_NESTING); 1831db3cbfffSKeith Busch nvme_process_cq(nvmeq); 1832db3cbfffSKeith Busch spin_unlock_irqrestore(&nvmeq->q_lock, flags); 1833db3cbfffSKeith Busch } 1834db3cbfffSKeith Busch 1835db3cbfffSKeith Busch nvme_del_queue_end(req, error); 1836db3cbfffSKeith Busch } 1837db3cbfffSKeith Busch 1838db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1839db3cbfffSKeith Busch { 1840db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1841db3cbfffSKeith Busch struct request *req; 1842db3cbfffSKeith Busch struct nvme_command cmd; 1843db3cbfffSKeith Busch 1844db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 1845db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 1846db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1847db3cbfffSKeith Busch 1848eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1849db3cbfffSKeith Busch if (IS_ERR(req)) 1850db3cbfffSKeith Busch return PTR_ERR(req); 1851db3cbfffSKeith Busch 1852db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 1853db3cbfffSKeith Busch req->end_io_data = nvmeq; 1854db3cbfffSKeith Busch 1855db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 1856db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 1857db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 1858db3cbfffSKeith Busch return 0; 1859db3cbfffSKeith Busch } 1860db3cbfffSKeith Busch 186170659060SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) 1862db3cbfffSKeith Busch { 186370659060SKeith Busch int pass; 1864db3cbfffSKeith Busch unsigned long timeout; 1865db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 1866db3cbfffSKeith Busch 1867db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 1868014a0d60SKeith Busch int sent = 0, i = queues; 1869db3cbfffSKeith Busch 1870db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 1871db3cbfffSKeith Busch retry: 1872db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 1873c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 1874c21377f8SGabriel Krisman Bertazi if (nvme_delete_queue(dev->queues[i], opcode)) 1875db3cbfffSKeith Busch break; 1876c21377f8SGabriel Krisman Bertazi 1877db3cbfffSKeith Busch while (sent--) { 1878db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 1879db3cbfffSKeith Busch if (timeout == 0) 1880db3cbfffSKeith Busch return; 1881db3cbfffSKeith Busch if (i) 1882db3cbfffSKeith Busch goto retry; 1883db3cbfffSKeith Busch } 1884db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 1885db3cbfffSKeith Busch } 1886db3cbfffSKeith Busch } 1887db3cbfffSKeith Busch 188857dacad5SJay Sternberg /* 188957dacad5SJay Sternberg * Return: error value if an error occurred setting up the queues or calling 189057dacad5SJay Sternberg * Identify Device. 0 if these succeeded, even if adding some of the 189157dacad5SJay Sternberg * namespaces failed. At the moment, these failures are silent. TBD which 189257dacad5SJay Sternberg * failures should be reported. 189357dacad5SJay Sternberg */ 189457dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 189557dacad5SJay Sternberg { 18965bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 189757dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 189857dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 189957dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 190057dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 190157dacad5SJay Sternberg dev->tagset.queue_depth = 190257dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 190357dacad5SJay Sternberg dev->tagset.cmd_size = nvme_cmd_size(dev); 190457dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 190557dacad5SJay Sternberg dev->tagset.driver_data = dev; 190657dacad5SJay Sternberg 190757dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->tagset)) 190857dacad5SJay Sternberg return 0; 19095bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 1910f9f38e33SHelen Koike 1911f9f38e33SHelen Koike nvme_dbbuf_set(dev); 1912949928c1SKeith Busch } else { 1913949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 1914949928c1SKeith Busch 1915949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 1916949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 191757dacad5SJay Sternberg } 1918949928c1SKeith Busch 191957dacad5SJay Sternberg return 0; 192057dacad5SJay Sternberg } 192157dacad5SJay Sternberg 1922b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 192357dacad5SJay Sternberg { 1924b00a726aSKeith Busch int result = -ENOMEM; 192557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 192657dacad5SJay Sternberg 192757dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 192857dacad5SJay Sternberg return result; 192957dacad5SJay Sternberg 193057dacad5SJay Sternberg pci_set_master(pdev); 193157dacad5SJay Sternberg 193257dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 193357dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 193457dacad5SJay Sternberg goto disable; 193557dacad5SJay Sternberg 19367a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 193757dacad5SJay Sternberg result = -ENODEV; 1938b00a726aSKeith Busch goto disable; 193957dacad5SJay Sternberg } 194057dacad5SJay Sternberg 194157dacad5SJay Sternberg /* 1942a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 1943a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 1944a5229050SKeith Busch * adjust this later. 194557dacad5SJay Sternberg */ 1946dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1947dca51e78SChristoph Hellwig if (result < 0) 1948dca51e78SChristoph Hellwig return result; 194957dacad5SJay Sternberg 195020d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 19517a67cbeaSChristoph Hellwig 195220d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 1953b27c1e68Sweiping zhang io_queue_depth); 195420d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 19557a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 19561f390c1fSStephan Günther 19571f390c1fSStephan Günther /* 19581f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 19591f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 19601f390c1fSStephan Günther */ 19611f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 19621f390c1fSStephan Günther dev->q_depth = 2; 19639bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 19649bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 19651f390c1fSStephan Günther dev->q_depth); 1966d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 1967d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 196820d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 1969d554b5e1SMartin K. Petersen dev->q_depth = 64; 1970d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 1971d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 19721f390c1fSStephan Günther } 19731f390c1fSStephan Günther 1974202021c1SStephen Bates /* 1975202021c1SStephen Bates * CMBs can currently only exist on >=1.2 PCIe devices. We only 19761c78f773SMax Gurtovoy * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group 19771c78f773SMax Gurtovoy * has no name we can pass NULL as final argument to 19781c78f773SMax Gurtovoy * sysfs_add_file_to_group. 1979202021c1SStephen Bates */ 1980202021c1SStephen Bates 19818ef2074dSGabriel Krisman Bertazi if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { 198257dacad5SJay Sternberg dev->cmb = nvme_map_cmb(dev); 19831c78f773SMax Gurtovoy if (dev->cmb) { 1984202021c1SStephen Bates if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1985202021c1SStephen Bates &dev_attr_cmb.attr, NULL)) 19869bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 1987202021c1SStephen Bates "failed to add sysfs attribute for CMB\n"); 1988202021c1SStephen Bates } 1989202021c1SStephen Bates } 1990202021c1SStephen Bates 1991a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 1992a0a3408eSKeith Busch pci_save_state(pdev); 199357dacad5SJay Sternberg return 0; 199457dacad5SJay Sternberg 199557dacad5SJay Sternberg disable: 199657dacad5SJay Sternberg pci_disable_device(pdev); 199757dacad5SJay Sternberg return result; 199857dacad5SJay Sternberg } 199957dacad5SJay Sternberg 200057dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 200157dacad5SJay Sternberg { 2002b00a726aSKeith Busch if (dev->bar) 2003b00a726aSKeith Busch iounmap(dev->bar); 2004a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2005b00a726aSKeith Busch } 2006b00a726aSKeith Busch 2007b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2008b00a726aSKeith Busch { 200957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 201057dacad5SJay Sternberg 2011f63572dfSJon Derrick nvme_release_cmb(dev); 2012dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 201357dacad5SJay Sternberg 2014a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2015a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 201657dacad5SJay Sternberg pci_disable_device(pdev); 201757dacad5SJay Sternberg } 2018a0a3408eSKeith Busch } 201957dacad5SJay Sternberg 2020a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 202157dacad5SJay Sternberg { 202270659060SKeith Busch int i, queues; 2023302ad8ccSKeith Busch bool dead = true; 2024302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 202557dacad5SJay Sternberg 202677bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2027302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2028302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2029302ad8ccSKeith Busch 2030ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2031ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2032302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2033302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2034302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 203557dacad5SJay Sternberg } 2036c21377f8SGabriel Krisman Bertazi 2037302ad8ccSKeith Busch /* 2038302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2039302ad8ccSKeith Busch * doing a safe shutdown. 2040302ad8ccSKeith Busch */ 204187ad72a5SChristoph Hellwig if (!dead) { 204287ad72a5SChristoph Hellwig if (shutdown) 2043302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 204487ad72a5SChristoph Hellwig 204587ad72a5SChristoph Hellwig /* 204687ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 204787ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 204887ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 204987ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 205087ad72a5SChristoph Hellwig */ 205187ad72a5SChristoph Hellwig if (dev->host_mem_descs) 205287ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 205387ad72a5SChristoph Hellwig 205487ad72a5SChristoph Hellwig } 2055302ad8ccSKeith Busch nvme_stop_queues(&dev->ctrl); 2056302ad8ccSKeith Busch 205770659060SKeith Busch queues = dev->online_queues - 1; 2058d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i > 0; i--) 2059c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[i]); 2060c21377f8SGabriel Krisman Bertazi 2061302ad8ccSKeith Busch if (dead) { 206282469c59SGabriel Krisman Bertazi /* A device might become IO incapable very soon during 206382469c59SGabriel Krisman Bertazi * probe, before the admin queue is configured. Thus, 206482469c59SGabriel Krisman Bertazi * queue_count can be 0 here. 206582469c59SGabriel Krisman Bertazi */ 2066d858e5f0SSagi Grimberg if (dev->ctrl.queue_count) 2067c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[0]); 206857dacad5SJay Sternberg } else { 206970659060SKeith Busch nvme_disable_io_queues(dev, queues); 2070a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 207157dacad5SJay Sternberg } 2072b00a726aSKeith Busch nvme_pci_disable(dev); 207357dacad5SJay Sternberg 2074e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2075e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2076302ad8ccSKeith Busch 2077302ad8ccSKeith Busch /* 2078302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2079302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2080302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2081302ad8ccSKeith Busch */ 2082302ad8ccSKeith Busch if (shutdown) 2083302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 208477bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 208557dacad5SJay Sternberg } 208657dacad5SJay Sternberg 208757dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 208857dacad5SJay Sternberg { 208957dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 209057dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 209157dacad5SJay Sternberg if (!dev->prp_page_pool) 209257dacad5SJay Sternberg return -ENOMEM; 209357dacad5SJay Sternberg 209457dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 209557dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 209657dacad5SJay Sternberg 256, 256, 0); 209757dacad5SJay Sternberg if (!dev->prp_small_pool) { 209857dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 209957dacad5SJay Sternberg return -ENOMEM; 210057dacad5SJay Sternberg } 210157dacad5SJay Sternberg return 0; 210257dacad5SJay Sternberg } 210357dacad5SJay Sternberg 210457dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 210557dacad5SJay Sternberg { 210657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 210757dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 210857dacad5SJay Sternberg } 210957dacad5SJay Sternberg 21101673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 211157dacad5SJay Sternberg { 21121673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 211357dacad5SJay Sternberg 2114f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 211557dacad5SJay Sternberg put_device(dev->dev); 211657dacad5SJay Sternberg if (dev->tagset.tags) 211757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 21181c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 21191c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 212057dacad5SJay Sternberg kfree(dev->queues); 2121e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 212257dacad5SJay Sternberg kfree(dev); 212357dacad5SJay Sternberg } 212457dacad5SJay Sternberg 2125f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2126f58944e2SKeith Busch { 2127237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2128f58944e2SKeith Busch 2129f58944e2SKeith Busch kref_get(&dev->ctrl.kref); 213069d9a99cSKeith Busch nvme_dev_disable(dev, false); 2131f58944e2SKeith Busch if (!schedule_work(&dev->remove_work)) 2132f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2133f58944e2SKeith Busch } 2134f58944e2SKeith Busch 2135fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 213657dacad5SJay Sternberg { 2137d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2138d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2139a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2140f58944e2SKeith Busch int result = -ENODEV; 214157dacad5SJay Sternberg 214282b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2143fd634f41SChristoph Hellwig goto out; 2144fd634f41SChristoph Hellwig 2145fd634f41SChristoph Hellwig /* 2146fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2147fd634f41SChristoph Hellwig * moving on. 2148fd634f41SChristoph Hellwig */ 2149b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2150a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2151fd634f41SChristoph Hellwig 2152b00a726aSKeith Busch result = nvme_pci_enable(dev); 215357dacad5SJay Sternberg if (result) 215457dacad5SJay Sternberg goto out; 215557dacad5SJay Sternberg 215601ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 215757dacad5SJay Sternberg if (result) 2158f58944e2SKeith Busch goto out; 215957dacad5SJay Sternberg 216057dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 216157dacad5SJay Sternberg if (result) 2162f58944e2SKeith Busch goto out; 216357dacad5SJay Sternberg 2164ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2165ce4541f4SChristoph Hellwig if (result) 2166f58944e2SKeith Busch goto out; 2167ce4541f4SChristoph Hellwig 2168e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2169e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 21704f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 21714f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2172e286bcfcSScott Bauer else if (was_suspend) 21734f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2174e286bcfcSScott Bauer } else { 2175e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2176e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2177e286bcfcSScott Bauer } 2178a98e58e5SScott Bauer 2179f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2180f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2181f9f38e33SHelen Koike if (result) 2182f9f38e33SHelen Koike dev_warn(dev->dev, 2183f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2184f9f38e33SHelen Koike } 2185f9f38e33SHelen Koike 21869620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 21879620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 21889620cfbaSChristoph Hellwig if (result < 0) 21899620cfbaSChristoph Hellwig goto out; 21909620cfbaSChristoph Hellwig } 219187ad72a5SChristoph Hellwig 219257dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 219357dacad5SJay Sternberg if (result) 2194f58944e2SKeith Busch goto out; 219557dacad5SJay Sternberg 219621f033f7SKeith Busch /* 219757dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 219857dacad5SJay Sternberg * any working I/O queue. 219957dacad5SJay Sternberg */ 220057dacad5SJay Sternberg if (dev->online_queues < 2) { 22011b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 22023b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 22035bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 220457dacad5SJay Sternberg } else { 220525646264SKeith Busch nvme_start_queues(&dev->ctrl); 2206302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 220757dacad5SJay Sternberg nvme_dev_add(dev); 2208302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 220957dacad5SJay Sternberg } 221057dacad5SJay Sternberg 2211bb8d261eSChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2212bb8d261eSChristoph Hellwig dev_warn(dev->ctrl.device, "failed to mark controller live\n"); 2213bb8d261eSChristoph Hellwig goto out; 2214bb8d261eSChristoph Hellwig } 221592911a55SChristoph Hellwig 2216d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 221757dacad5SJay Sternberg return; 221857dacad5SJay Sternberg 221957dacad5SJay Sternberg out: 2220f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 222157dacad5SJay Sternberg } 222257dacad5SJay Sternberg 22235c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 222457dacad5SJay Sternberg { 22255c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 222657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 222757dacad5SJay Sternberg 222869d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 222957dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2230921920abSKeith Busch device_release_driver(&pdev->dev); 22311673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 223257dacad5SJay Sternberg } 223357dacad5SJay Sternberg 22341c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 223557dacad5SJay Sternberg { 22361c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 22371c63dc66SChristoph Hellwig return 0; 223857dacad5SJay Sternberg } 22391c63dc66SChristoph Hellwig 22405fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 22415fd4ce1bSChristoph Hellwig { 22425fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 22435fd4ce1bSChristoph Hellwig return 0; 22445fd4ce1bSChristoph Hellwig } 22455fd4ce1bSChristoph Hellwig 22467fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 22477fd8930fSChristoph Hellwig { 22487fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 22497fd8930fSChristoph Hellwig return 0; 22507fd8930fSChristoph Hellwig } 22517fd8930fSChristoph Hellwig 22521c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 22531a353d85SMing Lin .name = "pcie", 2254e439bb12SSagi Grimberg .module = THIS_MODULE, 2255c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 22561c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 22575fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 22587fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 22591673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2260f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 22611c63dc66SChristoph Hellwig }; 226257dacad5SJay Sternberg 2263b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2264b00a726aSKeith Busch { 2265b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2266b00a726aSKeith Busch 2267a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2268b00a726aSKeith Busch return -ENODEV; 2269b00a726aSKeith Busch 227097f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2271b00a726aSKeith Busch goto release; 2272b00a726aSKeith Busch 2273b00a726aSKeith Busch return 0; 2274b00a726aSKeith Busch release: 2275a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2276b00a726aSKeith Busch return -ENODEV; 2277b00a726aSKeith Busch } 2278b00a726aSKeith Busch 2279ff5350a8SAndy Lutomirski static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) 2280ff5350a8SAndy Lutomirski { 2281ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2282ff5350a8SAndy Lutomirski /* 2283ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2284ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2285ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2286ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2287ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2288ff5350a8SAndy Lutomirski * laptops. 2289ff5350a8SAndy Lutomirski */ 2290ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2291ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2292ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2293ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 2294ff5350a8SAndy Lutomirski } 2295ff5350a8SAndy Lutomirski 2296ff5350a8SAndy Lutomirski return 0; 2297ff5350a8SAndy Lutomirski } 2298ff5350a8SAndy Lutomirski 229957dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 230057dacad5SJay Sternberg { 230157dacad5SJay Sternberg int node, result = -ENOMEM; 230257dacad5SJay Sternberg struct nvme_dev *dev; 2303ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 230457dacad5SJay Sternberg 230557dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 230657dacad5SJay Sternberg if (node == NUMA_NO_NODE) 23072fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 230857dacad5SJay Sternberg 230957dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 231057dacad5SJay Sternberg if (!dev) 231157dacad5SJay Sternberg return -ENOMEM; 231257dacad5SJay Sternberg dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), 231357dacad5SJay Sternberg GFP_KERNEL, node); 231457dacad5SJay Sternberg if (!dev->queues) 231557dacad5SJay Sternberg goto free; 231657dacad5SJay Sternberg 231757dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 231857dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 231957dacad5SJay Sternberg 2320b00a726aSKeith Busch result = nvme_dev_map(dev); 2321b00a726aSKeith Busch if (result) 2322b00c9b7aSChristophe JAILLET goto put_pci; 2323b00a726aSKeith Busch 2324d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 23255c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 232677bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2327db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2328f3ca80fcSChristoph Hellwig 2329f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2330f3ca80fcSChristoph Hellwig if (result) 2331b00c9b7aSChristophe JAILLET goto unmap; 2332f3ca80fcSChristoph Hellwig 2333ff5350a8SAndy Lutomirski quirks |= check_dell_samsung_bug(pdev); 2334ff5350a8SAndy Lutomirski 2335f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2336ff5350a8SAndy Lutomirski quirks); 2337f3ca80fcSChristoph Hellwig if (result) 2338f3ca80fcSChristoph Hellwig goto release_pools; 2339f3ca80fcSChristoph Hellwig 234082b057caSRakesh Pandit nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); 23411b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 23421b3c47c1SSagi Grimberg 2343d86c4d8eSChristoph Hellwig queue_work(nvme_wq, &dev->ctrl.reset_work); 234457dacad5SJay Sternberg return 0; 234557dacad5SJay Sternberg 234657dacad5SJay Sternberg release_pools: 234757dacad5SJay Sternberg nvme_release_prp_pools(dev); 2348b00c9b7aSChristophe JAILLET unmap: 2349b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 235057dacad5SJay Sternberg put_pci: 235157dacad5SJay Sternberg put_device(dev->dev); 235257dacad5SJay Sternberg free: 235357dacad5SJay Sternberg kfree(dev->queues); 235457dacad5SJay Sternberg kfree(dev); 235557dacad5SJay Sternberg return result; 235657dacad5SJay Sternberg } 235757dacad5SJay Sternberg 2358775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 235957dacad5SJay Sternberg { 236057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2361a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2362775755edSChristoph Hellwig } 236357dacad5SJay Sternberg 2364775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2365775755edSChristoph Hellwig { 2366f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2367d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 236857dacad5SJay Sternberg } 236957dacad5SJay Sternberg 237057dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 237157dacad5SJay Sternberg { 237257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2373a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 237457dacad5SJay Sternberg } 237557dacad5SJay Sternberg 2376f58944e2SKeith Busch /* 2377f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2378f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2379f58944e2SKeith Busch * order to proceed. 2380f58944e2SKeith Busch */ 238157dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 238257dacad5SJay Sternberg { 238357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 238457dacad5SJay Sternberg 2385bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2386bb8d261eSChristoph Hellwig 2387d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 238857dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 23890ff9d4e1SKeith Busch 23906db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 23910ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 23926db28edaSKeith Busch nvme_dev_disable(dev, false); 23936db28edaSKeith Busch } 23940ff9d4e1SKeith Busch 2395d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2396d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2397d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2398a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 239987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 240057dacad5SJay Sternberg nvme_dev_remove_admin(dev); 240157dacad5SJay Sternberg nvme_free_queues(dev, 0); 2402d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 240357dacad5SJay Sternberg nvme_release_prp_pools(dev); 2404b00a726aSKeith Busch nvme_dev_unmap(dev); 24051673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 240657dacad5SJay Sternberg } 240757dacad5SJay Sternberg 240813880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 240913880f5bSKeith Busch { 241013880f5bSKeith Busch int ret = 0; 241113880f5bSKeith Busch 241213880f5bSKeith Busch if (numvfs == 0) { 241313880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 241413880f5bSKeith Busch dev_warn(&pdev->dev, 241513880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 241613880f5bSKeith Busch return -EPERM; 241713880f5bSKeith Busch } 241813880f5bSKeith Busch pci_disable_sriov(pdev); 241913880f5bSKeith Busch return 0; 242013880f5bSKeith Busch } 242113880f5bSKeith Busch 242213880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 242313880f5bSKeith Busch return ret ? ret : numvfs; 242413880f5bSKeith Busch } 242513880f5bSKeith Busch 242657dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 242757dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 242857dacad5SJay Sternberg { 242957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 243057dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 243157dacad5SJay Sternberg 2432a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 243357dacad5SJay Sternberg return 0; 243457dacad5SJay Sternberg } 243557dacad5SJay Sternberg 243657dacad5SJay Sternberg static int nvme_resume(struct device *dev) 243757dacad5SJay Sternberg { 243857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 243957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 244057dacad5SJay Sternberg 2441d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 244257dacad5SJay Sternberg return 0; 244357dacad5SJay Sternberg } 244457dacad5SJay Sternberg #endif 244557dacad5SJay Sternberg 244657dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 244757dacad5SJay Sternberg 2448a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2449a0a3408eSKeith Busch pci_channel_state_t state) 2450a0a3408eSKeith Busch { 2451a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2452a0a3408eSKeith Busch 2453a0a3408eSKeith Busch /* 2454a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2455a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2456a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2457a0a3408eSKeith Busch */ 2458a0a3408eSKeith Busch switch (state) { 2459a0a3408eSKeith Busch case pci_channel_io_normal: 2460a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2461a0a3408eSKeith Busch case pci_channel_io_frozen: 2462d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2463d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2464a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2465a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2466a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2467d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2468d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2469a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2470a0a3408eSKeith Busch } 2471a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2472a0a3408eSKeith Busch } 2473a0a3408eSKeith Busch 2474a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2475a0a3408eSKeith Busch { 2476a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2477a0a3408eSKeith Busch 24781b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2479a0a3408eSKeith Busch pci_restore_state(pdev); 2480d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2481a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2482a0a3408eSKeith Busch } 2483a0a3408eSKeith Busch 2484a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2485a0a3408eSKeith Busch { 2486a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2487a0a3408eSKeith Busch } 2488a0a3408eSKeith Busch 248957dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 249057dacad5SJay Sternberg .error_detected = nvme_error_detected, 249157dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 249257dacad5SJay Sternberg .resume = nvme_error_resume, 2493775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2494775755edSChristoph Hellwig .reset_done = nvme_reset_done, 249557dacad5SJay Sternberg }; 249657dacad5SJay Sternberg 249757dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2498106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 249908095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2500e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 250199466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 250299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2503e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 250499466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 250599466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2506e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2507f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2508f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2509f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 251050af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 251150af47d0SAndy Lutomirski .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, 2512540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2513540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 251454adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 251554adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2516015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2517015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2518d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2519d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2520d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2521d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2522608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2523608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2524608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2525608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 252657dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2527c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2528124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 252957dacad5SJay Sternberg { 0, } 253057dacad5SJay Sternberg }; 253157dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 253257dacad5SJay Sternberg 253357dacad5SJay Sternberg static struct pci_driver nvme_driver = { 253457dacad5SJay Sternberg .name = "nvme", 253557dacad5SJay Sternberg .id_table = nvme_id_table, 253657dacad5SJay Sternberg .probe = nvme_probe, 253757dacad5SJay Sternberg .remove = nvme_remove, 253857dacad5SJay Sternberg .shutdown = nvme_shutdown, 253957dacad5SJay Sternberg .driver = { 254057dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 254157dacad5SJay Sternberg }, 254213880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 254357dacad5SJay Sternberg .err_handler = &nvme_err_handler, 254457dacad5SJay Sternberg }; 254557dacad5SJay Sternberg 254657dacad5SJay Sternberg static int __init nvme_init(void) 254757dacad5SJay Sternberg { 25489a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 254957dacad5SJay Sternberg } 255057dacad5SJay Sternberg 255157dacad5SJay Sternberg static void __exit nvme_exit(void) 255257dacad5SJay Sternberg { 255357dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 255457dacad5SJay Sternberg _nvme_check_size(); 255557dacad5SJay Sternberg } 255657dacad5SJay Sternberg 255757dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 255857dacad5SJay Sternberg MODULE_LICENSE("GPL"); 255957dacad5SJay Sternberg MODULE_VERSION("1.0"); 256057dacad5SJay Sternberg module_init(nvme_init); 256157dacad5SJay Sternberg module_exit(nvme_exit); 2562