157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 330f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3457dacad5SJay Sternberg 3557dacad5SJay Sternberg #include "nvme.h" 3657dacad5SJay Sternberg 3757dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3857dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3957dacad5SJay Sternberg 40a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 41adf68f21SChristoph Hellwig 42943e942eSJens Axboe /* 43943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 44943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 45943e942eSJens Axboe */ 46943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 47943e942eSJens Axboe #define NVME_MAX_SEGS 127 48943e942eSJens Axboe 4957dacad5SJay Sternberg static int use_threaded_interrupts; 5057dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 5157dacad5SJay Sternberg 5257dacad5SJay Sternberg static bool use_cmb_sqes = true; 5369f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5457dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5557dacad5SJay Sternberg 5687ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5787ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5887ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5987ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 6057dacad5SJay Sternberg 61a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 62a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 63a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 64a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 65a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 66a7a7cbe3SChaitanya Kulkarni 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 70b27c1e68Sweiping zhang .get = param_get_int, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 73b27c1e68Sweiping zhang static int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 75b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 76b27c1e68Sweiping zhang 771c63dc66SChristoph Hellwig struct nvme_dev; 781c63dc66SChristoph Hellwig struct nvme_queue; 7957dacad5SJay Sternberg 80a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 8157dacad5SJay Sternberg 8257dacad5SJay Sternberg /* 831c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 841c63dc66SChristoph Hellwig */ 851c63dc66SChristoph Hellwig struct nvme_dev { 86147b27e4SSagi Grimberg struct nvme_queue *queues; 871c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 881c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 891c63dc66SChristoph Hellwig u32 __iomem *dbs; 901c63dc66SChristoph Hellwig struct device *dev; 911c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 921c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 931c63dc66SChristoph Hellwig unsigned online_queues; 941c63dc66SChristoph Hellwig unsigned max_qid; 9522b55601SKeith Busch unsigned int num_vecs; 961c63dc66SChristoph Hellwig int q_depth; 971c63dc66SChristoph Hellwig u32 db_stride; 981c63dc66SChristoph Hellwig void __iomem *bar; 9997f6ef64SXu Yu unsigned long bar_mapped_size; 1005c8809e6SChristoph Hellwig struct work_struct remove_work; 10177bf25eaSKeith Busch struct mutex shutdown_lock; 1021c63dc66SChristoph Hellwig bool subsystem; 1031c63dc66SChristoph Hellwig u64 cmb_size; 1040f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1051c63dc66SChristoph Hellwig u32 cmbsz; 106202021c1SStephen Bates u32 cmbloc; 1071c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 108db3cbfffSKeith Busch struct completion ioq_wait; 10987ad72a5SChristoph Hellwig 110943e942eSJens Axboe mempool_t *iod_mempool; 111943e942eSJens Axboe 11287ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 113f9f38e33SHelen Koike u32 *dbbuf_dbs; 114f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 115f9f38e33SHelen Koike u32 *dbbuf_eis; 116f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 11787ad72a5SChristoph Hellwig 11887ad72a5SChristoph Hellwig /* host memory buffer support: */ 11987ad72a5SChristoph Hellwig u64 host_mem_size; 12087ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1214033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 12287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 12387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 12457dacad5SJay Sternberg }; 12557dacad5SJay Sternberg 126b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 127b27c1e68Sweiping zhang { 128b27c1e68Sweiping zhang int n = 0, ret; 129b27c1e68Sweiping zhang 130b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 131b27c1e68Sweiping zhang if (ret != 0 || n < 2) 132b27c1e68Sweiping zhang return -EINVAL; 133b27c1e68Sweiping zhang 134b27c1e68Sweiping zhang return param_set_int(val, kp); 135b27c1e68Sweiping zhang } 136b27c1e68Sweiping zhang 137f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 138f9f38e33SHelen Koike { 139f9f38e33SHelen Koike return qid * 2 * stride; 140f9f38e33SHelen Koike } 141f9f38e33SHelen Koike 142f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 143f9f38e33SHelen Koike { 144f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 145f9f38e33SHelen Koike } 146f9f38e33SHelen Koike 1471c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1481c63dc66SChristoph Hellwig { 1491c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1501c63dc66SChristoph Hellwig } 1511c63dc66SChristoph Hellwig 15257dacad5SJay Sternberg /* 15357dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 15457dacad5SJay Sternberg * commands and one for I/O commands). 15557dacad5SJay Sternberg */ 15657dacad5SJay Sternberg struct nvme_queue { 15757dacad5SJay Sternberg struct device *q_dmadev; 15857dacad5SJay Sternberg struct nvme_dev *dev; 1591ab0cd69SJens Axboe spinlock_t sq_lock; 16057dacad5SJay Sternberg struct nvme_command *sq_cmds; 1610f238ff5SLogan Gunthorpe bool sq_cmds_is_io; 1621ab0cd69SJens Axboe spinlock_t cq_lock ____cacheline_aligned_in_smp; 16357dacad5SJay Sternberg volatile struct nvme_completion *cqes; 16457dacad5SJay Sternberg struct blk_mq_tags **tags; 16557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 16657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 16757dacad5SJay Sternberg u32 __iomem *q_db; 16857dacad5SJay Sternberg u16 q_depth; 16957dacad5SJay Sternberg s16 cq_vector; 17057dacad5SJay Sternberg u16 sq_tail; 17157dacad5SJay Sternberg u16 cq_head; 17268fa9dbeSJens Axboe u16 last_cq_head; 17357dacad5SJay Sternberg u16 qid; 17457dacad5SJay Sternberg u8 cq_phase; 175f9f38e33SHelen Koike u32 *dbbuf_sq_db; 176f9f38e33SHelen Koike u32 *dbbuf_cq_db; 177f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 178f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 17957dacad5SJay Sternberg }; 18057dacad5SJay Sternberg 18157dacad5SJay Sternberg /* 18271bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 18371bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 184f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 18571bd150cSChristoph Hellwig * allocated to store the PRP list. 18671bd150cSChristoph Hellwig */ 18771bd150cSChristoph Hellwig struct nvme_iod { 188d49187e9SChristoph Hellwig struct nvme_request req; 189f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 190a7a7cbe3SChaitanya Kulkarni bool use_sgl; 191f4800d6dSChristoph Hellwig int aborted; 19271bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 19371bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 19471bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 19571bd150cSChristoph Hellwig dma_addr_t first_dma; 196bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 197f4800d6dSChristoph Hellwig struct scatterlist *sg; 198f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 19957dacad5SJay Sternberg }; 20057dacad5SJay Sternberg 20157dacad5SJay Sternberg /* 20257dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 20357dacad5SJay Sternberg */ 20457dacad5SJay Sternberg static inline void _nvme_check_size(void) 20557dacad5SJay Sternberg { 20657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 20757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 20857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 20957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 21057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 21157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 21257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 21357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2140add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2150add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 21657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 21757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 218f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 219f9f38e33SHelen Koike } 220f9f38e33SHelen Koike 221f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 222f9f38e33SHelen Koike { 223f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 224f9f38e33SHelen Koike } 225f9f38e33SHelen Koike 226f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 227f9f38e33SHelen Koike { 228f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 229f9f38e33SHelen Koike 230f9f38e33SHelen Koike if (dev->dbbuf_dbs) 231f9f38e33SHelen Koike return 0; 232f9f38e33SHelen Koike 233f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 234f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 235f9f38e33SHelen Koike GFP_KERNEL); 236f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 237f9f38e33SHelen Koike return -ENOMEM; 238f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 239f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 240f9f38e33SHelen Koike GFP_KERNEL); 241f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 242f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 243f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 244f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 245f9f38e33SHelen Koike return -ENOMEM; 246f9f38e33SHelen Koike } 247f9f38e33SHelen Koike 248f9f38e33SHelen Koike return 0; 249f9f38e33SHelen Koike } 250f9f38e33SHelen Koike 251f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 252f9f38e33SHelen Koike { 253f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 254f9f38e33SHelen Koike 255f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 256f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 257f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 258f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 259f9f38e33SHelen Koike } 260f9f38e33SHelen Koike if (dev->dbbuf_eis) { 261f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 262f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 263f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 264f9f38e33SHelen Koike } 265f9f38e33SHelen Koike } 266f9f38e33SHelen Koike 267f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 268f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 269f9f38e33SHelen Koike { 270f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 271f9f38e33SHelen Koike return; 272f9f38e33SHelen Koike 273f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 274f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 275f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 276f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 277f9f38e33SHelen Koike } 278f9f38e33SHelen Koike 279f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 280f9f38e33SHelen Koike { 281f9f38e33SHelen Koike struct nvme_command c; 282f9f38e33SHelen Koike 283f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 284f9f38e33SHelen Koike return; 285f9f38e33SHelen Koike 286f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 287f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 288f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 289f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 290f9f38e33SHelen Koike 291f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2929bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 293f9f38e33SHelen Koike /* Free memory and continue on */ 294f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 295f9f38e33SHelen Koike } 296f9f38e33SHelen Koike } 297f9f38e33SHelen Koike 298f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 299f9f38e33SHelen Koike { 300f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 301f9f38e33SHelen Koike } 302f9f38e33SHelen Koike 303f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 304f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 305f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 306f9f38e33SHelen Koike { 307f9f38e33SHelen Koike if (dbbuf_db) { 308f9f38e33SHelen Koike u16 old_value; 309f9f38e33SHelen Koike 310f9f38e33SHelen Koike /* 311f9f38e33SHelen Koike * Ensure that the queue is written before updating 312f9f38e33SHelen Koike * the doorbell in memory 313f9f38e33SHelen Koike */ 314f9f38e33SHelen Koike wmb(); 315f9f38e33SHelen Koike 316f9f38e33SHelen Koike old_value = *dbbuf_db; 317f9f38e33SHelen Koike *dbbuf_db = value; 318f9f38e33SHelen Koike 319f1ed3df2SMichal Wnukowski /* 320f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 321f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 322f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 323f1ed3df2SMichal Wnukowski * the doorbell. 324f1ed3df2SMichal Wnukowski */ 325f1ed3df2SMichal Wnukowski mb(); 326f1ed3df2SMichal Wnukowski 327f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 328f9f38e33SHelen Koike return false; 329f9f38e33SHelen Koike } 330f9f38e33SHelen Koike 331f9f38e33SHelen Koike return true; 33257dacad5SJay Sternberg } 33357dacad5SJay Sternberg 33457dacad5SJay Sternberg /* 33557dacad5SJay Sternberg * Max size of iod being embedded in the request payload 33657dacad5SJay Sternberg */ 33757dacad5SJay Sternberg #define NVME_INT_PAGES 2 3385fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 33957dacad5SJay Sternberg 34057dacad5SJay Sternberg /* 34157dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 34257dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 34357dacad5SJay Sternberg * the I/O. 34457dacad5SJay Sternberg */ 34557dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 34657dacad5SJay Sternberg { 3475fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3485fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 34957dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 35057dacad5SJay Sternberg } 35157dacad5SJay Sternberg 352a7a7cbe3SChaitanya Kulkarni /* 353a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 354a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 355a7a7cbe3SChaitanya Kulkarni */ 356a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 357f4800d6dSChristoph Hellwig { 358a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 359f4800d6dSChristoph Hellwig } 360f4800d6dSChristoph Hellwig 361a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 362a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 36357dacad5SJay Sternberg { 364a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 365a7a7cbe3SChaitanya Kulkarni 366a7a7cbe3SChaitanya Kulkarni if (use_sgl) 367a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 368a7a7cbe3SChaitanya Kulkarni else 369a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 370a7a7cbe3SChaitanya Kulkarni 371a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 372a7a7cbe3SChaitanya Kulkarni } 373a7a7cbe3SChaitanya Kulkarni 374a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 375a7a7cbe3SChaitanya Kulkarni { 376a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 377a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 378a7a7cbe3SChaitanya Kulkarni use_sgl); 379a7a7cbe3SChaitanya Kulkarni 380a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 38157dacad5SJay Sternberg } 38257dacad5SJay Sternberg 38357dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38457dacad5SJay Sternberg unsigned int hctx_idx) 38557dacad5SJay Sternberg { 38657dacad5SJay Sternberg struct nvme_dev *dev = data; 387147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 38857dacad5SJay Sternberg 38957dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 39057dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 39157dacad5SJay Sternberg WARN_ON(nvmeq->tags); 39257dacad5SJay Sternberg 39357dacad5SJay Sternberg hctx->driver_data = nvmeq; 39457dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 39557dacad5SJay Sternberg return 0; 39657dacad5SJay Sternberg } 39757dacad5SJay Sternberg 39857dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 39957dacad5SJay Sternberg { 40057dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 40157dacad5SJay Sternberg 40257dacad5SJay Sternberg nvmeq->tags = NULL; 40357dacad5SJay Sternberg } 40457dacad5SJay Sternberg 40557dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40657dacad5SJay Sternberg unsigned int hctx_idx) 40757dacad5SJay Sternberg { 40857dacad5SJay Sternberg struct nvme_dev *dev = data; 409147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41057dacad5SJay Sternberg 41157dacad5SJay Sternberg if (!nvmeq->tags) 41257dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 41357dacad5SJay Sternberg 41457dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41557dacad5SJay Sternberg hctx->driver_data = nvmeq; 41657dacad5SJay Sternberg return 0; 41757dacad5SJay Sternberg } 41857dacad5SJay Sternberg 419d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 420d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 42157dacad5SJay Sternberg { 422d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 423f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4240350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 425147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 42657dacad5SJay Sternberg 42757dacad5SJay Sternberg BUG_ON(!nvmeq); 428f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 42959e29ce6SSagi Grimberg 43059e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 43157dacad5SJay Sternberg return 0; 43257dacad5SJay Sternberg } 43357dacad5SJay Sternberg 434dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 435dca51e78SChristoph Hellwig { 436dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 437dca51e78SChristoph Hellwig 43822b55601SKeith Busch return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), 43922b55601SKeith Busch dev->num_vecs > 1 ? 1 /* admin queue */ : 0); 440dca51e78SChristoph Hellwig } 441dca51e78SChristoph Hellwig 44257dacad5SJay Sternberg /** 44390ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 44457dacad5SJay Sternberg * @nvmeq: The queue to use 44557dacad5SJay Sternberg * @cmd: The command to send 44657dacad5SJay Sternberg */ 44790ea5ca4SChristoph Hellwig static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 44857dacad5SJay Sternberg { 44990ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 4500f238ff5SLogan Gunthorpe 45190ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 45257dacad5SJay Sternberg 45390ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 45490ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 45590ea5ca4SChristoph Hellwig if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 45690ea5ca4SChristoph Hellwig nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 45790ea5ca4SChristoph Hellwig writel(nvmeq->sq_tail, nvmeq->q_db); 45890ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 45957dacad5SJay Sternberg } 46057dacad5SJay Sternberg 461a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 46257dacad5SJay Sternberg { 463f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 464a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 46557dacad5SJay Sternberg } 46657dacad5SJay Sternberg 467955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 468955b1b5aSMinwoo Im { 469955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 47020469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 471955b1b5aSMinwoo Im unsigned int avg_seg_size; 472955b1b5aSMinwoo Im 47320469a37SKeith Busch if (nseg == 0) 47420469a37SKeith Busch return false; 47520469a37SKeith Busch 47620469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 477955b1b5aSMinwoo Im 478955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 479955b1b5aSMinwoo Im return false; 480955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 481955b1b5aSMinwoo Im return false; 482955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 483955b1b5aSMinwoo Im return false; 484955b1b5aSMinwoo Im return true; 485955b1b5aSMinwoo Im } 486955b1b5aSMinwoo Im 487fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 48857dacad5SJay Sternberg { 489f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 490f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 491b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 492f4800d6dSChristoph Hellwig 493955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 494955b1b5aSMinwoo Im 495f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 496943e942eSJens Axboe iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 497f4800d6dSChristoph Hellwig if (!iod->sg) 498fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 499f4800d6dSChristoph Hellwig } else { 500f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 50157dacad5SJay Sternberg } 50257dacad5SJay Sternberg 503f4800d6dSChristoph Hellwig iod->aborted = 0; 50457dacad5SJay Sternberg iod->npages = -1; 50557dacad5SJay Sternberg iod->nents = 0; 506f4800d6dSChristoph Hellwig iod->length = size; 507f80ec966SKeith Busch 508fc17b653SChristoph Hellwig return BLK_STS_OK; 50957dacad5SJay Sternberg } 51057dacad5SJay Sternberg 511f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 51257dacad5SJay Sternberg { 513f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 514a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 515a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 516a7a7cbe3SChaitanya Kulkarni 51757dacad5SJay Sternberg int i; 51857dacad5SJay Sternberg 51957dacad5SJay Sternberg if (iod->npages == 0) 520a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 521a7a7cbe3SChaitanya Kulkarni dma_addr); 522a7a7cbe3SChaitanya Kulkarni 52357dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 524a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 525a7a7cbe3SChaitanya Kulkarni 526a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 527a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 528a7a7cbe3SChaitanya Kulkarni 529a7a7cbe3SChaitanya Kulkarni next_dma_addr = 530a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 531a7a7cbe3SChaitanya Kulkarni } else { 532a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 533a7a7cbe3SChaitanya Kulkarni 534a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 535a7a7cbe3SChaitanya Kulkarni } 536a7a7cbe3SChaitanya Kulkarni 537a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 538a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 53957dacad5SJay Sternberg } 54057dacad5SJay Sternberg 541f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 542943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 54357dacad5SJay Sternberg } 54457dacad5SJay Sternberg 545d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 546d0877473SKeith Busch { 547d0877473SKeith Busch int i; 548d0877473SKeith Busch struct scatterlist *sg; 549d0877473SKeith Busch 550d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 551d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 552d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 553d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 554d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 555d0877473SKeith Busch sg_dma_len(sg)); 556d0877473SKeith Busch } 557d0877473SKeith Busch } 558d0877473SKeith Busch 559a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 560a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 56157dacad5SJay Sternberg { 562f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 56357dacad5SJay Sternberg struct dma_pool *pool; 564b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 56557dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 56657dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 56757dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5685fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 56957dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 57057dacad5SJay Sternberg __le64 *prp_list; 571a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 57257dacad5SJay Sternberg dma_addr_t prp_dma; 57357dacad5SJay Sternberg int nprps, i; 57457dacad5SJay Sternberg 57557dacad5SJay Sternberg length -= (page_size - offset); 5765228b328SJan H. Schönherr if (length <= 0) { 5775228b328SJan H. Schönherr iod->first_dma = 0; 578a7a7cbe3SChaitanya Kulkarni goto done; 5795228b328SJan H. Schönherr } 58057dacad5SJay Sternberg 58157dacad5SJay Sternberg dma_len -= (page_size - offset); 58257dacad5SJay Sternberg if (dma_len) { 58357dacad5SJay Sternberg dma_addr += (page_size - offset); 58457dacad5SJay Sternberg } else { 58557dacad5SJay Sternberg sg = sg_next(sg); 58657dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 58757dacad5SJay Sternberg dma_len = sg_dma_len(sg); 58857dacad5SJay Sternberg } 58957dacad5SJay Sternberg 59057dacad5SJay Sternberg if (length <= page_size) { 59157dacad5SJay Sternberg iod->first_dma = dma_addr; 592a7a7cbe3SChaitanya Kulkarni goto done; 59357dacad5SJay Sternberg } 59457dacad5SJay Sternberg 59557dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 59657dacad5SJay Sternberg if (nprps <= (256 / 8)) { 59757dacad5SJay Sternberg pool = dev->prp_small_pool; 59857dacad5SJay Sternberg iod->npages = 0; 59957dacad5SJay Sternberg } else { 60057dacad5SJay Sternberg pool = dev->prp_page_pool; 60157dacad5SJay Sternberg iod->npages = 1; 60257dacad5SJay Sternberg } 60357dacad5SJay Sternberg 60469d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 60557dacad5SJay Sternberg if (!prp_list) { 60657dacad5SJay Sternberg iod->first_dma = dma_addr; 60757dacad5SJay Sternberg iod->npages = -1; 60886eea289SKeith Busch return BLK_STS_RESOURCE; 60957dacad5SJay Sternberg } 61057dacad5SJay Sternberg list[0] = prp_list; 61157dacad5SJay Sternberg iod->first_dma = prp_dma; 61257dacad5SJay Sternberg i = 0; 61357dacad5SJay Sternberg for (;;) { 61457dacad5SJay Sternberg if (i == page_size >> 3) { 61557dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 61669d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 61757dacad5SJay Sternberg if (!prp_list) 61886eea289SKeith Busch return BLK_STS_RESOURCE; 61957dacad5SJay Sternberg list[iod->npages++] = prp_list; 62057dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 62157dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 62257dacad5SJay Sternberg i = 1; 62357dacad5SJay Sternberg } 62457dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 62557dacad5SJay Sternberg dma_len -= page_size; 62657dacad5SJay Sternberg dma_addr += page_size; 62757dacad5SJay Sternberg length -= page_size; 62857dacad5SJay Sternberg if (length <= 0) 62957dacad5SJay Sternberg break; 63057dacad5SJay Sternberg if (dma_len > 0) 63157dacad5SJay Sternberg continue; 63286eea289SKeith Busch if (unlikely(dma_len < 0)) 63386eea289SKeith Busch goto bad_sgl; 63457dacad5SJay Sternberg sg = sg_next(sg); 63557dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 63657dacad5SJay Sternberg dma_len = sg_dma_len(sg); 63757dacad5SJay Sternberg } 63857dacad5SJay Sternberg 639a7a7cbe3SChaitanya Kulkarni done: 640a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 641a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 642a7a7cbe3SChaitanya Kulkarni 64386eea289SKeith Busch return BLK_STS_OK; 64486eea289SKeith Busch 64586eea289SKeith Busch bad_sgl: 646d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 647d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 648d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 64986eea289SKeith Busch return BLK_STS_IOERR; 65057dacad5SJay Sternberg } 65157dacad5SJay Sternberg 652a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 653a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 654a7a7cbe3SChaitanya Kulkarni { 655a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 656a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 657a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 658a7a7cbe3SChaitanya Kulkarni } 659a7a7cbe3SChaitanya Kulkarni 660a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 661a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 662a7a7cbe3SChaitanya Kulkarni { 663a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 664a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 665a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 666a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 667a7a7cbe3SChaitanya Kulkarni } else { 668a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 669a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 670a7a7cbe3SChaitanya Kulkarni } 671a7a7cbe3SChaitanya Kulkarni } 672a7a7cbe3SChaitanya Kulkarni 673a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 674b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 675a7a7cbe3SChaitanya Kulkarni { 676a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 677a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 678a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 679a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 680a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 681b0f2853bSChristoph Hellwig int i = 0; 682a7a7cbe3SChaitanya Kulkarni 683a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 684a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 685a7a7cbe3SChaitanya Kulkarni 686b0f2853bSChristoph Hellwig if (entries == 1) { 687a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 688a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 689a7a7cbe3SChaitanya Kulkarni } 690a7a7cbe3SChaitanya Kulkarni 691a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 692a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 693a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 694a7a7cbe3SChaitanya Kulkarni } else { 695a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 696a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 697a7a7cbe3SChaitanya Kulkarni } 698a7a7cbe3SChaitanya Kulkarni 699a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 700a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 701a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 702a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 703a7a7cbe3SChaitanya Kulkarni } 704a7a7cbe3SChaitanya Kulkarni 705a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 706a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 707a7a7cbe3SChaitanya Kulkarni 708a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 709a7a7cbe3SChaitanya Kulkarni 710a7a7cbe3SChaitanya Kulkarni do { 711a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 712a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 713a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 714a7a7cbe3SChaitanya Kulkarni 715a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 716a7a7cbe3SChaitanya Kulkarni if (!sg_list) 717a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 718a7a7cbe3SChaitanya Kulkarni 719a7a7cbe3SChaitanya Kulkarni i = 0; 720a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 721a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 722a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 723a7a7cbe3SChaitanya Kulkarni } 724a7a7cbe3SChaitanya Kulkarni 725a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 726a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 727b0f2853bSChristoph Hellwig } while (--entries > 0); 728a7a7cbe3SChaitanya Kulkarni 729a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 730a7a7cbe3SChaitanya Kulkarni } 731a7a7cbe3SChaitanya Kulkarni 732fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 733b131c61dSChristoph Hellwig struct nvme_command *cmnd) 73457dacad5SJay Sternberg { 735f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 736ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 737ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 738ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 739fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 740b0f2853bSChristoph Hellwig int nr_mapped; 74157dacad5SJay Sternberg 742f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 743ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 744ba1ca37eSChristoph Hellwig if (!iod->nents) 745ba1ca37eSChristoph Hellwig goto out; 746ba1ca37eSChristoph Hellwig 747fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 748b0f2853bSChristoph Hellwig nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 749b0f2853bSChristoph Hellwig DMA_ATTR_NO_WARN); 750b0f2853bSChristoph Hellwig if (!nr_mapped) 751ba1ca37eSChristoph Hellwig goto out; 752ba1ca37eSChristoph Hellwig 753955b1b5aSMinwoo Im if (iod->use_sgl) 754b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 755a7a7cbe3SChaitanya Kulkarni else 756a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 757a7a7cbe3SChaitanya Kulkarni 75886eea289SKeith Busch if (ret != BLK_STS_OK) 759ba1ca37eSChristoph Hellwig goto out_unmap; 760ba1ca37eSChristoph Hellwig 761fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 762ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 763ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 764ba1ca37eSChristoph Hellwig goto out_unmap; 765ba1ca37eSChristoph Hellwig 766bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 767bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 768ba1ca37eSChristoph Hellwig goto out_unmap; 769ba1ca37eSChristoph Hellwig 770bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 771ba1ca37eSChristoph Hellwig goto out_unmap; 77257dacad5SJay Sternberg } 77357dacad5SJay Sternberg 774ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 775bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 776fc17b653SChristoph Hellwig return BLK_STS_OK; 777ba1ca37eSChristoph Hellwig 778ba1ca37eSChristoph Hellwig out_unmap: 779ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 780ba1ca37eSChristoph Hellwig out: 781ba1ca37eSChristoph Hellwig return ret; 78257dacad5SJay Sternberg } 78357dacad5SJay Sternberg 784f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 785d4f6c3abSChristoph Hellwig { 786f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 787d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 788d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 789d4f6c3abSChristoph Hellwig 790d4f6c3abSChristoph Hellwig if (iod->nents) { 791d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 792f7f1fc36SMax Gurtovoy if (blk_integrity_rq(req)) 793bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 794d4f6c3abSChristoph Hellwig } 795d4f6c3abSChristoph Hellwig 796f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 797f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 79857dacad5SJay Sternberg } 79957dacad5SJay Sternberg 80057dacad5SJay Sternberg /* 80157dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 80257dacad5SJay Sternberg */ 803fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 80457dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 80557dacad5SJay Sternberg { 80657dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 80757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 80857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 80957dacad5SJay Sternberg struct request *req = bd->rq; 810ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 811ebe6d874SChristoph Hellwig blk_status_t ret; 81257dacad5SJay Sternberg 813d1f06f4aSJens Axboe /* 814d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 815d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 816d1f06f4aSJens Axboe */ 817d1f06f4aSJens Axboe if (unlikely(nvmeq->cq_vector < 0)) 818d1f06f4aSJens Axboe return BLK_STS_IOERR; 819d1f06f4aSJens Axboe 820f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 821fc17b653SChristoph Hellwig if (ret) 822f4800d6dSChristoph Hellwig return ret; 82357dacad5SJay Sternberg 824b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 825fc17b653SChristoph Hellwig if (ret) 826f9d03f96SChristoph Hellwig goto out_free_cmd; 82757dacad5SJay Sternberg 828fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 829b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 830fc17b653SChristoph Hellwig if (ret) 831f9d03f96SChristoph Hellwig goto out_cleanup_iod; 832fc17b653SChristoph Hellwig } 833ba1ca37eSChristoph Hellwig 834aae239e1SChristoph Hellwig blk_mq_start_request(req); 83590ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &cmnd); 836fc17b653SChristoph Hellwig return BLK_STS_OK; 837f9d03f96SChristoph Hellwig out_cleanup_iod: 838f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 839f9d03f96SChristoph Hellwig out_free_cmd: 840f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 841ba1ca37eSChristoph Hellwig return ret; 84257dacad5SJay Sternberg } 84357dacad5SJay Sternberg 84477f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 845eee417b0SChristoph Hellwig { 846f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 847eee417b0SChristoph Hellwig 84877f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 84977f02a7aSChristoph Hellwig nvme_complete_rq(req); 85057dacad5SJay Sternberg } 85157dacad5SJay Sternberg 852d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 853750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 854d783e0bdSMarta Rybczynska { 855750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 856750dde44SChristoph Hellwig nvmeq->cq_phase; 857d783e0bdSMarta Rybczynska } 858d783e0bdSMarta Rybczynska 859eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 86057dacad5SJay Sternberg { 861eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 86257dacad5SJay Sternberg 863eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 864eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 865eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 866eb281c82SSagi Grimberg } 867adf68f21SChristoph Hellwig 8685cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 86957dacad5SJay Sternberg { 8705cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 87157dacad5SJay Sternberg struct request *req; 872adf68f21SChristoph Hellwig 87383a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 8741b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 875aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 87683a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 87783a12fb7SSagi Grimberg return; 878aae239e1SChristoph Hellwig } 879aae239e1SChristoph Hellwig 880adf68f21SChristoph Hellwig /* 881adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 882adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 883adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 884adf68f21SChristoph Hellwig * for them but rather special case them here. 885adf68f21SChristoph Hellwig */ 886adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 88738dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 8887bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 88983a12fb7SSagi Grimberg cqe->status, &cqe->result); 890a0fa9647SJens Axboe return; 89157dacad5SJay Sternberg } 89257dacad5SJay Sternberg 89383a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 89483a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 89583a12fb7SSagi Grimberg } 89657dacad5SJay Sternberg 8975cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 89883a12fb7SSagi Grimberg { 8995cb525c8SJens Axboe while (start != end) { 9005cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 9015cb525c8SJens Axboe if (++start == nvmeq->q_depth) 9025cb525c8SJens Axboe start = 0; 9035cb525c8SJens Axboe } 9045cb525c8SJens Axboe } 90583a12fb7SSagi Grimberg 9065cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9075cb525c8SJens Axboe { 908920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 909920d13a8SSagi Grimberg nvmeq->cq_head = 0; 910920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 911920d13a8SSagi Grimberg } 912a0fa9647SJens Axboe } 913a0fa9647SJens Axboe 9145cb525c8SJens Axboe static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 9155cb525c8SJens Axboe u16 *end, int tag) 916a0fa9647SJens Axboe { 9175cb525c8SJens Axboe bool found = false; 91883a12fb7SSagi Grimberg 9195cb525c8SJens Axboe *start = nvmeq->cq_head; 9205cb525c8SJens Axboe while (!found && nvme_cqe_pending(nvmeq)) { 9215cb525c8SJens Axboe if (nvmeq->cqes[nvmeq->cq_head].command_id == tag) 9225cb525c8SJens Axboe found = true; 9235cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 92457dacad5SJay Sternberg } 9255cb525c8SJens Axboe *end = nvmeq->cq_head; 92657dacad5SJay Sternberg 9275cb525c8SJens Axboe if (*start != *end) 928eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 9295cb525c8SJens Axboe return found; 93057dacad5SJay Sternberg } 93157dacad5SJay Sternberg 93257dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 93357dacad5SJay Sternberg { 93457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 93568fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 9365cb525c8SJens Axboe u16 start, end; 9375cb525c8SJens Axboe 9381ab0cd69SJens Axboe spin_lock(&nvmeq->cq_lock); 93968fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 94068fa9dbeSJens Axboe ret = IRQ_HANDLED; 9415cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 94268fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 9431ab0cd69SJens Axboe spin_unlock(&nvmeq->cq_lock); 9445cb525c8SJens Axboe 94568fa9dbeSJens Axboe if (start != end) { 9465cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 9475cb525c8SJens Axboe return IRQ_HANDLED; 94857dacad5SJay Sternberg } 94957dacad5SJay Sternberg 95068fa9dbeSJens Axboe return ret; 95157dacad5SJay Sternberg } 95257dacad5SJay Sternberg 95357dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 95457dacad5SJay Sternberg { 95557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 956750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 95757dacad5SJay Sternberg return IRQ_WAKE_THREAD; 958d783e0bdSMarta Rybczynska return IRQ_NONE; 95957dacad5SJay Sternberg } 96057dacad5SJay Sternberg 9617776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 962a0fa9647SJens Axboe { 9635cb525c8SJens Axboe u16 start, end; 9645cb525c8SJens Axboe bool found; 965a0fa9647SJens Axboe 966750dde44SChristoph Hellwig if (!nvme_cqe_pending(nvmeq)) 967442e19b7SSagi Grimberg return 0; 968442e19b7SSagi Grimberg 9691ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 9705cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 9711ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 972442e19b7SSagi Grimberg 9735cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 974442e19b7SSagi Grimberg return found; 975a0fa9647SJens Axboe } 976a0fa9647SJens Axboe 9777776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 9787776db1cSKeith Busch { 9797776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 9807776db1cSKeith Busch 9817776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 9827776db1cSKeith Busch } 9837776db1cSKeith Busch 984ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 98557dacad5SJay Sternberg { 986f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 987147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 98857dacad5SJay Sternberg struct nvme_command c; 98957dacad5SJay Sternberg 99057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 99157dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 992ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 99390ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &c); 99457dacad5SJay Sternberg } 99557dacad5SJay Sternberg 99657dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 99757dacad5SJay Sternberg { 99857dacad5SJay Sternberg struct nvme_command c; 99957dacad5SJay Sternberg 100057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 100157dacad5SJay Sternberg c.delete_queue.opcode = opcode; 100257dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 100357dacad5SJay Sternberg 10041c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 100557dacad5SJay Sternberg } 100657dacad5SJay Sternberg 100757dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1008a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 100957dacad5SJay Sternberg { 101057dacad5SJay Sternberg struct nvme_command c; 101157dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 101257dacad5SJay Sternberg 101357dacad5SJay Sternberg /* 101416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 101557dacad5SJay Sternberg * is attached to the request. 101657dacad5SJay Sternberg */ 101757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 101857dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 101957dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 102057dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 102157dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 102257dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1023a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 102457dacad5SJay Sternberg 10251c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 102657dacad5SJay Sternberg } 102757dacad5SJay Sternberg 102857dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 102957dacad5SJay Sternberg struct nvme_queue *nvmeq) 103057dacad5SJay Sternberg { 10319abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 103257dacad5SJay Sternberg struct nvme_command c; 103381c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 103457dacad5SJay Sternberg 103557dacad5SJay Sternberg /* 10369abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 10379abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 10389abd68efSJens Axboe * URGENT. 10399abd68efSJens Axboe */ 10409abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 10419abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 10429abd68efSJens Axboe 10439abd68efSJens Axboe /* 104416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 104557dacad5SJay Sternberg * is attached to the request. 104657dacad5SJay Sternberg */ 104757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 104857dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 104957dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 105057dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 105157dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 105257dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 105357dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 105457dacad5SJay Sternberg 10551c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 105657dacad5SJay Sternberg } 105757dacad5SJay Sternberg 105857dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 105957dacad5SJay Sternberg { 106057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 106157dacad5SJay Sternberg } 106257dacad5SJay Sternberg 106357dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 106457dacad5SJay Sternberg { 106557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 106657dacad5SJay Sternberg } 106757dacad5SJay Sternberg 10682a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 106957dacad5SJay Sternberg { 1070f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1071f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 107257dacad5SJay Sternberg 107327fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 107427fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1075e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1076e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 107757dacad5SJay Sternberg } 107857dacad5SJay Sternberg 1079b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1080b2a0eb1aSKeith Busch { 1081b2a0eb1aSKeith Busch 1082b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1083b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1084b2a0eb1aSKeith Busch */ 1085b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1086b2a0eb1aSKeith Busch 1087ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1088ad70062cSJianchao Wang switch (dev->ctrl.state) { 1089ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1090ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1091b2a0eb1aSKeith Busch return false; 1092ad70062cSJianchao Wang default: 1093ad70062cSJianchao Wang break; 1094ad70062cSJianchao Wang } 1095b2a0eb1aSKeith Busch 1096b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1097b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1098b2a0eb1aSKeith Busch */ 1099b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1100b2a0eb1aSKeith Busch return false; 1101b2a0eb1aSKeith Busch 1102b2a0eb1aSKeith Busch return true; 1103b2a0eb1aSKeith Busch } 1104b2a0eb1aSKeith Busch 1105b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1106b2a0eb1aSKeith Busch { 1107b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1108b2a0eb1aSKeith Busch u16 pci_status; 1109b2a0eb1aSKeith Busch int result; 1110b2a0eb1aSKeith Busch 1111b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1112b2a0eb1aSKeith Busch &pci_status); 1113b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1114b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1115b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1116b2a0eb1aSKeith Busch csts, pci_status); 1117b2a0eb1aSKeith Busch else 1118b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1119b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1120b2a0eb1aSKeith Busch csts, result); 1121b2a0eb1aSKeith Busch } 1122b2a0eb1aSKeith Busch 112331c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 112457dacad5SJay Sternberg { 1125f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1126f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 112757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 112857dacad5SJay Sternberg struct request *abort_req; 112957dacad5SJay Sternberg struct nvme_command cmd; 1130b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1131b2a0eb1aSKeith Busch 1132651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1133651438bbSWen Xiong * the recovery mechanism will surely fail. 1134651438bbSWen Xiong */ 1135651438bbSWen Xiong mb(); 1136651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1137651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1138651438bbSWen Xiong 1139b2a0eb1aSKeith Busch /* 1140b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1141b2a0eb1aSKeith Busch */ 1142b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1143b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1144b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1145d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1146db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1147b2a0eb1aSKeith Busch } 114857dacad5SJay Sternberg 114931c7c7d2SChristoph Hellwig /* 11507776db1cSKeith Busch * Did we miss an interrupt? 11517776db1cSKeith Busch */ 11527776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 11537776db1cSKeith Busch dev_warn(dev->ctrl.device, 11547776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 11557776db1cSKeith Busch req->tag, nvmeq->qid); 1156db8c48e4SChristoph Hellwig return BLK_EH_DONE; 11577776db1cSKeith Busch } 11587776db1cSKeith Busch 11597776db1cSKeith Busch /* 1160fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1161fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1162fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1163db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1164fd634f41SChristoph Hellwig */ 11654244140dSKeith Busch switch (dev->ctrl.state) { 11664244140dSKeith Busch case NVME_CTRL_CONNECTING: 11674244140dSKeith Busch case NVME_CTRL_RESETTING: 1168b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1169fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1170fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1171a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 117227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1173db8c48e4SChristoph Hellwig return BLK_EH_DONE; 11744244140dSKeith Busch default: 11754244140dSKeith Busch break; 1176fd634f41SChristoph Hellwig } 1177fd634f41SChristoph Hellwig 1178fd634f41SChristoph Hellwig /* 1179e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1180e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1181e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 118231c7c7d2SChristoph Hellwig */ 1183f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 11841b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 118557dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 118657dacad5SJay Sternberg req->tag, nvmeq->qid); 1187a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1188d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1189e1569a16SKeith Busch 119027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1191db8c48e4SChristoph Hellwig return BLK_EH_DONE; 119257dacad5SJay Sternberg } 119357dacad5SJay Sternberg 1194e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1195e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1196e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1197e7a2a87dSChristoph Hellwig } 11987bf7d778SKeith Busch iod->aborted = 1; 119957dacad5SJay Sternberg 120057dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 120157dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 120257dacad5SJay Sternberg cmd.abort.cid = req->tag; 120357dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 120457dacad5SJay Sternberg 12051b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12061b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 120757dacad5SJay Sternberg req->tag, nvmeq->qid); 1208e7a2a87dSChristoph Hellwig 1209e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1210eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12116bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12126bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 121331c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 121457dacad5SJay Sternberg } 121557dacad5SJay Sternberg 1216e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1217e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1218e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 121957dacad5SJay Sternberg 122057dacad5SJay Sternberg /* 122157dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 122257dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 122357dacad5SJay Sternberg * as the device then is in a faulty state. 122457dacad5SJay Sternberg */ 122557dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 122657dacad5SJay Sternberg } 122757dacad5SJay Sternberg 122857dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 122957dacad5SJay Sternberg { 123057dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 123157dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 12320f238ff5SLogan Gunthorpe 12330f238ff5SLogan Gunthorpe if (nvmeq->sq_cmds) { 12340f238ff5SLogan Gunthorpe if (nvmeq->sq_cmds_is_io) 12350f238ff5SLogan Gunthorpe pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev), 12360f238ff5SLogan Gunthorpe nvmeq->sq_cmds, 12370f238ff5SLogan Gunthorpe SQ_SIZE(nvmeq->q_depth)); 12380f238ff5SLogan Gunthorpe else 12390f238ff5SLogan Gunthorpe dma_free_coherent(nvmeq->q_dmadev, 12400f238ff5SLogan Gunthorpe SQ_SIZE(nvmeq->q_depth), 12410f238ff5SLogan Gunthorpe nvmeq->sq_cmds, 12420f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr); 12430f238ff5SLogan Gunthorpe } 124457dacad5SJay Sternberg } 124557dacad5SJay Sternberg 124657dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 124757dacad5SJay Sternberg { 124857dacad5SJay Sternberg int i; 124957dacad5SJay Sternberg 1250d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1251d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1252147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 125357dacad5SJay Sternberg } 125457dacad5SJay Sternberg } 125557dacad5SJay Sternberg 125657dacad5SJay Sternberg /** 125757dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 125857dacad5SJay Sternberg * @nvmeq - queue to suspend 125957dacad5SJay Sternberg */ 126057dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 126157dacad5SJay Sternberg { 126257dacad5SJay Sternberg int vector; 126357dacad5SJay Sternberg 12641ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 126557dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 12661ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 126757dacad5SJay Sternberg return 1; 126857dacad5SJay Sternberg } 12690ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 127057dacad5SJay Sternberg nvmeq->dev->online_queues--; 127157dacad5SJay Sternberg nvmeq->cq_vector = -1; 12721ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 127357dacad5SJay Sternberg 1274d1f06f4aSJens Axboe /* 1275d1f06f4aSJens Axboe * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without 1276d1f06f4aSJens Axboe * having to grab the lock. 1277d1f06f4aSJens Axboe */ 1278d1f06f4aSJens Axboe mb(); 127957dacad5SJay Sternberg 12801c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1281c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 128257dacad5SJay Sternberg 12830ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 128457dacad5SJay Sternberg 128557dacad5SJay Sternberg return 0; 128657dacad5SJay Sternberg } 128757dacad5SJay Sternberg 1288a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 128957dacad5SJay Sternberg { 1290147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 12915cb525c8SJens Axboe u16 start, end; 129257dacad5SJay Sternberg 1293a5cdb68cSKeith Busch if (shutdown) 1294a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1295a5cdb68cSKeith Busch else 129620d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 129757dacad5SJay Sternberg 12981ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 12995cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 13001ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 13015cb525c8SJens Axboe 13025cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 130357dacad5SJay Sternberg } 130457dacad5SJay Sternberg 130557dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 130657dacad5SJay Sternberg int entry_size) 130757dacad5SJay Sternberg { 130857dacad5SJay Sternberg int q_depth = dev->q_depth; 13095fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13105fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 131157dacad5SJay Sternberg 131257dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 131357dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13145fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 131557dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 131657dacad5SJay Sternberg 131757dacad5SJay Sternberg /* 131857dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 131957dacad5SJay Sternberg * would be better to map queues in system memory with the 132057dacad5SJay Sternberg * original depth 132157dacad5SJay Sternberg */ 132257dacad5SJay Sternberg if (q_depth < 64) 132357dacad5SJay Sternberg return -ENOMEM; 132457dacad5SJay Sternberg } 132557dacad5SJay Sternberg 132657dacad5SJay Sternberg return q_depth; 132757dacad5SJay Sternberg } 132857dacad5SJay Sternberg 132957dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 133057dacad5SJay Sternberg int qid, int depth) 133157dacad5SJay Sternberg { 13320f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1333815c6704SKeith Busch 13340f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 13350f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 13360f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 13370f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 13380f238ff5SLogan Gunthorpe nvmeq->sq_cmds_is_io = true; 13390f238ff5SLogan Gunthorpe } 13400f238ff5SLogan Gunthorpe 13410f238ff5SLogan Gunthorpe if (!nvmeq->sq_cmds) { 134257dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 134357dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 13440f238ff5SLogan Gunthorpe nvmeq->sq_cmds_is_io = false; 13450f238ff5SLogan Gunthorpe } 13460f238ff5SLogan Gunthorpe 134757dacad5SJay Sternberg if (!nvmeq->sq_cmds) 134857dacad5SJay Sternberg return -ENOMEM; 134957dacad5SJay Sternberg return 0; 135057dacad5SJay Sternberg } 135157dacad5SJay Sternberg 1352a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 135357dacad5SJay Sternberg { 1354147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 135557dacad5SJay Sternberg 135662314e40SKeith Busch if (dev->ctrl.queue_count > qid) 135762314e40SKeith Busch return 0; 135857dacad5SJay Sternberg 135957dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 136057dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 136157dacad5SJay Sternberg if (!nvmeq->cqes) 136257dacad5SJay Sternberg goto free_nvmeq; 136357dacad5SJay Sternberg 136457dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 136557dacad5SJay Sternberg goto free_cqdma; 136657dacad5SJay Sternberg 136757dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 136857dacad5SJay Sternberg nvmeq->dev = dev; 13691ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 13701ab0cd69SJens Axboe spin_lock_init(&nvmeq->cq_lock); 137157dacad5SJay Sternberg nvmeq->cq_head = 0; 137257dacad5SJay Sternberg nvmeq->cq_phase = 1; 137357dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 137457dacad5SJay Sternberg nvmeq->q_depth = depth; 137557dacad5SJay Sternberg nvmeq->qid = qid; 137657dacad5SJay Sternberg nvmeq->cq_vector = -1; 1377d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 137857dacad5SJay Sternberg 1379147b27e4SSagi Grimberg return 0; 138057dacad5SJay Sternberg 138157dacad5SJay Sternberg free_cqdma: 138257dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 138357dacad5SJay Sternberg nvmeq->cq_dma_addr); 138457dacad5SJay Sternberg free_nvmeq: 1385147b27e4SSagi Grimberg return -ENOMEM; 138657dacad5SJay Sternberg } 138757dacad5SJay Sternberg 1388dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 138957dacad5SJay Sternberg { 13900ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 13910ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 13920ff199cbSChristoph Hellwig 13930ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 13940ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 13950ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 13960ff199cbSChristoph Hellwig } else { 13970ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 13980ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 13990ff199cbSChristoph Hellwig } 140057dacad5SJay Sternberg } 140157dacad5SJay Sternberg 140257dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 140357dacad5SJay Sternberg { 140457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 140557dacad5SJay Sternberg 14061ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 140757dacad5SJay Sternberg nvmeq->sq_tail = 0; 140857dacad5SJay Sternberg nvmeq->cq_head = 0; 140957dacad5SJay Sternberg nvmeq->cq_phase = 1; 141057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 141157dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1412f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 141357dacad5SJay Sternberg dev->online_queues++; 14141ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 141557dacad5SJay Sternberg } 141657dacad5SJay Sternberg 141757dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 141857dacad5SJay Sternberg { 141957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 142057dacad5SJay Sternberg int result; 1421a8e3e0bbSJianchao Wang s16 vector; 142257dacad5SJay Sternberg 142322b55601SKeith Busch /* 142422b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 142522b55601SKeith Busch * has only one vector available. 142622b55601SKeith Busch */ 1427a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 1428a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1429ded45505SKeith Busch if (result) 1430ded45505SKeith Busch return result; 143157dacad5SJay Sternberg 143257dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 143357dacad5SJay Sternberg if (result < 0) 1434ded45505SKeith Busch return result; 1435ded45505SKeith Busch else if (result) 143657dacad5SJay Sternberg goto release_cq; 143757dacad5SJay Sternberg 1438a8e3e0bbSJianchao Wang /* 1439a8e3e0bbSJianchao Wang * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will 1440a8e3e0bbSJianchao Wang * invoke free_irq for it and cause a 'Trying to free already-free IRQ 1441a8e3e0bbSJianchao Wang * xxx' warning if the create CQ/SQ command times out. 1442a8e3e0bbSJianchao Wang */ 1443a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1444161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 1445dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 144657dacad5SJay Sternberg if (result < 0) 144757dacad5SJay Sternberg goto release_sq; 144857dacad5SJay Sternberg 144957dacad5SJay Sternberg return result; 145057dacad5SJay Sternberg 145157dacad5SJay Sternberg release_sq: 1452a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 1453f25a2dfcSJianchao Wang dev->online_queues--; 145457dacad5SJay Sternberg adapter_delete_sq(dev, qid); 145557dacad5SJay Sternberg release_cq: 145657dacad5SJay Sternberg adapter_delete_cq(dev, qid); 145757dacad5SJay Sternberg return result; 145857dacad5SJay Sternberg } 145957dacad5SJay Sternberg 1460f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 146157dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 146277f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 146357dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 146457dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 14650350815aSChristoph Hellwig .init_request = nvme_init_request, 146657dacad5SJay Sternberg .timeout = nvme_timeout, 146757dacad5SJay Sternberg }; 146857dacad5SJay Sternberg 1469f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 147057dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 147177f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 147257dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 147357dacad5SJay Sternberg .init_request = nvme_init_request, 1474dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 147557dacad5SJay Sternberg .timeout = nvme_timeout, 1476a0fa9647SJens Axboe .poll = nvme_poll, 147757dacad5SJay Sternberg }; 147857dacad5SJay Sternberg 147957dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 148057dacad5SJay Sternberg { 14811c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 148269d9a99cSKeith Busch /* 148369d9a99cSKeith Busch * If the controller was reset during removal, it's possible 148469d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 148569d9a99cSKeith Busch * queue to flush these to completion. 148669d9a99cSKeith Busch */ 1487c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 14881c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 148957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 149057dacad5SJay Sternberg } 149157dacad5SJay Sternberg } 149257dacad5SJay Sternberg 149357dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 149457dacad5SJay Sternberg { 14951c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 149657dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 149757dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1498e3e9d50cSKeith Busch 149938dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 150057dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 150157dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1502a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1503d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 150457dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 150557dacad5SJay Sternberg 150657dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 150757dacad5SJay Sternberg return -ENOMEM; 150834b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 150957dacad5SJay Sternberg 15101c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 15111c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 151257dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 151357dacad5SJay Sternberg return -ENOMEM; 151457dacad5SJay Sternberg } 15151c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 151657dacad5SJay Sternberg nvme_dev_remove_admin(dev); 15171c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 151857dacad5SJay Sternberg return -ENODEV; 151957dacad5SJay Sternberg } 152057dacad5SJay Sternberg } else 1521c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 152257dacad5SJay Sternberg 152357dacad5SJay Sternberg return 0; 152457dacad5SJay Sternberg } 152557dacad5SJay Sternberg 152697f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 152797f6ef64SXu Yu { 152897f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 152997f6ef64SXu Yu } 153097f6ef64SXu Yu 153197f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 153297f6ef64SXu Yu { 153397f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 153497f6ef64SXu Yu 153597f6ef64SXu Yu if (size <= dev->bar_mapped_size) 153697f6ef64SXu Yu return 0; 153797f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 153897f6ef64SXu Yu return -ENOMEM; 153997f6ef64SXu Yu if (dev->bar) 154097f6ef64SXu Yu iounmap(dev->bar); 154197f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 154297f6ef64SXu Yu if (!dev->bar) { 154397f6ef64SXu Yu dev->bar_mapped_size = 0; 154497f6ef64SXu Yu return -ENOMEM; 154597f6ef64SXu Yu } 154697f6ef64SXu Yu dev->bar_mapped_size = size; 154797f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 154897f6ef64SXu Yu 154997f6ef64SXu Yu return 0; 155097f6ef64SXu Yu } 155197f6ef64SXu Yu 155201ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 155357dacad5SJay Sternberg { 155457dacad5SJay Sternberg int result; 155557dacad5SJay Sternberg u32 aqa; 155657dacad5SJay Sternberg struct nvme_queue *nvmeq; 155757dacad5SJay Sternberg 155897f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 155997f6ef64SXu Yu if (result < 0) 156097f6ef64SXu Yu return result; 156197f6ef64SXu Yu 15628ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 156320d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 156457dacad5SJay Sternberg 15657a67cbeaSChristoph Hellwig if (dev->subsystem && 15667a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 15677a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 156857dacad5SJay Sternberg 156920d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 157057dacad5SJay Sternberg if (result < 0) 157157dacad5SJay Sternberg return result; 157257dacad5SJay Sternberg 1573a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1574147b27e4SSagi Grimberg if (result) 1575147b27e4SSagi Grimberg return result; 157657dacad5SJay Sternberg 1577147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 157857dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 157957dacad5SJay Sternberg aqa |= aqa << 16; 158057dacad5SJay Sternberg 15817a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 15827a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 15837a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 158457dacad5SJay Sternberg 158520d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 158657dacad5SJay Sternberg if (result) 1587d4875622SKeith Busch return result; 158857dacad5SJay Sternberg 158957dacad5SJay Sternberg nvmeq->cq_vector = 0; 1590161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1591dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 159257dacad5SJay Sternberg if (result) { 159357dacad5SJay Sternberg nvmeq->cq_vector = -1; 1594d4875622SKeith Busch return result; 159557dacad5SJay Sternberg } 159657dacad5SJay Sternberg 159757dacad5SJay Sternberg return result; 159857dacad5SJay Sternberg } 159957dacad5SJay Sternberg 1600749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 160157dacad5SJay Sternberg { 1602949928c1SKeith Busch unsigned i, max; 1603749941f2SChristoph Hellwig int ret = 0; 160457dacad5SJay Sternberg 1605d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1606a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1607749941f2SChristoph Hellwig ret = -ENOMEM; 160857dacad5SJay Sternberg break; 1609749941f2SChristoph Hellwig } 1610749941f2SChristoph Hellwig } 161157dacad5SJay Sternberg 1612d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1613949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1614147b27e4SSagi Grimberg ret = nvme_create_queue(&dev->queues[i], i); 1615d4875622SKeith Busch if (ret) 161657dacad5SJay Sternberg break; 161757dacad5SJay Sternberg } 161857dacad5SJay Sternberg 1619749941f2SChristoph Hellwig /* 1620749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 16218adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 16228adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1623749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1624749941f2SChristoph Hellwig */ 1625749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 162657dacad5SJay Sternberg } 162757dacad5SJay Sternberg 1628202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1629202021c1SStephen Bates struct device_attribute *attr, 1630202021c1SStephen Bates char *buf) 1631202021c1SStephen Bates { 1632202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1633202021c1SStephen Bates 1634c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1635202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1636202021c1SStephen Bates } 1637202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1638202021c1SStephen Bates 163988de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 164057dacad5SJay Sternberg { 164188de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 164288de4598SChristoph Hellwig 164388de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 164488de4598SChristoph Hellwig } 164588de4598SChristoph Hellwig 164688de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 164788de4598SChristoph Hellwig { 164888de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 164988de4598SChristoph Hellwig } 165088de4598SChristoph Hellwig 1651f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 165257dacad5SJay Sternberg { 165388de4598SChristoph Hellwig u64 size, offset; 165457dacad5SJay Sternberg resource_size_t bar_size; 165557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 16568969f1f8SChristoph Hellwig int bar; 165757dacad5SJay Sternberg 16587a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1659f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1660f65efd6dSChristoph Hellwig return; 1661202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 166257dacad5SJay Sternberg 166388de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 166488de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 16658969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 16668969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 166757dacad5SJay Sternberg 166857dacad5SJay Sternberg if (offset > bar_size) 1669f65efd6dSChristoph Hellwig return; 167057dacad5SJay Sternberg 167157dacad5SJay Sternberg /* 167257dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 167357dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 167457dacad5SJay Sternberg * the reported size of the BAR 167557dacad5SJay Sternberg */ 167657dacad5SJay Sternberg if (size > bar_size - offset) 167757dacad5SJay Sternberg size = bar_size - offset; 167857dacad5SJay Sternberg 16790f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 16800f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 16810f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1682f65efd6dSChristoph Hellwig return; 16830f238ff5SLogan Gunthorpe } 16840f238ff5SLogan Gunthorpe 168557dacad5SJay Sternberg dev->cmb_size = size; 16860f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 16870f238ff5SLogan Gunthorpe 16880f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 16890f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 16900f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1691f65efd6dSChristoph Hellwig 1692f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1693f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1694f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1695f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 169657dacad5SJay Sternberg } 169757dacad5SJay Sternberg 169857dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 169957dacad5SJay Sternberg { 17000f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1701f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1702f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 17030f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1704f63572dfSJon Derrick } 170557dacad5SJay Sternberg } 170657dacad5SJay Sternberg 170787ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 170857dacad5SJay Sternberg { 17094033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 171087ad72a5SChristoph Hellwig struct nvme_command c; 171187ad72a5SChristoph Hellwig int ret; 171287ad72a5SChristoph Hellwig 171387ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 171487ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 171587ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 171687ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 171787ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 171887ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 171987ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 172087ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 172187ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 172287ad72a5SChristoph Hellwig 172387ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 172487ad72a5SChristoph Hellwig if (ret) { 172587ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 172687ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 172787ad72a5SChristoph Hellwig ret, bits); 172887ad72a5SChristoph Hellwig } 172987ad72a5SChristoph Hellwig return ret; 173087ad72a5SChristoph Hellwig } 173187ad72a5SChristoph Hellwig 173287ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 173387ad72a5SChristoph Hellwig { 173487ad72a5SChristoph Hellwig int i; 173587ad72a5SChristoph Hellwig 173687ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 173787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 173887ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 173987ad72a5SChristoph Hellwig 174087ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 174187ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 174287ad72a5SChristoph Hellwig } 174387ad72a5SChristoph Hellwig 174487ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 174587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 17464033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 17474033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 17484033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 174987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 17507e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 175187ad72a5SChristoph Hellwig } 175287ad72a5SChristoph Hellwig 175392dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 175492dc6895SChristoph Hellwig u32 chunk_size) 175587ad72a5SChristoph Hellwig { 175687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 175792dc6895SChristoph Hellwig u32 max_entries, len; 17584033f35dSChristoph Hellwig dma_addr_t descs_dma; 17592ee0e4edSDan Carpenter int i = 0; 176087ad72a5SChristoph Hellwig void **bufs; 17616fbcde66SMinwoo Im u64 size, tmp; 176287ad72a5SChristoph Hellwig 176387ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 176487ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 176587ad72a5SChristoph Hellwig max_entries = tmp; 1766044a9df1SChristoph Hellwig 1767044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1768044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1769044a9df1SChristoph Hellwig 17704033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 17714033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 177287ad72a5SChristoph Hellwig if (!descs) 177387ad72a5SChristoph Hellwig goto out; 177487ad72a5SChristoph Hellwig 177587ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 177687ad72a5SChristoph Hellwig if (!bufs) 177787ad72a5SChristoph Hellwig goto out_free_descs; 177887ad72a5SChristoph Hellwig 1779244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 178087ad72a5SChristoph Hellwig dma_addr_t dma_addr; 178187ad72a5SChristoph Hellwig 178250cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 178387ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 178487ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 178587ad72a5SChristoph Hellwig if (!bufs[i]) 178687ad72a5SChristoph Hellwig break; 178787ad72a5SChristoph Hellwig 178887ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 178987ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 179087ad72a5SChristoph Hellwig i++; 179187ad72a5SChristoph Hellwig } 179287ad72a5SChristoph Hellwig 179392dc6895SChristoph Hellwig if (!size) 179487ad72a5SChristoph Hellwig goto out_free_bufs; 179587ad72a5SChristoph Hellwig 179687ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 179787ad72a5SChristoph Hellwig dev->host_mem_size = size; 179887ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 17994033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 180087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 180187ad72a5SChristoph Hellwig return 0; 180287ad72a5SChristoph Hellwig 180387ad72a5SChristoph Hellwig out_free_bufs: 180487ad72a5SChristoph Hellwig while (--i >= 0) { 180587ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 180687ad72a5SChristoph Hellwig 180787ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 180887ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 180987ad72a5SChristoph Hellwig } 181087ad72a5SChristoph Hellwig 181187ad72a5SChristoph Hellwig kfree(bufs); 181287ad72a5SChristoph Hellwig out_free_descs: 18134033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 18144033f35dSChristoph Hellwig descs_dma); 181587ad72a5SChristoph Hellwig out: 181687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 181787ad72a5SChristoph Hellwig return -ENOMEM; 181887ad72a5SChristoph Hellwig } 181987ad72a5SChristoph Hellwig 182092dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 182192dc6895SChristoph Hellwig { 182292dc6895SChristoph Hellwig u32 chunk_size; 182392dc6895SChristoph Hellwig 182492dc6895SChristoph Hellwig /* start big and work our way down */ 182530f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1826044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 182792dc6895SChristoph Hellwig chunk_size /= 2) { 182892dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 182992dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 183092dc6895SChristoph Hellwig return 0; 183192dc6895SChristoph Hellwig nvme_free_host_mem(dev); 183292dc6895SChristoph Hellwig } 183392dc6895SChristoph Hellwig } 183492dc6895SChristoph Hellwig 183592dc6895SChristoph Hellwig return -ENOMEM; 183692dc6895SChristoph Hellwig } 183792dc6895SChristoph Hellwig 18389620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 183987ad72a5SChristoph Hellwig { 184087ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 184187ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 184287ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 184387ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 18446fbcde66SMinwoo Im int ret; 184587ad72a5SChristoph Hellwig 184687ad72a5SChristoph Hellwig preferred = min(preferred, max); 184787ad72a5SChristoph Hellwig if (min > max) { 184887ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 184987ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 185087ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 185187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 18529620cfbaSChristoph Hellwig return 0; 185387ad72a5SChristoph Hellwig } 185487ad72a5SChristoph Hellwig 185587ad72a5SChristoph Hellwig /* 185687ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 185787ad72a5SChristoph Hellwig */ 185887ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 185987ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 186087ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 186187ad72a5SChristoph Hellwig else 186287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 186387ad72a5SChristoph Hellwig } 186487ad72a5SChristoph Hellwig 186587ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 186692dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 186792dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 186892dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 18699620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 187087ad72a5SChristoph Hellwig } 187187ad72a5SChristoph Hellwig 187292dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 187392dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 187492dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 187592dc6895SChristoph Hellwig } 187692dc6895SChristoph Hellwig 18779620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 18789620cfbaSChristoph Hellwig if (ret) 187987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 18809620cfbaSChristoph Hellwig return ret; 188157dacad5SJay Sternberg } 188257dacad5SJay Sternberg 188357dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 188457dacad5SJay Sternberg { 1885147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 188657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 188797f6ef64SXu Yu int result, nr_io_queues; 188897f6ef64SXu Yu unsigned long size; 188957dacad5SJay Sternberg 189022b55601SKeith Busch struct irq_affinity affd = { 189122b55601SKeith Busch .pre_vectors = 1 189222b55601SKeith Busch }; 189322b55601SKeith Busch 189416ccfff2SMing Lei nr_io_queues = num_possible_cpus(); 18959a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 18969a0be7abSChristoph Hellwig if (result < 0) 189757dacad5SJay Sternberg return result; 18989a0be7abSChristoph Hellwig 1899f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1900a5229050SKeith Busch return 0; 190157dacad5SJay Sternberg 19020f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 190357dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 190457dacad5SJay Sternberg sizeof(struct nvme_command)); 190557dacad5SJay Sternberg if (result > 0) 190657dacad5SJay Sternberg dev->q_depth = result; 190757dacad5SJay Sternberg else 19080f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 190957dacad5SJay Sternberg } 191057dacad5SJay Sternberg 191157dacad5SJay Sternberg do { 191297f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 191397f6ef64SXu Yu result = nvme_remap_bar(dev, size); 191497f6ef64SXu Yu if (!result) 191557dacad5SJay Sternberg break; 191657dacad5SJay Sternberg if (!--nr_io_queues) 191757dacad5SJay Sternberg return -ENOMEM; 191857dacad5SJay Sternberg } while (1); 191957dacad5SJay Sternberg adminq->q_db = dev->dbs; 192057dacad5SJay Sternberg 192157dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 19220ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 192357dacad5SJay Sternberg 192457dacad5SJay Sternberg /* 192557dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 192657dacad5SJay Sternberg * setting up the full range we need. 192757dacad5SJay Sternberg */ 1928dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 192922b55601SKeith Busch result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1, 193022b55601SKeith Busch PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 193122b55601SKeith Busch if (result <= 0) 1932dca51e78SChristoph Hellwig return -EIO; 193322b55601SKeith Busch dev->num_vecs = result; 193422b55601SKeith Busch dev->max_qid = max(result - 1, 1); 193557dacad5SJay Sternberg 193657dacad5SJay Sternberg /* 193757dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 193857dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 193957dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 194057dacad5SJay Sternberg * number of interrupts. 194157dacad5SJay Sternberg */ 194257dacad5SJay Sternberg 1943dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 194457dacad5SJay Sternberg if (result) { 194557dacad5SJay Sternberg adminq->cq_vector = -1; 1946d4875622SKeith Busch return result; 194757dacad5SJay Sternberg } 1948749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 194957dacad5SJay Sternberg } 195057dacad5SJay Sternberg 19512a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1952db3cbfffSKeith Busch { 1953db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1954db3cbfffSKeith Busch 1955db3cbfffSKeith Busch blk_mq_free_request(req); 1956db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1957db3cbfffSKeith Busch } 1958db3cbfffSKeith Busch 19592a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1960db3cbfffSKeith Busch { 1961db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 19625cb525c8SJens Axboe u16 start, end; 1963db3cbfffSKeith Busch 1964db3cbfffSKeith Busch if (!error) { 1965db3cbfffSKeith Busch unsigned long flags; 1966db3cbfffSKeith Busch 19670bc88192SKeith Busch spin_lock_irqsave(&nvmeq->cq_lock, flags); 19685cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 19691ab0cd69SJens Axboe spin_unlock_irqrestore(&nvmeq->cq_lock, flags); 19705cb525c8SJens Axboe 19715cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1972db3cbfffSKeith Busch } 1973db3cbfffSKeith Busch 1974db3cbfffSKeith Busch nvme_del_queue_end(req, error); 1975db3cbfffSKeith Busch } 1976db3cbfffSKeith Busch 1977db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1978db3cbfffSKeith Busch { 1979db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1980db3cbfffSKeith Busch struct request *req; 1981db3cbfffSKeith Busch struct nvme_command cmd; 1982db3cbfffSKeith Busch 1983db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 1984db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 1985db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1986db3cbfffSKeith Busch 1987eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1988db3cbfffSKeith Busch if (IS_ERR(req)) 1989db3cbfffSKeith Busch return PTR_ERR(req); 1990db3cbfffSKeith Busch 1991db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 1992db3cbfffSKeith Busch req->end_io_data = nvmeq; 1993db3cbfffSKeith Busch 1994db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 1995db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 1996db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 1997db3cbfffSKeith Busch return 0; 1998db3cbfffSKeith Busch } 1999db3cbfffSKeith Busch 2000ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 2001db3cbfffSKeith Busch { 2002ee9aebb2SKeith Busch int pass, queues = dev->online_queues - 1; 2003db3cbfffSKeith Busch unsigned long timeout; 2004db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2005db3cbfffSKeith Busch 2006db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2007014a0d60SKeith Busch int sent = 0, i = queues; 2008db3cbfffSKeith Busch 2009db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2010db3cbfffSKeith Busch retry: 2011db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2012c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2013147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2014db3cbfffSKeith Busch break; 2015c21377f8SGabriel Krisman Bertazi 2016db3cbfffSKeith Busch while (sent--) { 2017db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2018db3cbfffSKeith Busch if (timeout == 0) 2019db3cbfffSKeith Busch return; 2020db3cbfffSKeith Busch if (i) 2021db3cbfffSKeith Busch goto retry; 2022db3cbfffSKeith Busch } 2023db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2024db3cbfffSKeith Busch } 2025db3cbfffSKeith Busch } 2026db3cbfffSKeith Busch 202757dacad5SJay Sternberg /* 20282b1b7e78SJianchao Wang * return error value only when tagset allocation failed 202957dacad5SJay Sternberg */ 203057dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 203157dacad5SJay Sternberg { 20322b1b7e78SJianchao Wang int ret; 20332b1b7e78SJianchao Wang 20345bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 203557dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 203657dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 203757dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 203857dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 203957dacad5SJay Sternberg dev->tagset.queue_depth = 204057dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2041a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2042a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2043a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2044a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2045a7a7cbe3SChaitanya Kulkarni } 204657dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 204757dacad5SJay Sternberg dev->tagset.driver_data = dev; 204857dacad5SJay Sternberg 20492b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 20502b1b7e78SJianchao Wang if (ret) { 20512b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 20522b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 20532b1b7e78SJianchao Wang return ret; 20542b1b7e78SJianchao Wang } 20555bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2056f9f38e33SHelen Koike 2057f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2058949928c1SKeith Busch } else { 2059949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2060949928c1SKeith Busch 2061949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2062949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 206357dacad5SJay Sternberg } 2064949928c1SKeith Busch 206557dacad5SJay Sternberg return 0; 206657dacad5SJay Sternberg } 206757dacad5SJay Sternberg 2068b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 206957dacad5SJay Sternberg { 2070b00a726aSKeith Busch int result = -ENOMEM; 207157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 207257dacad5SJay Sternberg 207357dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 207457dacad5SJay Sternberg return result; 207557dacad5SJay Sternberg 207657dacad5SJay Sternberg pci_set_master(pdev); 207757dacad5SJay Sternberg 207857dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 207957dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 208057dacad5SJay Sternberg goto disable; 208157dacad5SJay Sternberg 20827a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 208357dacad5SJay Sternberg result = -ENODEV; 2084b00a726aSKeith Busch goto disable; 208557dacad5SJay Sternberg } 208657dacad5SJay Sternberg 208757dacad5SJay Sternberg /* 2088a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2089a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2090a5229050SKeith Busch * adjust this later. 209157dacad5SJay Sternberg */ 2092dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2093dca51e78SChristoph Hellwig if (result < 0) 2094dca51e78SChristoph Hellwig return result; 209557dacad5SJay Sternberg 209620d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 20977a67cbeaSChristoph Hellwig 209820d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2099b27c1e68Sweiping zhang io_queue_depth); 210020d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 21017a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 21021f390c1fSStephan Günther 21031f390c1fSStephan Günther /* 21041f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 21051f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 21061f390c1fSStephan Günther */ 21071f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 21081f390c1fSStephan Günther dev->q_depth = 2; 21099bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 21109bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 21111f390c1fSStephan Günther dev->q_depth); 2112d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2113d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 211420d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2115d554b5e1SMartin K. Petersen dev->q_depth = 64; 2116d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2117d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 21181f390c1fSStephan Günther } 21191f390c1fSStephan Günther 2120f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2121202021c1SStephen Bates 2122a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2123a0a3408eSKeith Busch pci_save_state(pdev); 212457dacad5SJay Sternberg return 0; 212557dacad5SJay Sternberg 212657dacad5SJay Sternberg disable: 212757dacad5SJay Sternberg pci_disable_device(pdev); 212857dacad5SJay Sternberg return result; 212957dacad5SJay Sternberg } 213057dacad5SJay Sternberg 213157dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 213257dacad5SJay Sternberg { 2133b00a726aSKeith Busch if (dev->bar) 2134b00a726aSKeith Busch iounmap(dev->bar); 2135a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2136b00a726aSKeith Busch } 2137b00a726aSKeith Busch 2138b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2139b00a726aSKeith Busch { 214057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 214157dacad5SJay Sternberg 2142f63572dfSJon Derrick nvme_release_cmb(dev); 2143dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 214457dacad5SJay Sternberg 2145a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2146a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 214757dacad5SJay Sternberg pci_disable_device(pdev); 214857dacad5SJay Sternberg } 2149a0a3408eSKeith Busch } 215057dacad5SJay Sternberg 2151a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 215257dacad5SJay Sternberg { 2153ee9aebb2SKeith Busch int i; 2154302ad8ccSKeith Busch bool dead = true; 2155302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 215657dacad5SJay Sternberg 215777bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2158302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2159302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2160302ad8ccSKeith Busch 2161ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2162ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2163302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2164302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2165302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 216657dacad5SJay Sternberg } 2167c21377f8SGabriel Krisman Bertazi 2168302ad8ccSKeith Busch /* 2169302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2170302ad8ccSKeith Busch * doing a safe shutdown. 2171302ad8ccSKeith Busch */ 217287ad72a5SChristoph Hellwig if (!dead) { 217387ad72a5SChristoph Hellwig if (shutdown) 2174302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 21759a915a5bSJianchao Wang } 217687ad72a5SChristoph Hellwig 21779a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 21789a915a5bSJianchao Wang 217964ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 2180ee9aebb2SKeith Busch nvme_disable_io_queues(dev); 2181a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 218257dacad5SJay Sternberg } 2183ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2184ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2185ee9aebb2SKeith Busch 2186b00a726aSKeith Busch nvme_pci_disable(dev); 218757dacad5SJay Sternberg 2188e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2189e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2190302ad8ccSKeith Busch 2191302ad8ccSKeith Busch /* 2192302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2193302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2194302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2195302ad8ccSKeith Busch */ 2196302ad8ccSKeith Busch if (shutdown) 2197302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 219877bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 219957dacad5SJay Sternberg } 220057dacad5SJay Sternberg 220157dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 220257dacad5SJay Sternberg { 220357dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 220457dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 220557dacad5SJay Sternberg if (!dev->prp_page_pool) 220657dacad5SJay Sternberg return -ENOMEM; 220757dacad5SJay Sternberg 220857dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 220957dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 221057dacad5SJay Sternberg 256, 256, 0); 221157dacad5SJay Sternberg if (!dev->prp_small_pool) { 221257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 221357dacad5SJay Sternberg return -ENOMEM; 221457dacad5SJay Sternberg } 221557dacad5SJay Sternberg return 0; 221657dacad5SJay Sternberg } 221757dacad5SJay Sternberg 221857dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 221957dacad5SJay Sternberg { 222057dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 222157dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 222257dacad5SJay Sternberg } 222357dacad5SJay Sternberg 22241673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 222557dacad5SJay Sternberg { 22261673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 222757dacad5SJay Sternberg 2228f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 222957dacad5SJay Sternberg put_device(dev->dev); 223057dacad5SJay Sternberg if (dev->tagset.tags) 223157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 22321c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 22331c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 223457dacad5SJay Sternberg kfree(dev->queues); 2235e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2236943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 223757dacad5SJay Sternberg kfree(dev); 223857dacad5SJay Sternberg } 223957dacad5SJay Sternberg 2240f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2241f58944e2SKeith Busch { 2242237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2243f58944e2SKeith Busch 2244d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 224569d9a99cSKeith Busch nvme_dev_disable(dev, false); 22469f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 224703e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2248f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2249f58944e2SKeith Busch } 2250f58944e2SKeith Busch 2251fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 225257dacad5SJay Sternberg { 2253d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2254d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2255a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2256f58944e2SKeith Busch int result = -ENODEV; 22572b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 225857dacad5SJay Sternberg 225982b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2260fd634f41SChristoph Hellwig goto out; 2261fd634f41SChristoph Hellwig 2262fd634f41SChristoph Hellwig /* 2263fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2264fd634f41SChristoph Hellwig * moving on. 2265fd634f41SChristoph Hellwig */ 2266b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2267a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2268fd634f41SChristoph Hellwig 2269ad70062cSJianchao Wang /* 2270ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2271ad70062cSJianchao Wang * initializing procedure here. 2272ad70062cSJianchao Wang */ 2273ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2274ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2275ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2276ad70062cSJianchao Wang goto out; 2277ad70062cSJianchao Wang } 2278ad70062cSJianchao Wang 2279b00a726aSKeith Busch result = nvme_pci_enable(dev); 228057dacad5SJay Sternberg if (result) 228157dacad5SJay Sternberg goto out; 228257dacad5SJay Sternberg 228301ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 228457dacad5SJay Sternberg if (result) 2285f58944e2SKeith Busch goto out; 228657dacad5SJay Sternberg 228757dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 228857dacad5SJay Sternberg if (result) 2289f58944e2SKeith Busch goto out; 229057dacad5SJay Sternberg 2291943e942eSJens Axboe /* 2292943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2293943e942eSJens Axboe * over a single page. 2294943e942eSJens Axboe */ 2295943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2296943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2297943e942eSJens Axboe 2298ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2299ce4541f4SChristoph Hellwig if (result) 2300f58944e2SKeith Busch goto out; 2301ce4541f4SChristoph Hellwig 2302e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2303e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 23044f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 23054f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2306e286bcfcSScott Bauer else if (was_suspend) 23074f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2308e286bcfcSScott Bauer } else { 2309e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2310e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2311e286bcfcSScott Bauer } 2312a98e58e5SScott Bauer 2313f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2314f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2315f9f38e33SHelen Koike if (result) 2316f9f38e33SHelen Koike dev_warn(dev->dev, 2317f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2318f9f38e33SHelen Koike } 2319f9f38e33SHelen Koike 23209620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 23219620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 23229620cfbaSChristoph Hellwig if (result < 0) 23239620cfbaSChristoph Hellwig goto out; 23249620cfbaSChristoph Hellwig } 232587ad72a5SChristoph Hellwig 232657dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 232757dacad5SJay Sternberg if (result) 2328f58944e2SKeith Busch goto out; 232957dacad5SJay Sternberg 233021f033f7SKeith Busch /* 233157dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 233257dacad5SJay Sternberg * any working I/O queue. 233357dacad5SJay Sternberg */ 233457dacad5SJay Sternberg if (dev->online_queues < 2) { 23351b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 23363b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 23375bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 23382b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 233957dacad5SJay Sternberg } else { 234025646264SKeith Busch nvme_start_queues(&dev->ctrl); 2341302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 23422b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 23432b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 23442b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2345302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 234657dacad5SJay Sternberg } 234757dacad5SJay Sternberg 23482b1b7e78SJianchao Wang /* 23492b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 23502b1b7e78SJianchao Wang * recovery. 23512b1b7e78SJianchao Wang */ 23522b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 23532b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23542b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2355bb8d261eSChristoph Hellwig goto out; 2356bb8d261eSChristoph Hellwig } 235792911a55SChristoph Hellwig 2358d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 235957dacad5SJay Sternberg return; 236057dacad5SJay Sternberg 236157dacad5SJay Sternberg out: 2362f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 236357dacad5SJay Sternberg } 236457dacad5SJay Sternberg 23655c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 236657dacad5SJay Sternberg { 23675c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 236857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 236957dacad5SJay Sternberg 237057dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2371921920abSKeith Busch device_release_driver(&pdev->dev); 23721673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 237357dacad5SJay Sternberg } 237457dacad5SJay Sternberg 23751c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 237657dacad5SJay Sternberg { 23771c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 23781c63dc66SChristoph Hellwig return 0; 237957dacad5SJay Sternberg } 23801c63dc66SChristoph Hellwig 23815fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 23825fd4ce1bSChristoph Hellwig { 23835fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 23845fd4ce1bSChristoph Hellwig return 0; 23855fd4ce1bSChristoph Hellwig } 23865fd4ce1bSChristoph Hellwig 23877fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 23887fd8930fSChristoph Hellwig { 23897fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 23907fd8930fSChristoph Hellwig return 0; 23917fd8930fSChristoph Hellwig } 23927fd8930fSChristoph Hellwig 239397c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 239497c12223SKeith Busch { 239597c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 239697c12223SKeith Busch 239797c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 239897c12223SKeith Busch } 239997c12223SKeith Busch 24001c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 24011a353d85SMing Lin .name = "pcie", 2402e439bb12SSagi Grimberg .module = THIS_MODULE, 2403c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 24041c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 24055fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 24067fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 24071673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2408f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 240997c12223SKeith Busch .get_address = nvme_pci_get_address, 24101c63dc66SChristoph Hellwig }; 241157dacad5SJay Sternberg 2412b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2413b00a726aSKeith Busch { 2414b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2415b00a726aSKeith Busch 2416a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2417b00a726aSKeith Busch return -ENODEV; 2418b00a726aSKeith Busch 241997f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2420b00a726aSKeith Busch goto release; 2421b00a726aSKeith Busch 2422b00a726aSKeith Busch return 0; 2423b00a726aSKeith Busch release: 2424a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2425b00a726aSKeith Busch return -ENODEV; 2426b00a726aSKeith Busch } 2427b00a726aSKeith Busch 24288427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2429ff5350a8SAndy Lutomirski { 2430ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2431ff5350a8SAndy Lutomirski /* 2432ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2433ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2434ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2435ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2436ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2437ff5350a8SAndy Lutomirski * laptops. 2438ff5350a8SAndy Lutomirski */ 2439ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2440ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2441ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2442ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 24438427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 24448427bbc2SKai-Heng Feng /* 24458427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2446467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2447467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2448467c77d4SJarosław Janik * ASUS PRIME Z370-A 24498427bbc2SKai-Heng Feng */ 24508427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2451467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2452467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 24538427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2454ff5350a8SAndy Lutomirski } 2455ff5350a8SAndy Lutomirski 2456ff5350a8SAndy Lutomirski return 0; 2457ff5350a8SAndy Lutomirski } 2458ff5350a8SAndy Lutomirski 245918119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 246018119775SKeith Busch { 246118119775SKeith Busch struct nvme_dev *dev = data; 246280f513b5SKeith Busch 246318119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 246418119775SKeith Busch flush_work(&dev->ctrl.scan_work); 246580f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 246618119775SKeith Busch } 246718119775SKeith Busch 246857dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 246957dacad5SJay Sternberg { 247057dacad5SJay Sternberg int node, result = -ENOMEM; 247157dacad5SJay Sternberg struct nvme_dev *dev; 2472ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2473943e942eSJens Axboe size_t alloc_size; 247457dacad5SJay Sternberg 247557dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 247657dacad5SJay Sternberg if (node == NUMA_NO_NODE) 24772fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 247857dacad5SJay Sternberg 247957dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 248057dacad5SJay Sternberg if (!dev) 248157dacad5SJay Sternberg return -ENOMEM; 2482147b27e4SSagi Grimberg 2483147b27e4SSagi Grimberg dev->queues = kcalloc_node(num_possible_cpus() + 1, 2484147b27e4SSagi Grimberg sizeof(struct nvme_queue), GFP_KERNEL, node); 248557dacad5SJay Sternberg if (!dev->queues) 248657dacad5SJay Sternberg goto free; 248757dacad5SJay Sternberg 248857dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 248957dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 249057dacad5SJay Sternberg 2491b00a726aSKeith Busch result = nvme_dev_map(dev); 2492b00a726aSKeith Busch if (result) 2493b00c9b7aSChristophe JAILLET goto put_pci; 2494b00a726aSKeith Busch 2495d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 24965c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 249777bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2498db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2499f3ca80fcSChristoph Hellwig 2500f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2501f3ca80fcSChristoph Hellwig if (result) 2502b00c9b7aSChristophe JAILLET goto unmap; 2503f3ca80fcSChristoph Hellwig 25048427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2505ff5350a8SAndy Lutomirski 2506943e942eSJens Axboe /* 2507943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2508943e942eSJens Axboe * command we support. 2509943e942eSJens Axboe */ 2510943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2511943e942eSJens Axboe NVME_MAX_SEGS, true); 2512943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2513943e942eSJens Axboe 2514943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2515943e942eSJens Axboe mempool_kfree, 2516943e942eSJens Axboe (void *) alloc_size, 2517943e942eSJens Axboe GFP_KERNEL, node); 2518943e942eSJens Axboe if (!dev->iod_mempool) { 2519943e942eSJens Axboe result = -ENOMEM; 2520943e942eSJens Axboe goto release_pools; 2521943e942eSJens Axboe } 2522943e942eSJens Axboe 2523b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2524b6e44b4cSKeith Busch quirks); 2525b6e44b4cSKeith Busch if (result) 2526b6e44b4cSKeith Busch goto release_mempool; 2527b6e44b4cSKeith Busch 25281b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 25291b3c47c1SSagi Grimberg 253080f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 253118119775SKeith Busch async_schedule(nvme_async_probe, dev); 25324caff8fcSSagi Grimberg 253357dacad5SJay Sternberg return 0; 253457dacad5SJay Sternberg 2535b6e44b4cSKeith Busch release_mempool: 2536b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 253757dacad5SJay Sternberg release_pools: 253857dacad5SJay Sternberg nvme_release_prp_pools(dev); 2539b00c9b7aSChristophe JAILLET unmap: 2540b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 254157dacad5SJay Sternberg put_pci: 254257dacad5SJay Sternberg put_device(dev->dev); 254357dacad5SJay Sternberg free: 254457dacad5SJay Sternberg kfree(dev->queues); 254557dacad5SJay Sternberg kfree(dev); 254657dacad5SJay Sternberg return result; 254757dacad5SJay Sternberg } 254857dacad5SJay Sternberg 2549775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 255057dacad5SJay Sternberg { 255157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2552a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2553775755edSChristoph Hellwig } 255457dacad5SJay Sternberg 2555775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2556775755edSChristoph Hellwig { 2557f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 255879c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 255957dacad5SJay Sternberg } 256057dacad5SJay Sternberg 256157dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 256257dacad5SJay Sternberg { 256357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2564a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 256557dacad5SJay Sternberg } 256657dacad5SJay Sternberg 2567f58944e2SKeith Busch /* 2568f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2569f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2570f58944e2SKeith Busch * order to proceed. 2571f58944e2SKeith Busch */ 257257dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 257357dacad5SJay Sternberg { 257457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 257557dacad5SJay Sternberg 2576bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2577bb8d261eSChristoph Hellwig 2578d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 257957dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 25800ff9d4e1SKeith Busch 25816db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 25820ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 25831d39e692SKeith Busch nvme_dev_disable(dev, true); 25846db28edaSKeith Busch } 25850ff9d4e1SKeith Busch 2586d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2587d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2588d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2589a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 259087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 259157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 259257dacad5SJay Sternberg nvme_free_queues(dev, 0); 2593d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 259457dacad5SJay Sternberg nvme_release_prp_pools(dev); 2595b00a726aSKeith Busch nvme_dev_unmap(dev); 25961673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 259757dacad5SJay Sternberg } 259857dacad5SJay Sternberg 259957dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 260057dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 260157dacad5SJay Sternberg { 260257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 260357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 260457dacad5SJay Sternberg 2605a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 260657dacad5SJay Sternberg return 0; 260757dacad5SJay Sternberg } 260857dacad5SJay Sternberg 260957dacad5SJay Sternberg static int nvme_resume(struct device *dev) 261057dacad5SJay Sternberg { 261157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 261257dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 261357dacad5SJay Sternberg 2614d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 261557dacad5SJay Sternberg return 0; 261657dacad5SJay Sternberg } 261757dacad5SJay Sternberg #endif 261857dacad5SJay Sternberg 261957dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 262057dacad5SJay Sternberg 2621a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2622a0a3408eSKeith Busch pci_channel_state_t state) 2623a0a3408eSKeith Busch { 2624a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2625a0a3408eSKeith Busch 2626a0a3408eSKeith Busch /* 2627a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2628a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2629a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2630a0a3408eSKeith Busch */ 2631a0a3408eSKeith Busch switch (state) { 2632a0a3408eSKeith Busch case pci_channel_io_normal: 2633a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2634a0a3408eSKeith Busch case pci_channel_io_frozen: 2635d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2636d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2637a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2638a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2639a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2640d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2641d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2642a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2643a0a3408eSKeith Busch } 2644a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2645a0a3408eSKeith Busch } 2646a0a3408eSKeith Busch 2647a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2648a0a3408eSKeith Busch { 2649a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2650a0a3408eSKeith Busch 26511b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2652a0a3408eSKeith Busch pci_restore_state(pdev); 2653d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2654a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2655a0a3408eSKeith Busch } 2656a0a3408eSKeith Busch 2657a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2658a0a3408eSKeith Busch { 265972cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 266072cd4cc2SKeith Busch 266172cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2662a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2663a0a3408eSKeith Busch } 2664a0a3408eSKeith Busch 266557dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 266657dacad5SJay Sternberg .error_detected = nvme_error_detected, 266757dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 266857dacad5SJay Sternberg .resume = nvme_error_resume, 2669775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2670775755edSChristoph Hellwig .reset_done = nvme_reset_done, 267157dacad5SJay Sternberg }; 267257dacad5SJay Sternberg 267357dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2674106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 267508095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2676e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 267799466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 267899466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2679e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 268099466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 268199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2682e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2683f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2684f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2685f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 268650af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 26879abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 26889abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 2689540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2690540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 26910302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 26920302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 269354adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 269454adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 26958c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 26968c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2697015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2698015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2699d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2700d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2701d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2702d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2703608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2704608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2705608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2706608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2707ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2708ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 270957dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2710c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2711124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 271257dacad5SJay Sternberg { 0, } 271357dacad5SJay Sternberg }; 271457dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 271557dacad5SJay Sternberg 271657dacad5SJay Sternberg static struct pci_driver nvme_driver = { 271757dacad5SJay Sternberg .name = "nvme", 271857dacad5SJay Sternberg .id_table = nvme_id_table, 271957dacad5SJay Sternberg .probe = nvme_probe, 272057dacad5SJay Sternberg .remove = nvme_remove, 272157dacad5SJay Sternberg .shutdown = nvme_shutdown, 272257dacad5SJay Sternberg .driver = { 272357dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 272457dacad5SJay Sternberg }, 272574d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 272657dacad5SJay Sternberg .err_handler = &nvme_err_handler, 272757dacad5SJay Sternberg }; 272857dacad5SJay Sternberg 272957dacad5SJay Sternberg static int __init nvme_init(void) 273057dacad5SJay Sternberg { 27319a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 273257dacad5SJay Sternberg } 273357dacad5SJay Sternberg 273457dacad5SJay Sternberg static void __exit nvme_exit(void) 273557dacad5SJay Sternberg { 273657dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 273703e0f3a6SMing Lei flush_workqueue(nvme_wq); 273857dacad5SJay Sternberg _nvme_check_size(); 273957dacad5SJay Sternberg } 274057dacad5SJay Sternberg 274157dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 274257dacad5SJay Sternberg MODULE_LICENSE("GPL"); 274357dacad5SJay Sternberg MODULE_VERSION("1.0"); 274457dacad5SJay Sternberg module_init(nvme_init); 274557dacad5SJay Sternberg module_exit(nvme_exit); 2746