15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1457dacad5SJay Sternberg #include <linux/init.h> 1557dacad5SJay Sternberg #include <linux/interrupt.h> 1657dacad5SJay Sternberg #include <linux/io.h> 1757dacad5SJay Sternberg #include <linux/mm.h> 1857dacad5SJay Sternberg #include <linux/module.h> 1977bf25eaSKeith Busch #include <linux/mutex.h> 20d0877473SKeith Busch #include <linux/once.h> 2157dacad5SJay Sternberg #include <linux/pci.h> 22d916b1beSKeith Busch #include <linux/suspend.h> 2357dacad5SJay Sternberg #include <linux/t10-pi.h> 2457dacad5SJay Sternberg #include <linux/types.h> 259cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 26a98e58e5SScott Bauer #include <linux/sed-opal.h> 270f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2857dacad5SJay Sternberg 29604c01d5Syupeng #include "trace.h" 3057dacad5SJay Sternberg #include "nvme.h" 3157dacad5SJay Sternberg 32c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 338a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3457dacad5SJay Sternberg 35a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 36adf68f21SChristoph Hellwig 37943e942eSJens Axboe /* 38943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 39943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 40943e942eSJens Axboe */ 41943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 42943e942eSJens Axboe #define NVME_MAX_SEGS 127 43943e942eSJens Axboe 4457dacad5SJay Sternberg static int use_threaded_interrupts; 4557dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4657dacad5SJay Sternberg 4757dacad5SJay Sternberg static bool use_cmb_sqes = true; 4869f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4957dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5057dacad5SJay Sternberg 5187ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5287ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5387ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5487ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5557dacad5SJay Sternberg 56a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 57a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 58a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 59a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 60a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 61a7a7cbe3SChaitanya Kulkarni 62b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 63b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 64b27c1e68Sweiping zhang .set = io_queue_depth_set, 6561f3b896SChaitanya Kulkarni .get = param_get_uint, 66b27c1e68Sweiping zhang }; 67b27c1e68Sweiping zhang 6861f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 69b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 70b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 71b27c1e68Sweiping zhang 729c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 739c9e76d5SWeiping Zhang { 749c9e76d5SWeiping Zhang unsigned int n; 759c9e76d5SWeiping Zhang int ret; 769c9e76d5SWeiping Zhang 779c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 789c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 799c9e76d5SWeiping Zhang return -EINVAL; 809c9e76d5SWeiping Zhang return param_set_uint(val, kp); 819c9e76d5SWeiping Zhang } 829c9e76d5SWeiping Zhang 839c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 849c9e76d5SWeiping Zhang .set = io_queue_count_set, 859c9e76d5SWeiping Zhang .get = param_get_uint, 869c9e76d5SWeiping Zhang }; 879c9e76d5SWeiping Zhang 883f68baf7SKeith Busch static unsigned int write_queues; 899c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 903b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 913b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 923b6592f7SJens Axboe "will share a queue set."); 933b6592f7SJens Axboe 943f68baf7SKeith Busch static unsigned int poll_queues; 959c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 964b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 974b04cc6aSJens Axboe 98df4f9bc4SDavid E. Box static bool noacpi; 99df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 100df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 101df4f9bc4SDavid E. Box 1021c63dc66SChristoph Hellwig struct nvme_dev; 1031c63dc66SChristoph Hellwig struct nvme_queue; 10457dacad5SJay Sternberg 105a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1068fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 10757dacad5SJay Sternberg 10857dacad5SJay Sternberg /* 1091c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1101c63dc66SChristoph Hellwig */ 1111c63dc66SChristoph Hellwig struct nvme_dev { 112147b27e4SSagi Grimberg struct nvme_queue *queues; 1131c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1141c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1151c63dc66SChristoph Hellwig u32 __iomem *dbs; 1161c63dc66SChristoph Hellwig struct device *dev; 1171c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1181c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1191c63dc66SChristoph Hellwig unsigned online_queues; 1201c63dc66SChristoph Hellwig unsigned max_qid; 121e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12222b55601SKeith Busch unsigned int num_vecs; 1237442ddceSJohn Garry u32 q_depth; 124c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1251c63dc66SChristoph Hellwig u32 db_stride; 1261c63dc66SChristoph Hellwig void __iomem *bar; 12797f6ef64SXu Yu unsigned long bar_mapped_size; 1285c8809e6SChristoph Hellwig struct work_struct remove_work; 12977bf25eaSKeith Busch struct mutex shutdown_lock; 1301c63dc66SChristoph Hellwig bool subsystem; 1311c63dc66SChristoph Hellwig u64 cmb_size; 1320f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1331c63dc66SChristoph Hellwig u32 cmbsz; 134202021c1SStephen Bates u32 cmbloc; 1351c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 136d916b1beSKeith Busch u32 last_ps; 13787ad72a5SChristoph Hellwig 138943e942eSJens Axboe mempool_t *iod_mempool; 139943e942eSJens Axboe 14087ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 141f9f38e33SHelen Koike u32 *dbbuf_dbs; 142f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 143f9f38e33SHelen Koike u32 *dbbuf_eis; 144f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 14587ad72a5SChristoph Hellwig 14687ad72a5SChristoph Hellwig /* host memory buffer support: */ 14787ad72a5SChristoph Hellwig u64 host_mem_size; 14887ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1494033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15087ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15187ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1522a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1532a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1542a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 15557dacad5SJay Sternberg }; 15657dacad5SJay Sternberg 157b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 158b27c1e68Sweiping zhang { 15961f3b896SChaitanya Kulkarni int ret; 1607442ddceSJohn Garry u32 n; 161b27c1e68Sweiping zhang 1627442ddceSJohn Garry ret = kstrtou32(val, 10, &n); 163b27c1e68Sweiping zhang if (ret != 0 || n < 2) 164b27c1e68Sweiping zhang return -EINVAL; 165b27c1e68Sweiping zhang 1667442ddceSJohn Garry return param_set_uint(val, kp); 167b27c1e68Sweiping zhang } 168b27c1e68Sweiping zhang 169f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 170f9f38e33SHelen Koike { 171f9f38e33SHelen Koike return qid * 2 * stride; 172f9f38e33SHelen Koike } 173f9f38e33SHelen Koike 174f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 175f9f38e33SHelen Koike { 176f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 177f9f38e33SHelen Koike } 178f9f38e33SHelen Koike 1791c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1801c63dc66SChristoph Hellwig { 1811c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1821c63dc66SChristoph Hellwig } 1831c63dc66SChristoph Hellwig 18457dacad5SJay Sternberg /* 18557dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18657dacad5SJay Sternberg * commands and one for I/O commands). 18757dacad5SJay Sternberg */ 18857dacad5SJay Sternberg struct nvme_queue { 18957dacad5SJay Sternberg struct nvme_dev *dev; 1901ab0cd69SJens Axboe spinlock_t sq_lock; 191c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1923a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1933a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19474943d45SKeith Busch struct nvme_completion *cqes; 19557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19757dacad5SJay Sternberg u32 __iomem *q_db; 1987442ddceSJohn Garry u32 q_depth; 1997c349ddeSKeith Busch u16 cq_vector; 20057dacad5SJay Sternberg u16 sq_tail; 20157dacad5SJay Sternberg u16 cq_head; 20257dacad5SJay Sternberg u16 qid; 20357dacad5SJay Sternberg u8 cq_phase; 204c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2054e224106SChristoph Hellwig unsigned long flags; 2064e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20763223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 208d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2097c349ddeSKeith Busch #define NVMEQ_POLLED 3 210f9f38e33SHelen Koike u32 *dbbuf_sq_db; 211f9f38e33SHelen Koike u32 *dbbuf_cq_db; 212f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 213f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 214d1ed6aa1SChristoph Hellwig struct completion delete_done; 21557dacad5SJay Sternberg }; 21657dacad5SJay Sternberg 21757dacad5SJay Sternberg /* 2189b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2199b048119SChristoph Hellwig * 2209b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2219b048119SChristoph Hellwig * to the actual struct scatterlist. 22271bd150cSChristoph Hellwig */ 22371bd150cSChristoph Hellwig struct nvme_iod { 224d49187e9SChristoph Hellwig struct nvme_request req; 225f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 226a7a7cbe3SChaitanya Kulkarni bool use_sgl; 227f4800d6dSChristoph Hellwig int aborted; 22871bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22971bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 23071bd150cSChristoph Hellwig dma_addr_t first_dma; 231dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 232783b94bdSChristoph Hellwig dma_addr_t meta_dma; 233f4800d6dSChristoph Hellwig struct scatterlist *sg; 23457dacad5SJay Sternberg }; 23557dacad5SJay Sternberg 2362a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2373b6592f7SJens Axboe { 2382a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 239f9f38e33SHelen Koike } 240f9f38e33SHelen Koike 241f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 242f9f38e33SHelen Koike { 2432a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 244f9f38e33SHelen Koike 245f9f38e33SHelen Koike if (dev->dbbuf_dbs) 246f9f38e33SHelen Koike return 0; 247f9f38e33SHelen Koike 248f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 249f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 250f9f38e33SHelen Koike GFP_KERNEL); 251f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 252f9f38e33SHelen Koike return -ENOMEM; 253f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 254f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 255f9f38e33SHelen Koike GFP_KERNEL); 256f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 257f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 258f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 259f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 260f9f38e33SHelen Koike return -ENOMEM; 261f9f38e33SHelen Koike } 262f9f38e33SHelen Koike 263f9f38e33SHelen Koike return 0; 264f9f38e33SHelen Koike } 265f9f38e33SHelen Koike 266f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 267f9f38e33SHelen Koike { 2682a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 269f9f38e33SHelen Koike 270f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 271f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 272f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 273f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 274f9f38e33SHelen Koike } 275f9f38e33SHelen Koike if (dev->dbbuf_eis) { 276f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 277f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 278f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 279f9f38e33SHelen Koike } 280f9f38e33SHelen Koike } 281f9f38e33SHelen Koike 282f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 283f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 284f9f38e33SHelen Koike { 285f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 286f9f38e33SHelen Koike return; 287f9f38e33SHelen Koike 288f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 289f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 290f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 291f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 292f9f38e33SHelen Koike } 293f9f38e33SHelen Koike 294f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 295f9f38e33SHelen Koike { 296f9f38e33SHelen Koike struct nvme_command c; 297f9f38e33SHelen Koike 298f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 299f9f38e33SHelen Koike return; 300f9f38e33SHelen Koike 301f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 302f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 303f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 304f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 305f9f38e33SHelen Koike 306f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3079bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 308f9f38e33SHelen Koike /* Free memory and continue on */ 309f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 310f9f38e33SHelen Koike } 311f9f38e33SHelen Koike } 312f9f38e33SHelen Koike 313f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 314f9f38e33SHelen Koike { 315f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 316f9f38e33SHelen Koike } 317f9f38e33SHelen Koike 318f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 319f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 320f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 321f9f38e33SHelen Koike { 322f9f38e33SHelen Koike if (dbbuf_db) { 323f9f38e33SHelen Koike u16 old_value; 324f9f38e33SHelen Koike 325f9f38e33SHelen Koike /* 326f9f38e33SHelen Koike * Ensure that the queue is written before updating 327f9f38e33SHelen Koike * the doorbell in memory 328f9f38e33SHelen Koike */ 329f9f38e33SHelen Koike wmb(); 330f9f38e33SHelen Koike 331f9f38e33SHelen Koike old_value = *dbbuf_db; 332f9f38e33SHelen Koike *dbbuf_db = value; 333f9f38e33SHelen Koike 334f1ed3df2SMichal Wnukowski /* 335f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 336f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 337f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 338f1ed3df2SMichal Wnukowski * the doorbell. 339f1ed3df2SMichal Wnukowski */ 340f1ed3df2SMichal Wnukowski mb(); 341f1ed3df2SMichal Wnukowski 342f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 343f9f38e33SHelen Koike return false; 344f9f38e33SHelen Koike } 345f9f38e33SHelen Koike 346f9f38e33SHelen Koike return true; 34757dacad5SJay Sternberg } 34857dacad5SJay Sternberg 34957dacad5SJay Sternberg /* 35057dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 35157dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 35257dacad5SJay Sternberg * the I/O. 35357dacad5SJay Sternberg */ 354b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 35557dacad5SJay Sternberg { 356b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3576c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 35857dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 35957dacad5SJay Sternberg } 36057dacad5SJay Sternberg 361a7a7cbe3SChaitanya Kulkarni /* 362a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 363a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 364a7a7cbe3SChaitanya Kulkarni */ 365b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 366f4800d6dSChristoph Hellwig { 367b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 368b13c6393SChaitanya Kulkarni PAGE_SIZE); 369f4800d6dSChristoph Hellwig } 370f4800d6dSChristoph Hellwig 371b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 37257dacad5SJay Sternberg { 373b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 374a7a7cbe3SChaitanya Kulkarni 375b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 376b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 377a7a7cbe3SChaitanya Kulkarni } 378a7a7cbe3SChaitanya Kulkarni 37957dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38057dacad5SJay Sternberg unsigned int hctx_idx) 38157dacad5SJay Sternberg { 38257dacad5SJay Sternberg struct nvme_dev *dev = data; 383147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 38457dacad5SJay Sternberg 38557dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 38657dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 38757dacad5SJay Sternberg 38857dacad5SJay Sternberg hctx->driver_data = nvmeq; 38957dacad5SJay Sternberg return 0; 39057dacad5SJay Sternberg } 39157dacad5SJay Sternberg 39257dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39357dacad5SJay Sternberg unsigned int hctx_idx) 39457dacad5SJay Sternberg { 39557dacad5SJay Sternberg struct nvme_dev *dev = data; 396147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 39757dacad5SJay Sternberg 39857dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 39957dacad5SJay Sternberg hctx->driver_data = nvmeq; 40057dacad5SJay Sternberg return 0; 40157dacad5SJay Sternberg } 40257dacad5SJay Sternberg 403d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 404d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 40557dacad5SJay Sternberg { 406d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 407f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4080350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 409147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 41057dacad5SJay Sternberg 41157dacad5SJay Sternberg BUG_ON(!nvmeq); 412f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 41359e29ce6SSagi Grimberg 41459e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 41557dacad5SJay Sternberg return 0; 41657dacad5SJay Sternberg } 41757dacad5SJay Sternberg 4183b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4193b6592f7SJens Axboe { 4203b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4213b6592f7SJens Axboe if (dev->num_vecs > 1) 4223b6592f7SJens Axboe return 1; 4233b6592f7SJens Axboe 4243b6592f7SJens Axboe return 0; 4253b6592f7SJens Axboe } 4263b6592f7SJens Axboe 427dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 428dca51e78SChristoph Hellwig { 429dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4303b6592f7SJens Axboe int i, qoff, offset; 431dca51e78SChristoph Hellwig 4323b6592f7SJens Axboe offset = queue_irq_offset(dev); 4333b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4343b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4353b6592f7SJens Axboe 4363b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4373b6592f7SJens Axboe if (!map->nr_queues) { 438e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4397e849dd9SChristoph Hellwig continue; 4403b6592f7SJens Axboe } 4413b6592f7SJens Axboe 4424b04cc6aSJens Axboe /* 4434b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4444b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4454b04cc6aSJens Axboe */ 4463b6592f7SJens Axboe map->queue_offset = qoff; 447cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4483b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4494b04cc6aSJens Axboe else 4504b04cc6aSJens Axboe blk_mq_map_queues(map); 4513b6592f7SJens Axboe qoff += map->nr_queues; 4523b6592f7SJens Axboe offset += map->nr_queues; 4533b6592f7SJens Axboe } 4543b6592f7SJens Axboe 4553b6592f7SJens Axboe return 0; 456dca51e78SChristoph Hellwig } 457dca51e78SChristoph Hellwig 45854b2fceeSKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq) 45904f3eafdSJens Axboe { 46004f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 46104f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 46204f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 46304f3eafdSJens Axboe } 46404f3eafdSJens Axboe 46557dacad5SJay Sternberg /** 46690ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 46757dacad5SJay Sternberg * @nvmeq: The queue to use 46857dacad5SJay Sternberg * @cmd: The command to send 46904f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 47057dacad5SJay Sternberg */ 47104f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 47204f3eafdSJens Axboe bool write_sq) 47357dacad5SJay Sternberg { 47490ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 475c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 476c1e0cc7eSBenjamin Herrenschmidt cmd, sizeof(*cmd)); 47790ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 47890ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 47954b2fceeSKeith Busch if (write_sq) 48054b2fceeSKeith Busch nvme_write_sq_db(nvmeq); 48104f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 48204f3eafdSJens Axboe } 48304f3eafdSJens Axboe 48404f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 48504f3eafdSJens Axboe { 48604f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 48704f3eafdSJens Axboe 48804f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 48954b2fceeSKeith Busch nvme_write_sq_db(nvmeq); 49090ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 49157dacad5SJay Sternberg } 49257dacad5SJay Sternberg 493a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 49457dacad5SJay Sternberg { 495f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 496a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 49757dacad5SJay Sternberg } 49857dacad5SJay Sternberg 499955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 500955b1b5aSMinwoo Im { 501955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 50220469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 503955b1b5aSMinwoo Im unsigned int avg_seg_size; 504955b1b5aSMinwoo Im 50520469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 506955b1b5aSMinwoo Im 507955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 508955b1b5aSMinwoo Im return false; 509955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 510955b1b5aSMinwoo Im return false; 511955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 512955b1b5aSMinwoo Im return false; 513955b1b5aSMinwoo Im return true; 514955b1b5aSMinwoo Im } 515955b1b5aSMinwoo Im 5167fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 51757dacad5SJay Sternberg { 518f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5196c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 520a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 52157dacad5SJay Sternberg int i; 52257dacad5SJay Sternberg 523dff824b2SChristoph Hellwig if (iod->dma_len) { 524f2fa006fSIsrael Rukshin dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 525f2fa006fSIsrael Rukshin rq_dma_dir(req)); 526dff824b2SChristoph Hellwig return; 527dff824b2SChristoph Hellwig } 528dff824b2SChristoph Hellwig 529dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 530dff824b2SChristoph Hellwig 5317f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5327f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5337f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5347f73eac3SLogan Gunthorpe else 535dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5367fe07d14SChristoph Hellwig 5377fe07d14SChristoph Hellwig 53857dacad5SJay Sternberg if (iod->npages == 0) 539a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 540a7a7cbe3SChaitanya Kulkarni dma_addr); 541a7a7cbe3SChaitanya Kulkarni 54257dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 543a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 544a7a7cbe3SChaitanya Kulkarni 545a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 546a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 547a7a7cbe3SChaitanya Kulkarni 548a7a7cbe3SChaitanya Kulkarni next_dma_addr = 549a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 550a7a7cbe3SChaitanya Kulkarni } else { 551a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 552a7a7cbe3SChaitanya Kulkarni 553a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 554a7a7cbe3SChaitanya Kulkarni } 555a7a7cbe3SChaitanya Kulkarni 556a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 557a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 55857dacad5SJay Sternberg } 55957dacad5SJay Sternberg 560943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 56157dacad5SJay Sternberg } 56257dacad5SJay Sternberg 563d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 564d0877473SKeith Busch { 565d0877473SKeith Busch int i; 566d0877473SKeith Busch struct scatterlist *sg; 567d0877473SKeith Busch 568d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 569d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 570d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 571d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 572d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 573d0877473SKeith Busch sg_dma_len(sg)); 574d0877473SKeith Busch } 575d0877473SKeith Busch } 576d0877473SKeith Busch 577a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 578a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 57957dacad5SJay Sternberg { 580f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 58157dacad5SJay Sternberg struct dma_pool *pool; 582b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 58357dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 58457dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 58557dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5866c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 58757dacad5SJay Sternberg __le64 *prp_list; 588a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 58957dacad5SJay Sternberg dma_addr_t prp_dma; 59057dacad5SJay Sternberg int nprps, i; 59157dacad5SJay Sternberg 5926c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 5935228b328SJan H. Schönherr if (length <= 0) { 5945228b328SJan H. Schönherr iod->first_dma = 0; 595a7a7cbe3SChaitanya Kulkarni goto done; 5965228b328SJan H. Schönherr } 59757dacad5SJay Sternberg 5986c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 59957dacad5SJay Sternberg if (dma_len) { 6006c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 60157dacad5SJay Sternberg } else { 60257dacad5SJay Sternberg sg = sg_next(sg); 60357dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 60457dacad5SJay Sternberg dma_len = sg_dma_len(sg); 60557dacad5SJay Sternberg } 60657dacad5SJay Sternberg 6076c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 60857dacad5SJay Sternberg iod->first_dma = dma_addr; 609a7a7cbe3SChaitanya Kulkarni goto done; 61057dacad5SJay Sternberg } 61157dacad5SJay Sternberg 6126c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 61357dacad5SJay Sternberg if (nprps <= (256 / 8)) { 61457dacad5SJay Sternberg pool = dev->prp_small_pool; 61557dacad5SJay Sternberg iod->npages = 0; 61657dacad5SJay Sternberg } else { 61757dacad5SJay Sternberg pool = dev->prp_page_pool; 61857dacad5SJay Sternberg iod->npages = 1; 61957dacad5SJay Sternberg } 62057dacad5SJay Sternberg 62169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 62257dacad5SJay Sternberg if (!prp_list) { 62357dacad5SJay Sternberg iod->first_dma = dma_addr; 62457dacad5SJay Sternberg iod->npages = -1; 62586eea289SKeith Busch return BLK_STS_RESOURCE; 62657dacad5SJay Sternberg } 62757dacad5SJay Sternberg list[0] = prp_list; 62857dacad5SJay Sternberg iod->first_dma = prp_dma; 62957dacad5SJay Sternberg i = 0; 63057dacad5SJay Sternberg for (;;) { 6316c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 63257dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 63369d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 63457dacad5SJay Sternberg if (!prp_list) 63586eea289SKeith Busch return BLK_STS_RESOURCE; 63657dacad5SJay Sternberg list[iod->npages++] = prp_list; 63757dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 63857dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 63957dacad5SJay Sternberg i = 1; 64057dacad5SJay Sternberg } 64157dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6426c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6436c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6446c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 64557dacad5SJay Sternberg if (length <= 0) 64657dacad5SJay Sternberg break; 64757dacad5SJay Sternberg if (dma_len > 0) 64857dacad5SJay Sternberg continue; 64986eea289SKeith Busch if (unlikely(dma_len < 0)) 65086eea289SKeith Busch goto bad_sgl; 65157dacad5SJay Sternberg sg = sg_next(sg); 65257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65457dacad5SJay Sternberg } 65557dacad5SJay Sternberg 656a7a7cbe3SChaitanya Kulkarni done: 657a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 658a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 659a7a7cbe3SChaitanya Kulkarni 66086eea289SKeith Busch return BLK_STS_OK; 66186eea289SKeith Busch 66286eea289SKeith Busch bad_sgl: 663d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 664d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 665d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 66686eea289SKeith Busch return BLK_STS_IOERR; 66757dacad5SJay Sternberg } 66857dacad5SJay Sternberg 669a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 670a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 671a7a7cbe3SChaitanya Kulkarni { 672a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 673a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 674a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 675a7a7cbe3SChaitanya Kulkarni } 676a7a7cbe3SChaitanya Kulkarni 677a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 678a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 679a7a7cbe3SChaitanya Kulkarni { 680a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 681a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 682a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 683a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 684a7a7cbe3SChaitanya Kulkarni } else { 685a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 686a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 687a7a7cbe3SChaitanya Kulkarni } 688a7a7cbe3SChaitanya Kulkarni } 689a7a7cbe3SChaitanya Kulkarni 690a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 691b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 692a7a7cbe3SChaitanya Kulkarni { 693a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 694a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 695a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 696a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 697a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 698b0f2853bSChristoph Hellwig int i = 0; 699a7a7cbe3SChaitanya Kulkarni 700a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 701a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 702a7a7cbe3SChaitanya Kulkarni 703b0f2853bSChristoph Hellwig if (entries == 1) { 704a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 705a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 706a7a7cbe3SChaitanya Kulkarni } 707a7a7cbe3SChaitanya Kulkarni 708a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 709a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 710a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 711a7a7cbe3SChaitanya Kulkarni } else { 712a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 713a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 714a7a7cbe3SChaitanya Kulkarni } 715a7a7cbe3SChaitanya Kulkarni 716a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 717a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 718a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 719a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 720a7a7cbe3SChaitanya Kulkarni } 721a7a7cbe3SChaitanya Kulkarni 722a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 723a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 724a7a7cbe3SChaitanya Kulkarni 725a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni do { 728a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 729a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 730a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 731a7a7cbe3SChaitanya Kulkarni 732a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 733a7a7cbe3SChaitanya Kulkarni if (!sg_list) 734a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 735a7a7cbe3SChaitanya Kulkarni 736a7a7cbe3SChaitanya Kulkarni i = 0; 737a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 738a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 739a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 740a7a7cbe3SChaitanya Kulkarni } 741a7a7cbe3SChaitanya Kulkarni 742a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 743a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 744b0f2853bSChristoph Hellwig } while (--entries > 0); 745a7a7cbe3SChaitanya Kulkarni 746a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 747a7a7cbe3SChaitanya Kulkarni } 748a7a7cbe3SChaitanya Kulkarni 749dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 750dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 751dff824b2SChristoph Hellwig struct bio_vec *bv) 752dff824b2SChristoph Hellwig { 753dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7546c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7556c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 756dff824b2SChristoph Hellwig 757dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 758dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 759dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 760dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 761dff824b2SChristoph Hellwig 762dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 763dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 764dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 765359c1f88SBaolin Wang return BLK_STS_OK; 766dff824b2SChristoph Hellwig } 767dff824b2SChristoph Hellwig 76829791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 76929791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 77029791057SChristoph Hellwig struct bio_vec *bv) 77129791057SChristoph Hellwig { 77229791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 77329791057SChristoph Hellwig 77429791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 77529791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 77629791057SChristoph Hellwig return BLK_STS_RESOURCE; 77729791057SChristoph Hellwig iod->dma_len = bv->bv_len; 77829791057SChristoph Hellwig 779049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 78029791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 78129791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 78229791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 783359c1f88SBaolin Wang return BLK_STS_OK; 78429791057SChristoph Hellwig } 78529791057SChristoph Hellwig 786fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 787b131c61dSChristoph Hellwig struct nvme_command *cmnd) 78857dacad5SJay Sternberg { 789f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 79070479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 791b0f2853bSChristoph Hellwig int nr_mapped; 79257dacad5SJay Sternberg 793dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 794dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 795dff824b2SChristoph Hellwig 796dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 7976c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 798dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 799dff824b2SChristoph Hellwig &cmnd->rw, &bv); 80029791057SChristoph Hellwig 80129791057SChristoph Hellwig if (iod->nvmeq->qid && 80229791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 80329791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 80429791057SChristoph Hellwig &cmnd->rw, &bv); 805dff824b2SChristoph Hellwig } 806dff824b2SChristoph Hellwig } 807dff824b2SChristoph Hellwig 808dff824b2SChristoph Hellwig iod->dma_len = 0; 8099b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8109b048119SChristoph Hellwig if (!iod->sg) 8119b048119SChristoph Hellwig return BLK_STS_RESOURCE; 812f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 81370479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 814ba1ca37eSChristoph Hellwig if (!iod->nents) 815ba1ca37eSChristoph Hellwig goto out; 816ba1ca37eSChristoph Hellwig 817e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8182b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8192b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 820e0596ab2SLogan Gunthorpe else 821e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 82270479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 823b0f2853bSChristoph Hellwig if (!nr_mapped) 824ba1ca37eSChristoph Hellwig goto out; 825ba1ca37eSChristoph Hellwig 82670479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 827955b1b5aSMinwoo Im if (iod->use_sgl) 828b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 829a7a7cbe3SChaitanya Kulkarni else 830a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 831ba1ca37eSChristoph Hellwig out: 8324aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8337fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 834ba1ca37eSChristoph Hellwig return ret; 83557dacad5SJay Sternberg } 83657dacad5SJay Sternberg 8374aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8384aedb705SChristoph Hellwig struct nvme_command *cmnd) 8394aedb705SChristoph Hellwig { 8404aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8414aedb705SChristoph Hellwig 8424aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8434aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8444aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8454aedb705SChristoph Hellwig return BLK_STS_IOERR; 8464aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 847359c1f88SBaolin Wang return BLK_STS_OK; 8484aedb705SChristoph Hellwig } 8494aedb705SChristoph Hellwig 85057dacad5SJay Sternberg /* 85157dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 85257dacad5SJay Sternberg */ 853fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 85457dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 85557dacad5SJay Sternberg { 85657dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 85757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 85857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 85957dacad5SJay Sternberg struct request *req = bd->rq; 8609b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 861ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 862ebe6d874SChristoph Hellwig blk_status_t ret; 86357dacad5SJay Sternberg 8649b048119SChristoph Hellwig iod->aborted = 0; 8659b048119SChristoph Hellwig iod->npages = -1; 8669b048119SChristoph Hellwig iod->nents = 0; 8679b048119SChristoph Hellwig 868d1f06f4aSJens Axboe /* 869d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 870d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 871d1f06f4aSJens Axboe */ 8724e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 873d1f06f4aSJens Axboe return BLK_STS_IOERR; 874d1f06f4aSJens Axboe 875f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 876fc17b653SChristoph Hellwig if (ret) 877f4800d6dSChristoph Hellwig return ret; 87857dacad5SJay Sternberg 879fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 880b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 881fc17b653SChristoph Hellwig if (ret) 8829b048119SChristoph Hellwig goto out_free_cmd; 883fc17b653SChristoph Hellwig } 884ba1ca37eSChristoph Hellwig 8854aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 8864aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 8874aedb705SChristoph Hellwig if (ret) 8884aedb705SChristoph Hellwig goto out_unmap_data; 8894aedb705SChristoph Hellwig } 8904aedb705SChristoph Hellwig 891aae239e1SChristoph Hellwig blk_mq_start_request(req); 89204f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 893fc17b653SChristoph Hellwig return BLK_STS_OK; 8944aedb705SChristoph Hellwig out_unmap_data: 8954aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 896f9d03f96SChristoph Hellwig out_free_cmd: 897f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 898ba1ca37eSChristoph Hellwig return ret; 89957dacad5SJay Sternberg } 90057dacad5SJay Sternberg 90177f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 902eee417b0SChristoph Hellwig { 903f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9044aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 905eee417b0SChristoph Hellwig 9064aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9074aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9084aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 909b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9104aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 91177f02a7aSChristoph Hellwig nvme_complete_rq(req); 91257dacad5SJay Sternberg } 91357dacad5SJay Sternberg 914d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 915750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 916d783e0bdSMarta Rybczynska { 91774943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 91874943d45SKeith Busch 91974943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 920d783e0bdSMarta Rybczynska } 921d783e0bdSMarta Rybczynska 922eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 92357dacad5SJay Sternberg { 924eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 92557dacad5SJay Sternberg 926eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 927eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 928eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 929eb281c82SSagi Grimberg } 930adf68f21SChristoph Hellwig 931cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 932cfa27356SChristoph Hellwig { 933cfa27356SChristoph Hellwig if (!nvmeq->qid) 934cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 935cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 936cfa27356SChristoph Hellwig } 937cfa27356SChristoph Hellwig 9385cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 93957dacad5SJay Sternberg { 94074943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 94157dacad5SJay Sternberg struct request *req; 942adf68f21SChristoph Hellwig 94383a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9441b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 945aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 94683a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 94783a12fb7SSagi Grimberg return; 948aae239e1SChristoph Hellwig } 949aae239e1SChristoph Hellwig 950adf68f21SChristoph Hellwig /* 951adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 952adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 953adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 954adf68f21SChristoph Hellwig * for them but rather special case them here. 955adf68f21SChristoph Hellwig */ 95658a8df67SIsrael Rukshin if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) { 9577bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 95883a12fb7SSagi Grimberg cqe->status, &cqe->result); 959a0fa9647SJens Axboe return; 96057dacad5SJay Sternberg } 96157dacad5SJay Sternberg 962cfa27356SChristoph Hellwig req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id); 963604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 9642eb81a33SChristoph Hellwig if (!nvme_try_complete_req(req, cqe->status, cqe->result)) 965ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 96683a12fb7SSagi Grimberg } 96757dacad5SJay Sternberg 9685cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9695cb525c8SJens Axboe { 970a8de6639SAlexey Dobriyan u16 tmp = nvmeq->cq_head + 1; 971a8de6639SAlexey Dobriyan 972a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 973920d13a8SSagi Grimberg nvmeq->cq_head = 0; 974e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 975a8de6639SAlexey Dobriyan } else { 976a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 977920d13a8SSagi Grimberg } 978a0fa9647SJens Axboe } 979a0fa9647SJens Axboe 980324b494cSKeith Busch static inline int nvme_process_cq(struct nvme_queue *nvmeq) 981a0fa9647SJens Axboe { 9821052b8acSJens Axboe int found = 0; 98383a12fb7SSagi Grimberg 9841052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 9851052b8acSJens Axboe found++; 986b69e2ef2SKeith Busch /* 987b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 988b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 989b69e2ef2SKeith Busch */ 990b69e2ef2SKeith Busch dma_rmb(); 991324b494cSKeith Busch nvme_handle_cqe(nvmeq, nvmeq->cq_head); 9925cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 99357dacad5SJay Sternberg } 99457dacad5SJay Sternberg 995324b494cSKeith Busch if (found) 996eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 9975cb525c8SJens Axboe return found; 99857dacad5SJay Sternberg } 99957dacad5SJay Sternberg 100057dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 100157dacad5SJay Sternberg { 100257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 100368fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10045cb525c8SJens Axboe 10053a7afd8eSChristoph Hellwig /* 10063a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10073a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10083a7afd8eSChristoph Hellwig */ 10093a7afd8eSChristoph Hellwig rmb(); 1010324b494cSKeith Busch if (nvme_process_cq(nvmeq)) 1011324b494cSKeith Busch ret = IRQ_HANDLED; 10123a7afd8eSChristoph Hellwig wmb(); 10135cb525c8SJens Axboe 101468fa9dbeSJens Axboe return ret; 101557dacad5SJay Sternberg } 101657dacad5SJay Sternberg 101757dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 101857dacad5SJay Sternberg { 101957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10204e523547SBaolin Wang 1021750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 102257dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1023d783e0bdSMarta Rybczynska return IRQ_NONE; 102457dacad5SJay Sternberg } 102557dacad5SJay Sternberg 10260b2a8a9fSChristoph Hellwig /* 1027fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 10280b2a8a9fSChristoph Hellwig * Can be called from any context. 10290b2a8a9fSChristoph Hellwig */ 1030fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1031a0fa9647SJens Axboe { 10323a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1033a0fa9647SJens Axboe 1034fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1035fa059b85SKeith Busch 10363a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1037fa059b85SKeith Busch nvme_process_cq(nvmeq); 10383a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 103991a509f8SChristoph Hellwig } 1040442e19b7SSagi Grimberg 10419743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10427776db1cSKeith Busch { 10437776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1044dabcefabSJens Axboe bool found; 1045dabcefabSJens Axboe 1046dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1047dabcefabSJens Axboe return 0; 1048dabcefabSJens Axboe 10493a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1050324b494cSKeith Busch found = nvme_process_cq(nvmeq); 10513a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1052dabcefabSJens Axboe 1053dabcefabSJens Axboe return found; 1054dabcefabSJens Axboe } 1055dabcefabSJens Axboe 1056ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 105757dacad5SJay Sternberg { 1058f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1059147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 106057dacad5SJay Sternberg struct nvme_command c; 106157dacad5SJay Sternberg 106257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 106357dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1064ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 106504f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 106657dacad5SJay Sternberg } 106757dacad5SJay Sternberg 106857dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 106957dacad5SJay Sternberg { 107057dacad5SJay Sternberg struct nvme_command c; 107157dacad5SJay Sternberg 107257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 107357dacad5SJay Sternberg c.delete_queue.opcode = opcode; 107457dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 107557dacad5SJay Sternberg 10761c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 107757dacad5SJay Sternberg } 107857dacad5SJay Sternberg 107957dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1080a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 108157dacad5SJay Sternberg { 108257dacad5SJay Sternberg struct nvme_command c; 10834b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 10844b04cc6aSJens Axboe 10857c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 10864b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 108757dacad5SJay Sternberg 108857dacad5SJay Sternberg /* 108916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 109057dacad5SJay Sternberg * is attached to the request. 109157dacad5SJay Sternberg */ 109257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 109357dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 109457dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 109557dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 109657dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 109757dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1098a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 109957dacad5SJay Sternberg 11001c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 110157dacad5SJay Sternberg } 110257dacad5SJay Sternberg 110357dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 110457dacad5SJay Sternberg struct nvme_queue *nvmeq) 110557dacad5SJay Sternberg { 11069abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 110757dacad5SJay Sternberg struct nvme_command c; 110881c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 110957dacad5SJay Sternberg 111057dacad5SJay Sternberg /* 11119abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11129abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11139abd68efSJens Axboe * URGENT. 11149abd68efSJens Axboe */ 11159abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11169abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11179abd68efSJens Axboe 11189abd68efSJens Axboe /* 111916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 112057dacad5SJay Sternberg * is attached to the request. 112157dacad5SJay Sternberg */ 112257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112357dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 112457dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 112557dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 112657dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 112757dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 112857dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 112957dacad5SJay Sternberg 11301c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 113157dacad5SJay Sternberg } 113257dacad5SJay Sternberg 113357dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 113457dacad5SJay Sternberg { 113557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 113657dacad5SJay Sternberg } 113757dacad5SJay Sternberg 113857dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 113957dacad5SJay Sternberg { 114057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 114157dacad5SJay Sternberg } 114257dacad5SJay Sternberg 11432a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 114457dacad5SJay Sternberg { 1145f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1146f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 114757dacad5SJay Sternberg 114827fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 114927fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1150e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1151e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 115257dacad5SJay Sternberg } 115357dacad5SJay Sternberg 1154b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1155b2a0eb1aSKeith Busch { 1156b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1157b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1158b2a0eb1aSKeith Busch */ 1159b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1160b2a0eb1aSKeith Busch 1161ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1162ad70062cSJianchao Wang switch (dev->ctrl.state) { 1163ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1164ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1165b2a0eb1aSKeith Busch return false; 1166ad70062cSJianchao Wang default: 1167ad70062cSJianchao Wang break; 1168ad70062cSJianchao Wang } 1169b2a0eb1aSKeith Busch 1170b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1171b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1172b2a0eb1aSKeith Busch */ 1173b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1174b2a0eb1aSKeith Busch return false; 1175b2a0eb1aSKeith Busch 1176b2a0eb1aSKeith Busch return true; 1177b2a0eb1aSKeith Busch } 1178b2a0eb1aSKeith Busch 1179b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1180b2a0eb1aSKeith Busch { 1181b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1182b2a0eb1aSKeith Busch u16 pci_status; 1183b2a0eb1aSKeith Busch int result; 1184b2a0eb1aSKeith Busch 1185b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1186b2a0eb1aSKeith Busch &pci_status); 1187b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1188b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1189b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1190b2a0eb1aSKeith Busch csts, pci_status); 1191b2a0eb1aSKeith Busch else 1192b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1193b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1194b2a0eb1aSKeith Busch csts, result); 1195b2a0eb1aSKeith Busch } 1196b2a0eb1aSKeith Busch 119731c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 119857dacad5SJay Sternberg { 1199f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1200f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 120157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 120257dacad5SJay Sternberg struct request *abort_req; 120357dacad5SJay Sternberg struct nvme_command cmd; 1204b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1205b2a0eb1aSKeith Busch 1206651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1207651438bbSWen Xiong * the recovery mechanism will surely fail. 1208651438bbSWen Xiong */ 1209651438bbSWen Xiong mb(); 1210651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1211651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1212651438bbSWen Xiong 1213b2a0eb1aSKeith Busch /* 1214b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1215b2a0eb1aSKeith Busch */ 1216b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1217b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1218b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1219d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1220db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1221b2a0eb1aSKeith Busch } 122257dacad5SJay Sternberg 122331c7c7d2SChristoph Hellwig /* 12247776db1cSKeith Busch * Did we miss an interrupt? 12257776db1cSKeith Busch */ 1226fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1227fa059b85SKeith Busch nvme_poll(req->mq_hctx); 1228fa059b85SKeith Busch else 1229bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1230fa059b85SKeith Busch 1231bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 12327776db1cSKeith Busch dev_warn(dev->ctrl.device, 12337776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12347776db1cSKeith Busch req->tag, nvmeq->qid); 1235db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12367776db1cSKeith Busch } 12377776db1cSKeith Busch 12387776db1cSKeith Busch /* 1239fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1240fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1241fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1242db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1243fd634f41SChristoph Hellwig */ 12444244140dSKeith Busch switch (dev->ctrl.state) { 12454244140dSKeith Busch case NVME_CTRL_CONNECTING: 12462036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1247df561f66SGustavo A. R. Silva fallthrough; 12482036f726SKeith Busch case NVME_CTRL_DELETING: 1249b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1250fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1251fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 125227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 12537ad92f65STong Zhang nvme_dev_disable(dev, true); 1254db8c48e4SChristoph Hellwig return BLK_EH_DONE; 125539a9dd81SKeith Busch case NVME_CTRL_RESETTING: 125639a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 12574244140dSKeith Busch default: 12584244140dSKeith Busch break; 1259fd634f41SChristoph Hellwig } 1260fd634f41SChristoph Hellwig 1261fd634f41SChristoph Hellwig /* 1262e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1263e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1264e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 126531c7c7d2SChristoph Hellwig */ 1266f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12671b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 126857dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 126957dacad5SJay Sternberg req->tag, nvmeq->qid); 12707ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1271a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1272d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1273e1569a16SKeith Busch 1274db8c48e4SChristoph Hellwig return BLK_EH_DONE; 127557dacad5SJay Sternberg } 127657dacad5SJay Sternberg 1277e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1278e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1279e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1280e7a2a87dSChristoph Hellwig } 12817bf7d778SKeith Busch iod->aborted = 1; 128257dacad5SJay Sternberg 128357dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 128457dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 128557dacad5SJay Sternberg cmd.abort.cid = req->tag; 128657dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 128757dacad5SJay Sternberg 12881b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12891b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 129057dacad5SJay Sternberg req->tag, nvmeq->qid); 1291e7a2a87dSChristoph Hellwig 1292e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1293eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12946bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12956bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 129631c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 129757dacad5SJay Sternberg } 129857dacad5SJay Sternberg 1299e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1300e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1301e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 130257dacad5SJay Sternberg 130357dacad5SJay Sternberg /* 130457dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 130557dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 130657dacad5SJay Sternberg * as the device then is in a faulty state. 130757dacad5SJay Sternberg */ 130857dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 130957dacad5SJay Sternberg } 131057dacad5SJay Sternberg 131157dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 131257dacad5SJay Sternberg { 13138a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 131457dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 131563223078SChristoph Hellwig if (!nvmeq->sq_cmds) 131663223078SChristoph Hellwig return; 13170f238ff5SLogan Gunthorpe 131863223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 131988a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13208a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 132163223078SChristoph Hellwig } else { 13228a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 132363223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13240f238ff5SLogan Gunthorpe } 132557dacad5SJay Sternberg } 132657dacad5SJay Sternberg 132757dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 132857dacad5SJay Sternberg { 132957dacad5SJay Sternberg int i; 133057dacad5SJay Sternberg 1331d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1332d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1333147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 133457dacad5SJay Sternberg } 133557dacad5SJay Sternberg } 133657dacad5SJay Sternberg 133757dacad5SJay Sternberg /** 133857dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 133940581d1aSBart Van Assche * @nvmeq: queue to suspend 134057dacad5SJay Sternberg */ 134157dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 134257dacad5SJay Sternberg { 13434e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 134457dacad5SJay Sternberg return 1; 134557dacad5SJay Sternberg 13464e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1347d1f06f4aSJens Axboe mb(); 134857dacad5SJay Sternberg 13494e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13501c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1351c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13527c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 13534e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 135457dacad5SJay Sternberg return 0; 135557dacad5SJay Sternberg } 135657dacad5SJay Sternberg 13578fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 13588fae268bSKeith Busch { 13598fae268bSKeith Busch int i; 13608fae268bSKeith Busch 13618fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 13628fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 13638fae268bSKeith Busch } 13648fae268bSKeith Busch 1365a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 136657dacad5SJay Sternberg { 1367147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 136857dacad5SJay Sternberg 1369a5cdb68cSKeith Busch if (shutdown) 1370a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1371a5cdb68cSKeith Busch else 1372b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 137357dacad5SJay Sternberg 1374bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 137557dacad5SJay Sternberg } 137657dacad5SJay Sternberg 1377fa46c6fbSKeith Busch /* 1378fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 13799210c075SDongli Zhang * that can check this device's completion queues have synced, except 13809210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 13819210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1382fa46c6fbSKeith Busch */ 1383fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1384fa46c6fbSKeith Busch { 1385fa46c6fbSKeith Busch int i; 1386fa46c6fbSKeith Busch 13879210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 13889210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1389324b494cSKeith Busch nvme_process_cq(&dev->queues[i]); 13909210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 13919210c075SDongli Zhang } 1392fa46c6fbSKeith Busch } 1393fa46c6fbSKeith Busch 139457dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 139557dacad5SJay Sternberg int entry_size) 139657dacad5SJay Sternberg { 139757dacad5SJay Sternberg int q_depth = dev->q_depth; 13985fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13996c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 140057dacad5SJay Sternberg 140157dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 140257dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14034e523547SBaolin Wang 14046c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 140557dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 140657dacad5SJay Sternberg 140757dacad5SJay Sternberg /* 140857dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 140957dacad5SJay Sternberg * would be better to map queues in system memory with the 141057dacad5SJay Sternberg * original depth 141157dacad5SJay Sternberg */ 141257dacad5SJay Sternberg if (q_depth < 64) 141357dacad5SJay Sternberg return -ENOMEM; 141457dacad5SJay Sternberg } 141557dacad5SJay Sternberg 141657dacad5SJay Sternberg return q_depth; 141757dacad5SJay Sternberg } 141857dacad5SJay Sternberg 141957dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14208a1d09a6SBenjamin Herrenschmidt int qid) 142157dacad5SJay Sternberg { 14220f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1423815c6704SKeith Busch 14240f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14258a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1426bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14270f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14280f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 142963223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 143063223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 143163223078SChristoph Hellwig return 0; 143263223078SChristoph Hellwig } 1433bfac8e9fSAlan Mikhak 14348a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1435bfac8e9fSAlan Mikhak } 14360f238ff5SLogan Gunthorpe } 14370f238ff5SLogan Gunthorpe 14388a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 143957dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 144057dacad5SJay Sternberg if (!nvmeq->sq_cmds) 144157dacad5SJay Sternberg return -ENOMEM; 144257dacad5SJay Sternberg return 0; 144357dacad5SJay Sternberg } 144457dacad5SJay Sternberg 1445a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 144657dacad5SJay Sternberg { 1447147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 144857dacad5SJay Sternberg 144962314e40SKeith Busch if (dev->ctrl.queue_count > qid) 145062314e40SKeith Busch return 0; 145157dacad5SJay Sternberg 1452c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 14538a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 14548a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 145557dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 145657dacad5SJay Sternberg if (!nvmeq->cqes) 145757dacad5SJay Sternberg goto free_nvmeq; 145857dacad5SJay Sternberg 14598a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 146057dacad5SJay Sternberg goto free_cqdma; 146157dacad5SJay Sternberg 146257dacad5SJay Sternberg nvmeq->dev = dev; 14631ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14643a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 146557dacad5SJay Sternberg nvmeq->cq_head = 0; 146657dacad5SJay Sternberg nvmeq->cq_phase = 1; 146757dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 146857dacad5SJay Sternberg nvmeq->qid = qid; 1469d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 147057dacad5SJay Sternberg 1471147b27e4SSagi Grimberg return 0; 147257dacad5SJay Sternberg 147357dacad5SJay Sternberg free_cqdma: 14748a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 147557dacad5SJay Sternberg nvmeq->cq_dma_addr); 147657dacad5SJay Sternberg free_nvmeq: 1477147b27e4SSagi Grimberg return -ENOMEM; 147857dacad5SJay Sternberg } 147957dacad5SJay Sternberg 1480dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 148157dacad5SJay Sternberg { 14820ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14830ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14840ff199cbSChristoph Hellwig 14850ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14860ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14870ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14880ff199cbSChristoph Hellwig } else { 14890ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14900ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14910ff199cbSChristoph Hellwig } 149257dacad5SJay Sternberg } 149357dacad5SJay Sternberg 149457dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 149557dacad5SJay Sternberg { 149657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 149757dacad5SJay Sternberg 149857dacad5SJay Sternberg nvmeq->sq_tail = 0; 149957dacad5SJay Sternberg nvmeq->cq_head = 0; 150057dacad5SJay Sternberg nvmeq->cq_phase = 1; 150157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15028a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1503f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 150457dacad5SJay Sternberg dev->online_queues++; 15053a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 150657dacad5SJay Sternberg } 150757dacad5SJay Sternberg 15084b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 150957dacad5SJay Sternberg { 151057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 151157dacad5SJay Sternberg int result; 15127c349ddeSKeith Busch u16 vector = 0; 151357dacad5SJay Sternberg 1514d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1515d1ed6aa1SChristoph Hellwig 151622b55601SKeith Busch /* 151722b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 151822b55601SKeith Busch * has only one vector available. 151922b55601SKeith Busch */ 15204b04cc6aSJens Axboe if (!polled) 1521a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15224b04cc6aSJens Axboe else 15237c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15244b04cc6aSJens Axboe 1525a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1526ded45505SKeith Busch if (result) 1527ded45505SKeith Busch return result; 152857dacad5SJay Sternberg 152957dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 153057dacad5SJay Sternberg if (result < 0) 1531ded45505SKeith Busch return result; 1532c80b36cdSEdmund Nadolski if (result) 153357dacad5SJay Sternberg goto release_cq; 153457dacad5SJay Sternberg 1535a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1536161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15374b04cc6aSJens Axboe 15387c349ddeSKeith Busch if (!polled) { 1539dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 154057dacad5SJay Sternberg if (result < 0) 154157dacad5SJay Sternberg goto release_sq; 15424b04cc6aSJens Axboe } 154357dacad5SJay Sternberg 15444e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 154557dacad5SJay Sternberg return result; 154657dacad5SJay Sternberg 154757dacad5SJay Sternberg release_sq: 1548f25a2dfcSJianchao Wang dev->online_queues--; 154957dacad5SJay Sternberg adapter_delete_sq(dev, qid); 155057dacad5SJay Sternberg release_cq: 155157dacad5SJay Sternberg adapter_delete_cq(dev, qid); 155257dacad5SJay Sternberg return result; 155357dacad5SJay Sternberg } 155457dacad5SJay Sternberg 1555f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 155657dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 155777f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 155857dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 15590350815aSChristoph Hellwig .init_request = nvme_init_request, 156057dacad5SJay Sternberg .timeout = nvme_timeout, 156157dacad5SJay Sternberg }; 156257dacad5SJay Sternberg 1563f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1564376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1565376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1566376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1567376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1568376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1569376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1570376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1571c6d962aeSChristoph Hellwig .poll = nvme_poll, 1572dabcefabSJens Axboe }; 1573dabcefabSJens Axboe 157457dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 157557dacad5SJay Sternberg { 15761c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 157769d9a99cSKeith Busch /* 157869d9a99cSKeith Busch * If the controller was reset during removal, it's possible 157969d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 158069d9a99cSKeith Busch * queue to flush these to completion. 158169d9a99cSKeith Busch */ 1582c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15831c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 158457dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 158557dacad5SJay Sternberg } 158657dacad5SJay Sternberg } 158757dacad5SJay Sternberg 158857dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 158957dacad5SJay Sternberg { 15901c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 159157dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 159257dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1593e3e9d50cSKeith Busch 159438dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 159557dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1596d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1597d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1598d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 159957dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 160057dacad5SJay Sternberg 160157dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 160257dacad5SJay Sternberg return -ENOMEM; 160334b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 160457dacad5SJay Sternberg 16051c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16061c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 160757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 160857dacad5SJay Sternberg return -ENOMEM; 160957dacad5SJay Sternberg } 16101c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 161157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16121c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 161357dacad5SJay Sternberg return -ENODEV; 161457dacad5SJay Sternberg } 161557dacad5SJay Sternberg } else 1616c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 161757dacad5SJay Sternberg 161857dacad5SJay Sternberg return 0; 161957dacad5SJay Sternberg } 162057dacad5SJay Sternberg 162197f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 162297f6ef64SXu Yu { 162397f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 162497f6ef64SXu Yu } 162597f6ef64SXu Yu 162697f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 162797f6ef64SXu Yu { 162897f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 162997f6ef64SXu Yu 163097f6ef64SXu Yu if (size <= dev->bar_mapped_size) 163197f6ef64SXu Yu return 0; 163297f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 163397f6ef64SXu Yu return -ENOMEM; 163497f6ef64SXu Yu if (dev->bar) 163597f6ef64SXu Yu iounmap(dev->bar); 163697f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 163797f6ef64SXu Yu if (!dev->bar) { 163897f6ef64SXu Yu dev->bar_mapped_size = 0; 163997f6ef64SXu Yu return -ENOMEM; 164097f6ef64SXu Yu } 164197f6ef64SXu Yu dev->bar_mapped_size = size; 164297f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 164397f6ef64SXu Yu 164497f6ef64SXu Yu return 0; 164597f6ef64SXu Yu } 164697f6ef64SXu Yu 164701ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 164857dacad5SJay Sternberg { 164957dacad5SJay Sternberg int result; 165057dacad5SJay Sternberg u32 aqa; 165157dacad5SJay Sternberg struct nvme_queue *nvmeq; 165257dacad5SJay Sternberg 165397f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 165497f6ef64SXu Yu if (result < 0) 165597f6ef64SXu Yu return result; 165697f6ef64SXu Yu 16578ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 165820d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 165957dacad5SJay Sternberg 16607a67cbeaSChristoph Hellwig if (dev->subsystem && 16617a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16627a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 166357dacad5SJay Sternberg 1664b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 166557dacad5SJay Sternberg if (result < 0) 166657dacad5SJay Sternberg return result; 166757dacad5SJay Sternberg 1668a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1669147b27e4SSagi Grimberg if (result) 1670147b27e4SSagi Grimberg return result; 167157dacad5SJay Sternberg 1672635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1673635333e4SMax Gurtovoy 1674147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 167557dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 167657dacad5SJay Sternberg aqa |= aqa << 16; 167757dacad5SJay Sternberg 16787a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16797a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16807a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 168157dacad5SJay Sternberg 1682c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 168357dacad5SJay Sternberg if (result) 1684d4875622SKeith Busch return result; 168557dacad5SJay Sternberg 168657dacad5SJay Sternberg nvmeq->cq_vector = 0; 1687161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1688dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 168957dacad5SJay Sternberg if (result) { 16907c349ddeSKeith Busch dev->online_queues--; 1691d4875622SKeith Busch return result; 169257dacad5SJay Sternberg } 169357dacad5SJay Sternberg 16944e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 169557dacad5SJay Sternberg return result; 169657dacad5SJay Sternberg } 169757dacad5SJay Sternberg 1698749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 169957dacad5SJay Sternberg { 17004b04cc6aSJens Axboe unsigned i, max, rw_queues; 1701749941f2SChristoph Hellwig int ret = 0; 170257dacad5SJay Sternberg 1703d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1704a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1705749941f2SChristoph Hellwig ret = -ENOMEM; 170657dacad5SJay Sternberg break; 1707749941f2SChristoph Hellwig } 1708749941f2SChristoph Hellwig } 170957dacad5SJay Sternberg 1710d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1711e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1712e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1713e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17144b04cc6aSJens Axboe } else { 17154b04cc6aSJens Axboe rw_queues = max; 17164b04cc6aSJens Axboe } 17174b04cc6aSJens Axboe 1718949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17194b04cc6aSJens Axboe bool polled = i > rw_queues; 17204b04cc6aSJens Axboe 17214b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1722d4875622SKeith Busch if (ret) 172357dacad5SJay Sternberg break; 172457dacad5SJay Sternberg } 172557dacad5SJay Sternberg 1726749941f2SChristoph Hellwig /* 1727749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17288adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17298adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1730749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1731749941f2SChristoph Hellwig */ 1732749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 173357dacad5SJay Sternberg } 173457dacad5SJay Sternberg 1735202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1736202021c1SStephen Bates struct device_attribute *attr, 1737202021c1SStephen Bates char *buf) 1738202021c1SStephen Bates { 1739202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1740202021c1SStephen Bates 1741c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1742202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1743202021c1SStephen Bates } 1744202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1745202021c1SStephen Bates 174688de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 174757dacad5SJay Sternberg { 174888de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 174988de4598SChristoph Hellwig 175088de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 175188de4598SChristoph Hellwig } 175288de4598SChristoph Hellwig 175388de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 175488de4598SChristoph Hellwig { 175588de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 175688de4598SChristoph Hellwig } 175788de4598SChristoph Hellwig 1758f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 175957dacad5SJay Sternberg { 176088de4598SChristoph Hellwig u64 size, offset; 176157dacad5SJay Sternberg resource_size_t bar_size; 176257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17638969f1f8SChristoph Hellwig int bar; 176457dacad5SJay Sternberg 17659fe5c59fSKeith Busch if (dev->cmb_size) 17669fe5c59fSKeith Busch return; 17679fe5c59fSKeith Busch 17687a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1769f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1770f65efd6dSChristoph Hellwig return; 1771202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 177257dacad5SJay Sternberg 177388de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 177488de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17758969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17768969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 177757dacad5SJay Sternberg 177857dacad5SJay Sternberg if (offset > bar_size) 1779f65efd6dSChristoph Hellwig return; 178057dacad5SJay Sternberg 178157dacad5SJay Sternberg /* 178257dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 178357dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 178457dacad5SJay Sternberg * the reported size of the BAR 178557dacad5SJay Sternberg */ 178657dacad5SJay Sternberg if (size > bar_size - offset) 178757dacad5SJay Sternberg size = bar_size - offset; 178857dacad5SJay Sternberg 17890f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 17900f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 17910f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1792f65efd6dSChristoph Hellwig return; 17930f238ff5SLogan Gunthorpe } 17940f238ff5SLogan Gunthorpe 179557dacad5SJay Sternberg dev->cmb_size = size; 17960f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 17970f238ff5SLogan Gunthorpe 17980f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 17990f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18000f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1801f65efd6dSChristoph Hellwig 1802f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1803f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1804f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1805f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 180657dacad5SJay Sternberg } 180757dacad5SJay Sternberg 180857dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 180957dacad5SJay Sternberg { 18100f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1811f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1812f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18130f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1814f63572dfSJon Derrick } 181557dacad5SJay Sternberg } 181657dacad5SJay Sternberg 181787ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 181857dacad5SJay Sternberg { 18196c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 18204033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 182187ad72a5SChristoph Hellwig struct nvme_command c; 182287ad72a5SChristoph Hellwig int ret; 182387ad72a5SChristoph Hellwig 182487ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 182587ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 182687ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 182787ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 18286c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 182987ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 183087ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 183187ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 183287ad72a5SChristoph Hellwig 183387ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 183487ad72a5SChristoph Hellwig if (ret) { 183587ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 183687ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 183787ad72a5SChristoph Hellwig ret, bits); 183887ad72a5SChristoph Hellwig } 183987ad72a5SChristoph Hellwig return ret; 184087ad72a5SChristoph Hellwig } 184187ad72a5SChristoph Hellwig 184287ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 184387ad72a5SChristoph Hellwig { 184487ad72a5SChristoph Hellwig int i; 184587ad72a5SChristoph Hellwig 184687ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 184787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 18486c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 184987ad72a5SChristoph Hellwig 1850cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1851cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1852cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 185387ad72a5SChristoph Hellwig } 185487ad72a5SChristoph Hellwig 185587ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 185687ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18574033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18584033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18594033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 186087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18617e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 186287ad72a5SChristoph Hellwig } 186387ad72a5SChristoph Hellwig 186492dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 186592dc6895SChristoph Hellwig u32 chunk_size) 186687ad72a5SChristoph Hellwig { 186787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 186892dc6895SChristoph Hellwig u32 max_entries, len; 18694033f35dSChristoph Hellwig dma_addr_t descs_dma; 18702ee0e4edSDan Carpenter int i = 0; 187187ad72a5SChristoph Hellwig void **bufs; 18726fbcde66SMinwoo Im u64 size, tmp; 187387ad72a5SChristoph Hellwig 187487ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 187587ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 187687ad72a5SChristoph Hellwig max_entries = tmp; 1877044a9df1SChristoph Hellwig 1878044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1879044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1880044a9df1SChristoph Hellwig 1881750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 18824033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 188387ad72a5SChristoph Hellwig if (!descs) 188487ad72a5SChristoph Hellwig goto out; 188587ad72a5SChristoph Hellwig 188687ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 188787ad72a5SChristoph Hellwig if (!bufs) 188887ad72a5SChristoph Hellwig goto out_free_descs; 188987ad72a5SChristoph Hellwig 1890244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 189187ad72a5SChristoph Hellwig dma_addr_t dma_addr; 189287ad72a5SChristoph Hellwig 189350cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 189487ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 189587ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 189687ad72a5SChristoph Hellwig if (!bufs[i]) 189787ad72a5SChristoph Hellwig break; 189887ad72a5SChristoph Hellwig 189987ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 19006c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 190187ad72a5SChristoph Hellwig i++; 190287ad72a5SChristoph Hellwig } 190387ad72a5SChristoph Hellwig 190492dc6895SChristoph Hellwig if (!size) 190587ad72a5SChristoph Hellwig goto out_free_bufs; 190687ad72a5SChristoph Hellwig 190787ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 190887ad72a5SChristoph Hellwig dev->host_mem_size = size; 190987ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19104033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 191187ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 191287ad72a5SChristoph Hellwig return 0; 191387ad72a5SChristoph Hellwig 191487ad72a5SChristoph Hellwig out_free_bufs: 191587ad72a5SChristoph Hellwig while (--i >= 0) { 19166c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 191787ad72a5SChristoph Hellwig 1918cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1919cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1920cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 192187ad72a5SChristoph Hellwig } 192287ad72a5SChristoph Hellwig 192387ad72a5SChristoph Hellwig kfree(bufs); 192487ad72a5SChristoph Hellwig out_free_descs: 19254033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19264033f35dSChristoph Hellwig descs_dma); 192787ad72a5SChristoph Hellwig out: 192887ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 192987ad72a5SChristoph Hellwig return -ENOMEM; 193087ad72a5SChristoph Hellwig } 193187ad72a5SChristoph Hellwig 193292dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 193392dc6895SChristoph Hellwig { 19349dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 19359dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 19369dc54a0dSChaitanya Kulkarni u64 chunk_size; 193792dc6895SChristoph Hellwig 193892dc6895SChristoph Hellwig /* start big and work our way down */ 19399dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 194092dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 194192dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 194292dc6895SChristoph Hellwig return 0; 194392dc6895SChristoph Hellwig nvme_free_host_mem(dev); 194492dc6895SChristoph Hellwig } 194592dc6895SChristoph Hellwig } 194692dc6895SChristoph Hellwig 194792dc6895SChristoph Hellwig return -ENOMEM; 194892dc6895SChristoph Hellwig } 194992dc6895SChristoph Hellwig 19509620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 195187ad72a5SChristoph Hellwig { 195287ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 195387ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 195487ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 195587ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19566fbcde66SMinwoo Im int ret; 195787ad72a5SChristoph Hellwig 195887ad72a5SChristoph Hellwig preferred = min(preferred, max); 195987ad72a5SChristoph Hellwig if (min > max) { 196087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 196187ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 196287ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 196387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19649620cfbaSChristoph Hellwig return 0; 196587ad72a5SChristoph Hellwig } 196687ad72a5SChristoph Hellwig 196787ad72a5SChristoph Hellwig /* 196887ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 196987ad72a5SChristoph Hellwig */ 197087ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 197187ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 197287ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 197387ad72a5SChristoph Hellwig else 197487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 197587ad72a5SChristoph Hellwig } 197687ad72a5SChristoph Hellwig 197787ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 197892dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 197992dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 198092dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 19819620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 198287ad72a5SChristoph Hellwig } 198387ad72a5SChristoph Hellwig 198492dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 198592dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 198692dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 198792dc6895SChristoph Hellwig } 198892dc6895SChristoph Hellwig 19899620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 19909620cfbaSChristoph Hellwig if (ret) 199187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19929620cfbaSChristoph Hellwig return ret; 199357dacad5SJay Sternberg } 199457dacad5SJay Sternberg 1995612b7286SMing Lei /* 1996612b7286SMing Lei * nirqs is the number of interrupts available for write and read 1997612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 1998612b7286SMing Lei */ 1999612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20003b6592f7SJens Axboe { 2001612b7286SMing Lei struct nvme_dev *dev = affd->priv; 20022a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2003c45b1fa2SMing Lei 20043b6592f7SJens Axboe /* 2005ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2006612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2007612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2008612b7286SMing Lei * 2009612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2010612b7286SMing Lei * write and read queues. 2011612b7286SMing Lei * 2012612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2013612b7286SMing Lei * queue. 20143b6592f7SJens Axboe */ 2015612b7286SMing Lei if (!nrirqs) { 2016612b7286SMing Lei nrirqs = 1; 2017612b7286SMing Lei nr_read_queues = 0; 20182a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2019612b7286SMing Lei nr_read_queues = 0; 20202a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2021612b7286SMing Lei nr_read_queues = 1; 20223b6592f7SJens Axboe } else { 20232a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 20243b6592f7SJens Axboe } 2025612b7286SMing Lei 2026612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2027612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2028612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2029612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2030612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20313b6592f7SJens Axboe } 20323b6592f7SJens Axboe 20336451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20343b6592f7SJens Axboe { 20353b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20363b6592f7SJens Axboe struct irq_affinity affd = { 20373b6592f7SJens Axboe .pre_vectors = 1, 2038612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2039612b7286SMing Lei .priv = dev, 20403b6592f7SJens Axboe }; 20416451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20426451fe73SJens Axboe 20436451fe73SJens Axboe /* 20446451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20456451fe73SJens Axboe * queue left over for non-polled IO. 20466451fe73SJens Axboe */ 20472a5bcfddSWeiping Zhang this_p_queues = dev->nr_poll_queues; 20486451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20496451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20506451fe73SJens Axboe irq_queues = 1; 20516451fe73SJens Axboe } else { 2052c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20536451fe73SJens Axboe } 20546451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20553b6592f7SJens Axboe 2056612b7286SMing Lei /* Initialize for the single interrupt case */ 2057612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2058612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20593b6592f7SJens Axboe 206066341331SBenjamin Herrenschmidt /* 206166341331SBenjamin Herrenschmidt * Some Apple controllers require all queues to use the 206266341331SBenjamin Herrenschmidt * first vector. 206366341331SBenjamin Herrenschmidt */ 206466341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 206566341331SBenjamin Herrenschmidt irq_queues = 1; 206666341331SBenjamin Herrenschmidt 2067612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20683b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20693b6592f7SJens Axboe } 20703b6592f7SJens Axboe 20718fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 20728fae268bSKeith Busch { 20738fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 20748fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 20758fae268bSKeith Busch } 20768fae268bSKeith Busch 20772a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 20782a5bcfddSWeiping Zhang { 20792a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 20802a5bcfddSWeiping Zhang } 20812a5bcfddSWeiping Zhang 208257dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 208357dacad5SJay Sternberg { 2084147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 208557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 20862a5bcfddSWeiping Zhang unsigned int nr_io_queues; 208797f6ef64SXu Yu unsigned long size; 20882a5bcfddSWeiping Zhang int result; 208957dacad5SJay Sternberg 20902a5bcfddSWeiping Zhang /* 20912a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 20922a5bcfddSWeiping Zhang * stable values to work with. 20932a5bcfddSWeiping Zhang */ 20942a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 20952a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2096d38e9f04SBenjamin Herrenschmidt 2097d38e9f04SBenjamin Herrenschmidt /* 2098d38e9f04SBenjamin Herrenschmidt * If tags are shared with admin queue (Apple bug), then 2099d38e9f04SBenjamin Herrenschmidt * make sure we only use one IO queue. 2100d38e9f04SBenjamin Herrenschmidt */ 2101d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2102d38e9f04SBenjamin Herrenschmidt nr_io_queues = 1; 21032a5bcfddSWeiping Zhang else 21042a5bcfddSWeiping Zhang nr_io_queues = min(nvme_max_io_queues(dev), 21052a5bcfddSWeiping Zhang dev->nr_allocated_queues - 1); 2106d38e9f04SBenjamin Herrenschmidt 21079a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21089a0be7abSChristoph Hellwig if (result < 0) 210957dacad5SJay Sternberg return result; 21109a0be7abSChristoph Hellwig 2111f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2112a5229050SKeith Busch return 0; 211357dacad5SJay Sternberg 21144e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21154e224106SChristoph Hellwig 21160f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 211757dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 211857dacad5SJay Sternberg sizeof(struct nvme_command)); 211957dacad5SJay Sternberg if (result > 0) 212057dacad5SJay Sternberg dev->q_depth = result; 212157dacad5SJay Sternberg else 21220f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 212357dacad5SJay Sternberg } 212457dacad5SJay Sternberg 212557dacad5SJay Sternberg do { 212697f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 212797f6ef64SXu Yu result = nvme_remap_bar(dev, size); 212897f6ef64SXu Yu if (!result) 212957dacad5SJay Sternberg break; 213057dacad5SJay Sternberg if (!--nr_io_queues) 213157dacad5SJay Sternberg return -ENOMEM; 213257dacad5SJay Sternberg } while (1); 213357dacad5SJay Sternberg adminq->q_db = dev->dbs; 213457dacad5SJay Sternberg 21358fae268bSKeith Busch retry: 213657dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21370ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 213857dacad5SJay Sternberg 213957dacad5SJay Sternberg /* 214057dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 214157dacad5SJay Sternberg * setting up the full range we need. 214257dacad5SJay Sternberg */ 2143dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21443b6592f7SJens Axboe 21453b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 214622b55601SKeith Busch if (result <= 0) 2147dca51e78SChristoph Hellwig return -EIO; 21483b6592f7SJens Axboe 214922b55601SKeith Busch dev->num_vecs = result; 21504b04cc6aSJens Axboe result = max(result - 1, 1); 2151e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 215257dacad5SJay Sternberg 215357dacad5SJay Sternberg /* 215457dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 215557dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 215657dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 215757dacad5SJay Sternberg * number of interrupts. 215857dacad5SJay Sternberg */ 2159dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21607c349ddeSKeith Busch if (result) 2161d4875622SKeith Busch return result; 21624e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21638fae268bSKeith Busch 21648fae268bSKeith Busch result = nvme_create_io_queues(dev); 21658fae268bSKeith Busch if (result || dev->online_queues < 2) 21668fae268bSKeith Busch return result; 21678fae268bSKeith Busch 21688fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21698fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21708fae268bSKeith Busch nvme_disable_io_queues(dev); 21718fae268bSKeith Busch nvme_suspend_io_queues(dev); 21728fae268bSKeith Busch goto retry; 21738fae268bSKeith Busch } 21748fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21758fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21768fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21778fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21788fae268bSKeith Busch return 0; 217957dacad5SJay Sternberg } 218057dacad5SJay Sternberg 21812a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2182db3cbfffSKeith Busch { 2183db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2184db3cbfffSKeith Busch 2185db3cbfffSKeith Busch blk_mq_free_request(req); 2186d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2187db3cbfffSKeith Busch } 2188db3cbfffSKeith Busch 21892a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2190db3cbfffSKeith Busch { 2191db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2192db3cbfffSKeith Busch 2193d1ed6aa1SChristoph Hellwig if (error) 2194d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2195db3cbfffSKeith Busch 2196db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2197db3cbfffSKeith Busch } 2198db3cbfffSKeith Busch 2199db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2200db3cbfffSKeith Busch { 2201db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2202db3cbfffSKeith Busch struct request *req; 2203db3cbfffSKeith Busch struct nvme_command cmd; 2204db3cbfffSKeith Busch 2205db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2206db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2207db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2208db3cbfffSKeith Busch 2209eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2210db3cbfffSKeith Busch if (IS_ERR(req)) 2211db3cbfffSKeith Busch return PTR_ERR(req); 2212db3cbfffSKeith Busch 2213db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2214db3cbfffSKeith Busch req->end_io_data = nvmeq; 2215db3cbfffSKeith Busch 2216d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2217db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2218db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2219db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2220db3cbfffSKeith Busch return 0; 2221db3cbfffSKeith Busch } 2222db3cbfffSKeith Busch 22238fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2224db3cbfffSKeith Busch { 22255271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2226db3cbfffSKeith Busch unsigned long timeout; 2227db3cbfffSKeith Busch 2228db3cbfffSKeith Busch retry: 2229db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22305271edd4SChristoph Hellwig while (nr_queues > 0) { 22315271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2232db3cbfffSKeith Busch break; 22335271edd4SChristoph Hellwig nr_queues--; 22345271edd4SChristoph Hellwig sent++; 22355271edd4SChristoph Hellwig } 2236d1ed6aa1SChristoph Hellwig while (sent) { 2237d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2238d1ed6aa1SChristoph Hellwig 2239d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22405271edd4SChristoph Hellwig timeout); 2241db3cbfffSKeith Busch if (timeout == 0) 22425271edd4SChristoph Hellwig return false; 2243d1ed6aa1SChristoph Hellwig 2244d1ed6aa1SChristoph Hellwig sent--; 22455271edd4SChristoph Hellwig if (nr_queues) 2246db3cbfffSKeith Busch goto retry; 2247db3cbfffSKeith Busch } 22485271edd4SChristoph Hellwig return true; 2249db3cbfffSKeith Busch } 2250db3cbfffSKeith Busch 22515d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 225257dacad5SJay Sternberg { 22532b1b7e78SJianchao Wang int ret; 22542b1b7e78SJianchao Wang 22555bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2256c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 225757dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 22588fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2259ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2260ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 226157dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2262d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 226361f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 226461f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2265d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 226657dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 226757dacad5SJay Sternberg dev->tagset.driver_data = dev; 226857dacad5SJay Sternberg 2269d38e9f04SBenjamin Herrenschmidt /* 2270d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2271d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2272d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2273d38e9f04SBenjamin Herrenschmidt */ 2274d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2275d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2276d38e9f04SBenjamin Herrenschmidt 22772b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22782b1b7e78SJianchao Wang if (ret) { 22792b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22802b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22815d02a5c1SKeith Busch return; 22822b1b7e78SJianchao Wang } 22835bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2284949928c1SKeith Busch } else { 2285949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2286949928c1SKeith Busch 2287949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2288949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 228957dacad5SJay Sternberg } 2290949928c1SKeith Busch 2291e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 229257dacad5SJay Sternberg } 229357dacad5SJay Sternberg 2294b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 229557dacad5SJay Sternberg { 2296b00a726aSKeith Busch int result = -ENOMEM; 229757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 229857dacad5SJay Sternberg 229957dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 230057dacad5SJay Sternberg return result; 230157dacad5SJay Sternberg 230257dacad5SJay Sternberg pci_set_master(pdev); 230357dacad5SJay Sternberg 23044fe06923SChristoph Hellwig if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 230557dacad5SJay Sternberg goto disable; 230657dacad5SJay Sternberg 23077a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 230857dacad5SJay Sternberg result = -ENODEV; 2309b00a726aSKeith Busch goto disable; 231057dacad5SJay Sternberg } 231157dacad5SJay Sternberg 231257dacad5SJay Sternberg /* 2313a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2314a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2315a5229050SKeith Busch * adjust this later. 231657dacad5SJay Sternberg */ 2317dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2318dca51e78SChristoph Hellwig if (result < 0) 2319dca51e78SChristoph Hellwig return result; 232057dacad5SJay Sternberg 232120d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23227a67cbeaSChristoph Hellwig 23237442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2324b27c1e68Sweiping zhang io_queue_depth); 2325aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 232620d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23277a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23281f390c1fSStephan Günther 23291f390c1fSStephan Günther /* 233066341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 233166341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 233266341331SBenjamin Herrenschmidt * so we don't bother updating it here. 233366341331SBenjamin Herrenschmidt */ 233466341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 233566341331SBenjamin Herrenschmidt dev->io_sqes = 7; 233666341331SBenjamin Herrenschmidt else 2337c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 23381f390c1fSStephan Günther 23391f390c1fSStephan Günther /* 23401f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23411f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23421f390c1fSStephan Günther */ 23431f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23441f390c1fSStephan Günther dev->q_depth = 2; 23459bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23469bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23471f390c1fSStephan Günther dev->q_depth); 2348d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2349d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 235020d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2351d554b5e1SMartin K. Petersen dev->q_depth = 64; 2352d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2353d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23541f390c1fSStephan Günther } 23551f390c1fSStephan Günther 2356d38e9f04SBenjamin Herrenschmidt /* 2357d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2358d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2359d38e9f04SBenjamin Herrenschmidt */ 2360d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2361d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2362d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2363d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2364d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2365d38e9f04SBenjamin Herrenschmidt } 2366d38e9f04SBenjamin Herrenschmidt 2367d38e9f04SBenjamin Herrenschmidt 2368f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2369202021c1SStephen Bates 2370a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2371a0a3408eSKeith Busch pci_save_state(pdev); 237257dacad5SJay Sternberg return 0; 237357dacad5SJay Sternberg 237457dacad5SJay Sternberg disable: 237557dacad5SJay Sternberg pci_disable_device(pdev); 237657dacad5SJay Sternberg return result; 237757dacad5SJay Sternberg } 237857dacad5SJay Sternberg 237957dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 238057dacad5SJay Sternberg { 2381b00a726aSKeith Busch if (dev->bar) 2382b00a726aSKeith Busch iounmap(dev->bar); 2383a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2384b00a726aSKeith Busch } 2385b00a726aSKeith Busch 2386b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2387b00a726aSKeith Busch { 238857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 238957dacad5SJay Sternberg 2390dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 239157dacad5SJay Sternberg 2392a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2393a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 239457dacad5SJay Sternberg pci_disable_device(pdev); 239557dacad5SJay Sternberg } 2396a0a3408eSKeith Busch } 239757dacad5SJay Sternberg 2398a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 239957dacad5SJay Sternberg { 2400e43269e6SKeith Busch bool dead = true, freeze = false; 2401302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 240257dacad5SJay Sternberg 240377bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2404302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2405302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2406302ad8ccSKeith Busch 2407ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2408e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2409e43269e6SKeith Busch freeze = true; 2410302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2411e43269e6SKeith Busch } 2412302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2413302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 241457dacad5SJay Sternberg } 2415c21377f8SGabriel Krisman Bertazi 2416302ad8ccSKeith Busch /* 2417302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2418302ad8ccSKeith Busch * doing a safe shutdown. 2419302ad8ccSKeith Busch */ 2420e43269e6SKeith Busch if (!dead && shutdown && freeze) 2421302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 242287ad72a5SChristoph Hellwig 24239a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24249a915a5bSJianchao Wang 242564ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24268fae268bSKeith Busch nvme_disable_io_queues(dev); 2427a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 242857dacad5SJay Sternberg } 24298fae268bSKeith Busch nvme_suspend_io_queues(dev); 24308fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2431b00a726aSKeith Busch nvme_pci_disable(dev); 2432fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 243357dacad5SJay Sternberg 2434e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2435e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2436622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2437622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2438302ad8ccSKeith Busch 2439302ad8ccSKeith Busch /* 2440302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2441302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2442302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2443302ad8ccSKeith Busch */ 2444c8e9e9b7SKeith Busch if (shutdown) { 2445302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2446c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2447c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2448c8e9e9b7SKeith Busch } 244977bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 245057dacad5SJay Sternberg } 245157dacad5SJay Sternberg 2452c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2453c1ac9a4bSKeith Busch { 2454c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2455c1ac9a4bSKeith Busch return -EBUSY; 2456c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2457c1ac9a4bSKeith Busch return 0; 2458c1ac9a4bSKeith Busch } 2459c1ac9a4bSKeith Busch 246057dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 246157dacad5SJay Sternberg { 246257dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2463c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2464c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 246557dacad5SJay Sternberg if (!dev->prp_page_pool) 246657dacad5SJay Sternberg return -ENOMEM; 246757dacad5SJay Sternberg 246857dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 246957dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 247057dacad5SJay Sternberg 256, 256, 0); 247157dacad5SJay Sternberg if (!dev->prp_small_pool) { 247257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 247357dacad5SJay Sternberg return -ENOMEM; 247457dacad5SJay Sternberg } 247557dacad5SJay Sternberg return 0; 247657dacad5SJay Sternberg } 247757dacad5SJay Sternberg 247857dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 247957dacad5SJay Sternberg { 248057dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 248157dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 248257dacad5SJay Sternberg } 248357dacad5SJay Sternberg 2484770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2485770597ecSKeith Busch { 2486770597ecSKeith Busch if (dev->tagset.tags) 2487770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2488770597ecSKeith Busch dev->ctrl.tagset = NULL; 2489770597ecSKeith Busch } 2490770597ecSKeith Busch 24911673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 249257dacad5SJay Sternberg { 24931673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 249457dacad5SJay Sternberg 2495f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2496770597ecSKeith Busch nvme_free_tagset(dev); 24971c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24981c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2499e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2500943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2501253fd4acSIsrael Rukshin put_device(dev->dev); 2502253fd4acSIsrael Rukshin kfree(dev->queues); 250357dacad5SJay Sternberg kfree(dev); 250457dacad5SJay Sternberg } 250557dacad5SJay Sternberg 25067c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2507f58944e2SKeith Busch { 2508c1ac9a4bSKeith Busch /* 2509c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2510c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2511c1ac9a4bSKeith Busch */ 2512c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2513d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 251469d9a99cSKeith Busch nvme_dev_disable(dev, false); 25159f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 251603e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2517f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2518f58944e2SKeith Busch } 2519f58944e2SKeith Busch 2520fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 252157dacad5SJay Sternberg { 2522d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2523d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2524a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2525e71afda4SChaitanya Kulkarni int result; 252657dacad5SJay Sternberg 2527e71afda4SChaitanya Kulkarni if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2528e71afda4SChaitanya Kulkarni result = -ENODEV; 2529fd634f41SChristoph Hellwig goto out; 2530e71afda4SChaitanya Kulkarni } 2531fd634f41SChristoph Hellwig 2532fd634f41SChristoph Hellwig /* 2533fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2534fd634f41SChristoph Hellwig * moving on. 2535fd634f41SChristoph Hellwig */ 2536b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2537a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2538d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2539fd634f41SChristoph Hellwig 25405c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2541b00a726aSKeith Busch result = nvme_pci_enable(dev); 254257dacad5SJay Sternberg if (result) 25434726bcf3SKeith Busch goto out_unlock; 254457dacad5SJay Sternberg 254501ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 254657dacad5SJay Sternberg if (result) 25474726bcf3SKeith Busch goto out_unlock; 254857dacad5SJay Sternberg 254957dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 255057dacad5SJay Sternberg if (result) 25514726bcf3SKeith Busch goto out_unlock; 255257dacad5SJay Sternberg 2553943e942eSJens Axboe /* 2554943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2555943e942eSJens Axboe * over a single page. 2556943e942eSJens Axboe */ 25577637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 25587637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2559943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2560a48bc520SChristoph Hellwig 2561a48bc520SChristoph Hellwig /* 2562a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2563a48bc520SChristoph Hellwig */ 2564a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 2565a48bc520SChristoph Hellwig 25665c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25675c959d73SKeith Busch 25685c959d73SKeith Busch /* 25695c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25705c959d73SKeith Busch * initializing procedure here. 25715c959d73SKeith Busch */ 25725c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25735c959d73SKeith Busch dev_warn(dev->ctrl.device, 25745c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2575cee6c269SMinwoo Im result = -EBUSY; 25765c959d73SKeith Busch goto out; 25775c959d73SKeith Busch } 2578943e942eSJens Axboe 257995093350SMax Gurtovoy /* 258095093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 258195093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 258295093350SMax Gurtovoy */ 258395093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 258495093350SMax Gurtovoy 2585ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2586ce4541f4SChristoph Hellwig if (result) 2587f58944e2SKeith Busch goto out; 2588ce4541f4SChristoph Hellwig 2589e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2590e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25914f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25924f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2593e286bcfcSScott Bauer else if (was_suspend) 25944f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2595e286bcfcSScott Bauer } else { 2596e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2597e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2598e286bcfcSScott Bauer } 2599a98e58e5SScott Bauer 2600f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2601f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2602f9f38e33SHelen Koike if (result) 2603f9f38e33SHelen Koike dev_warn(dev->dev, 2604f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2605f9f38e33SHelen Koike } 2606f9f38e33SHelen Koike 26079620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 26089620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 26099620cfbaSChristoph Hellwig if (result < 0) 26109620cfbaSChristoph Hellwig goto out; 26119620cfbaSChristoph Hellwig } 261287ad72a5SChristoph Hellwig 261357dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 261457dacad5SJay Sternberg if (result) 2615f58944e2SKeith Busch goto out; 261657dacad5SJay Sternberg 261721f033f7SKeith Busch /* 261857dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 261957dacad5SJay Sternberg * any working I/O queue. 262057dacad5SJay Sternberg */ 262157dacad5SJay Sternberg if (dev->online_queues < 2) { 26221b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 26233b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 26245bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2625770597ecSKeith Busch nvme_free_tagset(dev); 262657dacad5SJay Sternberg } else { 262725646264SKeith Busch nvme_start_queues(&dev->ctrl); 2628302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26295d02a5c1SKeith Busch nvme_dev_add(dev); 2630302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 263157dacad5SJay Sternberg } 263257dacad5SJay Sternberg 26332b1b7e78SJianchao Wang /* 26342b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26352b1b7e78SJianchao Wang * recovery. 26362b1b7e78SJianchao Wang */ 26375d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 26382b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26395d02a5c1SKeith Busch "failed to mark controller live state\n"); 2640e71afda4SChaitanya Kulkarni result = -ENODEV; 2641bb8d261eSChristoph Hellwig goto out; 2642bb8d261eSChristoph Hellwig } 264392911a55SChristoph Hellwig 2644d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 264557dacad5SJay Sternberg return; 264657dacad5SJay Sternberg 26474726bcf3SKeith Busch out_unlock: 26484726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 264957dacad5SJay Sternberg out: 26507c1ce408SChaitanya Kulkarni if (result) 26517c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 26527c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 26537c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 265457dacad5SJay Sternberg } 265557dacad5SJay Sternberg 26565c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 265757dacad5SJay Sternberg { 26585c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 265957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 266057dacad5SJay Sternberg 266157dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2662921920abSKeith Busch device_release_driver(&pdev->dev); 26631673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 266457dacad5SJay Sternberg } 266557dacad5SJay Sternberg 26661c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 266757dacad5SJay Sternberg { 26681c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26691c63dc66SChristoph Hellwig return 0; 267057dacad5SJay Sternberg } 26711c63dc66SChristoph Hellwig 26725fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26735fd4ce1bSChristoph Hellwig { 26745fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26755fd4ce1bSChristoph Hellwig return 0; 26765fd4ce1bSChristoph Hellwig } 26775fd4ce1bSChristoph Hellwig 26787fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26797fd8930fSChristoph Hellwig { 26803a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 26817fd8930fSChristoph Hellwig return 0; 26827fd8930fSChristoph Hellwig } 26837fd8930fSChristoph Hellwig 268497c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 268597c12223SKeith Busch { 268697c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 268797c12223SKeith Busch 26882db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 268997c12223SKeith Busch } 269097c12223SKeith Busch 26911c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26921a353d85SMing Lin .name = "pcie", 2693e439bb12SSagi Grimberg .module = THIS_MODULE, 2694e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2695e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26961c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26975fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26987fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26991673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2700f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 270197c12223SKeith Busch .get_address = nvme_pci_get_address, 27021c63dc66SChristoph Hellwig }; 270357dacad5SJay Sternberg 2704b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2705b00a726aSKeith Busch { 2706b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2707b00a726aSKeith Busch 2708a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2709b00a726aSKeith Busch return -ENODEV; 2710b00a726aSKeith Busch 271197f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2712b00a726aSKeith Busch goto release; 2713b00a726aSKeith Busch 2714b00a726aSKeith Busch return 0; 2715b00a726aSKeith Busch release: 2716a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2717b00a726aSKeith Busch return -ENODEV; 2718b00a726aSKeith Busch } 2719b00a726aSKeith Busch 27208427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2721ff5350a8SAndy Lutomirski { 2722ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2723ff5350a8SAndy Lutomirski /* 2724ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2725ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2726ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2727ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2728ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2729ff5350a8SAndy Lutomirski * laptops. 2730ff5350a8SAndy Lutomirski */ 2731ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2732ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2733ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2734ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27358427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27368427bbc2SKai-Heng Feng /* 27378427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2738467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2739467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2740467c77d4SJarosław Janik * ASUS PRIME Z370-A 27418427bbc2SKai-Heng Feng */ 27428427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2743467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2744467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27458427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 27461fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 27471fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 27481fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 27491fae37acSShyjumon N /* 27501fae37acSShyjumon N * Forcing to use host managed nvme power settings for 27511fae37acSShyjumon N * lowest idle power with quick resume latency on 27521fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 27531fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 27541fae37acSShyjumon N */ 27551fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 27561fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 27571fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2758ff5350a8SAndy Lutomirski } 2759ff5350a8SAndy Lutomirski 2760ff5350a8SAndy Lutomirski return 0; 2761ff5350a8SAndy Lutomirski } 2762ff5350a8SAndy Lutomirski 2763df4f9bc4SDavid E. Box #ifdef CONFIG_ACPI 2764df4f9bc4SDavid E. Box static bool nvme_acpi_storage_d3(struct pci_dev *dev) 2765df4f9bc4SDavid E. Box { 2766df4f9bc4SDavid E. Box struct acpi_device *adev; 2767df4f9bc4SDavid E. Box struct pci_dev *root; 2768df4f9bc4SDavid E. Box acpi_handle handle; 2769df4f9bc4SDavid E. Box acpi_status status; 2770df4f9bc4SDavid E. Box u8 val; 2771df4f9bc4SDavid E. Box 2772df4f9bc4SDavid E. Box /* 2773df4f9bc4SDavid E. Box * Look for _DSD property specifying that the storage device on the port 2774df4f9bc4SDavid E. Box * must use D3 to support deep platform power savings during 2775df4f9bc4SDavid E. Box * suspend-to-idle. 2776df4f9bc4SDavid E. Box */ 2777df4f9bc4SDavid E. Box root = pcie_find_root_port(dev); 2778df4f9bc4SDavid E. Box if (!root) 2779df4f9bc4SDavid E. Box return false; 2780df4f9bc4SDavid E. Box 2781df4f9bc4SDavid E. Box adev = ACPI_COMPANION(&root->dev); 2782df4f9bc4SDavid E. Box if (!adev) 2783df4f9bc4SDavid E. Box return false; 2784df4f9bc4SDavid E. Box 2785df4f9bc4SDavid E. Box /* 2786df4f9bc4SDavid E. Box * The property is defined in the PXSX device for South complex ports 2787df4f9bc4SDavid E. Box * and in the PEGP device for North complex ports. 2788df4f9bc4SDavid E. Box */ 2789df4f9bc4SDavid E. Box status = acpi_get_handle(adev->handle, "PXSX", &handle); 2790df4f9bc4SDavid E. Box if (ACPI_FAILURE(status)) { 2791df4f9bc4SDavid E. Box status = acpi_get_handle(adev->handle, "PEGP", &handle); 2792df4f9bc4SDavid E. Box if (ACPI_FAILURE(status)) 2793df4f9bc4SDavid E. Box return false; 2794df4f9bc4SDavid E. Box } 2795df4f9bc4SDavid E. Box 2796df4f9bc4SDavid E. Box if (acpi_bus_get_device(handle, &adev)) 2797df4f9bc4SDavid E. Box return false; 2798df4f9bc4SDavid E. Box 2799df4f9bc4SDavid E. Box if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable", 2800df4f9bc4SDavid E. Box &val)) 2801df4f9bc4SDavid E. Box return false; 2802df4f9bc4SDavid E. Box return val == 1; 2803df4f9bc4SDavid E. Box } 2804df4f9bc4SDavid E. Box #else 2805df4f9bc4SDavid E. Box static inline bool nvme_acpi_storage_d3(struct pci_dev *dev) 2806df4f9bc4SDavid E. Box { 2807df4f9bc4SDavid E. Box return false; 2808df4f9bc4SDavid E. Box } 2809df4f9bc4SDavid E. Box #endif /* CONFIG_ACPI */ 2810df4f9bc4SDavid E. Box 281118119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 281218119775SKeith Busch { 281318119775SKeith Busch struct nvme_dev *dev = data; 281480f513b5SKeith Busch 2815bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 281618119775SKeith Busch flush_work(&dev->ctrl.scan_work); 281780f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 281818119775SKeith Busch } 281918119775SKeith Busch 282057dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 282157dacad5SJay Sternberg { 282257dacad5SJay Sternberg int node, result = -ENOMEM; 282357dacad5SJay Sternberg struct nvme_dev *dev; 2824ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2825943e942eSJens Axboe size_t alloc_size; 282657dacad5SJay Sternberg 282757dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 282857dacad5SJay Sternberg if (node == NUMA_NO_NODE) 28292fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 283057dacad5SJay Sternberg 283157dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 283257dacad5SJay Sternberg if (!dev) 283357dacad5SJay Sternberg return -ENOMEM; 2834147b27e4SSagi Grimberg 28352a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 28362a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 28372a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 28382a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 28392a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 284057dacad5SJay Sternberg if (!dev->queues) 284157dacad5SJay Sternberg goto free; 284257dacad5SJay Sternberg 284357dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 284457dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 284557dacad5SJay Sternberg 2846b00a726aSKeith Busch result = nvme_dev_map(dev); 2847b00a726aSKeith Busch if (result) 2848b00c9b7aSChristophe JAILLET goto put_pci; 2849b00a726aSKeith Busch 2850d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 28515c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 285277bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2853f3ca80fcSChristoph Hellwig 2854f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2855f3ca80fcSChristoph Hellwig if (result) 2856b00c9b7aSChristophe JAILLET goto unmap; 2857f3ca80fcSChristoph Hellwig 28588427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2859ff5350a8SAndy Lutomirski 2860df4f9bc4SDavid E. Box if (!noacpi && nvme_acpi_storage_d3(pdev)) { 2861df4f9bc4SDavid E. Box /* 2862df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 2863df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 2864df4f9bc4SDavid E. Box */ 2865df4f9bc4SDavid E. Box dev_info(&pdev->dev, 2866df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 2867df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 2868df4f9bc4SDavid E. Box } 2869df4f9bc4SDavid E. Box 2870943e942eSJens Axboe /* 2871943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2872943e942eSJens Axboe * command we support. 2873943e942eSJens Axboe */ 2874b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 2875943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2876943e942eSJens Axboe 2877943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2878943e942eSJens Axboe mempool_kfree, 2879943e942eSJens Axboe (void *) alloc_size, 2880943e942eSJens Axboe GFP_KERNEL, node); 2881943e942eSJens Axboe if (!dev->iod_mempool) { 2882943e942eSJens Axboe result = -ENOMEM; 2883943e942eSJens Axboe goto release_pools; 2884943e942eSJens Axboe } 2885943e942eSJens Axboe 2886b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2887b6e44b4cSKeith Busch quirks); 2888b6e44b4cSKeith Busch if (result) 2889b6e44b4cSKeith Busch goto release_mempool; 2890b6e44b4cSKeith Busch 28911b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 28921b3c47c1SSagi Grimberg 2893bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 289418119775SKeith Busch async_schedule(nvme_async_probe, dev); 28954caff8fcSSagi Grimberg 289657dacad5SJay Sternberg return 0; 289757dacad5SJay Sternberg 2898b6e44b4cSKeith Busch release_mempool: 2899b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 290057dacad5SJay Sternberg release_pools: 290157dacad5SJay Sternberg nvme_release_prp_pools(dev); 2902b00c9b7aSChristophe JAILLET unmap: 2903b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 290457dacad5SJay Sternberg put_pci: 290557dacad5SJay Sternberg put_device(dev->dev); 290657dacad5SJay Sternberg free: 290757dacad5SJay Sternberg kfree(dev->queues); 290857dacad5SJay Sternberg kfree(dev); 290957dacad5SJay Sternberg return result; 291057dacad5SJay Sternberg } 291157dacad5SJay Sternberg 2912775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 291357dacad5SJay Sternberg { 291457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2915c1ac9a4bSKeith Busch 2916c1ac9a4bSKeith Busch /* 2917c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 2918c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 2919c1ac9a4bSKeith Busch * with ->remove(). 2920c1ac9a4bSKeith Busch */ 2921c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 2922c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 2923775755edSChristoph Hellwig } 292457dacad5SJay Sternberg 2925775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2926775755edSChristoph Hellwig { 2927f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2928c1ac9a4bSKeith Busch 2929c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 2930c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 293157dacad5SJay Sternberg } 293257dacad5SJay Sternberg 293357dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 293457dacad5SJay Sternberg { 293557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 29364e523547SBaolin Wang 2937c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 293857dacad5SJay Sternberg } 293957dacad5SJay Sternberg 2940f58944e2SKeith Busch /* 2941f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2942f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2943f58944e2SKeith Busch * order to proceed. 2944f58944e2SKeith Busch */ 294557dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 294657dacad5SJay Sternberg { 294757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 294857dacad5SJay Sternberg 2949bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 295057dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 29510ff9d4e1SKeith Busch 29526db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 29530ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 29541d39e692SKeith Busch nvme_dev_disable(dev, true); 2955cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 29566db28edaSKeith Busch } 29570ff9d4e1SKeith Busch 2958d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2959d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2960d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2961a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 29629fe5c59fSKeith Busch nvme_release_cmb(dev); 296387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 296457dacad5SJay Sternberg nvme_dev_remove_admin(dev); 296557dacad5SJay Sternberg nvme_free_queues(dev, 0); 296657dacad5SJay Sternberg nvme_release_prp_pools(dev); 2967b00a726aSKeith Busch nvme_dev_unmap(dev); 2968726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 296957dacad5SJay Sternberg } 297057dacad5SJay Sternberg 297157dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 2972d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2973d916b1beSKeith Busch { 2974d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2975d916b1beSKeith Busch } 2976d916b1beSKeith Busch 2977d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2978d916b1beSKeith Busch { 2979d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2980d916b1beSKeith Busch } 2981d916b1beSKeith Busch 2982d916b1beSKeith Busch static int nvme_resume(struct device *dev) 2983d916b1beSKeith Busch { 2984d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2985d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2986d916b1beSKeith Busch 29874eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 2988d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2989c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 2990d916b1beSKeith Busch return 0; 2991d916b1beSKeith Busch } 2992d916b1beSKeith Busch 299357dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 299457dacad5SJay Sternberg { 299557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 299657dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 2997d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2998d916b1beSKeith Busch int ret = -EBUSY; 2999d916b1beSKeith Busch 30004eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 30014eaefe8cSRafael J. Wysocki 3002d916b1beSKeith Busch /* 3003d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3004d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3005d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3006d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3007d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3008d916b1beSKeith Busch * device fully. 30094eaefe8cSRafael J. Wysocki * 30104eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 30114eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 30124eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 30134eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3014b97120b1SChristoph Hellwig * 3015b97120b1SChristoph Hellwig * If a host memory buffer is enabled, shut down the device as the NVMe 3016b97120b1SChristoph Hellwig * specification allows the device to access the host memory buffer in 3017b97120b1SChristoph Hellwig * host DRAM from all power states, but hosts will fail access to DRAM 3018b97120b1SChristoph Hellwig * during S3. 3019d916b1beSKeith Busch */ 30204eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3021cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3022b97120b1SChristoph Hellwig ndev->nr_host_mem_descs || 3023c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3024c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3025d916b1beSKeith Busch 3026d916b1beSKeith Busch nvme_start_freeze(ctrl); 3027d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3028d916b1beSKeith Busch nvme_sync_queues(ctrl); 3029d916b1beSKeith Busch 30305d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3031d916b1beSKeith Busch goto unfreeze; 3032d916b1beSKeith Busch 3033d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3034d916b1beSKeith Busch if (ret < 0) 3035d916b1beSKeith Busch goto unfreeze; 3036d916b1beSKeith Busch 30377cbb5c6fSMario Limonciello /* 30387cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 30397cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 30407cbb5c6fSMario Limonciello * want pci interfering. 30417cbb5c6fSMario Limonciello */ 30427cbb5c6fSMario Limonciello pci_save_state(pdev); 30437cbb5c6fSMario Limonciello 3044d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3045d916b1beSKeith Busch if (ret < 0) 3046d916b1beSKeith Busch goto unfreeze; 3047d916b1beSKeith Busch 3048d916b1beSKeith Busch if (ret) { 30497cbb5c6fSMario Limonciello /* discard the saved state */ 30507cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 30517cbb5c6fSMario Limonciello 3052d916b1beSKeith Busch /* 3053d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 305405d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3055d916b1beSKeith Busch */ 3056c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3057d916b1beSKeith Busch ctrl->npss = 0; 3058d916b1beSKeith Busch } 3059d916b1beSKeith Busch unfreeze: 3060d916b1beSKeith Busch nvme_unfreeze(ctrl); 3061d916b1beSKeith Busch return ret; 3062d916b1beSKeith Busch } 3063d916b1beSKeith Busch 3064d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3065d916b1beSKeith Busch { 3066d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 30674e523547SBaolin Wang 3068c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 306957dacad5SJay Sternberg } 307057dacad5SJay Sternberg 3071d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 307257dacad5SJay Sternberg { 307357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 307457dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 307557dacad5SJay Sternberg 3076c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 307757dacad5SJay Sternberg } 307857dacad5SJay Sternberg 307921774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3080d916b1beSKeith Busch .suspend = nvme_suspend, 3081d916b1beSKeith Busch .resume = nvme_resume, 3082d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3083d916b1beSKeith Busch .thaw = nvme_simple_resume, 3084d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3085d916b1beSKeith Busch .restore = nvme_simple_resume, 3086d916b1beSKeith Busch }; 3087d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 308857dacad5SJay Sternberg 3089a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3090a0a3408eSKeith Busch pci_channel_state_t state) 3091a0a3408eSKeith Busch { 3092a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3093a0a3408eSKeith Busch 3094a0a3408eSKeith Busch /* 3095a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3096a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3097a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3098a0a3408eSKeith Busch */ 3099a0a3408eSKeith Busch switch (state) { 3100a0a3408eSKeith Busch case pci_channel_io_normal: 3101a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3102a0a3408eSKeith Busch case pci_channel_io_frozen: 3103d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3104d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3105a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3106a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3107a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3108d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3109d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3110a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3111a0a3408eSKeith Busch } 3112a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3113a0a3408eSKeith Busch } 3114a0a3408eSKeith Busch 3115a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3116a0a3408eSKeith Busch { 3117a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3118a0a3408eSKeith Busch 31191b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3120a0a3408eSKeith Busch pci_restore_state(pdev); 3121d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3122a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3123a0a3408eSKeith Busch } 3124a0a3408eSKeith Busch 3125a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3126a0a3408eSKeith Busch { 312772cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 312872cd4cc2SKeith Busch 312972cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3130a0a3408eSKeith Busch } 3131a0a3408eSKeith Busch 313257dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 313357dacad5SJay Sternberg .error_detected = nvme_error_detected, 313457dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 313557dacad5SJay Sternberg .resume = nvme_error_resume, 3136775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3137775755edSChristoph Hellwig .reset_done = nvme_reset_done, 313857dacad5SJay Sternberg }; 313957dacad5SJay Sternberg 314057dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3141972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 314208095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3143e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3144972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 314599466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3146e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3147972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 314899466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3149e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3150972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3151f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3152f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 315350af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 31549abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 31556c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3156ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3157ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 31586299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 31596299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3160540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 31617b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 31627b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 31635bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 31645bedd3afSChristoph Hellwig .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 31650302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 31660302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 316754adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 316854adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 31698c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 31708c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3171015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3172015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3173d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3174d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3175d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3176d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3177608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3178608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3179608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3180608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3181ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3182ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 318308b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 318408b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3185f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3186f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3187f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 31885611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 31895611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 319098f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 319198f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3192124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 319366341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 319466341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3195d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3196d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_SHARED_TAGS }, 31970b85f59dSAndy Shevchenko 31980b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 319957dacad5SJay Sternberg { 0, } 320057dacad5SJay Sternberg }; 320157dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 320257dacad5SJay Sternberg 320357dacad5SJay Sternberg static struct pci_driver nvme_driver = { 320457dacad5SJay Sternberg .name = "nvme", 320557dacad5SJay Sternberg .id_table = nvme_id_table, 320657dacad5SJay Sternberg .probe = nvme_probe, 320757dacad5SJay Sternberg .remove = nvme_remove, 320857dacad5SJay Sternberg .shutdown = nvme_shutdown, 3209d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 321057dacad5SJay Sternberg .driver = { 321157dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 321257dacad5SJay Sternberg }, 3213d916b1beSKeith Busch #endif 321474d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 321557dacad5SJay Sternberg .err_handler = &nvme_err_handler, 321657dacad5SJay Sternberg }; 321757dacad5SJay Sternberg 321857dacad5SJay Sternberg static int __init nvme_init(void) 321957dacad5SJay Sternberg { 322081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 322181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 322281101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3223612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 322417c33167SKeith Busch 32259a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 322657dacad5SJay Sternberg } 322757dacad5SJay Sternberg 322857dacad5SJay Sternberg static void __exit nvme_exit(void) 322957dacad5SJay Sternberg { 323057dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 323103e0f3a6SMing Lei flush_workqueue(nvme_wq); 323257dacad5SJay Sternberg } 323357dacad5SJay Sternberg 323457dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 323557dacad5SJay Sternberg MODULE_LICENSE("GPL"); 323657dacad5SJay Sternberg MODULE_VERSION("1.0"); 323757dacad5SJay Sternberg module_init(nvme_init); 323857dacad5SJay Sternberg module_exit(nvme_exit); 3239