1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/blkdev.h> 8 #include <linux/blk-mq.h> 9 #include <linux/blk-integrity.h> 10 #include <linux/compat.h> 11 #include <linux/delay.h> 12 #include <linux/errno.h> 13 #include <linux/hdreg.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/backing-dev.h> 17 #include <linux/slab.h> 18 #include <linux/types.h> 19 #include <linux/pr.h> 20 #include <linux/ptrace.h> 21 #include <linux/nvme_ioctl.h> 22 #include <linux/pm_qos.h> 23 #include <asm/unaligned.h> 24 25 #include "nvme.h" 26 #include "fabrics.h" 27 #include <linux/nvme-auth.h> 28 29 #define CREATE_TRACE_POINTS 30 #include "trace.h" 31 32 #define NVME_MINORS (1U << MINORBITS) 33 34 struct nvme_ns_info { 35 struct nvme_ns_ids ids; 36 u32 nsid; 37 __le32 anagrpid; 38 bool is_shared; 39 bool is_readonly; 40 bool is_ready; 41 bool is_removed; 42 }; 43 44 unsigned int admin_timeout = 60; 45 module_param(admin_timeout, uint, 0644); 46 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); 47 EXPORT_SYMBOL_GPL(admin_timeout); 48 49 unsigned int nvme_io_timeout = 30; 50 module_param_named(io_timeout, nvme_io_timeout, uint, 0644); 51 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); 52 EXPORT_SYMBOL_GPL(nvme_io_timeout); 53 54 static unsigned char shutdown_timeout = 5; 55 module_param(shutdown_timeout, byte, 0644); 56 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); 57 58 static u8 nvme_max_retries = 5; 59 module_param_named(max_retries, nvme_max_retries, byte, 0644); 60 MODULE_PARM_DESC(max_retries, "max number of retries a command may have"); 61 62 static unsigned long default_ps_max_latency_us = 100000; 63 module_param(default_ps_max_latency_us, ulong, 0644); 64 MODULE_PARM_DESC(default_ps_max_latency_us, 65 "max power saving latency for new devices; use PM QOS to change per device"); 66 67 static bool force_apst; 68 module_param(force_apst, bool, 0644); 69 MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off"); 70 71 static unsigned long apst_primary_timeout_ms = 100; 72 module_param(apst_primary_timeout_ms, ulong, 0644); 73 MODULE_PARM_DESC(apst_primary_timeout_ms, 74 "primary APST timeout in ms"); 75 76 static unsigned long apst_secondary_timeout_ms = 2000; 77 module_param(apst_secondary_timeout_ms, ulong, 0644); 78 MODULE_PARM_DESC(apst_secondary_timeout_ms, 79 "secondary APST timeout in ms"); 80 81 static unsigned long apst_primary_latency_tol_us = 15000; 82 module_param(apst_primary_latency_tol_us, ulong, 0644); 83 MODULE_PARM_DESC(apst_primary_latency_tol_us, 84 "primary APST latency tolerance in us"); 85 86 static unsigned long apst_secondary_latency_tol_us = 100000; 87 module_param(apst_secondary_latency_tol_us, ulong, 0644); 88 MODULE_PARM_DESC(apst_secondary_latency_tol_us, 89 "secondary APST latency tolerance in us"); 90 91 /* 92 * nvme_wq - hosts nvme related works that are not reset or delete 93 * nvme_reset_wq - hosts nvme reset works 94 * nvme_delete_wq - hosts nvme delete works 95 * 96 * nvme_wq will host works such as scan, aen handling, fw activation, 97 * keep-alive, periodic reconnects etc. nvme_reset_wq 98 * runs reset works which also flush works hosted on nvme_wq for 99 * serialization purposes. nvme_delete_wq host controller deletion 100 * works which flush reset works for serialization. 101 */ 102 struct workqueue_struct *nvme_wq; 103 EXPORT_SYMBOL_GPL(nvme_wq); 104 105 struct workqueue_struct *nvme_reset_wq; 106 EXPORT_SYMBOL_GPL(nvme_reset_wq); 107 108 struct workqueue_struct *nvme_delete_wq; 109 EXPORT_SYMBOL_GPL(nvme_delete_wq); 110 111 static LIST_HEAD(nvme_subsystems); 112 static DEFINE_MUTEX(nvme_subsystems_lock); 113 114 static DEFINE_IDA(nvme_instance_ida); 115 static dev_t nvme_ctrl_base_chr_devt; 116 static struct class *nvme_class; 117 static struct class *nvme_subsys_class; 118 119 static DEFINE_IDA(nvme_ns_chr_minor_ida); 120 static dev_t nvme_ns_chr_devt; 121 static struct class *nvme_ns_chr_class; 122 123 static void nvme_put_subsystem(struct nvme_subsystem *subsys); 124 static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl, 125 unsigned nsid); 126 static void nvme_update_keep_alive(struct nvme_ctrl *ctrl, 127 struct nvme_command *cmd); 128 129 void nvme_queue_scan(struct nvme_ctrl *ctrl) 130 { 131 /* 132 * Only new queue scan work when admin and IO queues are both alive 133 */ 134 if (ctrl->state == NVME_CTRL_LIVE && ctrl->tagset) 135 queue_work(nvme_wq, &ctrl->scan_work); 136 } 137 138 /* 139 * Use this function to proceed with scheduling reset_work for a controller 140 * that had previously been set to the resetting state. This is intended for 141 * code paths that can't be interrupted by other reset attempts. A hot removal 142 * may prevent this from succeeding. 143 */ 144 int nvme_try_sched_reset(struct nvme_ctrl *ctrl) 145 { 146 if (ctrl->state != NVME_CTRL_RESETTING) 147 return -EBUSY; 148 if (!queue_work(nvme_reset_wq, &ctrl->reset_work)) 149 return -EBUSY; 150 return 0; 151 } 152 EXPORT_SYMBOL_GPL(nvme_try_sched_reset); 153 154 static void nvme_failfast_work(struct work_struct *work) 155 { 156 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work), 157 struct nvme_ctrl, failfast_work); 158 159 if (ctrl->state != NVME_CTRL_CONNECTING) 160 return; 161 162 set_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags); 163 dev_info(ctrl->device, "failfast expired\n"); 164 nvme_kick_requeue_lists(ctrl); 165 } 166 167 static inline void nvme_start_failfast_work(struct nvme_ctrl *ctrl) 168 { 169 if (!ctrl->opts || ctrl->opts->fast_io_fail_tmo == -1) 170 return; 171 172 schedule_delayed_work(&ctrl->failfast_work, 173 ctrl->opts->fast_io_fail_tmo * HZ); 174 } 175 176 static inline void nvme_stop_failfast_work(struct nvme_ctrl *ctrl) 177 { 178 if (!ctrl->opts) 179 return; 180 181 cancel_delayed_work_sync(&ctrl->failfast_work); 182 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags); 183 } 184 185 186 int nvme_reset_ctrl(struct nvme_ctrl *ctrl) 187 { 188 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) 189 return -EBUSY; 190 if (!queue_work(nvme_reset_wq, &ctrl->reset_work)) 191 return -EBUSY; 192 return 0; 193 } 194 EXPORT_SYMBOL_GPL(nvme_reset_ctrl); 195 196 int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl) 197 { 198 int ret; 199 200 ret = nvme_reset_ctrl(ctrl); 201 if (!ret) { 202 flush_work(&ctrl->reset_work); 203 if (ctrl->state != NVME_CTRL_LIVE) 204 ret = -ENETRESET; 205 } 206 207 return ret; 208 } 209 210 static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl) 211 { 212 dev_info(ctrl->device, 213 "Removing ctrl: NQN \"%s\"\n", nvmf_ctrl_subsysnqn(ctrl)); 214 215 flush_work(&ctrl->reset_work); 216 nvme_stop_ctrl(ctrl); 217 nvme_remove_namespaces(ctrl); 218 ctrl->ops->delete_ctrl(ctrl); 219 nvme_uninit_ctrl(ctrl); 220 } 221 222 static void nvme_delete_ctrl_work(struct work_struct *work) 223 { 224 struct nvme_ctrl *ctrl = 225 container_of(work, struct nvme_ctrl, delete_work); 226 227 nvme_do_delete_ctrl(ctrl); 228 } 229 230 int nvme_delete_ctrl(struct nvme_ctrl *ctrl) 231 { 232 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING)) 233 return -EBUSY; 234 if (!queue_work(nvme_delete_wq, &ctrl->delete_work)) 235 return -EBUSY; 236 return 0; 237 } 238 EXPORT_SYMBOL_GPL(nvme_delete_ctrl); 239 240 void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl) 241 { 242 /* 243 * Keep a reference until nvme_do_delete_ctrl() complete, 244 * since ->delete_ctrl can free the controller. 245 */ 246 nvme_get_ctrl(ctrl); 247 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING)) 248 nvme_do_delete_ctrl(ctrl); 249 nvme_put_ctrl(ctrl); 250 } 251 252 static blk_status_t nvme_error_status(u16 status) 253 { 254 switch (status & 0x7ff) { 255 case NVME_SC_SUCCESS: 256 return BLK_STS_OK; 257 case NVME_SC_CAP_EXCEEDED: 258 return BLK_STS_NOSPC; 259 case NVME_SC_LBA_RANGE: 260 case NVME_SC_CMD_INTERRUPTED: 261 case NVME_SC_NS_NOT_READY: 262 return BLK_STS_TARGET; 263 case NVME_SC_BAD_ATTRIBUTES: 264 case NVME_SC_ONCS_NOT_SUPPORTED: 265 case NVME_SC_INVALID_OPCODE: 266 case NVME_SC_INVALID_FIELD: 267 case NVME_SC_INVALID_NS: 268 return BLK_STS_NOTSUPP; 269 case NVME_SC_WRITE_FAULT: 270 case NVME_SC_READ_ERROR: 271 case NVME_SC_UNWRITTEN_BLOCK: 272 case NVME_SC_ACCESS_DENIED: 273 case NVME_SC_READ_ONLY: 274 case NVME_SC_COMPARE_FAILED: 275 return BLK_STS_MEDIUM; 276 case NVME_SC_GUARD_CHECK: 277 case NVME_SC_APPTAG_CHECK: 278 case NVME_SC_REFTAG_CHECK: 279 case NVME_SC_INVALID_PI: 280 return BLK_STS_PROTECTION; 281 case NVME_SC_RESERVATION_CONFLICT: 282 return BLK_STS_NEXUS; 283 case NVME_SC_HOST_PATH_ERROR: 284 return BLK_STS_TRANSPORT; 285 case NVME_SC_ZONE_TOO_MANY_ACTIVE: 286 return BLK_STS_ZONE_ACTIVE_RESOURCE; 287 case NVME_SC_ZONE_TOO_MANY_OPEN: 288 return BLK_STS_ZONE_OPEN_RESOURCE; 289 default: 290 return BLK_STS_IOERR; 291 } 292 } 293 294 static void nvme_retry_req(struct request *req) 295 { 296 unsigned long delay = 0; 297 u16 crd; 298 299 /* The mask and shift result must be <= 3 */ 300 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11; 301 if (crd) 302 delay = nvme_req(req)->ctrl->crdt[crd - 1] * 100; 303 304 nvme_req(req)->retries++; 305 blk_mq_requeue_request(req, false); 306 blk_mq_delay_kick_requeue_list(req->q, delay); 307 } 308 309 static void nvme_log_error(struct request *req) 310 { 311 struct nvme_ns *ns = req->q->queuedata; 312 struct nvme_request *nr = nvme_req(req); 313 314 if (ns) { 315 pr_err_ratelimited("%s: %s(0x%x) @ LBA %llu, %llu blocks, %s (sct 0x%x / sc 0x%x) %s%s\n", 316 ns->disk ? ns->disk->disk_name : "?", 317 nvme_get_opcode_str(nr->cmd->common.opcode), 318 nr->cmd->common.opcode, 319 (unsigned long long)nvme_sect_to_lba(ns, blk_rq_pos(req)), 320 (unsigned long long)blk_rq_bytes(req) >> ns->lba_shift, 321 nvme_get_error_status_str(nr->status), 322 nr->status >> 8 & 7, /* Status Code Type */ 323 nr->status & 0xff, /* Status Code */ 324 nr->status & NVME_SC_MORE ? "MORE " : "", 325 nr->status & NVME_SC_DNR ? "DNR " : ""); 326 return; 327 } 328 329 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s\n", 330 dev_name(nr->ctrl->device), 331 nvme_get_admin_opcode_str(nr->cmd->common.opcode), 332 nr->cmd->common.opcode, 333 nvme_get_error_status_str(nr->status), 334 nr->status >> 8 & 7, /* Status Code Type */ 335 nr->status & 0xff, /* Status Code */ 336 nr->status & NVME_SC_MORE ? "MORE " : "", 337 nr->status & NVME_SC_DNR ? "DNR " : ""); 338 } 339 340 enum nvme_disposition { 341 COMPLETE, 342 RETRY, 343 FAILOVER, 344 AUTHENTICATE, 345 }; 346 347 static inline enum nvme_disposition nvme_decide_disposition(struct request *req) 348 { 349 if (likely(nvme_req(req)->status == 0)) 350 return COMPLETE; 351 352 if ((nvme_req(req)->status & 0x7ff) == NVME_SC_AUTH_REQUIRED) 353 return AUTHENTICATE; 354 355 if (blk_noretry_request(req) || 356 (nvme_req(req)->status & NVME_SC_DNR) || 357 nvme_req(req)->retries >= nvme_max_retries) 358 return COMPLETE; 359 360 if (req->cmd_flags & REQ_NVME_MPATH) { 361 if (nvme_is_path_error(nvme_req(req)->status) || 362 blk_queue_dying(req->q)) 363 return FAILOVER; 364 } else { 365 if (blk_queue_dying(req->q)) 366 return COMPLETE; 367 } 368 369 return RETRY; 370 } 371 372 static inline void nvme_end_req_zoned(struct request *req) 373 { 374 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) && 375 req_op(req) == REQ_OP_ZONE_APPEND) 376 req->__sector = nvme_lba_to_sect(req->q->queuedata, 377 le64_to_cpu(nvme_req(req)->result.u64)); 378 } 379 380 static inline void nvme_end_req(struct request *req) 381 { 382 blk_status_t status = nvme_error_status(nvme_req(req)->status); 383 384 if (unlikely(nvme_req(req)->status && !(req->rq_flags & RQF_QUIET))) 385 nvme_log_error(req); 386 nvme_end_req_zoned(req); 387 nvme_trace_bio_complete(req); 388 if (req->cmd_flags & REQ_NVME_MPATH) 389 nvme_mpath_end_request(req); 390 blk_mq_end_request(req, status); 391 } 392 393 void nvme_complete_rq(struct request *req) 394 { 395 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl; 396 397 trace_nvme_complete_rq(req); 398 nvme_cleanup_cmd(req); 399 400 /* 401 * Completions of long-running commands should not be able to 402 * defer sending of periodic keep alives, since the controller 403 * may have completed processing such commands a long time ago 404 * (arbitrarily close to command submission time). 405 * req->deadline - req->timeout is the command submission time 406 * in jiffies. 407 */ 408 if (ctrl->kas && 409 req->deadline - req->timeout >= ctrl->ka_last_check_time) 410 ctrl->comp_seen = true; 411 412 switch (nvme_decide_disposition(req)) { 413 case COMPLETE: 414 nvme_end_req(req); 415 return; 416 case RETRY: 417 nvme_retry_req(req); 418 return; 419 case FAILOVER: 420 nvme_failover_req(req); 421 return; 422 case AUTHENTICATE: 423 #ifdef CONFIG_NVME_AUTH 424 queue_work(nvme_wq, &ctrl->dhchap_auth_work); 425 nvme_retry_req(req); 426 #else 427 nvme_end_req(req); 428 #endif 429 return; 430 } 431 } 432 EXPORT_SYMBOL_GPL(nvme_complete_rq); 433 434 void nvme_complete_batch_req(struct request *req) 435 { 436 trace_nvme_complete_rq(req); 437 nvme_cleanup_cmd(req); 438 nvme_end_req_zoned(req); 439 } 440 EXPORT_SYMBOL_GPL(nvme_complete_batch_req); 441 442 /* 443 * Called to unwind from ->queue_rq on a failed command submission so that the 444 * multipathing code gets called to potentially failover to another path. 445 * The caller needs to unwind all transport specific resource allocations and 446 * must return propagate the return value. 447 */ 448 blk_status_t nvme_host_path_error(struct request *req) 449 { 450 nvme_req(req)->status = NVME_SC_HOST_PATH_ERROR; 451 blk_mq_set_request_complete(req); 452 nvme_complete_rq(req); 453 return BLK_STS_OK; 454 } 455 EXPORT_SYMBOL_GPL(nvme_host_path_error); 456 457 bool nvme_cancel_request(struct request *req, void *data) 458 { 459 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device, 460 "Cancelling I/O %d", req->tag); 461 462 /* don't abort one completed or idle request */ 463 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) 464 return true; 465 466 nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD; 467 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 468 blk_mq_complete_request(req); 469 return true; 470 } 471 EXPORT_SYMBOL_GPL(nvme_cancel_request); 472 473 void nvme_cancel_tagset(struct nvme_ctrl *ctrl) 474 { 475 if (ctrl->tagset) { 476 blk_mq_tagset_busy_iter(ctrl->tagset, 477 nvme_cancel_request, ctrl); 478 blk_mq_tagset_wait_completed_request(ctrl->tagset); 479 } 480 } 481 EXPORT_SYMBOL_GPL(nvme_cancel_tagset); 482 483 void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl) 484 { 485 if (ctrl->admin_tagset) { 486 blk_mq_tagset_busy_iter(ctrl->admin_tagset, 487 nvme_cancel_request, ctrl); 488 blk_mq_tagset_wait_completed_request(ctrl->admin_tagset); 489 } 490 } 491 EXPORT_SYMBOL_GPL(nvme_cancel_admin_tagset); 492 493 bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 494 enum nvme_ctrl_state new_state) 495 { 496 enum nvme_ctrl_state old_state; 497 unsigned long flags; 498 bool changed = false; 499 500 spin_lock_irqsave(&ctrl->lock, flags); 501 502 old_state = ctrl->state; 503 switch (new_state) { 504 case NVME_CTRL_LIVE: 505 switch (old_state) { 506 case NVME_CTRL_NEW: 507 case NVME_CTRL_RESETTING: 508 case NVME_CTRL_CONNECTING: 509 changed = true; 510 fallthrough; 511 default: 512 break; 513 } 514 break; 515 case NVME_CTRL_RESETTING: 516 switch (old_state) { 517 case NVME_CTRL_NEW: 518 case NVME_CTRL_LIVE: 519 changed = true; 520 fallthrough; 521 default: 522 break; 523 } 524 break; 525 case NVME_CTRL_CONNECTING: 526 switch (old_state) { 527 case NVME_CTRL_NEW: 528 case NVME_CTRL_RESETTING: 529 changed = true; 530 fallthrough; 531 default: 532 break; 533 } 534 break; 535 case NVME_CTRL_DELETING: 536 switch (old_state) { 537 case NVME_CTRL_LIVE: 538 case NVME_CTRL_RESETTING: 539 case NVME_CTRL_CONNECTING: 540 changed = true; 541 fallthrough; 542 default: 543 break; 544 } 545 break; 546 case NVME_CTRL_DELETING_NOIO: 547 switch (old_state) { 548 case NVME_CTRL_DELETING: 549 case NVME_CTRL_DEAD: 550 changed = true; 551 fallthrough; 552 default: 553 break; 554 } 555 break; 556 case NVME_CTRL_DEAD: 557 switch (old_state) { 558 case NVME_CTRL_DELETING: 559 changed = true; 560 fallthrough; 561 default: 562 break; 563 } 564 break; 565 default: 566 break; 567 } 568 569 if (changed) { 570 ctrl->state = new_state; 571 wake_up_all(&ctrl->state_wq); 572 } 573 574 spin_unlock_irqrestore(&ctrl->lock, flags); 575 if (!changed) 576 return false; 577 578 if (ctrl->state == NVME_CTRL_LIVE) { 579 if (old_state == NVME_CTRL_CONNECTING) 580 nvme_stop_failfast_work(ctrl); 581 nvme_kick_requeue_lists(ctrl); 582 } else if (ctrl->state == NVME_CTRL_CONNECTING && 583 old_state == NVME_CTRL_RESETTING) { 584 nvme_start_failfast_work(ctrl); 585 } 586 return changed; 587 } 588 EXPORT_SYMBOL_GPL(nvme_change_ctrl_state); 589 590 /* 591 * Returns true for sink states that can't ever transition back to live. 592 */ 593 static bool nvme_state_terminal(struct nvme_ctrl *ctrl) 594 { 595 switch (ctrl->state) { 596 case NVME_CTRL_NEW: 597 case NVME_CTRL_LIVE: 598 case NVME_CTRL_RESETTING: 599 case NVME_CTRL_CONNECTING: 600 return false; 601 case NVME_CTRL_DELETING: 602 case NVME_CTRL_DELETING_NOIO: 603 case NVME_CTRL_DEAD: 604 return true; 605 default: 606 WARN_ONCE(1, "Unhandled ctrl state:%d", ctrl->state); 607 return true; 608 } 609 } 610 611 /* 612 * Waits for the controller state to be resetting, or returns false if it is 613 * not possible to ever transition to that state. 614 */ 615 bool nvme_wait_reset(struct nvme_ctrl *ctrl) 616 { 617 wait_event(ctrl->state_wq, 618 nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) || 619 nvme_state_terminal(ctrl)); 620 return ctrl->state == NVME_CTRL_RESETTING; 621 } 622 EXPORT_SYMBOL_GPL(nvme_wait_reset); 623 624 static void nvme_free_ns_head(struct kref *ref) 625 { 626 struct nvme_ns_head *head = 627 container_of(ref, struct nvme_ns_head, ref); 628 629 nvme_mpath_remove_disk(head); 630 ida_free(&head->subsys->ns_ida, head->instance); 631 cleanup_srcu_struct(&head->srcu); 632 nvme_put_subsystem(head->subsys); 633 kfree(head); 634 } 635 636 bool nvme_tryget_ns_head(struct nvme_ns_head *head) 637 { 638 return kref_get_unless_zero(&head->ref); 639 } 640 641 void nvme_put_ns_head(struct nvme_ns_head *head) 642 { 643 kref_put(&head->ref, nvme_free_ns_head); 644 } 645 646 static void nvme_free_ns(struct kref *kref) 647 { 648 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref); 649 650 put_disk(ns->disk); 651 nvme_put_ns_head(ns->head); 652 nvme_put_ctrl(ns->ctrl); 653 kfree(ns); 654 } 655 656 static inline bool nvme_get_ns(struct nvme_ns *ns) 657 { 658 return kref_get_unless_zero(&ns->kref); 659 } 660 661 void nvme_put_ns(struct nvme_ns *ns) 662 { 663 kref_put(&ns->kref, nvme_free_ns); 664 } 665 EXPORT_SYMBOL_NS_GPL(nvme_put_ns, NVME_TARGET_PASSTHRU); 666 667 static inline void nvme_clear_nvme_request(struct request *req) 668 { 669 nvme_req(req)->status = 0; 670 nvme_req(req)->retries = 0; 671 nvme_req(req)->flags = 0; 672 req->rq_flags |= RQF_DONTPREP; 673 } 674 675 /* initialize a passthrough request */ 676 void nvme_init_request(struct request *req, struct nvme_command *cmd) 677 { 678 if (req->q->queuedata) 679 req->timeout = NVME_IO_TIMEOUT; 680 else /* no queuedata implies admin queue */ 681 req->timeout = NVME_ADMIN_TIMEOUT; 682 683 /* passthru commands should let the driver set the SGL flags */ 684 cmd->common.flags &= ~NVME_CMD_SGL_ALL; 685 686 req->cmd_flags |= REQ_FAILFAST_DRIVER; 687 if (req->mq_hctx->type == HCTX_TYPE_POLL) 688 req->cmd_flags |= REQ_POLLED; 689 nvme_clear_nvme_request(req); 690 req->rq_flags |= RQF_QUIET; 691 memcpy(nvme_req(req)->cmd, cmd, sizeof(*cmd)); 692 } 693 EXPORT_SYMBOL_GPL(nvme_init_request); 694 695 /* 696 * For something we're not in a state to send to the device the default action 697 * is to busy it and retry it after the controller state is recovered. However, 698 * if the controller is deleting or if anything is marked for failfast or 699 * nvme multipath it is immediately failed. 700 * 701 * Note: commands used to initialize the controller will be marked for failfast. 702 * Note: nvme cli/ioctl commands are marked for failfast. 703 */ 704 blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl, 705 struct request *rq) 706 { 707 if (ctrl->state != NVME_CTRL_DELETING_NOIO && 708 ctrl->state != NVME_CTRL_DELETING && 709 ctrl->state != NVME_CTRL_DEAD && 710 !test_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags) && 711 !blk_noretry_request(rq) && !(rq->cmd_flags & REQ_NVME_MPATH)) 712 return BLK_STS_RESOURCE; 713 return nvme_host_path_error(rq); 714 } 715 EXPORT_SYMBOL_GPL(nvme_fail_nonready_command); 716 717 bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 718 bool queue_live) 719 { 720 struct nvme_request *req = nvme_req(rq); 721 722 /* 723 * currently we have a problem sending passthru commands 724 * on the admin_q if the controller is not LIVE because we can't 725 * make sure that they are going out after the admin connect, 726 * controller enable and/or other commands in the initialization 727 * sequence. until the controller will be LIVE, fail with 728 * BLK_STS_RESOURCE so that they will be rescheduled. 729 */ 730 if (rq->q == ctrl->admin_q && (req->flags & NVME_REQ_USERCMD)) 731 return false; 732 733 if (ctrl->ops->flags & NVME_F_FABRICS) { 734 /* 735 * Only allow commands on a live queue, except for the connect 736 * command, which is require to set the queue live in the 737 * appropinquate states. 738 */ 739 switch (ctrl->state) { 740 case NVME_CTRL_CONNECTING: 741 if (blk_rq_is_passthrough(rq) && nvme_is_fabrics(req->cmd) && 742 (req->cmd->fabrics.fctype == nvme_fabrics_type_connect || 743 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_send || 744 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_receive)) 745 return true; 746 break; 747 default: 748 break; 749 case NVME_CTRL_DEAD: 750 return false; 751 } 752 } 753 754 return queue_live; 755 } 756 EXPORT_SYMBOL_GPL(__nvme_check_ready); 757 758 static inline void nvme_setup_flush(struct nvme_ns *ns, 759 struct nvme_command *cmnd) 760 { 761 memset(cmnd, 0, sizeof(*cmnd)); 762 cmnd->common.opcode = nvme_cmd_flush; 763 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id); 764 } 765 766 static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req, 767 struct nvme_command *cmnd) 768 { 769 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0; 770 struct nvme_dsm_range *range; 771 struct bio *bio; 772 773 /* 774 * Some devices do not consider the DSM 'Number of Ranges' field when 775 * determining how much data to DMA. Always allocate memory for maximum 776 * number of segments to prevent device reading beyond end of buffer. 777 */ 778 static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES; 779 780 range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN); 781 if (!range) { 782 /* 783 * If we fail allocation our range, fallback to the controller 784 * discard page. If that's also busy, it's safe to return 785 * busy, as we know we can make progress once that's freed. 786 */ 787 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy)) 788 return BLK_STS_RESOURCE; 789 790 range = page_address(ns->ctrl->discard_page); 791 } 792 793 if (queue_max_discard_segments(req->q) == 1) { 794 u64 slba = nvme_sect_to_lba(ns, blk_rq_pos(req)); 795 u32 nlb = blk_rq_sectors(req) >> (ns->lba_shift - 9); 796 797 range[0].cattr = cpu_to_le32(0); 798 range[0].nlb = cpu_to_le32(nlb); 799 range[0].slba = cpu_to_le64(slba); 800 n = 1; 801 } else { 802 __rq_for_each_bio(bio, req) { 803 u64 slba = nvme_sect_to_lba(ns, bio->bi_iter.bi_sector); 804 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift; 805 806 if (n < segments) { 807 range[n].cattr = cpu_to_le32(0); 808 range[n].nlb = cpu_to_le32(nlb); 809 range[n].slba = cpu_to_le64(slba); 810 } 811 n++; 812 } 813 } 814 815 if (WARN_ON_ONCE(n != segments)) { 816 if (virt_to_page(range) == ns->ctrl->discard_page) 817 clear_bit_unlock(0, &ns->ctrl->discard_page_busy); 818 else 819 kfree(range); 820 return BLK_STS_IOERR; 821 } 822 823 memset(cmnd, 0, sizeof(*cmnd)); 824 cmnd->dsm.opcode = nvme_cmd_dsm; 825 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id); 826 cmnd->dsm.nr = cpu_to_le32(segments - 1); 827 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); 828 829 bvec_set_virt(&req->special_vec, range, alloc_size); 830 req->rq_flags |= RQF_SPECIAL_PAYLOAD; 831 832 return BLK_STS_OK; 833 } 834 835 static void nvme_set_ref_tag(struct nvme_ns *ns, struct nvme_command *cmnd, 836 struct request *req) 837 { 838 u32 upper, lower; 839 u64 ref48; 840 841 /* both rw and write zeroes share the same reftag format */ 842 switch (ns->guard_type) { 843 case NVME_NVM_NS_16B_GUARD: 844 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req)); 845 break; 846 case NVME_NVM_NS_64B_GUARD: 847 ref48 = ext_pi_ref_tag(req); 848 lower = lower_32_bits(ref48); 849 upper = upper_32_bits(ref48); 850 851 cmnd->rw.reftag = cpu_to_le32(lower); 852 cmnd->rw.cdw3 = cpu_to_le32(upper); 853 break; 854 default: 855 break; 856 } 857 } 858 859 static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns, 860 struct request *req, struct nvme_command *cmnd) 861 { 862 memset(cmnd, 0, sizeof(*cmnd)); 863 864 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES) 865 return nvme_setup_discard(ns, req, cmnd); 866 867 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes; 868 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id); 869 cmnd->write_zeroes.slba = 870 cpu_to_le64(nvme_sect_to_lba(ns, blk_rq_pos(req))); 871 cmnd->write_zeroes.length = 872 cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); 873 874 if (!(req->cmd_flags & REQ_NOUNMAP) && (ns->features & NVME_NS_DEAC)) 875 cmnd->write_zeroes.control |= cpu_to_le16(NVME_WZ_DEAC); 876 877 if (nvme_ns_has_pi(ns)) { 878 cmnd->write_zeroes.control |= cpu_to_le16(NVME_RW_PRINFO_PRACT); 879 880 switch (ns->pi_type) { 881 case NVME_NS_DPS_PI_TYPE1: 882 case NVME_NS_DPS_PI_TYPE2: 883 nvme_set_ref_tag(ns, cmnd, req); 884 break; 885 } 886 } 887 888 return BLK_STS_OK; 889 } 890 891 static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns, 892 struct request *req, struct nvme_command *cmnd, 893 enum nvme_opcode op) 894 { 895 u16 control = 0; 896 u32 dsmgmt = 0; 897 898 if (req->cmd_flags & REQ_FUA) 899 control |= NVME_RW_FUA; 900 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) 901 control |= NVME_RW_LR; 902 903 if (req->cmd_flags & REQ_RAHEAD) 904 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; 905 906 cmnd->rw.opcode = op; 907 cmnd->rw.flags = 0; 908 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id); 909 cmnd->rw.cdw2 = 0; 910 cmnd->rw.cdw3 = 0; 911 cmnd->rw.metadata = 0; 912 cmnd->rw.slba = cpu_to_le64(nvme_sect_to_lba(ns, blk_rq_pos(req))); 913 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); 914 cmnd->rw.reftag = 0; 915 cmnd->rw.apptag = 0; 916 cmnd->rw.appmask = 0; 917 918 if (ns->ms) { 919 /* 920 * If formated with metadata, the block layer always provides a 921 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else 922 * we enable the PRACT bit for protection information or set the 923 * namespace capacity to zero to prevent any I/O. 924 */ 925 if (!blk_integrity_rq(req)) { 926 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns))) 927 return BLK_STS_NOTSUPP; 928 control |= NVME_RW_PRINFO_PRACT; 929 } 930 931 switch (ns->pi_type) { 932 case NVME_NS_DPS_PI_TYPE3: 933 control |= NVME_RW_PRINFO_PRCHK_GUARD; 934 break; 935 case NVME_NS_DPS_PI_TYPE1: 936 case NVME_NS_DPS_PI_TYPE2: 937 control |= NVME_RW_PRINFO_PRCHK_GUARD | 938 NVME_RW_PRINFO_PRCHK_REF; 939 if (op == nvme_cmd_zone_append) 940 control |= NVME_RW_APPEND_PIREMAP; 941 nvme_set_ref_tag(ns, cmnd, req); 942 break; 943 } 944 } 945 946 cmnd->rw.control = cpu_to_le16(control); 947 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); 948 return 0; 949 } 950 951 void nvme_cleanup_cmd(struct request *req) 952 { 953 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { 954 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl; 955 956 if (req->special_vec.bv_page == ctrl->discard_page) 957 clear_bit_unlock(0, &ctrl->discard_page_busy); 958 else 959 kfree(bvec_virt(&req->special_vec)); 960 } 961 } 962 EXPORT_SYMBOL_GPL(nvme_cleanup_cmd); 963 964 blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req) 965 { 966 struct nvme_command *cmd = nvme_req(req)->cmd; 967 blk_status_t ret = BLK_STS_OK; 968 969 if (!(req->rq_flags & RQF_DONTPREP)) 970 nvme_clear_nvme_request(req); 971 972 switch (req_op(req)) { 973 case REQ_OP_DRV_IN: 974 case REQ_OP_DRV_OUT: 975 /* these are setup prior to execution in nvme_init_request() */ 976 break; 977 case REQ_OP_FLUSH: 978 nvme_setup_flush(ns, cmd); 979 break; 980 case REQ_OP_ZONE_RESET_ALL: 981 case REQ_OP_ZONE_RESET: 982 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_RESET); 983 break; 984 case REQ_OP_ZONE_OPEN: 985 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_OPEN); 986 break; 987 case REQ_OP_ZONE_CLOSE: 988 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_CLOSE); 989 break; 990 case REQ_OP_ZONE_FINISH: 991 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_FINISH); 992 break; 993 case REQ_OP_WRITE_ZEROES: 994 ret = nvme_setup_write_zeroes(ns, req, cmd); 995 break; 996 case REQ_OP_DISCARD: 997 ret = nvme_setup_discard(ns, req, cmd); 998 break; 999 case REQ_OP_READ: 1000 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_read); 1001 break; 1002 case REQ_OP_WRITE: 1003 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_write); 1004 break; 1005 case REQ_OP_ZONE_APPEND: 1006 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_zone_append); 1007 break; 1008 default: 1009 WARN_ON_ONCE(1); 1010 return BLK_STS_IOERR; 1011 } 1012 1013 cmd->common.command_id = nvme_cid(req); 1014 trace_nvme_setup_cmd(req, cmd); 1015 return ret; 1016 } 1017 EXPORT_SYMBOL_GPL(nvme_setup_cmd); 1018 1019 /* 1020 * Return values: 1021 * 0: success 1022 * >0: nvme controller's cqe status response 1023 * <0: kernel error in lieu of controller response 1024 */ 1025 int nvme_execute_rq(struct request *rq, bool at_head) 1026 { 1027 blk_status_t status; 1028 1029 status = blk_execute_rq(rq, at_head); 1030 if (nvme_req(rq)->flags & NVME_REQ_CANCELLED) 1031 return -EINTR; 1032 if (nvme_req(rq)->status) 1033 return nvme_req(rq)->status; 1034 return blk_status_to_errno(status); 1035 } 1036 EXPORT_SYMBOL_NS_GPL(nvme_execute_rq, NVME_TARGET_PASSTHRU); 1037 1038 /* 1039 * Returns 0 on success. If the result is negative, it's a Linux error code; 1040 * if the result is positive, it's an NVM Express status code 1041 */ 1042 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 1043 union nvme_result *result, void *buffer, unsigned bufflen, 1044 int qid, int at_head, blk_mq_req_flags_t flags) 1045 { 1046 struct request *req; 1047 int ret; 1048 1049 if (qid == NVME_QID_ANY) 1050 req = blk_mq_alloc_request(q, nvme_req_op(cmd), flags); 1051 else 1052 req = blk_mq_alloc_request_hctx(q, nvme_req_op(cmd), flags, 1053 qid - 1); 1054 1055 if (IS_ERR(req)) 1056 return PTR_ERR(req); 1057 nvme_init_request(req, cmd); 1058 1059 if (buffer && bufflen) { 1060 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL); 1061 if (ret) 1062 goto out; 1063 } 1064 1065 ret = nvme_execute_rq(req, at_head); 1066 if (result && ret >= 0) 1067 *result = nvme_req(req)->result; 1068 out: 1069 blk_mq_free_request(req); 1070 return ret; 1071 } 1072 EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd); 1073 1074 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 1075 void *buffer, unsigned bufflen) 1076 { 1077 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 1078 NVME_QID_ANY, 0, 0); 1079 } 1080 EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd); 1081 1082 u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode) 1083 { 1084 u32 effects = 0; 1085 1086 if (ns) { 1087 effects = le32_to_cpu(ns->head->effects->iocs[opcode]); 1088 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC)) 1089 dev_warn_once(ctrl->device, 1090 "IO command:%02x has unusual effects:%08x\n", 1091 opcode, effects); 1092 1093 /* 1094 * NVME_CMD_EFFECTS_CSE_MASK causes a freeze all I/O queues, 1095 * which would deadlock when done on an I/O command. Note that 1096 * We already warn about an unusual effect above. 1097 */ 1098 effects &= ~NVME_CMD_EFFECTS_CSE_MASK; 1099 } else { 1100 effects = le32_to_cpu(ctrl->effects->acs[opcode]); 1101 } 1102 1103 return effects; 1104 } 1105 EXPORT_SYMBOL_NS_GPL(nvme_command_effects, NVME_TARGET_PASSTHRU); 1106 1107 u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode) 1108 { 1109 u32 effects = nvme_command_effects(ctrl, ns, opcode); 1110 1111 /* 1112 * For simplicity, IO to all namespaces is quiesced even if the command 1113 * effects say only one namespace is affected. 1114 */ 1115 if (effects & NVME_CMD_EFFECTS_CSE_MASK) { 1116 mutex_lock(&ctrl->scan_lock); 1117 mutex_lock(&ctrl->subsys->lock); 1118 nvme_mpath_start_freeze(ctrl->subsys); 1119 nvme_mpath_wait_freeze(ctrl->subsys); 1120 nvme_start_freeze(ctrl); 1121 nvme_wait_freeze(ctrl); 1122 } 1123 return effects; 1124 } 1125 EXPORT_SYMBOL_NS_GPL(nvme_passthru_start, NVME_TARGET_PASSTHRU); 1126 1127 void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects, 1128 struct nvme_command *cmd, int status) 1129 { 1130 if (effects & NVME_CMD_EFFECTS_CSE_MASK) { 1131 nvme_unfreeze(ctrl); 1132 nvme_mpath_unfreeze(ctrl->subsys); 1133 mutex_unlock(&ctrl->subsys->lock); 1134 mutex_unlock(&ctrl->scan_lock); 1135 } 1136 if (effects & NVME_CMD_EFFECTS_CCC) { 1137 dev_info(ctrl->device, 1138 "controller capabilities changed, reset may be required to take effect.\n"); 1139 } 1140 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC)) { 1141 nvme_queue_scan(ctrl); 1142 flush_work(&ctrl->scan_work); 1143 } 1144 if (ns) 1145 return; 1146 1147 switch (cmd->common.opcode) { 1148 case nvme_admin_set_features: 1149 switch (le32_to_cpu(cmd->common.cdw10) & 0xFF) { 1150 case NVME_FEAT_KATO: 1151 /* 1152 * Keep alive commands interval on the host should be 1153 * updated when KATO is modified by Set Features 1154 * commands. 1155 */ 1156 if (!status) 1157 nvme_update_keep_alive(ctrl, cmd); 1158 break; 1159 default: 1160 break; 1161 } 1162 break; 1163 default: 1164 break; 1165 } 1166 } 1167 EXPORT_SYMBOL_NS_GPL(nvme_passthru_end, NVME_TARGET_PASSTHRU); 1168 1169 /* 1170 * Recommended frequency for KATO commands per NVMe 1.4 section 7.12.1: 1171 * 1172 * The host should send Keep Alive commands at half of the Keep Alive Timeout 1173 * accounting for transport roundtrip times [..]. 1174 */ 1175 static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl) 1176 { 1177 unsigned long delay = ctrl->kato * HZ / 2; 1178 1179 /* 1180 * When using Traffic Based Keep Alive, we need to run 1181 * nvme_keep_alive_work at twice the normal frequency, as one 1182 * command completion can postpone sending a keep alive command 1183 * by up to twice the delay between runs. 1184 */ 1185 if (ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) 1186 delay /= 2; 1187 return delay; 1188 } 1189 1190 static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl) 1191 { 1192 queue_delayed_work(nvme_wq, &ctrl->ka_work, 1193 nvme_keep_alive_work_period(ctrl)); 1194 } 1195 1196 static enum rq_end_io_ret nvme_keep_alive_end_io(struct request *rq, 1197 blk_status_t status) 1198 { 1199 struct nvme_ctrl *ctrl = rq->end_io_data; 1200 unsigned long flags; 1201 bool startka = false; 1202 unsigned long rtt = jiffies - (rq->deadline - rq->timeout); 1203 unsigned long delay = nvme_keep_alive_work_period(ctrl); 1204 1205 /* 1206 * Subtract off the keepalive RTT so nvme_keep_alive_work runs 1207 * at the desired frequency. 1208 */ 1209 if (rtt <= delay) { 1210 delay -= rtt; 1211 } else { 1212 dev_warn(ctrl->device, "long keepalive RTT (%u ms)\n", 1213 jiffies_to_msecs(rtt)); 1214 delay = 0; 1215 } 1216 1217 blk_mq_free_request(rq); 1218 1219 if (status) { 1220 dev_err(ctrl->device, 1221 "failed nvme_keep_alive_end_io error=%d\n", 1222 status); 1223 return RQ_END_IO_NONE; 1224 } 1225 1226 ctrl->ka_last_check_time = jiffies; 1227 ctrl->comp_seen = false; 1228 spin_lock_irqsave(&ctrl->lock, flags); 1229 if (ctrl->state == NVME_CTRL_LIVE || 1230 ctrl->state == NVME_CTRL_CONNECTING) 1231 startka = true; 1232 spin_unlock_irqrestore(&ctrl->lock, flags); 1233 if (startka) 1234 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay); 1235 return RQ_END_IO_NONE; 1236 } 1237 1238 static void nvme_keep_alive_work(struct work_struct *work) 1239 { 1240 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work), 1241 struct nvme_ctrl, ka_work); 1242 bool comp_seen = ctrl->comp_seen; 1243 struct request *rq; 1244 1245 ctrl->ka_last_check_time = jiffies; 1246 1247 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) { 1248 dev_dbg(ctrl->device, 1249 "reschedule traffic based keep-alive timer\n"); 1250 ctrl->comp_seen = false; 1251 nvme_queue_keep_alive_work(ctrl); 1252 return; 1253 } 1254 1255 rq = blk_mq_alloc_request(ctrl->admin_q, nvme_req_op(&ctrl->ka_cmd), 1256 BLK_MQ_REQ_RESERVED | BLK_MQ_REQ_NOWAIT); 1257 if (IS_ERR(rq)) { 1258 /* allocation failure, reset the controller */ 1259 dev_err(ctrl->device, "keep-alive failed: %ld\n", PTR_ERR(rq)); 1260 nvme_reset_ctrl(ctrl); 1261 return; 1262 } 1263 nvme_init_request(rq, &ctrl->ka_cmd); 1264 1265 rq->timeout = ctrl->kato * HZ; 1266 rq->end_io = nvme_keep_alive_end_io; 1267 rq->end_io_data = ctrl; 1268 blk_execute_rq_nowait(rq, false); 1269 } 1270 1271 static void nvme_start_keep_alive(struct nvme_ctrl *ctrl) 1272 { 1273 if (unlikely(ctrl->kato == 0)) 1274 return; 1275 1276 nvme_queue_keep_alive_work(ctrl); 1277 } 1278 1279 void nvme_stop_keep_alive(struct nvme_ctrl *ctrl) 1280 { 1281 if (unlikely(ctrl->kato == 0)) 1282 return; 1283 1284 cancel_delayed_work_sync(&ctrl->ka_work); 1285 } 1286 EXPORT_SYMBOL_GPL(nvme_stop_keep_alive); 1287 1288 static void nvme_update_keep_alive(struct nvme_ctrl *ctrl, 1289 struct nvme_command *cmd) 1290 { 1291 unsigned int new_kato = 1292 DIV_ROUND_UP(le32_to_cpu(cmd->common.cdw11), 1000); 1293 1294 dev_info(ctrl->device, 1295 "keep alive interval updated from %u ms to %u ms\n", 1296 ctrl->kato * 1000 / 2, new_kato * 1000 / 2); 1297 1298 nvme_stop_keep_alive(ctrl); 1299 ctrl->kato = new_kato; 1300 nvme_start_keep_alive(ctrl); 1301 } 1302 1303 /* 1304 * In NVMe 1.0 the CNS field was just a binary controller or namespace 1305 * flag, thus sending any new CNS opcodes has a big chance of not working. 1306 * Qemu unfortunately had that bug after reporting a 1.1 version compliance 1307 * (but not for any later version). 1308 */ 1309 static bool nvme_ctrl_limited_cns(struct nvme_ctrl *ctrl) 1310 { 1311 if (ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS) 1312 return ctrl->vs < NVME_VS(1, 2, 0); 1313 return ctrl->vs < NVME_VS(1, 1, 0); 1314 } 1315 1316 static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id) 1317 { 1318 struct nvme_command c = { }; 1319 int error; 1320 1321 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ 1322 c.identify.opcode = nvme_admin_identify; 1323 c.identify.cns = NVME_ID_CNS_CTRL; 1324 1325 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL); 1326 if (!*id) 1327 return -ENOMEM; 1328 1329 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id, 1330 sizeof(struct nvme_id_ctrl)); 1331 if (error) 1332 kfree(*id); 1333 return error; 1334 } 1335 1336 static int nvme_process_ns_desc(struct nvme_ctrl *ctrl, struct nvme_ns_ids *ids, 1337 struct nvme_ns_id_desc *cur, bool *csi_seen) 1338 { 1339 const char *warn_str = "ctrl returned bogus length:"; 1340 void *data = cur; 1341 1342 switch (cur->nidt) { 1343 case NVME_NIDT_EUI64: 1344 if (cur->nidl != NVME_NIDT_EUI64_LEN) { 1345 dev_warn(ctrl->device, "%s %d for NVME_NIDT_EUI64\n", 1346 warn_str, cur->nidl); 1347 return -1; 1348 } 1349 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) 1350 return NVME_NIDT_EUI64_LEN; 1351 memcpy(ids->eui64, data + sizeof(*cur), NVME_NIDT_EUI64_LEN); 1352 return NVME_NIDT_EUI64_LEN; 1353 case NVME_NIDT_NGUID: 1354 if (cur->nidl != NVME_NIDT_NGUID_LEN) { 1355 dev_warn(ctrl->device, "%s %d for NVME_NIDT_NGUID\n", 1356 warn_str, cur->nidl); 1357 return -1; 1358 } 1359 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) 1360 return NVME_NIDT_NGUID_LEN; 1361 memcpy(ids->nguid, data + sizeof(*cur), NVME_NIDT_NGUID_LEN); 1362 return NVME_NIDT_NGUID_LEN; 1363 case NVME_NIDT_UUID: 1364 if (cur->nidl != NVME_NIDT_UUID_LEN) { 1365 dev_warn(ctrl->device, "%s %d for NVME_NIDT_UUID\n", 1366 warn_str, cur->nidl); 1367 return -1; 1368 } 1369 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) 1370 return NVME_NIDT_UUID_LEN; 1371 uuid_copy(&ids->uuid, data + sizeof(*cur)); 1372 return NVME_NIDT_UUID_LEN; 1373 case NVME_NIDT_CSI: 1374 if (cur->nidl != NVME_NIDT_CSI_LEN) { 1375 dev_warn(ctrl->device, "%s %d for NVME_NIDT_CSI\n", 1376 warn_str, cur->nidl); 1377 return -1; 1378 } 1379 memcpy(&ids->csi, data + sizeof(*cur), NVME_NIDT_CSI_LEN); 1380 *csi_seen = true; 1381 return NVME_NIDT_CSI_LEN; 1382 default: 1383 /* Skip unknown types */ 1384 return cur->nidl; 1385 } 1386 } 1387 1388 static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, 1389 struct nvme_ns_info *info) 1390 { 1391 struct nvme_command c = { }; 1392 bool csi_seen = false; 1393 int status, pos, len; 1394 void *data; 1395 1396 if (ctrl->vs < NVME_VS(1, 3, 0) && !nvme_multi_css(ctrl)) 1397 return 0; 1398 if (ctrl->quirks & NVME_QUIRK_NO_NS_DESC_LIST) 1399 return 0; 1400 1401 c.identify.opcode = nvme_admin_identify; 1402 c.identify.nsid = cpu_to_le32(info->nsid); 1403 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST; 1404 1405 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL); 1406 if (!data) 1407 return -ENOMEM; 1408 1409 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data, 1410 NVME_IDENTIFY_DATA_SIZE); 1411 if (status) { 1412 dev_warn(ctrl->device, 1413 "Identify Descriptors failed (nsid=%u, status=0x%x)\n", 1414 info->nsid, status); 1415 goto free_data; 1416 } 1417 1418 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) { 1419 struct nvme_ns_id_desc *cur = data + pos; 1420 1421 if (cur->nidl == 0) 1422 break; 1423 1424 len = nvme_process_ns_desc(ctrl, &info->ids, cur, &csi_seen); 1425 if (len < 0) 1426 break; 1427 1428 len += sizeof(*cur); 1429 } 1430 1431 if (nvme_multi_css(ctrl) && !csi_seen) { 1432 dev_warn(ctrl->device, "Command set not reported for nsid:%d\n", 1433 info->nsid); 1434 status = -EINVAL; 1435 } 1436 1437 free_data: 1438 kfree(data); 1439 return status; 1440 } 1441 1442 static int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid, 1443 struct nvme_id_ns **id) 1444 { 1445 struct nvme_command c = { }; 1446 int error; 1447 1448 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ 1449 c.identify.opcode = nvme_admin_identify; 1450 c.identify.nsid = cpu_to_le32(nsid); 1451 c.identify.cns = NVME_ID_CNS_NS; 1452 1453 *id = kmalloc(sizeof(**id), GFP_KERNEL); 1454 if (!*id) 1455 return -ENOMEM; 1456 1457 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id)); 1458 if (error) { 1459 dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error); 1460 kfree(*id); 1461 } 1462 return error; 1463 } 1464 1465 static int nvme_ns_info_from_identify(struct nvme_ctrl *ctrl, 1466 struct nvme_ns_info *info) 1467 { 1468 struct nvme_ns_ids *ids = &info->ids; 1469 struct nvme_id_ns *id; 1470 int ret; 1471 1472 ret = nvme_identify_ns(ctrl, info->nsid, &id); 1473 if (ret) 1474 return ret; 1475 1476 if (id->ncap == 0) { 1477 /* namespace not allocated or attached */ 1478 info->is_removed = true; 1479 return -ENODEV; 1480 } 1481 1482 info->anagrpid = id->anagrpid; 1483 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED; 1484 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO; 1485 info->is_ready = true; 1486 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) { 1487 dev_info(ctrl->device, 1488 "Ignoring bogus Namespace Identifiers\n"); 1489 } else { 1490 if (ctrl->vs >= NVME_VS(1, 1, 0) && 1491 !memchr_inv(ids->eui64, 0, sizeof(ids->eui64))) 1492 memcpy(ids->eui64, id->eui64, sizeof(ids->eui64)); 1493 if (ctrl->vs >= NVME_VS(1, 2, 0) && 1494 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid))) 1495 memcpy(ids->nguid, id->nguid, sizeof(ids->nguid)); 1496 } 1497 kfree(id); 1498 return 0; 1499 } 1500 1501 static int nvme_ns_info_from_id_cs_indep(struct nvme_ctrl *ctrl, 1502 struct nvme_ns_info *info) 1503 { 1504 struct nvme_id_ns_cs_indep *id; 1505 struct nvme_command c = { 1506 .identify.opcode = nvme_admin_identify, 1507 .identify.nsid = cpu_to_le32(info->nsid), 1508 .identify.cns = NVME_ID_CNS_NS_CS_INDEP, 1509 }; 1510 int ret; 1511 1512 id = kmalloc(sizeof(*id), GFP_KERNEL); 1513 if (!id) 1514 return -ENOMEM; 1515 1516 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id)); 1517 if (!ret) { 1518 info->anagrpid = id->anagrpid; 1519 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED; 1520 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO; 1521 info->is_ready = id->nstat & NVME_NSTAT_NRDY; 1522 } 1523 kfree(id); 1524 return ret; 1525 } 1526 1527 static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid, 1528 unsigned int dword11, void *buffer, size_t buflen, u32 *result) 1529 { 1530 union nvme_result res = { 0 }; 1531 struct nvme_command c = { }; 1532 int ret; 1533 1534 c.features.opcode = op; 1535 c.features.fid = cpu_to_le32(fid); 1536 c.features.dword11 = cpu_to_le32(dword11); 1537 1538 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res, 1539 buffer, buflen, NVME_QID_ANY, 0, 0); 1540 if (ret >= 0 && result) 1541 *result = le32_to_cpu(res.u32); 1542 return ret; 1543 } 1544 1545 int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, 1546 unsigned int dword11, void *buffer, size_t buflen, 1547 u32 *result) 1548 { 1549 return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer, 1550 buflen, result); 1551 } 1552 EXPORT_SYMBOL_GPL(nvme_set_features); 1553 1554 int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, 1555 unsigned int dword11, void *buffer, size_t buflen, 1556 u32 *result) 1557 { 1558 return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer, 1559 buflen, result); 1560 } 1561 EXPORT_SYMBOL_GPL(nvme_get_features); 1562 1563 int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count) 1564 { 1565 u32 q_count = (*count - 1) | ((*count - 1) << 16); 1566 u32 result; 1567 int status, nr_io_queues; 1568 1569 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0, 1570 &result); 1571 if (status < 0) 1572 return status; 1573 1574 /* 1575 * Degraded controllers might return an error when setting the queue 1576 * count. We still want to be able to bring them online and offer 1577 * access to the admin queue, as that might be only way to fix them up. 1578 */ 1579 if (status > 0) { 1580 dev_err(ctrl->device, "Could not set queue count (%d)\n", status); 1581 *count = 0; 1582 } else { 1583 nr_io_queues = min(result & 0xffff, result >> 16) + 1; 1584 *count = min(*count, nr_io_queues); 1585 } 1586 1587 return 0; 1588 } 1589 EXPORT_SYMBOL_GPL(nvme_set_queue_count); 1590 1591 #define NVME_AEN_SUPPORTED \ 1592 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \ 1593 NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE) 1594 1595 static void nvme_enable_aen(struct nvme_ctrl *ctrl) 1596 { 1597 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED; 1598 int status; 1599 1600 if (!supported_aens) 1601 return; 1602 1603 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens, 1604 NULL, 0, &result); 1605 if (status) 1606 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n", 1607 supported_aens); 1608 1609 queue_work(nvme_wq, &ctrl->async_event_work); 1610 } 1611 1612 static int nvme_ns_open(struct nvme_ns *ns) 1613 { 1614 1615 /* should never be called due to GENHD_FL_HIDDEN */ 1616 if (WARN_ON_ONCE(nvme_ns_head_multipath(ns->head))) 1617 goto fail; 1618 if (!nvme_get_ns(ns)) 1619 goto fail; 1620 if (!try_module_get(ns->ctrl->ops->module)) 1621 goto fail_put_ns; 1622 1623 return 0; 1624 1625 fail_put_ns: 1626 nvme_put_ns(ns); 1627 fail: 1628 return -ENXIO; 1629 } 1630 1631 static void nvme_ns_release(struct nvme_ns *ns) 1632 { 1633 1634 module_put(ns->ctrl->ops->module); 1635 nvme_put_ns(ns); 1636 } 1637 1638 static int nvme_open(struct gendisk *disk, blk_mode_t mode) 1639 { 1640 return nvme_ns_open(disk->private_data); 1641 } 1642 1643 static void nvme_release(struct gendisk *disk) 1644 { 1645 nvme_ns_release(disk->private_data); 1646 } 1647 1648 int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo) 1649 { 1650 /* some standard values */ 1651 geo->heads = 1 << 6; 1652 geo->sectors = 1 << 5; 1653 geo->cylinders = get_capacity(bdev->bd_disk) >> 11; 1654 return 0; 1655 } 1656 1657 #ifdef CONFIG_BLK_DEV_INTEGRITY 1658 static void nvme_init_integrity(struct gendisk *disk, struct nvme_ns *ns, 1659 u32 max_integrity_segments) 1660 { 1661 struct blk_integrity integrity = { }; 1662 1663 switch (ns->pi_type) { 1664 case NVME_NS_DPS_PI_TYPE3: 1665 switch (ns->guard_type) { 1666 case NVME_NVM_NS_16B_GUARD: 1667 integrity.profile = &t10_pi_type3_crc; 1668 integrity.tag_size = sizeof(u16) + sizeof(u32); 1669 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE; 1670 break; 1671 case NVME_NVM_NS_64B_GUARD: 1672 integrity.profile = &ext_pi_type3_crc64; 1673 integrity.tag_size = sizeof(u16) + 6; 1674 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE; 1675 break; 1676 default: 1677 integrity.profile = NULL; 1678 break; 1679 } 1680 break; 1681 case NVME_NS_DPS_PI_TYPE1: 1682 case NVME_NS_DPS_PI_TYPE2: 1683 switch (ns->guard_type) { 1684 case NVME_NVM_NS_16B_GUARD: 1685 integrity.profile = &t10_pi_type1_crc; 1686 integrity.tag_size = sizeof(u16); 1687 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE; 1688 break; 1689 case NVME_NVM_NS_64B_GUARD: 1690 integrity.profile = &ext_pi_type1_crc64; 1691 integrity.tag_size = sizeof(u16); 1692 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE; 1693 break; 1694 default: 1695 integrity.profile = NULL; 1696 break; 1697 } 1698 break; 1699 default: 1700 integrity.profile = NULL; 1701 break; 1702 } 1703 1704 integrity.tuple_size = ns->ms; 1705 blk_integrity_register(disk, &integrity); 1706 blk_queue_max_integrity_segments(disk->queue, max_integrity_segments); 1707 } 1708 #else 1709 static void nvme_init_integrity(struct gendisk *disk, struct nvme_ns *ns, 1710 u32 max_integrity_segments) 1711 { 1712 } 1713 #endif /* CONFIG_BLK_DEV_INTEGRITY */ 1714 1715 static void nvme_config_discard(struct gendisk *disk, struct nvme_ns *ns) 1716 { 1717 struct nvme_ctrl *ctrl = ns->ctrl; 1718 struct request_queue *queue = disk->queue; 1719 u32 size = queue_logical_block_size(queue); 1720 1721 if (ctrl->dmrsl && ctrl->dmrsl <= nvme_sect_to_lba(ns, UINT_MAX)) 1722 ctrl->max_discard_sectors = nvme_lba_to_sect(ns, ctrl->dmrsl); 1723 1724 if (ctrl->max_discard_sectors == 0) { 1725 blk_queue_max_discard_sectors(queue, 0); 1726 return; 1727 } 1728 1729 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) < 1730 NVME_DSM_MAX_RANGES); 1731 1732 queue->limits.discard_granularity = size; 1733 1734 /* If discard is already enabled, don't reset queue limits */ 1735 if (queue->limits.max_discard_sectors) 1736 return; 1737 1738 blk_queue_max_discard_sectors(queue, ctrl->max_discard_sectors); 1739 blk_queue_max_discard_segments(queue, ctrl->max_discard_segments); 1740 1741 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES) 1742 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX); 1743 } 1744 1745 static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b) 1746 { 1747 return uuid_equal(&a->uuid, &b->uuid) && 1748 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 && 1749 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0 && 1750 a->csi == b->csi; 1751 } 1752 1753 static int nvme_init_ms(struct nvme_ns *ns, struct nvme_id_ns *id) 1754 { 1755 bool first = id->dps & NVME_NS_DPS_PI_FIRST; 1756 unsigned lbaf = nvme_lbaf_index(id->flbas); 1757 struct nvme_ctrl *ctrl = ns->ctrl; 1758 struct nvme_command c = { }; 1759 struct nvme_id_ns_nvm *nvm; 1760 int ret = 0; 1761 u32 elbaf; 1762 1763 ns->pi_size = 0; 1764 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); 1765 if (!(ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)) { 1766 ns->pi_size = sizeof(struct t10_pi_tuple); 1767 ns->guard_type = NVME_NVM_NS_16B_GUARD; 1768 goto set_pi; 1769 } 1770 1771 nvm = kzalloc(sizeof(*nvm), GFP_KERNEL); 1772 if (!nvm) 1773 return -ENOMEM; 1774 1775 c.identify.opcode = nvme_admin_identify; 1776 c.identify.nsid = cpu_to_le32(ns->head->ns_id); 1777 c.identify.cns = NVME_ID_CNS_CS_NS; 1778 c.identify.csi = NVME_CSI_NVM; 1779 1780 ret = nvme_submit_sync_cmd(ns->ctrl->admin_q, &c, nvm, sizeof(*nvm)); 1781 if (ret) 1782 goto free_data; 1783 1784 elbaf = le32_to_cpu(nvm->elbaf[lbaf]); 1785 1786 /* no support for storage tag formats right now */ 1787 if (nvme_elbaf_sts(elbaf)) 1788 goto free_data; 1789 1790 ns->guard_type = nvme_elbaf_guard_type(elbaf); 1791 switch (ns->guard_type) { 1792 case NVME_NVM_NS_64B_GUARD: 1793 ns->pi_size = sizeof(struct crc64_pi_tuple); 1794 break; 1795 case NVME_NVM_NS_16B_GUARD: 1796 ns->pi_size = sizeof(struct t10_pi_tuple); 1797 break; 1798 default: 1799 break; 1800 } 1801 1802 free_data: 1803 kfree(nvm); 1804 set_pi: 1805 if (ns->pi_size && (first || ns->ms == ns->pi_size)) 1806 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK; 1807 else 1808 ns->pi_type = 0; 1809 1810 return ret; 1811 } 1812 1813 static void nvme_configure_metadata(struct nvme_ns *ns, struct nvme_id_ns *id) 1814 { 1815 struct nvme_ctrl *ctrl = ns->ctrl; 1816 1817 if (nvme_init_ms(ns, id)) 1818 return; 1819 1820 ns->features &= ~(NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS); 1821 if (!ns->ms || !(ctrl->ops->flags & NVME_F_METADATA_SUPPORTED)) 1822 return; 1823 1824 if (ctrl->ops->flags & NVME_F_FABRICS) { 1825 /* 1826 * The NVMe over Fabrics specification only supports metadata as 1827 * part of the extended data LBA. We rely on HCA/HBA support to 1828 * remap the separate metadata buffer from the block layer. 1829 */ 1830 if (WARN_ON_ONCE(!(id->flbas & NVME_NS_FLBAS_META_EXT))) 1831 return; 1832 1833 ns->features |= NVME_NS_EXT_LBAS; 1834 1835 /* 1836 * The current fabrics transport drivers support namespace 1837 * metadata formats only if nvme_ns_has_pi() returns true. 1838 * Suppress support for all other formats so the namespace will 1839 * have a 0 capacity and not be usable through the block stack. 1840 * 1841 * Note, this check will need to be modified if any drivers 1842 * gain the ability to use other metadata formats. 1843 */ 1844 if (ctrl->max_integrity_segments && nvme_ns_has_pi(ns)) 1845 ns->features |= NVME_NS_METADATA_SUPPORTED; 1846 } else { 1847 /* 1848 * For PCIe controllers, we can't easily remap the separate 1849 * metadata buffer from the block layer and thus require a 1850 * separate metadata buffer for block layer metadata/PI support. 1851 * We allow extended LBAs for the passthrough interface, though. 1852 */ 1853 if (id->flbas & NVME_NS_FLBAS_META_EXT) 1854 ns->features |= NVME_NS_EXT_LBAS; 1855 else 1856 ns->features |= NVME_NS_METADATA_SUPPORTED; 1857 } 1858 } 1859 1860 static void nvme_set_queue_limits(struct nvme_ctrl *ctrl, 1861 struct request_queue *q) 1862 { 1863 bool vwc = ctrl->vwc & NVME_CTRL_VWC_PRESENT; 1864 1865 if (ctrl->max_hw_sectors) { 1866 u32 max_segments = 1867 (ctrl->max_hw_sectors / (NVME_CTRL_PAGE_SIZE >> 9)) + 1; 1868 1869 max_segments = min_not_zero(max_segments, ctrl->max_segments); 1870 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors); 1871 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX)); 1872 } 1873 blk_queue_virt_boundary(q, NVME_CTRL_PAGE_SIZE - 1); 1874 blk_queue_dma_alignment(q, 3); 1875 blk_queue_write_cache(q, vwc, vwc); 1876 } 1877 1878 static void nvme_update_disk_info(struct gendisk *disk, 1879 struct nvme_ns *ns, struct nvme_id_ns *id) 1880 { 1881 sector_t capacity = nvme_lba_to_sect(ns, le64_to_cpu(id->nsze)); 1882 u32 bs = 1U << ns->lba_shift; 1883 u32 atomic_bs, phys_bs, io_opt = 0; 1884 1885 /* 1886 * The block layer can't support LBA sizes larger than the page size 1887 * yet, so catch this early and don't allow block I/O. 1888 */ 1889 if (ns->lba_shift > PAGE_SHIFT) { 1890 capacity = 0; 1891 bs = (1 << 9); 1892 } 1893 1894 blk_integrity_unregister(disk); 1895 1896 atomic_bs = phys_bs = bs; 1897 if (id->nabo == 0) { 1898 /* 1899 * Bit 1 indicates whether NAWUPF is defined for this namespace 1900 * and whether it should be used instead of AWUPF. If NAWUPF == 1901 * 0 then AWUPF must be used instead. 1902 */ 1903 if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf) 1904 atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs; 1905 else 1906 atomic_bs = (1 + ns->ctrl->subsys->awupf) * bs; 1907 } 1908 1909 if (id->nsfeat & NVME_NS_FEAT_IO_OPT) { 1910 /* NPWG = Namespace Preferred Write Granularity */ 1911 phys_bs = bs * (1 + le16_to_cpu(id->npwg)); 1912 /* NOWS = Namespace Optimal Write Size */ 1913 io_opt = bs * (1 + le16_to_cpu(id->nows)); 1914 } 1915 1916 blk_queue_logical_block_size(disk->queue, bs); 1917 /* 1918 * Linux filesystems assume writing a single physical block is 1919 * an atomic operation. Hence limit the physical block size to the 1920 * value of the Atomic Write Unit Power Fail parameter. 1921 */ 1922 blk_queue_physical_block_size(disk->queue, min(phys_bs, atomic_bs)); 1923 blk_queue_io_min(disk->queue, phys_bs); 1924 blk_queue_io_opt(disk->queue, io_opt); 1925 1926 /* 1927 * Register a metadata profile for PI, or the plain non-integrity NVMe 1928 * metadata masquerading as Type 0 if supported, otherwise reject block 1929 * I/O to namespaces with metadata except when the namespace supports 1930 * PI, as it can strip/insert in that case. 1931 */ 1932 if (ns->ms) { 1933 if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) && 1934 (ns->features & NVME_NS_METADATA_SUPPORTED)) 1935 nvme_init_integrity(disk, ns, 1936 ns->ctrl->max_integrity_segments); 1937 else if (!nvme_ns_has_pi(ns)) 1938 capacity = 0; 1939 } 1940 1941 set_capacity_and_notify(disk, capacity); 1942 1943 nvme_config_discard(disk, ns); 1944 blk_queue_max_write_zeroes_sectors(disk->queue, 1945 ns->ctrl->max_zeroes_sectors); 1946 } 1947 1948 static bool nvme_ns_is_readonly(struct nvme_ns *ns, struct nvme_ns_info *info) 1949 { 1950 return info->is_readonly || test_bit(NVME_NS_FORCE_RO, &ns->flags); 1951 } 1952 1953 static inline bool nvme_first_scan(struct gendisk *disk) 1954 { 1955 /* nvme_alloc_ns() scans the disk prior to adding it */ 1956 return !disk_live(disk); 1957 } 1958 1959 static void nvme_set_chunk_sectors(struct nvme_ns *ns, struct nvme_id_ns *id) 1960 { 1961 struct nvme_ctrl *ctrl = ns->ctrl; 1962 u32 iob; 1963 1964 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) && 1965 is_power_of_2(ctrl->max_hw_sectors)) 1966 iob = ctrl->max_hw_sectors; 1967 else 1968 iob = nvme_lba_to_sect(ns, le16_to_cpu(id->noiob)); 1969 1970 if (!iob) 1971 return; 1972 1973 if (!is_power_of_2(iob)) { 1974 if (nvme_first_scan(ns->disk)) 1975 pr_warn("%s: ignoring unaligned IO boundary:%u\n", 1976 ns->disk->disk_name, iob); 1977 return; 1978 } 1979 1980 if (blk_queue_is_zoned(ns->disk->queue)) { 1981 if (nvme_first_scan(ns->disk)) 1982 pr_warn("%s: ignoring zoned namespace IO boundary\n", 1983 ns->disk->disk_name); 1984 return; 1985 } 1986 1987 blk_queue_chunk_sectors(ns->queue, iob); 1988 } 1989 1990 static int nvme_update_ns_info_generic(struct nvme_ns *ns, 1991 struct nvme_ns_info *info) 1992 { 1993 blk_mq_freeze_queue(ns->disk->queue); 1994 nvme_set_queue_limits(ns->ctrl, ns->queue); 1995 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info)); 1996 blk_mq_unfreeze_queue(ns->disk->queue); 1997 1998 if (nvme_ns_head_multipath(ns->head)) { 1999 blk_mq_freeze_queue(ns->head->disk->queue); 2000 set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info)); 2001 nvme_mpath_revalidate_paths(ns); 2002 blk_stack_limits(&ns->head->disk->queue->limits, 2003 &ns->queue->limits, 0); 2004 ns->head->disk->flags |= GENHD_FL_HIDDEN; 2005 blk_mq_unfreeze_queue(ns->head->disk->queue); 2006 } 2007 2008 /* Hide the block-interface for these devices */ 2009 ns->disk->flags |= GENHD_FL_HIDDEN; 2010 set_bit(NVME_NS_READY, &ns->flags); 2011 2012 return 0; 2013 } 2014 2015 static int nvme_update_ns_info_block(struct nvme_ns *ns, 2016 struct nvme_ns_info *info) 2017 { 2018 struct nvme_id_ns *id; 2019 unsigned lbaf; 2020 int ret; 2021 2022 ret = nvme_identify_ns(ns->ctrl, info->nsid, &id); 2023 if (ret) 2024 return ret; 2025 2026 blk_mq_freeze_queue(ns->disk->queue); 2027 lbaf = nvme_lbaf_index(id->flbas); 2028 ns->lba_shift = id->lbaf[lbaf].ds; 2029 nvme_set_queue_limits(ns->ctrl, ns->queue); 2030 2031 nvme_configure_metadata(ns, id); 2032 nvme_set_chunk_sectors(ns, id); 2033 nvme_update_disk_info(ns->disk, ns, id); 2034 2035 if (ns->head->ids.csi == NVME_CSI_ZNS) { 2036 ret = nvme_update_zone_info(ns, lbaf); 2037 if (ret) { 2038 blk_mq_unfreeze_queue(ns->disk->queue); 2039 goto out; 2040 } 2041 } 2042 2043 /* 2044 * Only set the DEAC bit if the device guarantees that reads from 2045 * deallocated data return zeroes. While the DEAC bit does not 2046 * require that, it must be a no-op if reads from deallocated data 2047 * do not return zeroes. 2048 */ 2049 if ((id->dlfeat & 0x7) == 0x1 && (id->dlfeat & (1 << 3))) 2050 ns->features |= NVME_NS_DEAC; 2051 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info)); 2052 set_bit(NVME_NS_READY, &ns->flags); 2053 blk_mq_unfreeze_queue(ns->disk->queue); 2054 2055 if (blk_queue_is_zoned(ns->queue)) { 2056 ret = nvme_revalidate_zones(ns); 2057 if (ret && !nvme_first_scan(ns->disk)) 2058 goto out; 2059 } 2060 2061 if (nvme_ns_head_multipath(ns->head)) { 2062 blk_mq_freeze_queue(ns->head->disk->queue); 2063 nvme_update_disk_info(ns->head->disk, ns, id); 2064 set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info)); 2065 nvme_mpath_revalidate_paths(ns); 2066 blk_stack_limits(&ns->head->disk->queue->limits, 2067 &ns->queue->limits, 0); 2068 disk_update_readahead(ns->head->disk); 2069 blk_mq_unfreeze_queue(ns->head->disk->queue); 2070 } 2071 2072 ret = 0; 2073 out: 2074 /* 2075 * If probing fails due an unsupported feature, hide the block device, 2076 * but still allow other access. 2077 */ 2078 if (ret == -ENODEV) { 2079 ns->disk->flags |= GENHD_FL_HIDDEN; 2080 set_bit(NVME_NS_READY, &ns->flags); 2081 ret = 0; 2082 } 2083 kfree(id); 2084 return ret; 2085 } 2086 2087 static int nvme_update_ns_info(struct nvme_ns *ns, struct nvme_ns_info *info) 2088 { 2089 switch (info->ids.csi) { 2090 case NVME_CSI_ZNS: 2091 if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) { 2092 dev_info(ns->ctrl->device, 2093 "block device for nsid %u not supported without CONFIG_BLK_DEV_ZONED\n", 2094 info->nsid); 2095 return nvme_update_ns_info_generic(ns, info); 2096 } 2097 return nvme_update_ns_info_block(ns, info); 2098 case NVME_CSI_NVM: 2099 return nvme_update_ns_info_block(ns, info); 2100 default: 2101 dev_info(ns->ctrl->device, 2102 "block device for nsid %u not supported (csi %u)\n", 2103 info->nsid, info->ids.csi); 2104 return nvme_update_ns_info_generic(ns, info); 2105 } 2106 } 2107 2108 static char nvme_pr_type(enum pr_type type) 2109 { 2110 switch (type) { 2111 case PR_WRITE_EXCLUSIVE: 2112 return 1; 2113 case PR_EXCLUSIVE_ACCESS: 2114 return 2; 2115 case PR_WRITE_EXCLUSIVE_REG_ONLY: 2116 return 3; 2117 case PR_EXCLUSIVE_ACCESS_REG_ONLY: 2118 return 4; 2119 case PR_WRITE_EXCLUSIVE_ALL_REGS: 2120 return 5; 2121 case PR_EXCLUSIVE_ACCESS_ALL_REGS: 2122 return 6; 2123 default: 2124 return 0; 2125 } 2126 } 2127 2128 static int nvme_send_ns_head_pr_command(struct block_device *bdev, 2129 struct nvme_command *c, u8 data[16]) 2130 { 2131 struct nvme_ns_head *head = bdev->bd_disk->private_data; 2132 int srcu_idx = srcu_read_lock(&head->srcu); 2133 struct nvme_ns *ns = nvme_find_path(head); 2134 int ret = -EWOULDBLOCK; 2135 2136 if (ns) { 2137 c->common.nsid = cpu_to_le32(ns->head->ns_id); 2138 ret = nvme_submit_sync_cmd(ns->queue, c, data, 16); 2139 } 2140 srcu_read_unlock(&head->srcu, srcu_idx); 2141 return ret; 2142 } 2143 2144 static int nvme_send_ns_pr_command(struct nvme_ns *ns, struct nvme_command *c, 2145 u8 data[16]) 2146 { 2147 c->common.nsid = cpu_to_le32(ns->head->ns_id); 2148 return nvme_submit_sync_cmd(ns->queue, c, data, 16); 2149 } 2150 2151 static int nvme_sc_to_pr_err(int nvme_sc) 2152 { 2153 if (nvme_is_path_error(nvme_sc)) 2154 return PR_STS_PATH_FAILED; 2155 2156 switch (nvme_sc) { 2157 case NVME_SC_SUCCESS: 2158 return PR_STS_SUCCESS; 2159 case NVME_SC_RESERVATION_CONFLICT: 2160 return PR_STS_RESERVATION_CONFLICT; 2161 case NVME_SC_ONCS_NOT_SUPPORTED: 2162 return -EOPNOTSUPP; 2163 case NVME_SC_BAD_ATTRIBUTES: 2164 case NVME_SC_INVALID_OPCODE: 2165 case NVME_SC_INVALID_FIELD: 2166 case NVME_SC_INVALID_NS: 2167 return -EINVAL; 2168 default: 2169 return PR_STS_IOERR; 2170 } 2171 } 2172 2173 static int nvme_pr_command(struct block_device *bdev, u32 cdw10, 2174 u64 key, u64 sa_key, u8 op) 2175 { 2176 struct nvme_command c = { }; 2177 u8 data[16] = { 0, }; 2178 int ret; 2179 2180 put_unaligned_le64(key, &data[0]); 2181 put_unaligned_le64(sa_key, &data[8]); 2182 2183 c.common.opcode = op; 2184 c.common.cdw10 = cpu_to_le32(cdw10); 2185 2186 if (IS_ENABLED(CONFIG_NVME_MULTIPATH) && 2187 bdev->bd_disk->fops == &nvme_ns_head_ops) 2188 ret = nvme_send_ns_head_pr_command(bdev, &c, data); 2189 else 2190 ret = nvme_send_ns_pr_command(bdev->bd_disk->private_data, &c, 2191 data); 2192 if (ret < 0) 2193 return ret; 2194 2195 return nvme_sc_to_pr_err(ret); 2196 } 2197 2198 static int nvme_pr_register(struct block_device *bdev, u64 old, 2199 u64 new, unsigned flags) 2200 { 2201 u32 cdw10; 2202 2203 if (flags & ~PR_FL_IGNORE_KEY) 2204 return -EOPNOTSUPP; 2205 2206 cdw10 = old ? 2 : 0; 2207 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0; 2208 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */ 2209 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register); 2210 } 2211 2212 static int nvme_pr_reserve(struct block_device *bdev, u64 key, 2213 enum pr_type type, unsigned flags) 2214 { 2215 u32 cdw10; 2216 2217 if (flags & ~PR_FL_IGNORE_KEY) 2218 return -EOPNOTSUPP; 2219 2220 cdw10 = nvme_pr_type(type) << 8; 2221 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0); 2222 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire); 2223 } 2224 2225 static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new, 2226 enum pr_type type, bool abort) 2227 { 2228 u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1); 2229 2230 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire); 2231 } 2232 2233 static int nvme_pr_clear(struct block_device *bdev, u64 key) 2234 { 2235 u32 cdw10 = 1 | (key ? 0 : 1 << 3); 2236 2237 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release); 2238 } 2239 2240 static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type) 2241 { 2242 u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 0 : 1 << 3); 2243 2244 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release); 2245 } 2246 2247 const struct pr_ops nvme_pr_ops = { 2248 .pr_register = nvme_pr_register, 2249 .pr_reserve = nvme_pr_reserve, 2250 .pr_release = nvme_pr_release, 2251 .pr_preempt = nvme_pr_preempt, 2252 .pr_clear = nvme_pr_clear, 2253 }; 2254 2255 #ifdef CONFIG_BLK_SED_OPAL 2256 static int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, 2257 bool send) 2258 { 2259 struct nvme_ctrl *ctrl = data; 2260 struct nvme_command cmd = { }; 2261 2262 if (send) 2263 cmd.common.opcode = nvme_admin_security_send; 2264 else 2265 cmd.common.opcode = nvme_admin_security_recv; 2266 cmd.common.nsid = 0; 2267 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8); 2268 cmd.common.cdw11 = cpu_to_le32(len); 2269 2270 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len, 2271 NVME_QID_ANY, 1, 0); 2272 } 2273 2274 static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended) 2275 { 2276 if (ctrl->oacs & NVME_CTRL_OACS_SEC_SUPP) { 2277 if (!ctrl->opal_dev) 2278 ctrl->opal_dev = init_opal_dev(ctrl, &nvme_sec_submit); 2279 else if (was_suspended) 2280 opal_unlock_from_suspend(ctrl->opal_dev); 2281 } else { 2282 free_opal_dev(ctrl->opal_dev); 2283 ctrl->opal_dev = NULL; 2284 } 2285 } 2286 #else 2287 static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended) 2288 { 2289 } 2290 #endif /* CONFIG_BLK_SED_OPAL */ 2291 2292 #ifdef CONFIG_BLK_DEV_ZONED 2293 static int nvme_report_zones(struct gendisk *disk, sector_t sector, 2294 unsigned int nr_zones, report_zones_cb cb, void *data) 2295 { 2296 return nvme_ns_report_zones(disk->private_data, sector, nr_zones, cb, 2297 data); 2298 } 2299 #else 2300 #define nvme_report_zones NULL 2301 #endif /* CONFIG_BLK_DEV_ZONED */ 2302 2303 const struct block_device_operations nvme_bdev_ops = { 2304 .owner = THIS_MODULE, 2305 .ioctl = nvme_ioctl, 2306 .compat_ioctl = blkdev_compat_ptr_ioctl, 2307 .open = nvme_open, 2308 .release = nvme_release, 2309 .getgeo = nvme_getgeo, 2310 .report_zones = nvme_report_zones, 2311 .pr_ops = &nvme_pr_ops, 2312 }; 2313 2314 static int nvme_wait_ready(struct nvme_ctrl *ctrl, u32 mask, u32 val, 2315 u32 timeout, const char *op) 2316 { 2317 unsigned long timeout_jiffies = jiffies + timeout * HZ; 2318 u32 csts; 2319 int ret; 2320 2321 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) { 2322 if (csts == ~0) 2323 return -ENODEV; 2324 if ((csts & mask) == val) 2325 break; 2326 2327 usleep_range(1000, 2000); 2328 if (fatal_signal_pending(current)) 2329 return -EINTR; 2330 if (time_after(jiffies, timeout_jiffies)) { 2331 dev_err(ctrl->device, 2332 "Device not ready; aborting %s, CSTS=0x%x\n", 2333 op, csts); 2334 return -ENODEV; 2335 } 2336 } 2337 2338 return ret; 2339 } 2340 2341 int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown) 2342 { 2343 int ret; 2344 2345 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK; 2346 if (shutdown) 2347 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL; 2348 else 2349 ctrl->ctrl_config &= ~NVME_CC_ENABLE; 2350 2351 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config); 2352 if (ret) 2353 return ret; 2354 2355 if (shutdown) { 2356 return nvme_wait_ready(ctrl, NVME_CSTS_SHST_MASK, 2357 NVME_CSTS_SHST_CMPLT, 2358 ctrl->shutdown_timeout, "shutdown"); 2359 } 2360 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) 2361 msleep(NVME_QUIRK_DELAY_AMOUNT); 2362 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, 0, 2363 (NVME_CAP_TIMEOUT(ctrl->cap) + 1) / 2, "reset"); 2364 } 2365 EXPORT_SYMBOL_GPL(nvme_disable_ctrl); 2366 2367 int nvme_enable_ctrl(struct nvme_ctrl *ctrl) 2368 { 2369 unsigned dev_page_min; 2370 u32 timeout; 2371 int ret; 2372 2373 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap); 2374 if (ret) { 2375 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret); 2376 return ret; 2377 } 2378 dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12; 2379 2380 if (NVME_CTRL_PAGE_SHIFT < dev_page_min) { 2381 dev_err(ctrl->device, 2382 "Minimum device page size %u too large for host (%u)\n", 2383 1 << dev_page_min, 1 << NVME_CTRL_PAGE_SHIFT); 2384 return -ENODEV; 2385 } 2386 2387 if (NVME_CAP_CSS(ctrl->cap) & NVME_CAP_CSS_CSI) 2388 ctrl->ctrl_config = NVME_CC_CSS_CSI; 2389 else 2390 ctrl->ctrl_config = NVME_CC_CSS_NVM; 2391 2392 if (ctrl->cap & NVME_CAP_CRMS_CRWMS) { 2393 u32 crto; 2394 2395 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CRTO, &crto); 2396 if (ret) { 2397 dev_err(ctrl->device, "Reading CRTO failed (%d)\n", 2398 ret); 2399 return ret; 2400 } 2401 2402 if (ctrl->cap & NVME_CAP_CRMS_CRIMS) { 2403 ctrl->ctrl_config |= NVME_CC_CRIME; 2404 timeout = NVME_CRTO_CRIMT(crto); 2405 } else { 2406 timeout = NVME_CRTO_CRWMT(crto); 2407 } 2408 } else { 2409 timeout = NVME_CAP_TIMEOUT(ctrl->cap); 2410 } 2411 2412 ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; 2413 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE; 2414 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; 2415 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config); 2416 if (ret) 2417 return ret; 2418 2419 /* Flush write to device (required if transport is PCI) */ 2420 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config); 2421 if (ret) 2422 return ret; 2423 2424 ctrl->ctrl_config |= NVME_CC_ENABLE; 2425 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config); 2426 if (ret) 2427 return ret; 2428 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, NVME_CSTS_RDY, 2429 (timeout + 1) / 2, "initialisation"); 2430 } 2431 EXPORT_SYMBOL_GPL(nvme_enable_ctrl); 2432 2433 static int nvme_configure_timestamp(struct nvme_ctrl *ctrl) 2434 { 2435 __le64 ts; 2436 int ret; 2437 2438 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP)) 2439 return 0; 2440 2441 ts = cpu_to_le64(ktime_to_ms(ktime_get_real())); 2442 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts), 2443 NULL); 2444 if (ret) 2445 dev_warn_once(ctrl->device, 2446 "could not set timestamp (%d)\n", ret); 2447 return ret; 2448 } 2449 2450 static int nvme_configure_host_options(struct nvme_ctrl *ctrl) 2451 { 2452 struct nvme_feat_host_behavior *host; 2453 u8 acre = 0, lbafee = 0; 2454 int ret; 2455 2456 /* Don't bother enabling the feature if retry delay is not reported */ 2457 if (ctrl->crdt[0]) 2458 acre = NVME_ENABLE_ACRE; 2459 if (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS) 2460 lbafee = NVME_ENABLE_LBAFEE; 2461 2462 if (!acre && !lbafee) 2463 return 0; 2464 2465 host = kzalloc(sizeof(*host), GFP_KERNEL); 2466 if (!host) 2467 return 0; 2468 2469 host->acre = acre; 2470 host->lbafee = lbafee; 2471 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0, 2472 host, sizeof(*host), NULL); 2473 kfree(host); 2474 return ret; 2475 } 2476 2477 /* 2478 * The function checks whether the given total (exlat + enlat) latency of 2479 * a power state allows the latter to be used as an APST transition target. 2480 * It does so by comparing the latency to the primary and secondary latency 2481 * tolerances defined by module params. If there's a match, the corresponding 2482 * timeout value is returned and the matching tolerance index (1 or 2) is 2483 * reported. 2484 */ 2485 static bool nvme_apst_get_transition_time(u64 total_latency, 2486 u64 *transition_time, unsigned *last_index) 2487 { 2488 if (total_latency <= apst_primary_latency_tol_us) { 2489 if (*last_index == 1) 2490 return false; 2491 *last_index = 1; 2492 *transition_time = apst_primary_timeout_ms; 2493 return true; 2494 } 2495 if (apst_secondary_timeout_ms && 2496 total_latency <= apst_secondary_latency_tol_us) { 2497 if (*last_index <= 2) 2498 return false; 2499 *last_index = 2; 2500 *transition_time = apst_secondary_timeout_ms; 2501 return true; 2502 } 2503 return false; 2504 } 2505 2506 /* 2507 * APST (Autonomous Power State Transition) lets us program a table of power 2508 * state transitions that the controller will perform automatically. 2509 * 2510 * Depending on module params, one of the two supported techniques will be used: 2511 * 2512 * - If the parameters provide explicit timeouts and tolerances, they will be 2513 * used to build a table with up to 2 non-operational states to transition to. 2514 * The default parameter values were selected based on the values used by 2515 * Microsoft's and Intel's NVMe drivers. Yet, since we don't implement dynamic 2516 * regeneration of the APST table in the event of switching between external 2517 * and battery power, the timeouts and tolerances reflect a compromise 2518 * between values used by Microsoft for AC and battery scenarios. 2519 * - If not, we'll configure the table with a simple heuristic: we are willing 2520 * to spend at most 2% of the time transitioning between power states. 2521 * Therefore, when running in any given state, we will enter the next 2522 * lower-power non-operational state after waiting 50 * (enlat + exlat) 2523 * microseconds, as long as that state's exit latency is under the requested 2524 * maximum latency. 2525 * 2526 * We will not autonomously enter any non-operational state for which the total 2527 * latency exceeds ps_max_latency_us. 2528 * 2529 * Users can set ps_max_latency_us to zero to turn off APST. 2530 */ 2531 static int nvme_configure_apst(struct nvme_ctrl *ctrl) 2532 { 2533 struct nvme_feat_auto_pst *table; 2534 unsigned apste = 0; 2535 u64 max_lat_us = 0; 2536 __le64 target = 0; 2537 int max_ps = -1; 2538 int state; 2539 int ret; 2540 unsigned last_lt_index = UINT_MAX; 2541 2542 /* 2543 * If APST isn't supported or if we haven't been initialized yet, 2544 * then don't do anything. 2545 */ 2546 if (!ctrl->apsta) 2547 return 0; 2548 2549 if (ctrl->npss > 31) { 2550 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n"); 2551 return 0; 2552 } 2553 2554 table = kzalloc(sizeof(*table), GFP_KERNEL); 2555 if (!table) 2556 return 0; 2557 2558 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) { 2559 /* Turn off APST. */ 2560 dev_dbg(ctrl->device, "APST disabled\n"); 2561 goto done; 2562 } 2563 2564 /* 2565 * Walk through all states from lowest- to highest-power. 2566 * According to the spec, lower-numbered states use more power. NPSS, 2567 * despite the name, is the index of the lowest-power state, not the 2568 * number of states. 2569 */ 2570 for (state = (int)ctrl->npss; state >= 0; state--) { 2571 u64 total_latency_us, exit_latency_us, transition_ms; 2572 2573 if (target) 2574 table->entries[state] = target; 2575 2576 /* 2577 * Don't allow transitions to the deepest state if it's quirked 2578 * off. 2579 */ 2580 if (state == ctrl->npss && 2581 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) 2582 continue; 2583 2584 /* 2585 * Is this state a useful non-operational state for higher-power 2586 * states to autonomously transition to? 2587 */ 2588 if (!(ctrl->psd[state].flags & NVME_PS_FLAGS_NON_OP_STATE)) 2589 continue; 2590 2591 exit_latency_us = (u64)le32_to_cpu(ctrl->psd[state].exit_lat); 2592 if (exit_latency_us > ctrl->ps_max_latency_us) 2593 continue; 2594 2595 total_latency_us = exit_latency_us + 2596 le32_to_cpu(ctrl->psd[state].entry_lat); 2597 2598 /* 2599 * This state is good. It can be used as the APST idle target 2600 * for higher power states. 2601 */ 2602 if (apst_primary_timeout_ms && apst_primary_latency_tol_us) { 2603 if (!nvme_apst_get_transition_time(total_latency_us, 2604 &transition_ms, &last_lt_index)) 2605 continue; 2606 } else { 2607 transition_ms = total_latency_us + 19; 2608 do_div(transition_ms, 20); 2609 if (transition_ms > (1 << 24) - 1) 2610 transition_ms = (1 << 24) - 1; 2611 } 2612 2613 target = cpu_to_le64((state << 3) | (transition_ms << 8)); 2614 if (max_ps == -1) 2615 max_ps = state; 2616 if (total_latency_us > max_lat_us) 2617 max_lat_us = total_latency_us; 2618 } 2619 2620 if (max_ps == -1) 2621 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n"); 2622 else 2623 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n", 2624 max_ps, max_lat_us, (int)sizeof(*table), table); 2625 apste = 1; 2626 2627 done: 2628 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste, 2629 table, sizeof(*table), NULL); 2630 if (ret) 2631 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret); 2632 kfree(table); 2633 return ret; 2634 } 2635 2636 static void nvme_set_latency_tolerance(struct device *dev, s32 val) 2637 { 2638 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); 2639 u64 latency; 2640 2641 switch (val) { 2642 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT: 2643 case PM_QOS_LATENCY_ANY: 2644 latency = U64_MAX; 2645 break; 2646 2647 default: 2648 latency = val; 2649 } 2650 2651 if (ctrl->ps_max_latency_us != latency) { 2652 ctrl->ps_max_latency_us = latency; 2653 if (ctrl->state == NVME_CTRL_LIVE) 2654 nvme_configure_apst(ctrl); 2655 } 2656 } 2657 2658 struct nvme_core_quirk_entry { 2659 /* 2660 * NVMe model and firmware strings are padded with spaces. For 2661 * simplicity, strings in the quirk table are padded with NULLs 2662 * instead. 2663 */ 2664 u16 vid; 2665 const char *mn; 2666 const char *fr; 2667 unsigned long quirks; 2668 }; 2669 2670 static const struct nvme_core_quirk_entry core_quirks[] = { 2671 { 2672 /* 2673 * This Toshiba device seems to die using any APST states. See: 2674 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11 2675 */ 2676 .vid = 0x1179, 2677 .mn = "THNSF5256GPUK TOSHIBA", 2678 .quirks = NVME_QUIRK_NO_APST, 2679 }, 2680 { 2681 /* 2682 * This LiteON CL1-3D*-Q11 firmware version has a race 2683 * condition associated with actions related to suspend to idle 2684 * LiteON has resolved the problem in future firmware 2685 */ 2686 .vid = 0x14a4, 2687 .fr = "22301111", 2688 .quirks = NVME_QUIRK_SIMPLE_SUSPEND, 2689 }, 2690 { 2691 /* 2692 * This Kioxia CD6-V Series / HPE PE8030 device times out and 2693 * aborts I/O during any load, but more easily reproducible 2694 * with discards (fstrim). 2695 * 2696 * The device is left in a state where it is also not possible 2697 * to use "nvme set-feature" to disable APST, but booting with 2698 * nvme_core.default_ps_max_latency=0 works. 2699 */ 2700 .vid = 0x1e0f, 2701 .mn = "KCD6XVUL6T40", 2702 .quirks = NVME_QUIRK_NO_APST, 2703 }, 2704 { 2705 /* 2706 * The external Samsung X5 SSD fails initialization without a 2707 * delay before checking if it is ready and has a whole set of 2708 * other problems. To make this even more interesting, it 2709 * shares the PCI ID with internal Samsung 970 Evo Plus that 2710 * does not need or want these quirks. 2711 */ 2712 .vid = 0x144d, 2713 .mn = "Samsung Portable SSD X5", 2714 .quirks = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 2715 NVME_QUIRK_NO_DEEPEST_PS | 2716 NVME_QUIRK_IGNORE_DEV_SUBNQN, 2717 } 2718 }; 2719 2720 /* match is null-terminated but idstr is space-padded. */ 2721 static bool string_matches(const char *idstr, const char *match, size_t len) 2722 { 2723 size_t matchlen; 2724 2725 if (!match) 2726 return true; 2727 2728 matchlen = strlen(match); 2729 WARN_ON_ONCE(matchlen > len); 2730 2731 if (memcmp(idstr, match, matchlen)) 2732 return false; 2733 2734 for (; matchlen < len; matchlen++) 2735 if (idstr[matchlen] != ' ') 2736 return false; 2737 2738 return true; 2739 } 2740 2741 static bool quirk_matches(const struct nvme_id_ctrl *id, 2742 const struct nvme_core_quirk_entry *q) 2743 { 2744 return q->vid == le16_to_cpu(id->vid) && 2745 string_matches(id->mn, q->mn, sizeof(id->mn)) && 2746 string_matches(id->fr, q->fr, sizeof(id->fr)); 2747 } 2748 2749 static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl, 2750 struct nvme_id_ctrl *id) 2751 { 2752 size_t nqnlen; 2753 int off; 2754 2755 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) { 2756 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE); 2757 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) { 2758 strscpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE); 2759 return; 2760 } 2761 2762 if (ctrl->vs >= NVME_VS(1, 2, 1)) 2763 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n"); 2764 } 2765 2766 /* 2767 * Generate a "fake" NQN similar to the one in Section 4.5 of the NVMe 2768 * Base Specification 2.0. It is slightly different from the format 2769 * specified there due to historic reasons, and we can't change it now. 2770 */ 2771 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE, 2772 "nqn.2014.08.org.nvmexpress:%04x%04x", 2773 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid)); 2774 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn)); 2775 off += sizeof(id->sn); 2776 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn)); 2777 off += sizeof(id->mn); 2778 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off); 2779 } 2780 2781 static void nvme_release_subsystem(struct device *dev) 2782 { 2783 struct nvme_subsystem *subsys = 2784 container_of(dev, struct nvme_subsystem, dev); 2785 2786 if (subsys->instance >= 0) 2787 ida_free(&nvme_instance_ida, subsys->instance); 2788 kfree(subsys); 2789 } 2790 2791 static void nvme_destroy_subsystem(struct kref *ref) 2792 { 2793 struct nvme_subsystem *subsys = 2794 container_of(ref, struct nvme_subsystem, ref); 2795 2796 mutex_lock(&nvme_subsystems_lock); 2797 list_del(&subsys->entry); 2798 mutex_unlock(&nvme_subsystems_lock); 2799 2800 ida_destroy(&subsys->ns_ida); 2801 device_del(&subsys->dev); 2802 put_device(&subsys->dev); 2803 } 2804 2805 static void nvme_put_subsystem(struct nvme_subsystem *subsys) 2806 { 2807 kref_put(&subsys->ref, nvme_destroy_subsystem); 2808 } 2809 2810 static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn) 2811 { 2812 struct nvme_subsystem *subsys; 2813 2814 lockdep_assert_held(&nvme_subsystems_lock); 2815 2816 /* 2817 * Fail matches for discovery subsystems. This results 2818 * in each discovery controller bound to a unique subsystem. 2819 * This avoids issues with validating controller values 2820 * that can only be true when there is a single unique subsystem. 2821 * There may be multiple and completely independent entities 2822 * that provide discovery controllers. 2823 */ 2824 if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME)) 2825 return NULL; 2826 2827 list_for_each_entry(subsys, &nvme_subsystems, entry) { 2828 if (strcmp(subsys->subnqn, subsysnqn)) 2829 continue; 2830 if (!kref_get_unless_zero(&subsys->ref)) 2831 continue; 2832 return subsys; 2833 } 2834 2835 return NULL; 2836 } 2837 2838 static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl) 2839 { 2840 return ctrl->opts && ctrl->opts->discovery_nqn; 2841 } 2842 2843 static bool nvme_validate_cntlid(struct nvme_subsystem *subsys, 2844 struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) 2845 { 2846 struct nvme_ctrl *tmp; 2847 2848 lockdep_assert_held(&nvme_subsystems_lock); 2849 2850 list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) { 2851 if (nvme_state_terminal(tmp)) 2852 continue; 2853 2854 if (tmp->cntlid == ctrl->cntlid) { 2855 dev_err(ctrl->device, 2856 "Duplicate cntlid %u with %s, subsys %s, rejecting\n", 2857 ctrl->cntlid, dev_name(tmp->device), 2858 subsys->subnqn); 2859 return false; 2860 } 2861 2862 if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) || 2863 nvme_discovery_ctrl(ctrl)) 2864 continue; 2865 2866 dev_err(ctrl->device, 2867 "Subsystem does not support multiple controllers\n"); 2868 return false; 2869 } 2870 2871 return true; 2872 } 2873 2874 static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) 2875 { 2876 struct nvme_subsystem *subsys, *found; 2877 int ret; 2878 2879 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL); 2880 if (!subsys) 2881 return -ENOMEM; 2882 2883 subsys->instance = -1; 2884 mutex_init(&subsys->lock); 2885 kref_init(&subsys->ref); 2886 INIT_LIST_HEAD(&subsys->ctrls); 2887 INIT_LIST_HEAD(&subsys->nsheads); 2888 nvme_init_subnqn(subsys, ctrl, id); 2889 memcpy(subsys->serial, id->sn, sizeof(subsys->serial)); 2890 memcpy(subsys->model, id->mn, sizeof(subsys->model)); 2891 subsys->vendor_id = le16_to_cpu(id->vid); 2892 subsys->cmic = id->cmic; 2893 2894 /* Versions prior to 1.4 don't necessarily report a valid type */ 2895 if (id->cntrltype == NVME_CTRL_DISC || 2896 !strcmp(subsys->subnqn, NVME_DISC_SUBSYS_NAME)) 2897 subsys->subtype = NVME_NQN_DISC; 2898 else 2899 subsys->subtype = NVME_NQN_NVME; 2900 2901 if (nvme_discovery_ctrl(ctrl) && subsys->subtype != NVME_NQN_DISC) { 2902 dev_err(ctrl->device, 2903 "Subsystem %s is not a discovery controller", 2904 subsys->subnqn); 2905 kfree(subsys); 2906 return -EINVAL; 2907 } 2908 subsys->awupf = le16_to_cpu(id->awupf); 2909 nvme_mpath_default_iopolicy(subsys); 2910 2911 subsys->dev.class = nvme_subsys_class; 2912 subsys->dev.release = nvme_release_subsystem; 2913 subsys->dev.groups = nvme_subsys_attrs_groups; 2914 dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance); 2915 device_initialize(&subsys->dev); 2916 2917 mutex_lock(&nvme_subsystems_lock); 2918 found = __nvme_find_get_subsystem(subsys->subnqn); 2919 if (found) { 2920 put_device(&subsys->dev); 2921 subsys = found; 2922 2923 if (!nvme_validate_cntlid(subsys, ctrl, id)) { 2924 ret = -EINVAL; 2925 goto out_put_subsystem; 2926 } 2927 } else { 2928 ret = device_add(&subsys->dev); 2929 if (ret) { 2930 dev_err(ctrl->device, 2931 "failed to register subsystem device.\n"); 2932 put_device(&subsys->dev); 2933 goto out_unlock; 2934 } 2935 ida_init(&subsys->ns_ida); 2936 list_add_tail(&subsys->entry, &nvme_subsystems); 2937 } 2938 2939 ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj, 2940 dev_name(ctrl->device)); 2941 if (ret) { 2942 dev_err(ctrl->device, 2943 "failed to create sysfs link from subsystem.\n"); 2944 goto out_put_subsystem; 2945 } 2946 2947 if (!found) 2948 subsys->instance = ctrl->instance; 2949 ctrl->subsys = subsys; 2950 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls); 2951 mutex_unlock(&nvme_subsystems_lock); 2952 return 0; 2953 2954 out_put_subsystem: 2955 nvme_put_subsystem(subsys); 2956 out_unlock: 2957 mutex_unlock(&nvme_subsystems_lock); 2958 return ret; 2959 } 2960 2961 int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, 2962 void *log, size_t size, u64 offset) 2963 { 2964 struct nvme_command c = { }; 2965 u32 dwlen = nvme_bytes_to_numd(size); 2966 2967 c.get_log_page.opcode = nvme_admin_get_log_page; 2968 c.get_log_page.nsid = cpu_to_le32(nsid); 2969 c.get_log_page.lid = log_page; 2970 c.get_log_page.lsp = lsp; 2971 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1)); 2972 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16); 2973 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset)); 2974 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset)); 2975 c.get_log_page.csi = csi; 2976 2977 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size); 2978 } 2979 2980 static int nvme_get_effects_log(struct nvme_ctrl *ctrl, u8 csi, 2981 struct nvme_effects_log **log) 2982 { 2983 struct nvme_effects_log *cel = xa_load(&ctrl->cels, csi); 2984 int ret; 2985 2986 if (cel) 2987 goto out; 2988 2989 cel = kzalloc(sizeof(*cel), GFP_KERNEL); 2990 if (!cel) 2991 return -ENOMEM; 2992 2993 ret = nvme_get_log(ctrl, 0x00, NVME_LOG_CMD_EFFECTS, 0, csi, 2994 cel, sizeof(*cel), 0); 2995 if (ret) { 2996 kfree(cel); 2997 return ret; 2998 } 2999 3000 xa_store(&ctrl->cels, csi, cel, GFP_KERNEL); 3001 out: 3002 *log = cel; 3003 return 0; 3004 } 3005 3006 static inline u32 nvme_mps_to_sectors(struct nvme_ctrl *ctrl, u32 units) 3007 { 3008 u32 page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12, val; 3009 3010 if (check_shl_overflow(1U, units + page_shift - 9, &val)) 3011 return UINT_MAX; 3012 return val; 3013 } 3014 3015 static int nvme_init_non_mdts_limits(struct nvme_ctrl *ctrl) 3016 { 3017 struct nvme_command c = { }; 3018 struct nvme_id_ctrl_nvm *id; 3019 int ret; 3020 3021 if (ctrl->oncs & NVME_CTRL_ONCS_DSM) { 3022 ctrl->max_discard_sectors = UINT_MAX; 3023 ctrl->max_discard_segments = NVME_DSM_MAX_RANGES; 3024 } else { 3025 ctrl->max_discard_sectors = 0; 3026 ctrl->max_discard_segments = 0; 3027 } 3028 3029 /* 3030 * Even though NVMe spec explicitly states that MDTS is not applicable 3031 * to the write-zeroes, we are cautious and limit the size to the 3032 * controllers max_hw_sectors value, which is based on the MDTS field 3033 * and possibly other limiting factors. 3034 */ 3035 if ((ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) && 3036 !(ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES)) 3037 ctrl->max_zeroes_sectors = ctrl->max_hw_sectors; 3038 else 3039 ctrl->max_zeroes_sectors = 0; 3040 3041 if (ctrl->subsys->subtype != NVME_NQN_NVME || 3042 nvme_ctrl_limited_cns(ctrl) || 3043 test_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags)) 3044 return 0; 3045 3046 id = kzalloc(sizeof(*id), GFP_KERNEL); 3047 if (!id) 3048 return -ENOMEM; 3049 3050 c.identify.opcode = nvme_admin_identify; 3051 c.identify.cns = NVME_ID_CNS_CS_CTRL; 3052 c.identify.csi = NVME_CSI_NVM; 3053 3054 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id)); 3055 if (ret) 3056 goto free_data; 3057 3058 if (id->dmrl) 3059 ctrl->max_discard_segments = id->dmrl; 3060 ctrl->dmrsl = le32_to_cpu(id->dmrsl); 3061 if (id->wzsl) 3062 ctrl->max_zeroes_sectors = nvme_mps_to_sectors(ctrl, id->wzsl); 3063 3064 free_data: 3065 if (ret > 0) 3066 set_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags); 3067 kfree(id); 3068 return ret; 3069 } 3070 3071 static void nvme_init_known_nvm_effects(struct nvme_ctrl *ctrl) 3072 { 3073 struct nvme_effects_log *log = ctrl->effects; 3074 3075 log->acs[nvme_admin_format_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC | 3076 NVME_CMD_EFFECTS_NCC | 3077 NVME_CMD_EFFECTS_CSE_MASK); 3078 log->acs[nvme_admin_sanitize_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC | 3079 NVME_CMD_EFFECTS_CSE_MASK); 3080 3081 /* 3082 * The spec says the result of a security receive command depends on 3083 * the previous security send command. As such, many vendors log this 3084 * command as one to submitted only when no other commands to the same 3085 * namespace are outstanding. The intention is to tell the host to 3086 * prevent mixing security send and receive. 3087 * 3088 * This driver can only enforce such exclusive access against IO 3089 * queues, though. We are not readily able to enforce such a rule for 3090 * two commands to the admin queue, which is the only queue that 3091 * matters for this command. 3092 * 3093 * Rather than blindly freezing the IO queues for this effect that 3094 * doesn't even apply to IO, mask it off. 3095 */ 3096 log->acs[nvme_admin_security_recv] &= cpu_to_le32(~NVME_CMD_EFFECTS_CSE_MASK); 3097 3098 log->iocs[nvme_cmd_write] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC); 3099 log->iocs[nvme_cmd_write_zeroes] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC); 3100 log->iocs[nvme_cmd_write_uncor] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC); 3101 } 3102 3103 static int nvme_init_effects(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) 3104 { 3105 int ret = 0; 3106 3107 if (ctrl->effects) 3108 return 0; 3109 3110 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) { 3111 ret = nvme_get_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects); 3112 if (ret < 0) 3113 return ret; 3114 } 3115 3116 if (!ctrl->effects) { 3117 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL); 3118 if (!ctrl->effects) 3119 return -ENOMEM; 3120 xa_store(&ctrl->cels, NVME_CSI_NVM, ctrl->effects, GFP_KERNEL); 3121 } 3122 3123 nvme_init_known_nvm_effects(ctrl); 3124 return 0; 3125 } 3126 3127 static int nvme_init_identify(struct nvme_ctrl *ctrl) 3128 { 3129 struct nvme_id_ctrl *id; 3130 u32 max_hw_sectors; 3131 bool prev_apst_enabled; 3132 int ret; 3133 3134 ret = nvme_identify_ctrl(ctrl, &id); 3135 if (ret) { 3136 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret); 3137 return -EIO; 3138 } 3139 3140 if (!(ctrl->ops->flags & NVME_F_FABRICS)) 3141 ctrl->cntlid = le16_to_cpu(id->cntlid); 3142 3143 if (!ctrl->identified) { 3144 unsigned int i; 3145 3146 /* 3147 * Check for quirks. Quirk can depend on firmware version, 3148 * so, in principle, the set of quirks present can change 3149 * across a reset. As a possible future enhancement, we 3150 * could re-scan for quirks every time we reinitialize 3151 * the device, but we'd have to make sure that the driver 3152 * behaves intelligently if the quirks change. 3153 */ 3154 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) { 3155 if (quirk_matches(id, &core_quirks[i])) 3156 ctrl->quirks |= core_quirks[i].quirks; 3157 } 3158 3159 ret = nvme_init_subsystem(ctrl, id); 3160 if (ret) 3161 goto out_free; 3162 3163 ret = nvme_init_effects(ctrl, id); 3164 if (ret) 3165 goto out_free; 3166 } 3167 memcpy(ctrl->subsys->firmware_rev, id->fr, 3168 sizeof(ctrl->subsys->firmware_rev)); 3169 3170 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) { 3171 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n"); 3172 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS; 3173 } 3174 3175 ctrl->crdt[0] = le16_to_cpu(id->crdt1); 3176 ctrl->crdt[1] = le16_to_cpu(id->crdt2); 3177 ctrl->crdt[2] = le16_to_cpu(id->crdt3); 3178 3179 ctrl->oacs = le16_to_cpu(id->oacs); 3180 ctrl->oncs = le16_to_cpu(id->oncs); 3181 ctrl->mtfa = le16_to_cpu(id->mtfa); 3182 ctrl->oaes = le32_to_cpu(id->oaes); 3183 ctrl->wctemp = le16_to_cpu(id->wctemp); 3184 ctrl->cctemp = le16_to_cpu(id->cctemp); 3185 3186 atomic_set(&ctrl->abort_limit, id->acl + 1); 3187 ctrl->vwc = id->vwc; 3188 if (id->mdts) 3189 max_hw_sectors = nvme_mps_to_sectors(ctrl, id->mdts); 3190 else 3191 max_hw_sectors = UINT_MAX; 3192 ctrl->max_hw_sectors = 3193 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors); 3194 3195 nvme_set_queue_limits(ctrl, ctrl->admin_q); 3196 ctrl->sgls = le32_to_cpu(id->sgls); 3197 ctrl->kas = le16_to_cpu(id->kas); 3198 ctrl->max_namespaces = le32_to_cpu(id->mnan); 3199 ctrl->ctratt = le32_to_cpu(id->ctratt); 3200 3201 ctrl->cntrltype = id->cntrltype; 3202 ctrl->dctype = id->dctype; 3203 3204 if (id->rtd3e) { 3205 /* us -> s */ 3206 u32 transition_time = le32_to_cpu(id->rtd3e) / USEC_PER_SEC; 3207 3208 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time, 3209 shutdown_timeout, 60); 3210 3211 if (ctrl->shutdown_timeout != shutdown_timeout) 3212 dev_info(ctrl->device, 3213 "Shutdown timeout set to %u seconds\n", 3214 ctrl->shutdown_timeout); 3215 } else 3216 ctrl->shutdown_timeout = shutdown_timeout; 3217 3218 ctrl->npss = id->npss; 3219 ctrl->apsta = id->apsta; 3220 prev_apst_enabled = ctrl->apst_enabled; 3221 if (ctrl->quirks & NVME_QUIRK_NO_APST) { 3222 if (force_apst && id->apsta) { 3223 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n"); 3224 ctrl->apst_enabled = true; 3225 } else { 3226 ctrl->apst_enabled = false; 3227 } 3228 } else { 3229 ctrl->apst_enabled = id->apsta; 3230 } 3231 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd)); 3232 3233 if (ctrl->ops->flags & NVME_F_FABRICS) { 3234 ctrl->icdoff = le16_to_cpu(id->icdoff); 3235 ctrl->ioccsz = le32_to_cpu(id->ioccsz); 3236 ctrl->iorcsz = le32_to_cpu(id->iorcsz); 3237 ctrl->maxcmd = le16_to_cpu(id->maxcmd); 3238 3239 /* 3240 * In fabrics we need to verify the cntlid matches the 3241 * admin connect 3242 */ 3243 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) { 3244 dev_err(ctrl->device, 3245 "Mismatching cntlid: Connect %u vs Identify " 3246 "%u, rejecting\n", 3247 ctrl->cntlid, le16_to_cpu(id->cntlid)); 3248 ret = -EINVAL; 3249 goto out_free; 3250 } 3251 3252 if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) { 3253 dev_err(ctrl->device, 3254 "keep-alive support is mandatory for fabrics\n"); 3255 ret = -EINVAL; 3256 goto out_free; 3257 } 3258 } else { 3259 ctrl->hmpre = le32_to_cpu(id->hmpre); 3260 ctrl->hmmin = le32_to_cpu(id->hmmin); 3261 ctrl->hmminds = le32_to_cpu(id->hmminds); 3262 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd); 3263 } 3264 3265 ret = nvme_mpath_init_identify(ctrl, id); 3266 if (ret < 0) 3267 goto out_free; 3268 3269 if (ctrl->apst_enabled && !prev_apst_enabled) 3270 dev_pm_qos_expose_latency_tolerance(ctrl->device); 3271 else if (!ctrl->apst_enabled && prev_apst_enabled) 3272 dev_pm_qos_hide_latency_tolerance(ctrl->device); 3273 3274 out_free: 3275 kfree(id); 3276 return ret; 3277 } 3278 3279 /* 3280 * Initialize the cached copies of the Identify data and various controller 3281 * register in our nvme_ctrl structure. This should be called as soon as 3282 * the admin queue is fully up and running. 3283 */ 3284 int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended) 3285 { 3286 int ret; 3287 3288 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs); 3289 if (ret) { 3290 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret); 3291 return ret; 3292 } 3293 3294 ctrl->sqsize = min_t(u16, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize); 3295 3296 if (ctrl->vs >= NVME_VS(1, 1, 0)) 3297 ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap); 3298 3299 ret = nvme_init_identify(ctrl); 3300 if (ret) 3301 return ret; 3302 3303 ret = nvme_configure_apst(ctrl); 3304 if (ret < 0) 3305 return ret; 3306 3307 ret = nvme_configure_timestamp(ctrl); 3308 if (ret < 0) 3309 return ret; 3310 3311 ret = nvme_configure_host_options(ctrl); 3312 if (ret < 0) 3313 return ret; 3314 3315 nvme_configure_opal(ctrl, was_suspended); 3316 3317 if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) { 3318 /* 3319 * Do not return errors unless we are in a controller reset, 3320 * the controller works perfectly fine without hwmon. 3321 */ 3322 ret = nvme_hwmon_init(ctrl); 3323 if (ret == -EINTR) 3324 return ret; 3325 } 3326 3327 ctrl->identified = true; 3328 3329 return 0; 3330 } 3331 EXPORT_SYMBOL_GPL(nvme_init_ctrl_finish); 3332 3333 static int nvme_dev_open(struct inode *inode, struct file *file) 3334 { 3335 struct nvme_ctrl *ctrl = 3336 container_of(inode->i_cdev, struct nvme_ctrl, cdev); 3337 3338 switch (ctrl->state) { 3339 case NVME_CTRL_LIVE: 3340 break; 3341 default: 3342 return -EWOULDBLOCK; 3343 } 3344 3345 nvme_get_ctrl(ctrl); 3346 if (!try_module_get(ctrl->ops->module)) { 3347 nvme_put_ctrl(ctrl); 3348 return -EINVAL; 3349 } 3350 3351 file->private_data = ctrl; 3352 return 0; 3353 } 3354 3355 static int nvme_dev_release(struct inode *inode, struct file *file) 3356 { 3357 struct nvme_ctrl *ctrl = 3358 container_of(inode->i_cdev, struct nvme_ctrl, cdev); 3359 3360 module_put(ctrl->ops->module); 3361 nvme_put_ctrl(ctrl); 3362 return 0; 3363 } 3364 3365 static const struct file_operations nvme_dev_fops = { 3366 .owner = THIS_MODULE, 3367 .open = nvme_dev_open, 3368 .release = nvme_dev_release, 3369 .unlocked_ioctl = nvme_dev_ioctl, 3370 .compat_ioctl = compat_ptr_ioctl, 3371 .uring_cmd = nvme_dev_uring_cmd, 3372 }; 3373 3374 static struct nvme_ns_head *nvme_find_ns_head(struct nvme_ctrl *ctrl, 3375 unsigned nsid) 3376 { 3377 struct nvme_ns_head *h; 3378 3379 lockdep_assert_held(&ctrl->subsys->lock); 3380 3381 list_for_each_entry(h, &ctrl->subsys->nsheads, entry) { 3382 /* 3383 * Private namespaces can share NSIDs under some conditions. 3384 * In that case we can't use the same ns_head for namespaces 3385 * with the same NSID. 3386 */ 3387 if (h->ns_id != nsid || !nvme_is_unique_nsid(ctrl, h)) 3388 continue; 3389 if (!list_empty(&h->list) && nvme_tryget_ns_head(h)) 3390 return h; 3391 } 3392 3393 return NULL; 3394 } 3395 3396 static int nvme_subsys_check_duplicate_ids(struct nvme_subsystem *subsys, 3397 struct nvme_ns_ids *ids) 3398 { 3399 bool has_uuid = !uuid_is_null(&ids->uuid); 3400 bool has_nguid = memchr_inv(ids->nguid, 0, sizeof(ids->nguid)); 3401 bool has_eui64 = memchr_inv(ids->eui64, 0, sizeof(ids->eui64)); 3402 struct nvme_ns_head *h; 3403 3404 lockdep_assert_held(&subsys->lock); 3405 3406 list_for_each_entry(h, &subsys->nsheads, entry) { 3407 if (has_uuid && uuid_equal(&ids->uuid, &h->ids.uuid)) 3408 return -EINVAL; 3409 if (has_nguid && 3410 memcmp(&ids->nguid, &h->ids.nguid, sizeof(ids->nguid)) == 0) 3411 return -EINVAL; 3412 if (has_eui64 && 3413 memcmp(&ids->eui64, &h->ids.eui64, sizeof(ids->eui64)) == 0) 3414 return -EINVAL; 3415 } 3416 3417 return 0; 3418 } 3419 3420 static void nvme_cdev_rel(struct device *dev) 3421 { 3422 ida_free(&nvme_ns_chr_minor_ida, MINOR(dev->devt)); 3423 } 3424 3425 void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device) 3426 { 3427 cdev_device_del(cdev, cdev_device); 3428 put_device(cdev_device); 3429 } 3430 3431 int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device, 3432 const struct file_operations *fops, struct module *owner) 3433 { 3434 int minor, ret; 3435 3436 minor = ida_alloc(&nvme_ns_chr_minor_ida, GFP_KERNEL); 3437 if (minor < 0) 3438 return minor; 3439 cdev_device->devt = MKDEV(MAJOR(nvme_ns_chr_devt), minor); 3440 cdev_device->class = nvme_ns_chr_class; 3441 cdev_device->release = nvme_cdev_rel; 3442 device_initialize(cdev_device); 3443 cdev_init(cdev, fops); 3444 cdev->owner = owner; 3445 ret = cdev_device_add(cdev, cdev_device); 3446 if (ret) 3447 put_device(cdev_device); 3448 3449 return ret; 3450 } 3451 3452 static int nvme_ns_chr_open(struct inode *inode, struct file *file) 3453 { 3454 return nvme_ns_open(container_of(inode->i_cdev, struct nvme_ns, cdev)); 3455 } 3456 3457 static int nvme_ns_chr_release(struct inode *inode, struct file *file) 3458 { 3459 nvme_ns_release(container_of(inode->i_cdev, struct nvme_ns, cdev)); 3460 return 0; 3461 } 3462 3463 static const struct file_operations nvme_ns_chr_fops = { 3464 .owner = THIS_MODULE, 3465 .open = nvme_ns_chr_open, 3466 .release = nvme_ns_chr_release, 3467 .unlocked_ioctl = nvme_ns_chr_ioctl, 3468 .compat_ioctl = compat_ptr_ioctl, 3469 .uring_cmd = nvme_ns_chr_uring_cmd, 3470 .uring_cmd_iopoll = nvme_ns_chr_uring_cmd_iopoll, 3471 }; 3472 3473 static int nvme_add_ns_cdev(struct nvme_ns *ns) 3474 { 3475 int ret; 3476 3477 ns->cdev_device.parent = ns->ctrl->device; 3478 ret = dev_set_name(&ns->cdev_device, "ng%dn%d", 3479 ns->ctrl->instance, ns->head->instance); 3480 if (ret) 3481 return ret; 3482 3483 return nvme_cdev_add(&ns->cdev, &ns->cdev_device, &nvme_ns_chr_fops, 3484 ns->ctrl->ops->module); 3485 } 3486 3487 static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl, 3488 struct nvme_ns_info *info) 3489 { 3490 struct nvme_ns_head *head; 3491 size_t size = sizeof(*head); 3492 int ret = -ENOMEM; 3493 3494 #ifdef CONFIG_NVME_MULTIPATH 3495 size += num_possible_nodes() * sizeof(struct nvme_ns *); 3496 #endif 3497 3498 head = kzalloc(size, GFP_KERNEL); 3499 if (!head) 3500 goto out; 3501 ret = ida_alloc_min(&ctrl->subsys->ns_ida, 1, GFP_KERNEL); 3502 if (ret < 0) 3503 goto out_free_head; 3504 head->instance = ret; 3505 INIT_LIST_HEAD(&head->list); 3506 ret = init_srcu_struct(&head->srcu); 3507 if (ret) 3508 goto out_ida_remove; 3509 head->subsys = ctrl->subsys; 3510 head->ns_id = info->nsid; 3511 head->ids = info->ids; 3512 head->shared = info->is_shared; 3513 kref_init(&head->ref); 3514 3515 if (head->ids.csi) { 3516 ret = nvme_get_effects_log(ctrl, head->ids.csi, &head->effects); 3517 if (ret) 3518 goto out_cleanup_srcu; 3519 } else 3520 head->effects = ctrl->effects; 3521 3522 ret = nvme_mpath_alloc_disk(ctrl, head); 3523 if (ret) 3524 goto out_cleanup_srcu; 3525 3526 list_add_tail(&head->entry, &ctrl->subsys->nsheads); 3527 3528 kref_get(&ctrl->subsys->ref); 3529 3530 return head; 3531 out_cleanup_srcu: 3532 cleanup_srcu_struct(&head->srcu); 3533 out_ida_remove: 3534 ida_free(&ctrl->subsys->ns_ida, head->instance); 3535 out_free_head: 3536 kfree(head); 3537 out: 3538 if (ret > 0) 3539 ret = blk_status_to_errno(nvme_error_status(ret)); 3540 return ERR_PTR(ret); 3541 } 3542 3543 static int nvme_global_check_duplicate_ids(struct nvme_subsystem *this, 3544 struct nvme_ns_ids *ids) 3545 { 3546 struct nvme_subsystem *s; 3547 int ret = 0; 3548 3549 /* 3550 * Note that this check is racy as we try to avoid holding the global 3551 * lock over the whole ns_head creation. But it is only intended as 3552 * a sanity check anyway. 3553 */ 3554 mutex_lock(&nvme_subsystems_lock); 3555 list_for_each_entry(s, &nvme_subsystems, entry) { 3556 if (s == this) 3557 continue; 3558 mutex_lock(&s->lock); 3559 ret = nvme_subsys_check_duplicate_ids(s, ids); 3560 mutex_unlock(&s->lock); 3561 if (ret) 3562 break; 3563 } 3564 mutex_unlock(&nvme_subsystems_lock); 3565 3566 return ret; 3567 } 3568 3569 static int nvme_init_ns_head(struct nvme_ns *ns, struct nvme_ns_info *info) 3570 { 3571 struct nvme_ctrl *ctrl = ns->ctrl; 3572 struct nvme_ns_head *head = NULL; 3573 int ret; 3574 3575 ret = nvme_global_check_duplicate_ids(ctrl->subsys, &info->ids); 3576 if (ret) { 3577 dev_err(ctrl->device, 3578 "globally duplicate IDs for nsid %d\n", info->nsid); 3579 nvme_print_device_info(ctrl); 3580 return ret; 3581 } 3582 3583 mutex_lock(&ctrl->subsys->lock); 3584 head = nvme_find_ns_head(ctrl, info->nsid); 3585 if (!head) { 3586 ret = nvme_subsys_check_duplicate_ids(ctrl->subsys, &info->ids); 3587 if (ret) { 3588 dev_err(ctrl->device, 3589 "duplicate IDs in subsystem for nsid %d\n", 3590 info->nsid); 3591 goto out_unlock; 3592 } 3593 head = nvme_alloc_ns_head(ctrl, info); 3594 if (IS_ERR(head)) { 3595 ret = PTR_ERR(head); 3596 goto out_unlock; 3597 } 3598 } else { 3599 ret = -EINVAL; 3600 if (!info->is_shared || !head->shared) { 3601 dev_err(ctrl->device, 3602 "Duplicate unshared namespace %d\n", 3603 info->nsid); 3604 goto out_put_ns_head; 3605 } 3606 if (!nvme_ns_ids_equal(&head->ids, &info->ids)) { 3607 dev_err(ctrl->device, 3608 "IDs don't match for shared namespace %d\n", 3609 info->nsid); 3610 goto out_put_ns_head; 3611 } 3612 3613 if (!multipath) { 3614 dev_warn(ctrl->device, 3615 "Found shared namespace %d, but multipathing not supported.\n", 3616 info->nsid); 3617 dev_warn_once(ctrl->device, 3618 "Support for shared namespaces without CONFIG_NVME_MULTIPATH is deprecated and will be removed in Linux 6.0\n."); 3619 } 3620 } 3621 3622 list_add_tail_rcu(&ns->siblings, &head->list); 3623 ns->head = head; 3624 mutex_unlock(&ctrl->subsys->lock); 3625 return 0; 3626 3627 out_put_ns_head: 3628 nvme_put_ns_head(head); 3629 out_unlock: 3630 mutex_unlock(&ctrl->subsys->lock); 3631 return ret; 3632 } 3633 3634 struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid) 3635 { 3636 struct nvme_ns *ns, *ret = NULL; 3637 3638 down_read(&ctrl->namespaces_rwsem); 3639 list_for_each_entry(ns, &ctrl->namespaces, list) { 3640 if (ns->head->ns_id == nsid) { 3641 if (!nvme_get_ns(ns)) 3642 continue; 3643 ret = ns; 3644 break; 3645 } 3646 if (ns->head->ns_id > nsid) 3647 break; 3648 } 3649 up_read(&ctrl->namespaces_rwsem); 3650 return ret; 3651 } 3652 EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, NVME_TARGET_PASSTHRU); 3653 3654 /* 3655 * Add the namespace to the controller list while keeping the list ordered. 3656 */ 3657 static void nvme_ns_add_to_ctrl_list(struct nvme_ns *ns) 3658 { 3659 struct nvme_ns *tmp; 3660 3661 list_for_each_entry_reverse(tmp, &ns->ctrl->namespaces, list) { 3662 if (tmp->head->ns_id < ns->head->ns_id) { 3663 list_add(&ns->list, &tmp->list); 3664 return; 3665 } 3666 } 3667 list_add(&ns->list, &ns->ctrl->namespaces); 3668 } 3669 3670 static void nvme_alloc_ns(struct nvme_ctrl *ctrl, struct nvme_ns_info *info) 3671 { 3672 struct nvme_ns *ns; 3673 struct gendisk *disk; 3674 int node = ctrl->numa_node; 3675 3676 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node); 3677 if (!ns) 3678 return; 3679 3680 disk = blk_mq_alloc_disk(ctrl->tagset, ns); 3681 if (IS_ERR(disk)) 3682 goto out_free_ns; 3683 disk->fops = &nvme_bdev_ops; 3684 disk->private_data = ns; 3685 3686 ns->disk = disk; 3687 ns->queue = disk->queue; 3688 3689 if (ctrl->opts && ctrl->opts->data_digest) 3690 blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, ns->queue); 3691 3692 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue); 3693 if (ctrl->ops->supports_pci_p2pdma && 3694 ctrl->ops->supports_pci_p2pdma(ctrl)) 3695 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue); 3696 3697 ns->ctrl = ctrl; 3698 kref_init(&ns->kref); 3699 3700 if (nvme_init_ns_head(ns, info)) 3701 goto out_cleanup_disk; 3702 3703 /* 3704 * If multipathing is enabled, the device name for all disks and not 3705 * just those that represent shared namespaces needs to be based on the 3706 * subsystem instance. Using the controller instance for private 3707 * namespaces could lead to naming collisions between shared and private 3708 * namespaces if they don't use a common numbering scheme. 3709 * 3710 * If multipathing is not enabled, disk names must use the controller 3711 * instance as shared namespaces will show up as multiple block 3712 * devices. 3713 */ 3714 if (nvme_ns_head_multipath(ns->head)) { 3715 sprintf(disk->disk_name, "nvme%dc%dn%d", ctrl->subsys->instance, 3716 ctrl->instance, ns->head->instance); 3717 disk->flags |= GENHD_FL_HIDDEN; 3718 } else if (multipath) { 3719 sprintf(disk->disk_name, "nvme%dn%d", ctrl->subsys->instance, 3720 ns->head->instance); 3721 } else { 3722 sprintf(disk->disk_name, "nvme%dn%d", ctrl->instance, 3723 ns->head->instance); 3724 } 3725 3726 if (nvme_update_ns_info(ns, info)) 3727 goto out_unlink_ns; 3728 3729 down_write(&ctrl->namespaces_rwsem); 3730 nvme_ns_add_to_ctrl_list(ns); 3731 up_write(&ctrl->namespaces_rwsem); 3732 nvme_get_ctrl(ctrl); 3733 3734 if (device_add_disk(ctrl->device, ns->disk, nvme_ns_id_attr_groups)) 3735 goto out_cleanup_ns_from_list; 3736 3737 if (!nvme_ns_head_multipath(ns->head)) 3738 nvme_add_ns_cdev(ns); 3739 3740 nvme_mpath_add_disk(ns, info->anagrpid); 3741 nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name); 3742 3743 return; 3744 3745 out_cleanup_ns_from_list: 3746 nvme_put_ctrl(ctrl); 3747 down_write(&ctrl->namespaces_rwsem); 3748 list_del_init(&ns->list); 3749 up_write(&ctrl->namespaces_rwsem); 3750 out_unlink_ns: 3751 mutex_lock(&ctrl->subsys->lock); 3752 list_del_rcu(&ns->siblings); 3753 if (list_empty(&ns->head->list)) 3754 list_del_init(&ns->head->entry); 3755 mutex_unlock(&ctrl->subsys->lock); 3756 nvme_put_ns_head(ns->head); 3757 out_cleanup_disk: 3758 put_disk(disk); 3759 out_free_ns: 3760 kfree(ns); 3761 } 3762 3763 static void nvme_ns_remove(struct nvme_ns *ns) 3764 { 3765 bool last_path = false; 3766 3767 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags)) 3768 return; 3769 3770 clear_bit(NVME_NS_READY, &ns->flags); 3771 set_capacity(ns->disk, 0); 3772 nvme_fault_inject_fini(&ns->fault_inject); 3773 3774 /* 3775 * Ensure that !NVME_NS_READY is seen by other threads to prevent 3776 * this ns going back into current_path. 3777 */ 3778 synchronize_srcu(&ns->head->srcu); 3779 3780 /* wait for concurrent submissions */ 3781 if (nvme_mpath_clear_current_path(ns)) 3782 synchronize_srcu(&ns->head->srcu); 3783 3784 mutex_lock(&ns->ctrl->subsys->lock); 3785 list_del_rcu(&ns->siblings); 3786 if (list_empty(&ns->head->list)) { 3787 list_del_init(&ns->head->entry); 3788 last_path = true; 3789 } 3790 mutex_unlock(&ns->ctrl->subsys->lock); 3791 3792 /* guarantee not available in head->list */ 3793 synchronize_srcu(&ns->head->srcu); 3794 3795 if (!nvme_ns_head_multipath(ns->head)) 3796 nvme_cdev_del(&ns->cdev, &ns->cdev_device); 3797 del_gendisk(ns->disk); 3798 3799 down_write(&ns->ctrl->namespaces_rwsem); 3800 list_del_init(&ns->list); 3801 up_write(&ns->ctrl->namespaces_rwsem); 3802 3803 if (last_path) 3804 nvme_mpath_shutdown_disk(ns->head); 3805 nvme_put_ns(ns); 3806 } 3807 3808 static void nvme_ns_remove_by_nsid(struct nvme_ctrl *ctrl, u32 nsid) 3809 { 3810 struct nvme_ns *ns = nvme_find_get_ns(ctrl, nsid); 3811 3812 if (ns) { 3813 nvme_ns_remove(ns); 3814 nvme_put_ns(ns); 3815 } 3816 } 3817 3818 static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_info *info) 3819 { 3820 int ret = NVME_SC_INVALID_NS | NVME_SC_DNR; 3821 3822 if (!nvme_ns_ids_equal(&ns->head->ids, &info->ids)) { 3823 dev_err(ns->ctrl->device, 3824 "identifiers changed for nsid %d\n", ns->head->ns_id); 3825 goto out; 3826 } 3827 3828 ret = nvme_update_ns_info(ns, info); 3829 out: 3830 /* 3831 * Only remove the namespace if we got a fatal error back from the 3832 * device, otherwise ignore the error and just move on. 3833 * 3834 * TODO: we should probably schedule a delayed retry here. 3835 */ 3836 if (ret > 0 && (ret & NVME_SC_DNR)) 3837 nvme_ns_remove(ns); 3838 } 3839 3840 static void nvme_scan_ns(struct nvme_ctrl *ctrl, unsigned nsid) 3841 { 3842 struct nvme_ns_info info = { .nsid = nsid }; 3843 struct nvme_ns *ns; 3844 int ret; 3845 3846 if (nvme_identify_ns_descs(ctrl, &info)) 3847 return; 3848 3849 if (info.ids.csi != NVME_CSI_NVM && !nvme_multi_css(ctrl)) { 3850 dev_warn(ctrl->device, 3851 "command set not reported for nsid: %d\n", nsid); 3852 return; 3853 } 3854 3855 /* 3856 * If available try to use the Command Set Idependent Identify Namespace 3857 * data structure to find all the generic information that is needed to 3858 * set up a namespace. If not fall back to the legacy version. 3859 */ 3860 if ((ctrl->cap & NVME_CAP_CRMS_CRIMS) || 3861 (info.ids.csi != NVME_CSI_NVM && info.ids.csi != NVME_CSI_ZNS)) 3862 ret = nvme_ns_info_from_id_cs_indep(ctrl, &info); 3863 else 3864 ret = nvme_ns_info_from_identify(ctrl, &info); 3865 3866 if (info.is_removed) 3867 nvme_ns_remove_by_nsid(ctrl, nsid); 3868 3869 /* 3870 * Ignore the namespace if it is not ready. We will get an AEN once it 3871 * becomes ready and restart the scan. 3872 */ 3873 if (ret || !info.is_ready) 3874 return; 3875 3876 ns = nvme_find_get_ns(ctrl, nsid); 3877 if (ns) { 3878 nvme_validate_ns(ns, &info); 3879 nvme_put_ns(ns); 3880 } else { 3881 nvme_alloc_ns(ctrl, &info); 3882 } 3883 } 3884 3885 static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl, 3886 unsigned nsid) 3887 { 3888 struct nvme_ns *ns, *next; 3889 LIST_HEAD(rm_list); 3890 3891 down_write(&ctrl->namespaces_rwsem); 3892 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) { 3893 if (ns->head->ns_id > nsid) 3894 list_move_tail(&ns->list, &rm_list); 3895 } 3896 up_write(&ctrl->namespaces_rwsem); 3897 3898 list_for_each_entry_safe(ns, next, &rm_list, list) 3899 nvme_ns_remove(ns); 3900 3901 } 3902 3903 static int nvme_scan_ns_list(struct nvme_ctrl *ctrl) 3904 { 3905 const int nr_entries = NVME_IDENTIFY_DATA_SIZE / sizeof(__le32); 3906 __le32 *ns_list; 3907 u32 prev = 0; 3908 int ret = 0, i; 3909 3910 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL); 3911 if (!ns_list) 3912 return -ENOMEM; 3913 3914 for (;;) { 3915 struct nvme_command cmd = { 3916 .identify.opcode = nvme_admin_identify, 3917 .identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST, 3918 .identify.nsid = cpu_to_le32(prev), 3919 }; 3920 3921 ret = nvme_submit_sync_cmd(ctrl->admin_q, &cmd, ns_list, 3922 NVME_IDENTIFY_DATA_SIZE); 3923 if (ret) { 3924 dev_warn(ctrl->device, 3925 "Identify NS List failed (status=0x%x)\n", ret); 3926 goto free; 3927 } 3928 3929 for (i = 0; i < nr_entries; i++) { 3930 u32 nsid = le32_to_cpu(ns_list[i]); 3931 3932 if (!nsid) /* end of the list? */ 3933 goto out; 3934 nvme_scan_ns(ctrl, nsid); 3935 while (++prev < nsid) 3936 nvme_ns_remove_by_nsid(ctrl, prev); 3937 } 3938 } 3939 out: 3940 nvme_remove_invalid_namespaces(ctrl, prev); 3941 free: 3942 kfree(ns_list); 3943 return ret; 3944 } 3945 3946 static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl) 3947 { 3948 struct nvme_id_ctrl *id; 3949 u32 nn, i; 3950 3951 if (nvme_identify_ctrl(ctrl, &id)) 3952 return; 3953 nn = le32_to_cpu(id->nn); 3954 kfree(id); 3955 3956 for (i = 1; i <= nn; i++) 3957 nvme_scan_ns(ctrl, i); 3958 3959 nvme_remove_invalid_namespaces(ctrl, nn); 3960 } 3961 3962 static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl) 3963 { 3964 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32); 3965 __le32 *log; 3966 int error; 3967 3968 log = kzalloc(log_size, GFP_KERNEL); 3969 if (!log) 3970 return; 3971 3972 /* 3973 * We need to read the log to clear the AEN, but we don't want to rely 3974 * on it for the changed namespace information as userspace could have 3975 * raced with us in reading the log page, which could cause us to miss 3976 * updates. 3977 */ 3978 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0, 3979 NVME_CSI_NVM, log, log_size, 0); 3980 if (error) 3981 dev_warn(ctrl->device, 3982 "reading changed ns log failed: %d\n", error); 3983 3984 kfree(log); 3985 } 3986 3987 static void nvme_scan_work(struct work_struct *work) 3988 { 3989 struct nvme_ctrl *ctrl = 3990 container_of(work, struct nvme_ctrl, scan_work); 3991 int ret; 3992 3993 /* No tagset on a live ctrl means IO queues could not created */ 3994 if (ctrl->state != NVME_CTRL_LIVE || !ctrl->tagset) 3995 return; 3996 3997 /* 3998 * Identify controller limits can change at controller reset due to 3999 * new firmware download, even though it is not common we cannot ignore 4000 * such scenario. Controller's non-mdts limits are reported in the unit 4001 * of logical blocks that is dependent on the format of attached 4002 * namespace. Hence re-read the limits at the time of ns allocation. 4003 */ 4004 ret = nvme_init_non_mdts_limits(ctrl); 4005 if (ret < 0) { 4006 dev_warn(ctrl->device, 4007 "reading non-mdts-limits failed: %d\n", ret); 4008 return; 4009 } 4010 4011 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) { 4012 dev_info(ctrl->device, "rescanning namespaces.\n"); 4013 nvme_clear_changed_ns_log(ctrl); 4014 } 4015 4016 mutex_lock(&ctrl->scan_lock); 4017 if (nvme_ctrl_limited_cns(ctrl)) { 4018 nvme_scan_ns_sequential(ctrl); 4019 } else { 4020 /* 4021 * Fall back to sequential scan if DNR is set to handle broken 4022 * devices which should support Identify NS List (as per the VS 4023 * they report) but don't actually support it. 4024 */ 4025 ret = nvme_scan_ns_list(ctrl); 4026 if (ret > 0 && ret & NVME_SC_DNR) 4027 nvme_scan_ns_sequential(ctrl); 4028 } 4029 mutex_unlock(&ctrl->scan_lock); 4030 } 4031 4032 /* 4033 * This function iterates the namespace list unlocked to allow recovery from 4034 * controller failure. It is up to the caller to ensure the namespace list is 4035 * not modified by scan work while this function is executing. 4036 */ 4037 void nvme_remove_namespaces(struct nvme_ctrl *ctrl) 4038 { 4039 struct nvme_ns *ns, *next; 4040 LIST_HEAD(ns_list); 4041 4042 /* 4043 * make sure to requeue I/O to all namespaces as these 4044 * might result from the scan itself and must complete 4045 * for the scan_work to make progress 4046 */ 4047 nvme_mpath_clear_ctrl_paths(ctrl); 4048 4049 /* prevent racing with ns scanning */ 4050 flush_work(&ctrl->scan_work); 4051 4052 /* 4053 * The dead states indicates the controller was not gracefully 4054 * disconnected. In that case, we won't be able to flush any data while 4055 * removing the namespaces' disks; fail all the queues now to avoid 4056 * potentially having to clean up the failed sync later. 4057 */ 4058 if (ctrl->state == NVME_CTRL_DEAD) { 4059 nvme_mark_namespaces_dead(ctrl); 4060 nvme_unquiesce_io_queues(ctrl); 4061 } 4062 4063 /* this is a no-op when called from the controller reset handler */ 4064 nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING_NOIO); 4065 4066 down_write(&ctrl->namespaces_rwsem); 4067 list_splice_init(&ctrl->namespaces, &ns_list); 4068 up_write(&ctrl->namespaces_rwsem); 4069 4070 list_for_each_entry_safe(ns, next, &ns_list, list) 4071 nvme_ns_remove(ns); 4072 } 4073 EXPORT_SYMBOL_GPL(nvme_remove_namespaces); 4074 4075 static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env) 4076 { 4077 const struct nvme_ctrl *ctrl = 4078 container_of(dev, struct nvme_ctrl, ctrl_device); 4079 struct nvmf_ctrl_options *opts = ctrl->opts; 4080 int ret; 4081 4082 ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name); 4083 if (ret) 4084 return ret; 4085 4086 if (opts) { 4087 ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr); 4088 if (ret) 4089 return ret; 4090 4091 ret = add_uevent_var(env, "NVME_TRSVCID=%s", 4092 opts->trsvcid ?: "none"); 4093 if (ret) 4094 return ret; 4095 4096 ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s", 4097 opts->host_traddr ?: "none"); 4098 if (ret) 4099 return ret; 4100 4101 ret = add_uevent_var(env, "NVME_HOST_IFACE=%s", 4102 opts->host_iface ?: "none"); 4103 } 4104 return ret; 4105 } 4106 4107 static void nvme_change_uevent(struct nvme_ctrl *ctrl, char *envdata) 4108 { 4109 char *envp[2] = { envdata, NULL }; 4110 4111 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp); 4112 } 4113 4114 static void nvme_aen_uevent(struct nvme_ctrl *ctrl) 4115 { 4116 char *envp[2] = { NULL, NULL }; 4117 u32 aen_result = ctrl->aen_result; 4118 4119 ctrl->aen_result = 0; 4120 if (!aen_result) 4121 return; 4122 4123 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result); 4124 if (!envp[0]) 4125 return; 4126 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp); 4127 kfree(envp[0]); 4128 } 4129 4130 static void nvme_async_event_work(struct work_struct *work) 4131 { 4132 struct nvme_ctrl *ctrl = 4133 container_of(work, struct nvme_ctrl, async_event_work); 4134 4135 nvme_aen_uevent(ctrl); 4136 4137 /* 4138 * The transport drivers must guarantee AER submission here is safe by 4139 * flushing ctrl async_event_work after changing the controller state 4140 * from LIVE and before freeing the admin queue. 4141 */ 4142 if (ctrl->state == NVME_CTRL_LIVE) 4143 ctrl->ops->submit_async_event(ctrl); 4144 } 4145 4146 static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl) 4147 { 4148 4149 u32 csts; 4150 4151 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) 4152 return false; 4153 4154 if (csts == ~0) 4155 return false; 4156 4157 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP)); 4158 } 4159 4160 static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl) 4161 { 4162 struct nvme_fw_slot_info_log *log; 4163 4164 log = kmalloc(sizeof(*log), GFP_KERNEL); 4165 if (!log) 4166 return; 4167 4168 if (nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_FW_SLOT, 0, NVME_CSI_NVM, 4169 log, sizeof(*log), 0)) 4170 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n"); 4171 kfree(log); 4172 } 4173 4174 static void nvme_fw_act_work(struct work_struct *work) 4175 { 4176 struct nvme_ctrl *ctrl = container_of(work, 4177 struct nvme_ctrl, fw_act_work); 4178 unsigned long fw_act_timeout; 4179 4180 if (ctrl->mtfa) 4181 fw_act_timeout = jiffies + 4182 msecs_to_jiffies(ctrl->mtfa * 100); 4183 else 4184 fw_act_timeout = jiffies + 4185 msecs_to_jiffies(admin_timeout * 1000); 4186 4187 nvme_quiesce_io_queues(ctrl); 4188 while (nvme_ctrl_pp_status(ctrl)) { 4189 if (time_after(jiffies, fw_act_timeout)) { 4190 dev_warn(ctrl->device, 4191 "Fw activation timeout, reset controller\n"); 4192 nvme_try_sched_reset(ctrl); 4193 return; 4194 } 4195 msleep(100); 4196 } 4197 4198 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE)) 4199 return; 4200 4201 nvme_unquiesce_io_queues(ctrl); 4202 /* read FW slot information to clear the AER */ 4203 nvme_get_fw_slot_info(ctrl); 4204 4205 queue_work(nvme_wq, &ctrl->async_event_work); 4206 } 4207 4208 static u32 nvme_aer_type(u32 result) 4209 { 4210 return result & 0x7; 4211 } 4212 4213 static u32 nvme_aer_subtype(u32 result) 4214 { 4215 return (result & 0xff00) >> 8; 4216 } 4217 4218 static bool nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result) 4219 { 4220 u32 aer_notice_type = nvme_aer_subtype(result); 4221 bool requeue = true; 4222 4223 switch (aer_notice_type) { 4224 case NVME_AER_NOTICE_NS_CHANGED: 4225 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events); 4226 nvme_queue_scan(ctrl); 4227 break; 4228 case NVME_AER_NOTICE_FW_ACT_STARTING: 4229 /* 4230 * We are (ab)using the RESETTING state to prevent subsequent 4231 * recovery actions from interfering with the controller's 4232 * firmware activation. 4233 */ 4234 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) { 4235 nvme_auth_stop(ctrl); 4236 requeue = false; 4237 queue_work(nvme_wq, &ctrl->fw_act_work); 4238 } 4239 break; 4240 #ifdef CONFIG_NVME_MULTIPATH 4241 case NVME_AER_NOTICE_ANA: 4242 if (!ctrl->ana_log_buf) 4243 break; 4244 queue_work(nvme_wq, &ctrl->ana_work); 4245 break; 4246 #endif 4247 case NVME_AER_NOTICE_DISC_CHANGED: 4248 ctrl->aen_result = result; 4249 break; 4250 default: 4251 dev_warn(ctrl->device, "async event result %08x\n", result); 4252 } 4253 return requeue; 4254 } 4255 4256 static void nvme_handle_aer_persistent_error(struct nvme_ctrl *ctrl) 4257 { 4258 dev_warn(ctrl->device, "resetting controller due to AER\n"); 4259 nvme_reset_ctrl(ctrl); 4260 } 4261 4262 void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 4263 volatile union nvme_result *res) 4264 { 4265 u32 result = le32_to_cpu(res->u32); 4266 u32 aer_type = nvme_aer_type(result); 4267 u32 aer_subtype = nvme_aer_subtype(result); 4268 bool requeue = true; 4269 4270 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS) 4271 return; 4272 4273 trace_nvme_async_event(ctrl, result); 4274 switch (aer_type) { 4275 case NVME_AER_NOTICE: 4276 requeue = nvme_handle_aen_notice(ctrl, result); 4277 break; 4278 case NVME_AER_ERROR: 4279 /* 4280 * For a persistent internal error, don't run async_event_work 4281 * to submit a new AER. The controller reset will do it. 4282 */ 4283 if (aer_subtype == NVME_AER_ERROR_PERSIST_INT_ERR) { 4284 nvme_handle_aer_persistent_error(ctrl); 4285 return; 4286 } 4287 fallthrough; 4288 case NVME_AER_SMART: 4289 case NVME_AER_CSS: 4290 case NVME_AER_VS: 4291 ctrl->aen_result = result; 4292 break; 4293 default: 4294 break; 4295 } 4296 4297 if (requeue) 4298 queue_work(nvme_wq, &ctrl->async_event_work); 4299 } 4300 EXPORT_SYMBOL_GPL(nvme_complete_async_event); 4301 4302 int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 4303 const struct blk_mq_ops *ops, unsigned int cmd_size) 4304 { 4305 int ret; 4306 4307 memset(set, 0, sizeof(*set)); 4308 set->ops = ops; 4309 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 4310 if (ctrl->ops->flags & NVME_F_FABRICS) 4311 set->reserved_tags = NVMF_RESERVED_TAGS; 4312 set->numa_node = ctrl->numa_node; 4313 set->flags = BLK_MQ_F_NO_SCHED; 4314 if (ctrl->ops->flags & NVME_F_BLOCKING) 4315 set->flags |= BLK_MQ_F_BLOCKING; 4316 set->cmd_size = cmd_size; 4317 set->driver_data = ctrl; 4318 set->nr_hw_queues = 1; 4319 set->timeout = NVME_ADMIN_TIMEOUT; 4320 ret = blk_mq_alloc_tag_set(set); 4321 if (ret) 4322 return ret; 4323 4324 ctrl->admin_q = blk_mq_init_queue(set); 4325 if (IS_ERR(ctrl->admin_q)) { 4326 ret = PTR_ERR(ctrl->admin_q); 4327 goto out_free_tagset; 4328 } 4329 4330 if (ctrl->ops->flags & NVME_F_FABRICS) { 4331 ctrl->fabrics_q = blk_mq_init_queue(set); 4332 if (IS_ERR(ctrl->fabrics_q)) { 4333 ret = PTR_ERR(ctrl->fabrics_q); 4334 goto out_cleanup_admin_q; 4335 } 4336 } 4337 4338 ctrl->admin_tagset = set; 4339 return 0; 4340 4341 out_cleanup_admin_q: 4342 blk_mq_destroy_queue(ctrl->admin_q); 4343 blk_put_queue(ctrl->admin_q); 4344 out_free_tagset: 4345 blk_mq_free_tag_set(set); 4346 ctrl->admin_q = NULL; 4347 ctrl->fabrics_q = NULL; 4348 return ret; 4349 } 4350 EXPORT_SYMBOL_GPL(nvme_alloc_admin_tag_set); 4351 4352 void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl) 4353 { 4354 blk_mq_destroy_queue(ctrl->admin_q); 4355 blk_put_queue(ctrl->admin_q); 4356 if (ctrl->ops->flags & NVME_F_FABRICS) { 4357 blk_mq_destroy_queue(ctrl->fabrics_q); 4358 blk_put_queue(ctrl->fabrics_q); 4359 } 4360 blk_mq_free_tag_set(ctrl->admin_tagset); 4361 } 4362 EXPORT_SYMBOL_GPL(nvme_remove_admin_tag_set); 4363 4364 int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 4365 const struct blk_mq_ops *ops, unsigned int nr_maps, 4366 unsigned int cmd_size) 4367 { 4368 int ret; 4369 4370 memset(set, 0, sizeof(*set)); 4371 set->ops = ops; 4372 set->queue_depth = min_t(unsigned, ctrl->sqsize, BLK_MQ_MAX_DEPTH - 1); 4373 /* 4374 * Some Apple controllers requires tags to be unique across admin and 4375 * the (only) I/O queue, so reserve the first 32 tags of the I/O queue. 4376 */ 4377 if (ctrl->quirks & NVME_QUIRK_SHARED_TAGS) 4378 set->reserved_tags = NVME_AQ_DEPTH; 4379 else if (ctrl->ops->flags & NVME_F_FABRICS) 4380 set->reserved_tags = NVMF_RESERVED_TAGS; 4381 set->numa_node = ctrl->numa_node; 4382 set->flags = BLK_MQ_F_SHOULD_MERGE; 4383 if (ctrl->ops->flags & NVME_F_BLOCKING) 4384 set->flags |= BLK_MQ_F_BLOCKING; 4385 set->cmd_size = cmd_size, 4386 set->driver_data = ctrl; 4387 set->nr_hw_queues = ctrl->queue_count - 1; 4388 set->timeout = NVME_IO_TIMEOUT; 4389 set->nr_maps = nr_maps; 4390 ret = blk_mq_alloc_tag_set(set); 4391 if (ret) 4392 return ret; 4393 4394 if (ctrl->ops->flags & NVME_F_FABRICS) { 4395 ctrl->connect_q = blk_mq_init_queue(set); 4396 if (IS_ERR(ctrl->connect_q)) { 4397 ret = PTR_ERR(ctrl->connect_q); 4398 goto out_free_tag_set; 4399 } 4400 blk_queue_flag_set(QUEUE_FLAG_SKIP_TAGSET_QUIESCE, 4401 ctrl->connect_q); 4402 } 4403 4404 ctrl->tagset = set; 4405 return 0; 4406 4407 out_free_tag_set: 4408 blk_mq_free_tag_set(set); 4409 ctrl->connect_q = NULL; 4410 return ret; 4411 } 4412 EXPORT_SYMBOL_GPL(nvme_alloc_io_tag_set); 4413 4414 void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl) 4415 { 4416 if (ctrl->ops->flags & NVME_F_FABRICS) { 4417 blk_mq_destroy_queue(ctrl->connect_q); 4418 blk_put_queue(ctrl->connect_q); 4419 } 4420 blk_mq_free_tag_set(ctrl->tagset); 4421 } 4422 EXPORT_SYMBOL_GPL(nvme_remove_io_tag_set); 4423 4424 void nvme_stop_ctrl(struct nvme_ctrl *ctrl) 4425 { 4426 nvme_mpath_stop(ctrl); 4427 nvme_auth_stop(ctrl); 4428 nvme_stop_keep_alive(ctrl); 4429 nvme_stop_failfast_work(ctrl); 4430 flush_work(&ctrl->async_event_work); 4431 cancel_work_sync(&ctrl->fw_act_work); 4432 if (ctrl->ops->stop_ctrl) 4433 ctrl->ops->stop_ctrl(ctrl); 4434 } 4435 EXPORT_SYMBOL_GPL(nvme_stop_ctrl); 4436 4437 void nvme_start_ctrl(struct nvme_ctrl *ctrl) 4438 { 4439 nvme_start_keep_alive(ctrl); 4440 4441 nvme_enable_aen(ctrl); 4442 4443 /* 4444 * persistent discovery controllers need to send indication to userspace 4445 * to re-read the discovery log page to learn about possible changes 4446 * that were missed. We identify persistent discovery controllers by 4447 * checking that they started once before, hence are reconnecting back. 4448 */ 4449 if (test_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags) && 4450 nvme_discovery_ctrl(ctrl)) 4451 nvme_change_uevent(ctrl, "NVME_EVENT=rediscover"); 4452 4453 if (ctrl->queue_count > 1) { 4454 nvme_queue_scan(ctrl); 4455 nvme_unquiesce_io_queues(ctrl); 4456 nvme_mpath_update(ctrl); 4457 } 4458 4459 nvme_change_uevent(ctrl, "NVME_EVENT=connected"); 4460 set_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags); 4461 } 4462 EXPORT_SYMBOL_GPL(nvme_start_ctrl); 4463 4464 void nvme_uninit_ctrl(struct nvme_ctrl *ctrl) 4465 { 4466 nvme_hwmon_exit(ctrl); 4467 nvme_fault_inject_fini(&ctrl->fault_inject); 4468 dev_pm_qos_hide_latency_tolerance(ctrl->device); 4469 cdev_device_del(&ctrl->cdev, ctrl->device); 4470 nvme_put_ctrl(ctrl); 4471 } 4472 EXPORT_SYMBOL_GPL(nvme_uninit_ctrl); 4473 4474 static void nvme_free_cels(struct nvme_ctrl *ctrl) 4475 { 4476 struct nvme_effects_log *cel; 4477 unsigned long i; 4478 4479 xa_for_each(&ctrl->cels, i, cel) { 4480 xa_erase(&ctrl->cels, i); 4481 kfree(cel); 4482 } 4483 4484 xa_destroy(&ctrl->cels); 4485 } 4486 4487 static void nvme_free_ctrl(struct device *dev) 4488 { 4489 struct nvme_ctrl *ctrl = 4490 container_of(dev, struct nvme_ctrl, ctrl_device); 4491 struct nvme_subsystem *subsys = ctrl->subsys; 4492 4493 if (!subsys || ctrl->instance != subsys->instance) 4494 ida_free(&nvme_instance_ida, ctrl->instance); 4495 4496 nvme_free_cels(ctrl); 4497 nvme_mpath_uninit(ctrl); 4498 nvme_auth_stop(ctrl); 4499 nvme_auth_free(ctrl); 4500 __free_page(ctrl->discard_page); 4501 free_opal_dev(ctrl->opal_dev); 4502 4503 if (subsys) { 4504 mutex_lock(&nvme_subsystems_lock); 4505 list_del(&ctrl->subsys_entry); 4506 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device)); 4507 mutex_unlock(&nvme_subsystems_lock); 4508 } 4509 4510 ctrl->ops->free_ctrl(ctrl); 4511 4512 if (subsys) 4513 nvme_put_subsystem(subsys); 4514 } 4515 4516 /* 4517 * Initialize a NVMe controller structures. This needs to be called during 4518 * earliest initialization so that we have the initialized structured around 4519 * during probing. 4520 */ 4521 int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 4522 const struct nvme_ctrl_ops *ops, unsigned long quirks) 4523 { 4524 int ret; 4525 4526 ctrl->state = NVME_CTRL_NEW; 4527 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags); 4528 spin_lock_init(&ctrl->lock); 4529 mutex_init(&ctrl->scan_lock); 4530 INIT_LIST_HEAD(&ctrl->namespaces); 4531 xa_init(&ctrl->cels); 4532 init_rwsem(&ctrl->namespaces_rwsem); 4533 ctrl->dev = dev; 4534 ctrl->ops = ops; 4535 ctrl->quirks = quirks; 4536 ctrl->numa_node = NUMA_NO_NODE; 4537 INIT_WORK(&ctrl->scan_work, nvme_scan_work); 4538 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work); 4539 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work); 4540 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work); 4541 init_waitqueue_head(&ctrl->state_wq); 4542 4543 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work); 4544 INIT_DELAYED_WORK(&ctrl->failfast_work, nvme_failfast_work); 4545 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd)); 4546 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive; 4547 4548 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) > 4549 PAGE_SIZE); 4550 ctrl->discard_page = alloc_page(GFP_KERNEL); 4551 if (!ctrl->discard_page) { 4552 ret = -ENOMEM; 4553 goto out; 4554 } 4555 4556 ret = ida_alloc(&nvme_instance_ida, GFP_KERNEL); 4557 if (ret < 0) 4558 goto out; 4559 ctrl->instance = ret; 4560 4561 device_initialize(&ctrl->ctrl_device); 4562 ctrl->device = &ctrl->ctrl_device; 4563 ctrl->device->devt = MKDEV(MAJOR(nvme_ctrl_base_chr_devt), 4564 ctrl->instance); 4565 ctrl->device->class = nvme_class; 4566 ctrl->device->parent = ctrl->dev; 4567 if (ops->dev_attr_groups) 4568 ctrl->device->groups = ops->dev_attr_groups; 4569 else 4570 ctrl->device->groups = nvme_dev_attr_groups; 4571 ctrl->device->release = nvme_free_ctrl; 4572 dev_set_drvdata(ctrl->device, ctrl); 4573 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance); 4574 if (ret) 4575 goto out_release_instance; 4576 4577 nvme_get_ctrl(ctrl); 4578 cdev_init(&ctrl->cdev, &nvme_dev_fops); 4579 ctrl->cdev.owner = ops->module; 4580 ret = cdev_device_add(&ctrl->cdev, ctrl->device); 4581 if (ret) 4582 goto out_free_name; 4583 4584 /* 4585 * Initialize latency tolerance controls. The sysfs files won't 4586 * be visible to userspace unless the device actually supports APST. 4587 */ 4588 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance; 4589 dev_pm_qos_update_user_latency_tolerance(ctrl->device, 4590 min(default_ps_max_latency_us, (unsigned long)S32_MAX)); 4591 4592 nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device)); 4593 nvme_mpath_init_ctrl(ctrl); 4594 ret = nvme_auth_init_ctrl(ctrl); 4595 if (ret) 4596 goto out_free_cdev; 4597 4598 return 0; 4599 out_free_cdev: 4600 nvme_fault_inject_fini(&ctrl->fault_inject); 4601 dev_pm_qos_hide_latency_tolerance(ctrl->device); 4602 cdev_device_del(&ctrl->cdev, ctrl->device); 4603 out_free_name: 4604 nvme_put_ctrl(ctrl); 4605 kfree_const(ctrl->device->kobj.name); 4606 out_release_instance: 4607 ida_free(&nvme_instance_ida, ctrl->instance); 4608 out: 4609 if (ctrl->discard_page) 4610 __free_page(ctrl->discard_page); 4611 return ret; 4612 } 4613 EXPORT_SYMBOL_GPL(nvme_init_ctrl); 4614 4615 /* let I/O to all namespaces fail in preparation for surprise removal */ 4616 void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl) 4617 { 4618 struct nvme_ns *ns; 4619 4620 down_read(&ctrl->namespaces_rwsem); 4621 list_for_each_entry(ns, &ctrl->namespaces, list) 4622 blk_mark_disk_dead(ns->disk); 4623 up_read(&ctrl->namespaces_rwsem); 4624 } 4625 EXPORT_SYMBOL_GPL(nvme_mark_namespaces_dead); 4626 4627 void nvme_unfreeze(struct nvme_ctrl *ctrl) 4628 { 4629 struct nvme_ns *ns; 4630 4631 down_read(&ctrl->namespaces_rwsem); 4632 list_for_each_entry(ns, &ctrl->namespaces, list) 4633 blk_mq_unfreeze_queue(ns->queue); 4634 up_read(&ctrl->namespaces_rwsem); 4635 } 4636 EXPORT_SYMBOL_GPL(nvme_unfreeze); 4637 4638 int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout) 4639 { 4640 struct nvme_ns *ns; 4641 4642 down_read(&ctrl->namespaces_rwsem); 4643 list_for_each_entry(ns, &ctrl->namespaces, list) { 4644 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout); 4645 if (timeout <= 0) 4646 break; 4647 } 4648 up_read(&ctrl->namespaces_rwsem); 4649 return timeout; 4650 } 4651 EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout); 4652 4653 void nvme_wait_freeze(struct nvme_ctrl *ctrl) 4654 { 4655 struct nvme_ns *ns; 4656 4657 down_read(&ctrl->namespaces_rwsem); 4658 list_for_each_entry(ns, &ctrl->namespaces, list) 4659 blk_mq_freeze_queue_wait(ns->queue); 4660 up_read(&ctrl->namespaces_rwsem); 4661 } 4662 EXPORT_SYMBOL_GPL(nvme_wait_freeze); 4663 4664 void nvme_start_freeze(struct nvme_ctrl *ctrl) 4665 { 4666 struct nvme_ns *ns; 4667 4668 down_read(&ctrl->namespaces_rwsem); 4669 list_for_each_entry(ns, &ctrl->namespaces, list) 4670 blk_freeze_queue_start(ns->queue); 4671 up_read(&ctrl->namespaces_rwsem); 4672 } 4673 EXPORT_SYMBOL_GPL(nvme_start_freeze); 4674 4675 void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl) 4676 { 4677 if (!ctrl->tagset) 4678 return; 4679 if (!test_and_set_bit(NVME_CTRL_STOPPED, &ctrl->flags)) 4680 blk_mq_quiesce_tagset(ctrl->tagset); 4681 else 4682 blk_mq_wait_quiesce_done(ctrl->tagset); 4683 } 4684 EXPORT_SYMBOL_GPL(nvme_quiesce_io_queues); 4685 4686 void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl) 4687 { 4688 if (!ctrl->tagset) 4689 return; 4690 if (test_and_clear_bit(NVME_CTRL_STOPPED, &ctrl->flags)) 4691 blk_mq_unquiesce_tagset(ctrl->tagset); 4692 } 4693 EXPORT_SYMBOL_GPL(nvme_unquiesce_io_queues); 4694 4695 void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl) 4696 { 4697 if (!test_and_set_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags)) 4698 blk_mq_quiesce_queue(ctrl->admin_q); 4699 else 4700 blk_mq_wait_quiesce_done(ctrl->admin_q->tag_set); 4701 } 4702 EXPORT_SYMBOL_GPL(nvme_quiesce_admin_queue); 4703 4704 void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl) 4705 { 4706 if (test_and_clear_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags)) 4707 blk_mq_unquiesce_queue(ctrl->admin_q); 4708 } 4709 EXPORT_SYMBOL_GPL(nvme_unquiesce_admin_queue); 4710 4711 void nvme_sync_io_queues(struct nvme_ctrl *ctrl) 4712 { 4713 struct nvme_ns *ns; 4714 4715 down_read(&ctrl->namespaces_rwsem); 4716 list_for_each_entry(ns, &ctrl->namespaces, list) 4717 blk_sync_queue(ns->queue); 4718 up_read(&ctrl->namespaces_rwsem); 4719 } 4720 EXPORT_SYMBOL_GPL(nvme_sync_io_queues); 4721 4722 void nvme_sync_queues(struct nvme_ctrl *ctrl) 4723 { 4724 nvme_sync_io_queues(ctrl); 4725 if (ctrl->admin_q) 4726 blk_sync_queue(ctrl->admin_q); 4727 } 4728 EXPORT_SYMBOL_GPL(nvme_sync_queues); 4729 4730 struct nvme_ctrl *nvme_ctrl_from_file(struct file *file) 4731 { 4732 if (file->f_op != &nvme_dev_fops) 4733 return NULL; 4734 return file->private_data; 4735 } 4736 EXPORT_SYMBOL_NS_GPL(nvme_ctrl_from_file, NVME_TARGET_PASSTHRU); 4737 4738 /* 4739 * Check we didn't inadvertently grow the command structure sizes: 4740 */ 4741 static inline void _nvme_check_size(void) 4742 { 4743 BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64); 4744 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 4745 BUILD_BUG_ON(sizeof(struct nvme_identify) != 64); 4746 BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 4747 BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64); 4748 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 4749 BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64); 4750 BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64); 4751 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 4752 BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64); 4753 BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 4754 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 4755 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 4756 BUILD_BUG_ON(sizeof(struct nvme_id_ns_cs_indep) != 4757 NVME_IDENTIFY_DATA_SIZE); 4758 BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE); 4759 BUILD_BUG_ON(sizeof(struct nvme_id_ns_nvm) != NVME_IDENTIFY_DATA_SIZE); 4760 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE); 4761 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_nvm) != NVME_IDENTIFY_DATA_SIZE); 4762 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 4763 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 4764 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 4765 BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64); 4766 BUILD_BUG_ON(sizeof(struct nvme_feat_host_behavior) != 512); 4767 } 4768 4769 4770 static int __init nvme_core_init(void) 4771 { 4772 int result = -ENOMEM; 4773 4774 _nvme_check_size(); 4775 4776 nvme_wq = alloc_workqueue("nvme-wq", 4777 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0); 4778 if (!nvme_wq) 4779 goto out; 4780 4781 nvme_reset_wq = alloc_workqueue("nvme-reset-wq", 4782 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0); 4783 if (!nvme_reset_wq) 4784 goto destroy_wq; 4785 4786 nvme_delete_wq = alloc_workqueue("nvme-delete-wq", 4787 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0); 4788 if (!nvme_delete_wq) 4789 goto destroy_reset_wq; 4790 4791 result = alloc_chrdev_region(&nvme_ctrl_base_chr_devt, 0, 4792 NVME_MINORS, "nvme"); 4793 if (result < 0) 4794 goto destroy_delete_wq; 4795 4796 nvme_class = class_create("nvme"); 4797 if (IS_ERR(nvme_class)) { 4798 result = PTR_ERR(nvme_class); 4799 goto unregister_chrdev; 4800 } 4801 nvme_class->dev_uevent = nvme_class_uevent; 4802 4803 nvme_subsys_class = class_create("nvme-subsystem"); 4804 if (IS_ERR(nvme_subsys_class)) { 4805 result = PTR_ERR(nvme_subsys_class); 4806 goto destroy_class; 4807 } 4808 4809 result = alloc_chrdev_region(&nvme_ns_chr_devt, 0, NVME_MINORS, 4810 "nvme-generic"); 4811 if (result < 0) 4812 goto destroy_subsys_class; 4813 4814 nvme_ns_chr_class = class_create("nvme-generic"); 4815 if (IS_ERR(nvme_ns_chr_class)) { 4816 result = PTR_ERR(nvme_ns_chr_class); 4817 goto unregister_generic_ns; 4818 } 4819 4820 result = nvme_init_auth(); 4821 if (result) 4822 goto destroy_ns_chr; 4823 return 0; 4824 4825 destroy_ns_chr: 4826 class_destroy(nvme_ns_chr_class); 4827 unregister_generic_ns: 4828 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS); 4829 destroy_subsys_class: 4830 class_destroy(nvme_subsys_class); 4831 destroy_class: 4832 class_destroy(nvme_class); 4833 unregister_chrdev: 4834 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS); 4835 destroy_delete_wq: 4836 destroy_workqueue(nvme_delete_wq); 4837 destroy_reset_wq: 4838 destroy_workqueue(nvme_reset_wq); 4839 destroy_wq: 4840 destroy_workqueue(nvme_wq); 4841 out: 4842 return result; 4843 } 4844 4845 static void __exit nvme_core_exit(void) 4846 { 4847 nvme_exit_auth(); 4848 class_destroy(nvme_ns_chr_class); 4849 class_destroy(nvme_subsys_class); 4850 class_destroy(nvme_class); 4851 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS); 4852 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS); 4853 destroy_workqueue(nvme_delete_wq); 4854 destroy_workqueue(nvme_reset_wq); 4855 destroy_workqueue(nvme_wq); 4856 ida_destroy(&nvme_ns_chr_minor_ida); 4857 ida_destroy(&nvme_instance_ida); 4858 } 4859 4860 MODULE_LICENSE("GPL"); 4861 MODULE_VERSION("1.0"); 4862 module_init(nvme_core_init); 4863 module_exit(nvme_core_exit); 4864