1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2012 Intel Corporation. All rights reserved. 8 * Copyright (C) 2015 EMC Corporation. All Rights Reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * BSD LICENSE 15 * 16 * Copyright(c) 2012 Intel Corporation. All rights reserved. 17 * Copyright (C) 2015 EMC Corporation. All Rights Reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 23 * * Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * * Redistributions in binary form must reproduce the above copy 26 * notice, this list of conditions and the following disclaimer in 27 * the documentation and/or other materials provided with the 28 * distribution. 29 * * Neither the name of Intel Corporation nor the names of its 30 * contributors may be used to endorse or promote products derived 31 * from this software without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 44 * 45 * Intel PCIe NTB Linux driver 46 * 47 * Contact Information: 48 * Jon Mason <jon.mason@intel.com> 49 */ 50 51 #ifndef NTB_HW_INTEL_H 52 #define NTB_HW_INTEL_H 53 54 #include <linux/ntb.h> 55 #include <linux/pci.h> 56 57 /* PCI device IDs */ 58 #define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725 59 #define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726 60 #define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727 61 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D 62 #define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E 63 #define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F 64 #define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D 65 #define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E 66 #define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F 67 #define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D 68 #define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E 69 #define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F 70 #define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D 71 #define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E 72 #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F 73 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C 74 75 /* Ntb control and link status */ 76 #define NTB_CTL_CFG_LOCK BIT(0) 77 #define NTB_CTL_DISABLE BIT(1) 78 #define NTB_CTL_S2P_BAR2_SNOOP BIT(2) 79 #define NTB_CTL_P2S_BAR2_SNOOP BIT(4) 80 #define NTB_CTL_S2P_BAR4_SNOOP BIT(6) 81 #define NTB_CTL_P2S_BAR4_SNOOP BIT(8) 82 #define NTB_CTL_S2P_BAR5_SNOOP BIT(12) 83 #define NTB_CTL_P2S_BAR5_SNOOP BIT(14) 84 85 #define NTB_LNK_STA_ACTIVE_BIT 0x2000 86 #define NTB_LNK_STA_SPEED_MASK 0x000f 87 #define NTB_LNK_STA_WIDTH_MASK 0x03f0 88 #define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT)) 89 #define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK) 90 #define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4) 91 92 /* flags to indicate unsafe api */ 93 #define NTB_UNSAFE_DB BIT_ULL(0) 94 #define NTB_UNSAFE_SPAD BIT_ULL(1) 95 96 #define NTB_BAR_MASK_64 ~(0xfull) 97 #define NTB_BAR_MASK_32 ~(0xfu) 98 99 struct intel_ntb_dev; 100 101 struct intel_ntb_reg { 102 int (*poll_link)(struct intel_ntb_dev *ndev); 103 int (*link_is_up)(struct intel_ntb_dev *ndev); 104 u64 (*db_ioread)(void __iomem *mmio); 105 void (*db_iowrite)(u64 db_bits, void __iomem *mmio); 106 unsigned long ntb_ctl; 107 resource_size_t db_size; 108 int mw_bar[]; 109 }; 110 111 struct intel_ntb_alt_reg { 112 unsigned long db_bell; 113 unsigned long db_mask; 114 unsigned long db_clear; 115 unsigned long spad; 116 }; 117 118 struct intel_ntb_xlat_reg { 119 unsigned long bar0_base; 120 unsigned long bar2_xlat; 121 unsigned long bar2_limit; 122 }; 123 124 struct intel_b2b_addr { 125 phys_addr_t bar0_addr; 126 phys_addr_t bar2_addr64; 127 phys_addr_t bar4_addr64; 128 phys_addr_t bar4_addr32; 129 phys_addr_t bar5_addr32; 130 }; 131 132 struct intel_ntb_vec { 133 struct intel_ntb_dev *ndev; 134 int num; 135 }; 136 137 struct intel_ntb_dev { 138 struct ntb_dev ntb; 139 140 /* offset of peer bar0 in b2b bar */ 141 unsigned long b2b_off; 142 /* mw idx used to access peer bar0 */ 143 unsigned int b2b_idx; 144 145 /* BAR45 is split into BAR4 and BAR5 */ 146 bool bar4_split; 147 148 u32 ntb_ctl; 149 u32 lnk_sta; 150 151 unsigned char mw_count; 152 unsigned char spad_count; 153 unsigned char db_count; 154 unsigned char db_vec_count; 155 unsigned char db_vec_shift; 156 157 u64 db_valid_mask; 158 u64 db_link_mask; 159 u64 db_mask; 160 161 /* synchronize rmw access of db_mask and hw reg */ 162 spinlock_t db_mask_lock; 163 164 struct msix_entry *msix; 165 struct intel_ntb_vec *vec; 166 167 const struct intel_ntb_reg *reg; 168 const struct intel_ntb_alt_reg *self_reg; 169 const struct intel_ntb_alt_reg *peer_reg; 170 const struct intel_ntb_xlat_reg *xlat_reg; 171 void __iomem *self_mmio; 172 void __iomem *peer_mmio; 173 phys_addr_t peer_addr; 174 175 unsigned long last_ts; 176 struct delayed_work hb_timer; 177 178 unsigned long hwerr_flags; 179 unsigned long unsafe_flags; 180 unsigned long unsafe_flags_ignore; 181 182 struct dentry *debugfs_dir; 183 struct dentry *debugfs_info; 184 }; 185 186 #define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb) 187 #define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \ 188 hb_timer.work) 189 190 static inline int pdev_is_gen1(struct pci_dev *pdev) 191 { 192 switch (pdev->device) { 193 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF: 194 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB: 195 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT: 196 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX: 197 case PCI_DEVICE_ID_INTEL_NTB_SS_BDX: 198 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF: 199 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB: 200 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT: 201 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX: 202 case PCI_DEVICE_ID_INTEL_NTB_PS_BDX: 203 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF: 204 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB: 205 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT: 206 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX: 207 case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX: 208 return 1; 209 } 210 return 0; 211 } 212 213 static inline int pdev_is_gen3(struct pci_dev *pdev) 214 { 215 if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX) 216 return 1; 217 218 return 0; 219 } 220 221 #ifndef ioread64 222 #ifdef readq 223 #define ioread64 readq 224 #else 225 #define ioread64 _ioread64 226 static inline u64 _ioread64(void __iomem *mmio) 227 { 228 u64 low, high; 229 230 low = ioread32(mmio); 231 high = ioread32(mmio + sizeof(u32)); 232 return low | (high << 32); 233 } 234 #endif 235 #endif 236 237 #ifndef iowrite64 238 #ifdef writeq 239 #define iowrite64 writeq 240 #else 241 #define iowrite64 _iowrite64 242 static inline void _iowrite64(u64 val, void __iomem *mmio) 243 { 244 iowrite32(val, mmio); 245 iowrite32(val >> 32, mmio + sizeof(u32)); 246 } 247 #endif 248 #endif 249 250 #endif 251