1 /* 2 * I2C Link Layer for PN544 HCI based Driver 3 * 4 * Copyright (C) 2012 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/crc-ccitt.h> 22 #include <linux/module.h> 23 #include <linux/i2c.h> 24 #include <linux/gpio.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_irq.h> 27 #include <linux/acpi.h> 28 #include <linux/miscdevice.h> 29 #include <linux/interrupt.h> 30 #include <linux/delay.h> 31 #include <linux/nfc.h> 32 #include <linux/firmware.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/platform_data/pn544.h> 35 #include <asm/unaligned.h> 36 37 #include <net/nfc/hci.h> 38 #include <net/nfc/llc.h> 39 #include <net/nfc/nfc.h> 40 41 #include "pn544.h" 42 43 #define PN544_I2C_FRAME_HEADROOM 1 44 #define PN544_I2C_FRAME_TAILROOM 2 45 46 /* GPIO names */ 47 #define PN544_GPIO_NAME_IRQ "pn544_irq" 48 #define PN544_GPIO_NAME_FW "pn544_fw" 49 #define PN544_GPIO_NAME_EN "pn544_en" 50 51 /* framing in HCI mode */ 52 #define PN544_HCI_I2C_LLC_LEN 1 53 #define PN544_HCI_I2C_LLC_CRC 2 54 #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \ 55 PN544_HCI_I2C_LLC_CRC) 56 #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC) 57 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29 58 #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \ 59 PN544_HCI_I2C_LLC_MAX_PAYLOAD) 60 61 static struct i2c_device_id pn544_hci_i2c_id_table[] = { 62 {"pn544", 0}, 63 {} 64 }; 65 66 MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table); 67 68 static const struct acpi_device_id pn544_hci_i2c_acpi_match[] = { 69 {"NXP5440", 0}, 70 {} 71 }; 72 73 MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match); 74 75 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c" 76 77 /* 78 * Exposed through the 4 most significant bytes 79 * from the HCI SW_VERSION first byte, a.k.a. 80 * SW RomLib. 81 */ 82 #define PN544_HW_VARIANT_C2 0xa 83 #define PN544_HW_VARIANT_C3 0xb 84 85 #define PN544_FW_CMD_RESET 0x01 86 #define PN544_FW_CMD_WRITE 0x08 87 #define PN544_FW_CMD_CHECK 0x06 88 #define PN544_FW_CMD_SECURE_WRITE 0x0C 89 #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D 90 91 struct pn544_i2c_fw_frame_write { 92 u8 cmd; 93 u16 be_length; 94 u8 be_dest_addr[3]; 95 u16 be_datalen; 96 u8 data[]; 97 } __packed; 98 99 struct pn544_i2c_fw_frame_check { 100 u8 cmd; 101 u16 be_length; 102 u8 be_start_addr[3]; 103 u16 be_datalen; 104 u16 be_crc; 105 } __packed; 106 107 struct pn544_i2c_fw_frame_response { 108 u8 status; 109 u16 be_length; 110 } __packed; 111 112 struct pn544_i2c_fw_blob { 113 u32 be_size; 114 u32 be_destaddr; 115 u8 data[]; 116 }; 117 118 struct pn544_i2c_fw_secure_frame { 119 u8 cmd; 120 u16 be_datalen; 121 u8 data[]; 122 } __packed; 123 124 struct pn544_i2c_fw_secure_blob { 125 u64 header; 126 u8 data[]; 127 }; 128 129 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01 130 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02 131 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08 132 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B 133 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11 134 #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13 135 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18 136 #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19 137 #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D 138 #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20 139 #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21 140 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74 141 #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0 142 #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6 143 144 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 145 146 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7 147 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE 148 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8 149 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\ 150 PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\ 151 PN544_FW_WRITE_BUFFER_MAX_LEN) 152 #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3 153 #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\ 154 PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN) 155 #define PN544_FW_SECURE_FRAME_HEADER_LEN 3 156 #define PN544_FW_SECURE_BLOB_HEADER_LEN 8 157 158 #define FW_WORK_STATE_IDLE 1 159 #define FW_WORK_STATE_START 2 160 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3 161 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4 162 #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5 163 164 struct pn544_i2c_phy { 165 struct i2c_client *i2c_dev; 166 struct nfc_hci_dev *hdev; 167 168 unsigned int gpio_en; 169 unsigned int gpio_fw; 170 unsigned int en_polarity; 171 172 u8 hw_variant; 173 174 struct work_struct fw_work; 175 int fw_work_state; 176 char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1]; 177 const struct firmware *fw; 178 u32 fw_blob_dest_addr; 179 size_t fw_blob_size; 180 const u8 *fw_blob_data; 181 size_t fw_written; 182 size_t fw_size; 183 184 int fw_cmd_result; 185 186 int powered; 187 int run_mode; 188 189 int hard_fault; /* 190 * < 0 if hardware error occured (e.g. i2c err) 191 * and prevents normal operation. 192 */ 193 }; 194 195 #define I2C_DUMP_SKB(info, skb) \ 196 do { \ 197 pr_debug("%s:\n", info); \ 198 print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ 199 16, 1, (skb)->data, (skb)->len, 0); \ 200 } while (0) 201 202 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) 203 { 204 int polarity, retry, ret; 205 char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 }; 206 int count = sizeof(rset_cmd); 207 208 nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); 209 210 /* Disable fw download */ 211 gpio_set_value_cansleep(phy->gpio_fw, 0); 212 213 for (polarity = 0; polarity < 2; polarity++) { 214 phy->en_polarity = polarity; 215 retry = 3; 216 while (retry--) { 217 /* power off */ 218 gpio_set_value_cansleep(phy->gpio_en, 219 !phy->en_polarity); 220 usleep_range(10000, 15000); 221 222 /* power on */ 223 gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); 224 usleep_range(10000, 15000); 225 226 /* send reset */ 227 dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n"); 228 ret = i2c_master_send(phy->i2c_dev, rset_cmd, count); 229 if (ret == count) { 230 nfc_info(&phy->i2c_dev->dev, 231 "nfc_en polarity : active %s\n", 232 (polarity == 0 ? "low" : "high")); 233 goto out; 234 } 235 } 236 } 237 238 nfc_err(&phy->i2c_dev->dev, 239 "Could not detect nfc_en polarity, fallback to active high\n"); 240 241 out: 242 gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); 243 } 244 245 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode) 246 { 247 gpio_set_value_cansleep(phy->gpio_fw, 248 run_mode == PN544_FW_MODE ? 1 : 0); 249 gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); 250 usleep_range(10000, 15000); 251 252 phy->run_mode = run_mode; 253 } 254 255 static int pn544_hci_i2c_enable(void *phy_id) 256 { 257 struct pn544_i2c_phy *phy = phy_id; 258 259 pr_info("%s\n", __func__); 260 261 pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE); 262 263 phy->powered = 1; 264 265 return 0; 266 } 267 268 static void pn544_hci_i2c_disable(void *phy_id) 269 { 270 struct pn544_i2c_phy *phy = phy_id; 271 272 gpio_set_value_cansleep(phy->gpio_fw, 0); 273 gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); 274 usleep_range(10000, 15000); 275 276 gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); 277 usleep_range(10000, 15000); 278 279 gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); 280 usleep_range(10000, 15000); 281 282 phy->powered = 0; 283 } 284 285 static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb) 286 { 287 u16 crc; 288 int len; 289 290 len = skb->len + 2; 291 *skb_push(skb, 1) = len; 292 293 crc = crc_ccitt(0xffff, skb->data, skb->len); 294 crc = ~crc; 295 *skb_put(skb, 1) = crc & 0xff; 296 *skb_put(skb, 1) = crc >> 8; 297 } 298 299 static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb) 300 { 301 skb_pull(skb, PN544_I2C_FRAME_HEADROOM); 302 skb_trim(skb, PN544_I2C_FRAME_TAILROOM); 303 } 304 305 /* 306 * Writing a frame must not return the number of written bytes. 307 * It must return either zero for success, or <0 for error. 308 * In addition, it must not alter the skb 309 */ 310 static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb) 311 { 312 int r; 313 struct pn544_i2c_phy *phy = phy_id; 314 struct i2c_client *client = phy->i2c_dev; 315 316 if (phy->hard_fault != 0) 317 return phy->hard_fault; 318 319 usleep_range(3000, 6000); 320 321 pn544_hci_i2c_add_len_crc(skb); 322 323 I2C_DUMP_SKB("i2c frame written", skb); 324 325 r = i2c_master_send(client, skb->data, skb->len); 326 327 if (r == -EREMOTEIO) { /* Retry, chip was in standby */ 328 usleep_range(6000, 10000); 329 r = i2c_master_send(client, skb->data, skb->len); 330 } 331 332 if (r >= 0) { 333 if (r != skb->len) 334 r = -EREMOTEIO; 335 else 336 r = 0; 337 } 338 339 pn544_hci_i2c_remove_len_crc(skb); 340 341 return r; 342 } 343 344 static int check_crc(u8 *buf, int buflen) 345 { 346 int len; 347 u16 crc; 348 349 len = buf[0] + 1; 350 crc = crc_ccitt(0xffff, buf, len - 2); 351 crc = ~crc; 352 353 if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) { 354 pr_err("CRC error 0x%x != 0x%x 0x%x\n", 355 crc, buf[len - 1], buf[len - 2]); 356 pr_info("%s: BAD CRC\n", __func__); 357 print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE, 358 16, 2, buf, buflen, false); 359 return -EPERM; 360 } 361 return 0; 362 } 363 364 /* 365 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees 366 * that i2c bus will be flushed and that next read will start on a new frame. 367 * returned skb contains only LLC header and payload. 368 * returns: 369 * -EREMOTEIO : i2c read error (fatal) 370 * -EBADMSG : frame was incorrect and discarded 371 * -ENOMEM : cannot allocate skb, frame dropped 372 */ 373 static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb) 374 { 375 int r; 376 u8 len; 377 u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1]; 378 struct i2c_client *client = phy->i2c_dev; 379 380 r = i2c_master_recv(client, &len, 1); 381 if (r != 1) { 382 nfc_err(&client->dev, "cannot read len byte\n"); 383 return -EREMOTEIO; 384 } 385 386 if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) || 387 (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) { 388 nfc_err(&client->dev, "invalid len byte\n"); 389 r = -EBADMSG; 390 goto flush; 391 } 392 393 *skb = alloc_skb(1 + len, GFP_KERNEL); 394 if (*skb == NULL) { 395 r = -ENOMEM; 396 goto flush; 397 } 398 399 *skb_put(*skb, 1) = len; 400 401 r = i2c_master_recv(client, skb_put(*skb, len), len); 402 if (r != len) { 403 kfree_skb(*skb); 404 return -EREMOTEIO; 405 } 406 407 I2C_DUMP_SKB("i2c frame read", *skb); 408 409 r = check_crc((*skb)->data, (*skb)->len); 410 if (r != 0) { 411 kfree_skb(*skb); 412 r = -EBADMSG; 413 goto flush; 414 } 415 416 skb_pull(*skb, 1); 417 skb_trim(*skb, (*skb)->len - 2); 418 419 usleep_range(3000, 6000); 420 421 return 0; 422 423 flush: 424 if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0) 425 r = -EREMOTEIO; 426 427 usleep_range(3000, 6000); 428 429 return r; 430 } 431 432 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy) 433 { 434 int r; 435 struct pn544_i2c_fw_frame_response response; 436 struct i2c_client *client = phy->i2c_dev; 437 438 r = i2c_master_recv(client, (char *) &response, sizeof(response)); 439 if (r != sizeof(response)) { 440 nfc_err(&client->dev, "cannot read fw status\n"); 441 return -EIO; 442 } 443 444 usleep_range(3000, 6000); 445 446 switch (response.status) { 447 case 0: 448 return 0; 449 case PN544_FW_CMD_RESULT_CHUNK_OK: 450 return response.status; 451 case PN544_FW_CMD_RESULT_TIMEOUT: 452 return -ETIMEDOUT; 453 case PN544_FW_CMD_RESULT_BAD_CRC: 454 return -ENODATA; 455 case PN544_FW_CMD_RESULT_ACCESS_DENIED: 456 return -EACCES; 457 case PN544_FW_CMD_RESULT_PROTOCOL_ERROR: 458 return -EPROTO; 459 case PN544_FW_CMD_RESULT_INVALID_PARAMETER: 460 return -EINVAL; 461 case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND: 462 return -ENOTSUPP; 463 case PN544_FW_CMD_RESULT_INVALID_LENGTH: 464 return -EBADMSG; 465 case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR: 466 return -ENOKEY; 467 case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR: 468 return -EINVAL; 469 case PN544_FW_CMD_RESULT_MEMORY_ERROR: 470 return -ENOMEM; 471 case PN544_FW_CMD_RESULT_COMMAND_REJECTED: 472 return -EACCES; 473 case PN544_FW_CMD_RESULT_WRITE_FAILED: 474 case PN544_FW_CMD_RESULT_CHUNK_ERROR: 475 return -EIO; 476 default: 477 return -EIO; 478 } 479 } 480 481 /* 482 * Reads an shdlc frame from the chip. This is not as straightforward as it 483 * seems. There are cases where we could loose the frame start synchronization. 484 * The frame format is len-data-crc, and corruption can occur anywhere while 485 * transiting on i2c bus, such that we could read an invalid len. 486 * In order to recover synchronization with the next frame, we must be sure 487 * to read the real amount of data without using the len byte. We do this by 488 * assuming the following: 489 * - the chip will always present only one single complete frame on the bus 490 * before triggering the interrupt 491 * - the chip will not present a new frame until we have completely read 492 * the previous one (or until we have handled the interrupt). 493 * The tricky case is when we read a corrupted len that is less than the real 494 * len. We must detect this here in order to determine that we need to flush 495 * the bus. This is the reason why we check the crc here. 496 */ 497 static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id) 498 { 499 struct pn544_i2c_phy *phy = phy_id; 500 struct i2c_client *client; 501 struct sk_buff *skb = NULL; 502 int r; 503 504 if (!phy || irq != phy->i2c_dev->irq) { 505 WARN_ON_ONCE(1); 506 return IRQ_NONE; 507 } 508 509 client = phy->i2c_dev; 510 dev_dbg(&client->dev, "IRQ\n"); 511 512 if (phy->hard_fault != 0) 513 return IRQ_HANDLED; 514 515 if (phy->run_mode == PN544_FW_MODE) { 516 phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy); 517 schedule_work(&phy->fw_work); 518 } else { 519 r = pn544_hci_i2c_read(phy, &skb); 520 if (r == -EREMOTEIO) { 521 phy->hard_fault = r; 522 523 nfc_hci_recv_frame(phy->hdev, NULL); 524 525 return IRQ_HANDLED; 526 } else if ((r == -ENOMEM) || (r == -EBADMSG)) { 527 return IRQ_HANDLED; 528 } 529 530 nfc_hci_recv_frame(phy->hdev, skb); 531 } 532 return IRQ_HANDLED; 533 } 534 535 static struct nfc_phy_ops i2c_phy_ops = { 536 .write = pn544_hci_i2c_write, 537 .enable = pn544_hci_i2c_enable, 538 .disable = pn544_hci_i2c_disable, 539 }; 540 541 static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name, 542 u8 hw_variant) 543 { 544 struct pn544_i2c_phy *phy = phy_id; 545 546 pr_info("Starting Firmware Download (%s)\n", firmware_name); 547 548 strcpy(phy->firmware_name, firmware_name); 549 550 phy->hw_variant = hw_variant; 551 phy->fw_work_state = FW_WORK_STATE_START; 552 553 schedule_work(&phy->fw_work); 554 555 return 0; 556 } 557 558 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy, 559 int result) 560 { 561 pr_info("Firmware Download Complete, result=%d\n", result); 562 563 pn544_hci_i2c_disable(phy); 564 565 phy->fw_work_state = FW_WORK_STATE_IDLE; 566 567 if (phy->fw) { 568 release_firmware(phy->fw); 569 phy->fw = NULL; 570 } 571 572 nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result); 573 } 574 575 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr, 576 const u8 *data, u16 datalen) 577 { 578 u8 frame[PN544_FW_I2C_MAX_PAYLOAD]; 579 struct pn544_i2c_fw_frame_write *framep; 580 u16 params_len; 581 int framelen; 582 int r; 583 584 if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN) 585 datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN; 586 587 framep = (struct pn544_i2c_fw_frame_write *) frame; 588 589 params_len = sizeof(framep->be_dest_addr) + 590 sizeof(framep->be_datalen) + datalen; 591 framelen = params_len + sizeof(framep->cmd) + 592 sizeof(framep->be_length); 593 594 framep->cmd = PN544_FW_CMD_WRITE; 595 596 put_unaligned_be16(params_len, &framep->be_length); 597 598 framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16; 599 framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8; 600 framep->be_dest_addr[2] = dest_addr & 0xff; 601 602 put_unaligned_be16(datalen, &framep->be_datalen); 603 604 memcpy(framep->data, data, datalen); 605 606 r = i2c_master_send(client, frame, framelen); 607 608 if (r == framelen) 609 return datalen; 610 else if (r < 0) 611 return r; 612 else 613 return -EIO; 614 } 615 616 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr, 617 const u8 *data, u16 datalen) 618 { 619 struct pn544_i2c_fw_frame_check frame; 620 int r; 621 u16 crc; 622 623 /* calculate local crc for the data we want to check */ 624 crc = crc_ccitt(0xffff, data, datalen); 625 626 frame.cmd = PN544_FW_CMD_CHECK; 627 628 put_unaligned_be16(sizeof(frame.be_start_addr) + 629 sizeof(frame.be_datalen) + sizeof(frame.be_crc), 630 &frame.be_length); 631 632 /* tell the chip the memory region to which our crc applies */ 633 frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16; 634 frame.be_start_addr[1] = (start_addr & 0xff00) >> 8; 635 frame.be_start_addr[2] = start_addr & 0xff; 636 637 put_unaligned_be16(datalen, &frame.be_datalen); 638 639 /* 640 * and give our local crc. Chip will calculate its own crc for the 641 * region and compare with ours. 642 */ 643 put_unaligned_be16(crc, &frame.be_crc); 644 645 r = i2c_master_send(client, (const char *) &frame, sizeof(frame)); 646 647 if (r == sizeof(frame)) 648 return 0; 649 else if (r < 0) 650 return r; 651 else 652 return -EIO; 653 } 654 655 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy) 656 { 657 int r; 658 659 r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev, 660 phy->fw_blob_dest_addr + phy->fw_written, 661 phy->fw_blob_data + phy->fw_written, 662 phy->fw_blob_size - phy->fw_written); 663 if (r < 0) 664 return r; 665 666 phy->fw_written += r; 667 phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER; 668 669 return 0; 670 } 671 672 static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy, 673 const u8 *data, u16 datalen) 674 { 675 u8 buf[PN544_FW_I2C_MAX_PAYLOAD]; 676 struct pn544_i2c_fw_secure_frame *chunk; 677 int chunklen; 678 int r; 679 680 if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN) 681 datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN; 682 683 chunk = (struct pn544_i2c_fw_secure_frame *) buf; 684 685 chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE; 686 687 put_unaligned_be16(datalen, &chunk->be_datalen); 688 689 memcpy(chunk->data, data, datalen); 690 691 chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen; 692 693 r = i2c_master_send(phy->i2c_dev, buf, chunklen); 694 695 if (r == chunklen) 696 return datalen; 697 else if (r < 0) 698 return r; 699 else 700 return -EIO; 701 702 } 703 704 static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy) 705 { 706 struct pn544_i2c_fw_secure_frame *framep; 707 int r; 708 709 framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data; 710 if (phy->fw_written == 0) 711 phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen) 712 + PN544_FW_SECURE_FRAME_HEADER_LEN; 713 714 /* Only secure write command can be chunked*/ 715 if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD && 716 framep->cmd != PN544_FW_CMD_SECURE_WRITE) 717 return -EINVAL; 718 719 /* The firmware also have other commands, we just send them directly */ 720 if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) { 721 r = i2c_master_send(phy->i2c_dev, 722 (const char *) phy->fw_blob_data, phy->fw_blob_size); 723 724 if (r == phy->fw_blob_size) 725 goto exit; 726 else if (r < 0) 727 return r; 728 else 729 return -EIO; 730 } 731 732 r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy, 733 phy->fw_blob_data + phy->fw_written, 734 phy->fw_blob_size - phy->fw_written); 735 if (r < 0) 736 return r; 737 738 exit: 739 phy->fw_written += r; 740 phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER; 741 742 /* SW reset command will not trig any response from PN544 */ 743 if (framep->cmd == PN544_FW_CMD_RESET) { 744 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 745 phy->fw_cmd_result = 0; 746 schedule_work(&phy->fw_work); 747 } 748 749 return 0; 750 } 751 752 static void pn544_hci_i2c_fw_work(struct work_struct *work) 753 { 754 struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy, 755 fw_work); 756 int r; 757 struct pn544_i2c_fw_blob *blob; 758 struct pn544_i2c_fw_secure_blob *secure_blob; 759 760 switch (phy->fw_work_state) { 761 case FW_WORK_STATE_START: 762 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 763 764 r = request_firmware(&phy->fw, phy->firmware_name, 765 &phy->i2c_dev->dev); 766 if (r < 0) 767 goto exit_state_start; 768 769 phy->fw_written = 0; 770 771 switch (phy->hw_variant) { 772 case PN544_HW_VARIANT_C2: 773 blob = (struct pn544_i2c_fw_blob *) phy->fw->data; 774 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 775 phy->fw_blob_dest_addr = get_unaligned_be32( 776 &blob->be_destaddr); 777 phy->fw_blob_data = blob->data; 778 779 r = pn544_hci_i2c_fw_write_chunk(phy); 780 break; 781 case PN544_HW_VARIANT_C3: 782 secure_blob = (struct pn544_i2c_fw_secure_blob *) 783 phy->fw->data; 784 phy->fw_blob_data = secure_blob->data; 785 phy->fw_size = phy->fw->size; 786 r = pn544_hci_i2c_fw_secure_write_frame(phy); 787 break; 788 default: 789 r = -ENOTSUPP; 790 break; 791 } 792 793 exit_state_start: 794 if (r < 0) 795 pn544_hci_i2c_fw_work_complete(phy, r); 796 break; 797 798 case FW_WORK_STATE_WAIT_WRITE_ANSWER: 799 r = phy->fw_cmd_result; 800 if (r < 0) 801 goto exit_state_wait_write_answer; 802 803 if (phy->fw_written == phy->fw_blob_size) { 804 r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev, 805 phy->fw_blob_dest_addr, 806 phy->fw_blob_data, 807 phy->fw_blob_size); 808 if (r < 0) 809 goto exit_state_wait_write_answer; 810 phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER; 811 break; 812 } 813 814 r = pn544_hci_i2c_fw_write_chunk(phy); 815 816 exit_state_wait_write_answer: 817 if (r < 0) 818 pn544_hci_i2c_fw_work_complete(phy, r); 819 break; 820 821 case FW_WORK_STATE_WAIT_CHECK_ANSWER: 822 r = phy->fw_cmd_result; 823 if (r < 0) 824 goto exit_state_wait_check_answer; 825 826 blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data + 827 phy->fw_blob_size); 828 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 829 if (phy->fw_blob_size != 0) { 830 phy->fw_blob_dest_addr = 831 get_unaligned_be32(&blob->be_destaddr); 832 phy->fw_blob_data = blob->data; 833 834 phy->fw_written = 0; 835 r = pn544_hci_i2c_fw_write_chunk(phy); 836 } 837 838 exit_state_wait_check_answer: 839 if (r < 0 || phy->fw_blob_size == 0) 840 pn544_hci_i2c_fw_work_complete(phy, r); 841 break; 842 843 case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER: 844 r = phy->fw_cmd_result; 845 if (r < 0) 846 goto exit_state_wait_secure_write_answer; 847 848 if (r == PN544_FW_CMD_RESULT_CHUNK_OK) { 849 r = pn544_hci_i2c_fw_secure_write_frame(phy); 850 goto exit_state_wait_secure_write_answer; 851 } 852 853 if (phy->fw_written == phy->fw_blob_size) { 854 secure_blob = (struct pn544_i2c_fw_secure_blob *) 855 (phy->fw_blob_data + phy->fw_blob_size); 856 phy->fw_size -= phy->fw_blob_size + 857 PN544_FW_SECURE_BLOB_HEADER_LEN; 858 if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN 859 + PN544_FW_SECURE_FRAME_HEADER_LEN) { 860 phy->fw_blob_data = secure_blob->data; 861 862 phy->fw_written = 0; 863 r = pn544_hci_i2c_fw_secure_write_frame(phy); 864 } 865 } 866 867 exit_state_wait_secure_write_answer: 868 if (r < 0 || phy->fw_size == 0) 869 pn544_hci_i2c_fw_work_complete(phy, r); 870 break; 871 872 default: 873 break; 874 } 875 } 876 877 static int pn544_hci_i2c_acpi_request_resources(struct i2c_client *client) 878 { 879 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 880 struct gpio_desc *gpiod_en, *gpiod_fw; 881 struct device *dev = &client->dev; 882 883 /* Get EN GPIO from ACPI */ 884 gpiod_en = devm_gpiod_get_index(dev, PN544_GPIO_NAME_EN, 1, 885 GPIOD_OUT_LOW); 886 if (IS_ERR(gpiod_en)) { 887 nfc_err(dev, "Unable to get EN GPIO\n"); 888 return -ENODEV; 889 } 890 891 phy->gpio_en = desc_to_gpio(gpiod_en); 892 893 /* Get FW GPIO from ACPI */ 894 gpiod_fw = devm_gpiod_get_index(dev, PN544_GPIO_NAME_FW, 2, 895 GPIOD_OUT_LOW); 896 if (IS_ERR(gpiod_fw)) { 897 nfc_err(dev, "Unable to get FW GPIO\n"); 898 return -ENODEV; 899 } 900 901 phy->gpio_fw = desc_to_gpio(gpiod_fw); 902 903 return 0; 904 } 905 906 static int pn544_hci_i2c_of_request_resources(struct i2c_client *client) 907 { 908 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 909 struct device_node *pp; 910 int ret; 911 912 pp = client->dev.of_node; 913 if (!pp) { 914 ret = -ENODEV; 915 goto err_dt; 916 } 917 918 /* Obtention of EN GPIO from device tree */ 919 ret = of_get_named_gpio(pp, "enable-gpios", 0); 920 if (ret < 0) { 921 if (ret != -EPROBE_DEFER) 922 nfc_err(&client->dev, 923 "Failed to get EN gpio, error: %d\n", ret); 924 goto err_dt; 925 } 926 phy->gpio_en = ret; 927 928 /* Configuration of EN GPIO */ 929 ret = gpio_request(phy->gpio_en, PN544_GPIO_NAME_EN); 930 if (ret) { 931 nfc_err(&client->dev, "Fail EN pin\n"); 932 goto err_dt; 933 } 934 ret = gpio_direction_output(phy->gpio_en, 0); 935 if (ret) { 936 nfc_err(&client->dev, "Fail EN pin direction\n"); 937 goto err_gpio_en; 938 } 939 940 /* Obtention of FW GPIO from device tree */ 941 ret = of_get_named_gpio(pp, "firmware-gpios", 0); 942 if (ret < 0) { 943 if (ret != -EPROBE_DEFER) 944 nfc_err(&client->dev, 945 "Failed to get FW gpio, error: %d\n", ret); 946 goto err_gpio_en; 947 } 948 phy->gpio_fw = ret; 949 950 /* Configuration of FW GPIO */ 951 ret = gpio_request(phy->gpio_fw, PN544_GPIO_NAME_FW); 952 if (ret) { 953 nfc_err(&client->dev, "Fail FW pin\n"); 954 goto err_gpio_en; 955 } 956 ret = gpio_direction_output(phy->gpio_fw, 0); 957 if (ret) { 958 nfc_err(&client->dev, "Fail FW pin direction\n"); 959 goto err_gpio_fw; 960 } 961 962 return 0; 963 964 err_gpio_fw: 965 gpio_free(phy->gpio_fw); 966 err_gpio_en: 967 gpio_free(phy->gpio_en); 968 err_dt: 969 return ret; 970 } 971 972 static int pn544_hci_i2c_probe(struct i2c_client *client, 973 const struct i2c_device_id *id) 974 { 975 struct pn544_i2c_phy *phy; 976 struct pn544_nfc_platform_data *pdata; 977 int r = 0; 978 979 dev_dbg(&client->dev, "%s\n", __func__); 980 dev_dbg(&client->dev, "IRQ: %d\n", client->irq); 981 982 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 983 nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); 984 return -ENODEV; 985 } 986 987 phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy), 988 GFP_KERNEL); 989 if (!phy) 990 return -ENOMEM; 991 992 INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work); 993 phy->fw_work_state = FW_WORK_STATE_IDLE; 994 995 phy->i2c_dev = client; 996 i2c_set_clientdata(client, phy); 997 998 pdata = client->dev.platform_data; 999 1000 /* No platform data, using device tree. */ 1001 if (!pdata && client->dev.of_node) { 1002 r = pn544_hci_i2c_of_request_resources(client); 1003 if (r) { 1004 nfc_err(&client->dev, "No DT data\n"); 1005 return r; 1006 } 1007 /* Using platform data. */ 1008 } else if (pdata) { 1009 1010 if (pdata->request_resources == NULL) { 1011 nfc_err(&client->dev, "request_resources() missing\n"); 1012 return -EINVAL; 1013 } 1014 1015 r = pdata->request_resources(client); 1016 if (r) { 1017 nfc_err(&client->dev, 1018 "Cannot get platform resources\n"); 1019 return r; 1020 } 1021 1022 phy->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE); 1023 phy->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET); 1024 /* Using ACPI */ 1025 } else if (ACPI_HANDLE(&client->dev)) { 1026 r = pn544_hci_i2c_acpi_request_resources(client); 1027 if (r) { 1028 nfc_err(&client->dev, 1029 "Cannot get ACPI data\n"); 1030 return r; 1031 } 1032 } else { 1033 nfc_err(&client->dev, "No platform data\n"); 1034 return -EINVAL; 1035 } 1036 1037 pn544_hci_i2c_platform_init(phy); 1038 1039 r = request_threaded_irq(client->irq, NULL, pn544_hci_i2c_irq_thread_fn, 1040 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1041 PN544_HCI_I2C_DRIVER_NAME, phy); 1042 if (r < 0) { 1043 nfc_err(&client->dev, "Unable to register IRQ handler\n"); 1044 goto err_rti; 1045 } 1046 1047 r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME, 1048 PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM, 1049 PN544_HCI_I2C_LLC_MAX_PAYLOAD, 1050 pn544_hci_i2c_fw_download, &phy->hdev); 1051 if (r < 0) 1052 goto err_hci; 1053 1054 return 0; 1055 1056 err_hci: 1057 free_irq(client->irq, phy); 1058 1059 err_rti: 1060 if (!pdata) { 1061 gpio_free(phy->gpio_en); 1062 gpio_free(phy->gpio_fw); 1063 } else if (pdata->free_resources) { 1064 pdata->free_resources(); 1065 } 1066 1067 return r; 1068 } 1069 1070 static int pn544_hci_i2c_remove(struct i2c_client *client) 1071 { 1072 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 1073 struct pn544_nfc_platform_data *pdata = client->dev.platform_data; 1074 1075 dev_dbg(&client->dev, "%s\n", __func__); 1076 1077 cancel_work_sync(&phy->fw_work); 1078 if (phy->fw_work_state != FW_WORK_STATE_IDLE) 1079 pn544_hci_i2c_fw_work_complete(phy, -ENODEV); 1080 1081 pn544_hci_remove(phy->hdev); 1082 1083 if (phy->powered) 1084 pn544_hci_i2c_disable(phy); 1085 1086 free_irq(client->irq, phy); 1087 1088 /* No platform data, GPIOs have been requested by this driver */ 1089 if (!pdata) { 1090 gpio_free(phy->gpio_en); 1091 gpio_free(phy->gpio_fw); 1092 /* Using platform data */ 1093 } else if (pdata->free_resources) { 1094 pdata->free_resources(); 1095 } 1096 1097 return 0; 1098 } 1099 1100 static const struct of_device_id of_pn544_i2c_match[] = { 1101 { .compatible = "nxp,pn544-i2c", }, 1102 {}, 1103 }; 1104 MODULE_DEVICE_TABLE(of, of_pn544_i2c_match); 1105 1106 static struct i2c_driver pn544_hci_i2c_driver = { 1107 .driver = { 1108 .name = PN544_HCI_I2C_DRIVER_NAME, 1109 .of_match_table = of_match_ptr(of_pn544_i2c_match), 1110 .acpi_match_table = ACPI_PTR(pn544_hci_i2c_acpi_match), 1111 }, 1112 .probe = pn544_hci_i2c_probe, 1113 .id_table = pn544_hci_i2c_id_table, 1114 .remove = pn544_hci_i2c_remove, 1115 }; 1116 1117 module_i2c_driver(pn544_hci_i2c_driver); 1118 1119 MODULE_LICENSE("GPL"); 1120 MODULE_DESCRIPTION(DRIVER_DESC); 1121