1 /* 2 * I2C Link Layer for PN544 HCI based Driver 3 * 4 * Copyright (C) 2012 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/crc-ccitt.h> 22 #include <linux/module.h> 23 #include <linux/i2c.h> 24 #include <linux/gpio.h> 25 #include <linux/miscdevice.h> 26 #include <linux/interrupt.h> 27 #include <linux/delay.h> 28 #include <linux/nfc.h> 29 #include <linux/firmware.h> 30 #include <linux/unaligned/access_ok.h> 31 #include <linux/platform_data/pn544.h> 32 33 #include <net/nfc/hci.h> 34 #include <net/nfc/llc.h> 35 #include <net/nfc/nfc.h> 36 37 #include "pn544.h" 38 39 #define PN544_I2C_FRAME_HEADROOM 1 40 #define PN544_I2C_FRAME_TAILROOM 2 41 42 /* framing in HCI mode */ 43 #define PN544_HCI_I2C_LLC_LEN 1 44 #define PN544_HCI_I2C_LLC_CRC 2 45 #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \ 46 PN544_HCI_I2C_LLC_CRC) 47 #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC) 48 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29 49 #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \ 50 PN544_HCI_I2C_LLC_MAX_PAYLOAD) 51 52 static struct i2c_device_id pn544_hci_i2c_id_table[] = { 53 {"pn544", 0}, 54 {} 55 }; 56 57 MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table); 58 59 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c" 60 61 #define PN544_FW_CMD_WRITE 0x08 62 #define PN544_FW_CMD_CHECK 0x06 63 64 struct pn544_i2c_fw_frame_write { 65 u8 cmd; 66 u16 be_length; 67 u8 be_dest_addr[3]; 68 u16 be_datalen; 69 u8 data[]; 70 } __packed; 71 72 struct pn544_i2c_fw_frame_check { 73 u8 cmd; 74 u16 be_length; 75 u8 be_start_addr[3]; 76 u16 be_datalen; 77 u16 be_crc; 78 } __packed; 79 80 struct pn544_i2c_fw_frame_response { 81 u8 status; 82 u16 be_length; 83 } __packed; 84 85 struct pn544_i2c_fw_blob { 86 u32 be_size; 87 u32 be_destaddr; 88 u8 data[]; 89 }; 90 91 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01 92 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02 93 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08 94 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B 95 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11 96 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18 97 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74 98 99 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 100 101 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7 102 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE 103 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8 104 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\ 105 PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\ 106 PN544_FW_WRITE_BUFFER_MAX_LEN) 107 108 #define FW_WORK_STATE_IDLE 1 109 #define FW_WORK_STATE_START 2 110 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3 111 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4 112 113 struct pn544_i2c_phy { 114 struct i2c_client *i2c_dev; 115 struct nfc_hci_dev *hdev; 116 117 unsigned int gpio_en; 118 unsigned int gpio_irq; 119 unsigned int gpio_fw; 120 unsigned int en_polarity; 121 122 struct work_struct fw_work; 123 int fw_work_state; 124 char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1]; 125 const struct firmware *fw; 126 u32 fw_blob_dest_addr; 127 size_t fw_blob_size; 128 const u8 *fw_blob_data; 129 size_t fw_written; 130 int fw_cmd_result; 131 132 int powered; 133 int run_mode; 134 135 int hard_fault; /* 136 * < 0 if hardware error occured (e.g. i2c err) 137 * and prevents normal operation. 138 */ 139 }; 140 141 #define I2C_DUMP_SKB(info, skb) \ 142 do { \ 143 pr_debug("%s:\n", info); \ 144 print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ 145 16, 1, (skb)->data, (skb)->len, 0); \ 146 } while (0) 147 148 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) 149 { 150 int polarity, retry, ret; 151 char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 }; 152 int count = sizeof(rset_cmd); 153 154 nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); 155 156 /* Disable fw download */ 157 gpio_set_value(phy->gpio_fw, 0); 158 159 for (polarity = 0; polarity < 2; polarity++) { 160 phy->en_polarity = polarity; 161 retry = 3; 162 while (retry--) { 163 /* power off */ 164 gpio_set_value(phy->gpio_en, !phy->en_polarity); 165 usleep_range(10000, 15000); 166 167 /* power on */ 168 gpio_set_value(phy->gpio_en, phy->en_polarity); 169 usleep_range(10000, 15000); 170 171 /* send reset */ 172 dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n"); 173 ret = i2c_master_send(phy->i2c_dev, rset_cmd, count); 174 if (ret == count) { 175 nfc_info(&phy->i2c_dev->dev, 176 "nfc_en polarity : active %s\n", 177 (polarity == 0 ? "low" : "high")); 178 goto out; 179 } 180 } 181 } 182 183 nfc_err(&phy->i2c_dev->dev, 184 "Could not detect nfc_en polarity, fallback to active high\n"); 185 186 out: 187 gpio_set_value(phy->gpio_en, !phy->en_polarity); 188 } 189 190 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode) 191 { 192 gpio_set_value(phy->gpio_fw, run_mode == PN544_FW_MODE ? 1 : 0); 193 gpio_set_value(phy->gpio_en, phy->en_polarity); 194 usleep_range(10000, 15000); 195 196 phy->run_mode = run_mode; 197 } 198 199 static int pn544_hci_i2c_enable(void *phy_id) 200 { 201 struct pn544_i2c_phy *phy = phy_id; 202 203 pr_info("%s\n", __func__); 204 205 pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE); 206 207 phy->powered = 1; 208 209 return 0; 210 } 211 212 static void pn544_hci_i2c_disable(void *phy_id) 213 { 214 struct pn544_i2c_phy *phy = phy_id; 215 216 gpio_set_value(phy->gpio_fw, 0); 217 gpio_set_value(phy->gpio_en, !phy->en_polarity); 218 usleep_range(10000, 15000); 219 220 gpio_set_value(phy->gpio_en, phy->en_polarity); 221 usleep_range(10000, 15000); 222 223 gpio_set_value(phy->gpio_en, !phy->en_polarity); 224 usleep_range(10000, 15000); 225 226 phy->powered = 0; 227 } 228 229 static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb) 230 { 231 u16 crc; 232 int len; 233 234 len = skb->len + 2; 235 *skb_push(skb, 1) = len; 236 237 crc = crc_ccitt(0xffff, skb->data, skb->len); 238 crc = ~crc; 239 *skb_put(skb, 1) = crc & 0xff; 240 *skb_put(skb, 1) = crc >> 8; 241 } 242 243 static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb) 244 { 245 skb_pull(skb, PN544_I2C_FRAME_HEADROOM); 246 skb_trim(skb, PN544_I2C_FRAME_TAILROOM); 247 } 248 249 /* 250 * Writing a frame must not return the number of written bytes. 251 * It must return either zero for success, or <0 for error. 252 * In addition, it must not alter the skb 253 */ 254 static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb) 255 { 256 int r; 257 struct pn544_i2c_phy *phy = phy_id; 258 struct i2c_client *client = phy->i2c_dev; 259 260 if (phy->hard_fault != 0) 261 return phy->hard_fault; 262 263 usleep_range(3000, 6000); 264 265 pn544_hci_i2c_add_len_crc(skb); 266 267 I2C_DUMP_SKB("i2c frame written", skb); 268 269 r = i2c_master_send(client, skb->data, skb->len); 270 271 if (r == -EREMOTEIO) { /* Retry, chip was in standby */ 272 usleep_range(6000, 10000); 273 r = i2c_master_send(client, skb->data, skb->len); 274 } 275 276 if (r >= 0) { 277 if (r != skb->len) 278 r = -EREMOTEIO; 279 else 280 r = 0; 281 } 282 283 pn544_hci_i2c_remove_len_crc(skb); 284 285 return r; 286 } 287 288 static int check_crc(u8 *buf, int buflen) 289 { 290 int len; 291 u16 crc; 292 293 len = buf[0] + 1; 294 crc = crc_ccitt(0xffff, buf, len - 2); 295 crc = ~crc; 296 297 if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) { 298 pr_err("CRC error 0x%x != 0x%x 0x%x\n", 299 crc, buf[len - 1], buf[len - 2]); 300 pr_info("%s: BAD CRC\n", __func__); 301 print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE, 302 16, 2, buf, buflen, false); 303 return -EPERM; 304 } 305 return 0; 306 } 307 308 /* 309 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees 310 * that i2c bus will be flushed and that next read will start on a new frame. 311 * returned skb contains only LLC header and payload. 312 * returns: 313 * -EREMOTEIO : i2c read error (fatal) 314 * -EBADMSG : frame was incorrect and discarded 315 * -ENOMEM : cannot allocate skb, frame dropped 316 */ 317 static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb) 318 { 319 int r; 320 u8 len; 321 u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1]; 322 struct i2c_client *client = phy->i2c_dev; 323 324 r = i2c_master_recv(client, &len, 1); 325 if (r != 1) { 326 nfc_err(&client->dev, "cannot read len byte\n"); 327 return -EREMOTEIO; 328 } 329 330 if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) || 331 (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) { 332 nfc_err(&client->dev, "invalid len byte\n"); 333 r = -EBADMSG; 334 goto flush; 335 } 336 337 *skb = alloc_skb(1 + len, GFP_KERNEL); 338 if (*skb == NULL) { 339 r = -ENOMEM; 340 goto flush; 341 } 342 343 *skb_put(*skb, 1) = len; 344 345 r = i2c_master_recv(client, skb_put(*skb, len), len); 346 if (r != len) { 347 kfree_skb(*skb); 348 return -EREMOTEIO; 349 } 350 351 I2C_DUMP_SKB("i2c frame read", *skb); 352 353 r = check_crc((*skb)->data, (*skb)->len); 354 if (r != 0) { 355 kfree_skb(*skb); 356 r = -EBADMSG; 357 goto flush; 358 } 359 360 skb_pull(*skb, 1); 361 skb_trim(*skb, (*skb)->len - 2); 362 363 usleep_range(3000, 6000); 364 365 return 0; 366 367 flush: 368 if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0) 369 r = -EREMOTEIO; 370 371 usleep_range(3000, 6000); 372 373 return r; 374 } 375 376 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy) 377 { 378 int r; 379 struct pn544_i2c_fw_frame_response response; 380 struct i2c_client *client = phy->i2c_dev; 381 382 r = i2c_master_recv(client, (char *) &response, sizeof(response)); 383 if (r != sizeof(response)) { 384 nfc_err(&client->dev, "cannot read fw status\n"); 385 return -EIO; 386 } 387 388 usleep_range(3000, 6000); 389 390 switch (response.status) { 391 case 0: 392 return 0; 393 case PN544_FW_CMD_RESULT_TIMEOUT: 394 return -ETIMEDOUT; 395 case PN544_FW_CMD_RESULT_BAD_CRC: 396 return -ENODATA; 397 case PN544_FW_CMD_RESULT_ACCESS_DENIED: 398 return -EACCES; 399 case PN544_FW_CMD_RESULT_PROTOCOL_ERROR: 400 return -EPROTO; 401 case PN544_FW_CMD_RESULT_INVALID_PARAMETER: 402 return -EINVAL; 403 case PN544_FW_CMD_RESULT_INVALID_LENGTH: 404 return -EBADMSG; 405 case PN544_FW_CMD_RESULT_WRITE_FAILED: 406 return -EIO; 407 default: 408 return -EIO; 409 } 410 } 411 412 /* 413 * Reads an shdlc frame from the chip. This is not as straightforward as it 414 * seems. There are cases where we could loose the frame start synchronization. 415 * The frame format is len-data-crc, and corruption can occur anywhere while 416 * transiting on i2c bus, such that we could read an invalid len. 417 * In order to recover synchronization with the next frame, we must be sure 418 * to read the real amount of data without using the len byte. We do this by 419 * assuming the following: 420 * - the chip will always present only one single complete frame on the bus 421 * before triggering the interrupt 422 * - the chip will not present a new frame until we have completely read 423 * the previous one (or until we have handled the interrupt). 424 * The tricky case is when we read a corrupted len that is less than the real 425 * len. We must detect this here in order to determine that we need to flush 426 * the bus. This is the reason why we check the crc here. 427 */ 428 static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id) 429 { 430 struct pn544_i2c_phy *phy = phy_id; 431 struct i2c_client *client; 432 struct sk_buff *skb = NULL; 433 int r; 434 435 if (!phy || irq != phy->i2c_dev->irq) { 436 WARN_ON_ONCE(1); 437 return IRQ_NONE; 438 } 439 440 client = phy->i2c_dev; 441 dev_dbg(&client->dev, "IRQ\n"); 442 443 if (phy->hard_fault != 0) 444 return IRQ_HANDLED; 445 446 if (phy->run_mode == PN544_FW_MODE) { 447 phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy); 448 schedule_work(&phy->fw_work); 449 } else { 450 r = pn544_hci_i2c_read(phy, &skb); 451 if (r == -EREMOTEIO) { 452 phy->hard_fault = r; 453 454 nfc_hci_recv_frame(phy->hdev, NULL); 455 456 return IRQ_HANDLED; 457 } else if ((r == -ENOMEM) || (r == -EBADMSG)) { 458 return IRQ_HANDLED; 459 } 460 461 nfc_hci_recv_frame(phy->hdev, skb); 462 } 463 return IRQ_HANDLED; 464 } 465 466 static struct nfc_phy_ops i2c_phy_ops = { 467 .write = pn544_hci_i2c_write, 468 .enable = pn544_hci_i2c_enable, 469 .disable = pn544_hci_i2c_disable, 470 }; 471 472 static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name) 473 { 474 struct pn544_i2c_phy *phy = phy_id; 475 476 pr_info("Starting Firmware Download (%s)\n", firmware_name); 477 478 strcpy(phy->firmware_name, firmware_name); 479 480 phy->fw_work_state = FW_WORK_STATE_START; 481 482 schedule_work(&phy->fw_work); 483 484 return 0; 485 } 486 487 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy, 488 int result) 489 { 490 pr_info("Firmware Download Complete, result=%d\n", result); 491 492 pn544_hci_i2c_disable(phy); 493 494 phy->fw_work_state = FW_WORK_STATE_IDLE; 495 496 if (phy->fw) { 497 release_firmware(phy->fw); 498 phy->fw = NULL; 499 } 500 501 nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result); 502 } 503 504 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr, 505 const u8 *data, u16 datalen) 506 { 507 u8 frame[PN544_FW_I2C_MAX_PAYLOAD]; 508 struct pn544_i2c_fw_frame_write *framep; 509 u16 params_len; 510 int framelen; 511 int r; 512 513 if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN) 514 datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN; 515 516 framep = (struct pn544_i2c_fw_frame_write *) frame; 517 518 params_len = sizeof(framep->be_dest_addr) + 519 sizeof(framep->be_datalen) + datalen; 520 framelen = params_len + sizeof(framep->cmd) + 521 sizeof(framep->be_length); 522 523 framep->cmd = PN544_FW_CMD_WRITE; 524 525 put_unaligned_be16(params_len, &framep->be_length); 526 527 framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16; 528 framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8; 529 framep->be_dest_addr[2] = dest_addr & 0xff; 530 531 put_unaligned_be16(datalen, &framep->be_datalen); 532 533 memcpy(framep->data, data, datalen); 534 535 r = i2c_master_send(client, frame, framelen); 536 537 if (r == framelen) 538 return datalen; 539 else if (r < 0) 540 return r; 541 else 542 return -EIO; 543 } 544 545 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr, 546 const u8 *data, u16 datalen) 547 { 548 struct pn544_i2c_fw_frame_check frame; 549 int r; 550 u16 crc; 551 552 /* calculate local crc for the data we want to check */ 553 crc = crc_ccitt(0xffff, data, datalen); 554 555 frame.cmd = PN544_FW_CMD_CHECK; 556 557 put_unaligned_be16(sizeof(frame.be_start_addr) + 558 sizeof(frame.be_datalen) + sizeof(frame.be_crc), 559 &frame.be_length); 560 561 /* tell the chip the memory region to which our crc applies */ 562 frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16; 563 frame.be_start_addr[1] = (start_addr & 0xff00) >> 8; 564 frame.be_start_addr[2] = start_addr & 0xff; 565 566 put_unaligned_be16(datalen, &frame.be_datalen); 567 568 /* 569 * and give our local crc. Chip will calculate its own crc for the 570 * region and compare with ours. 571 */ 572 put_unaligned_be16(crc, &frame.be_crc); 573 574 r = i2c_master_send(client, (const char *) &frame, sizeof(frame)); 575 576 if (r == sizeof(frame)) 577 return 0; 578 else if (r < 0) 579 return r; 580 else 581 return -EIO; 582 } 583 584 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy) 585 { 586 int r; 587 588 r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev, 589 phy->fw_blob_dest_addr + phy->fw_written, 590 phy->fw_blob_data + phy->fw_written, 591 phy->fw_blob_size - phy->fw_written); 592 if (r < 0) 593 return r; 594 595 phy->fw_written += r; 596 phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER; 597 598 return 0; 599 } 600 601 static void pn544_hci_i2c_fw_work(struct work_struct *work) 602 { 603 struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy, 604 fw_work); 605 int r; 606 struct pn544_i2c_fw_blob *blob; 607 608 switch (phy->fw_work_state) { 609 case FW_WORK_STATE_START: 610 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 611 612 r = request_firmware(&phy->fw, phy->firmware_name, 613 &phy->i2c_dev->dev); 614 if (r < 0) 615 goto exit_state_start; 616 617 blob = (struct pn544_i2c_fw_blob *) phy->fw->data; 618 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 619 phy->fw_blob_dest_addr = get_unaligned_be32(&blob->be_destaddr); 620 phy->fw_blob_data = blob->data; 621 622 phy->fw_written = 0; 623 r = pn544_hci_i2c_fw_write_chunk(phy); 624 625 exit_state_start: 626 if (r < 0) 627 pn544_hci_i2c_fw_work_complete(phy, r); 628 break; 629 630 case FW_WORK_STATE_WAIT_WRITE_ANSWER: 631 r = phy->fw_cmd_result; 632 if (r < 0) 633 goto exit_state_wait_write_answer; 634 635 if (phy->fw_written == phy->fw_blob_size) { 636 r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev, 637 phy->fw_blob_dest_addr, 638 phy->fw_blob_data, 639 phy->fw_blob_size); 640 if (r < 0) 641 goto exit_state_wait_write_answer; 642 phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER; 643 break; 644 } 645 646 r = pn544_hci_i2c_fw_write_chunk(phy); 647 648 exit_state_wait_write_answer: 649 if (r < 0) 650 pn544_hci_i2c_fw_work_complete(phy, r); 651 break; 652 653 case FW_WORK_STATE_WAIT_CHECK_ANSWER: 654 r = phy->fw_cmd_result; 655 if (r < 0) 656 goto exit_state_wait_check_answer; 657 658 blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data + 659 phy->fw_blob_size); 660 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 661 if (phy->fw_blob_size != 0) { 662 phy->fw_blob_dest_addr = 663 get_unaligned_be32(&blob->be_destaddr); 664 phy->fw_blob_data = blob->data; 665 666 phy->fw_written = 0; 667 r = pn544_hci_i2c_fw_write_chunk(phy); 668 } 669 670 exit_state_wait_check_answer: 671 if (r < 0 || phy->fw_blob_size == 0) 672 pn544_hci_i2c_fw_work_complete(phy, r); 673 break; 674 675 default: 676 break; 677 } 678 } 679 680 static int pn544_hci_i2c_probe(struct i2c_client *client, 681 const struct i2c_device_id *id) 682 { 683 struct pn544_i2c_phy *phy; 684 struct pn544_nfc_platform_data *pdata; 685 int r = 0; 686 687 dev_dbg(&client->dev, "%s\n", __func__); 688 dev_dbg(&client->dev, "IRQ: %d\n", client->irq); 689 690 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 691 nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); 692 return -ENODEV; 693 } 694 695 phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy), 696 GFP_KERNEL); 697 if (!phy) { 698 nfc_err(&client->dev, 699 "Cannot allocate memory for pn544 i2c phy.\n"); 700 return -ENOMEM; 701 } 702 703 INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work); 704 phy->fw_work_state = FW_WORK_STATE_IDLE; 705 706 phy->i2c_dev = client; 707 i2c_set_clientdata(client, phy); 708 709 pdata = client->dev.platform_data; 710 if (pdata == NULL) { 711 nfc_err(&client->dev, "No platform data\n"); 712 return -EINVAL; 713 } 714 715 if (pdata->request_resources == NULL) { 716 nfc_err(&client->dev, "request_resources() missing\n"); 717 return -EINVAL; 718 } 719 720 r = pdata->request_resources(client); 721 if (r) { 722 nfc_err(&client->dev, "Cannot get platform resources\n"); 723 return r; 724 } 725 726 phy->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE); 727 phy->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET); 728 phy->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ); 729 730 pn544_hci_i2c_platform_init(phy); 731 732 r = request_threaded_irq(client->irq, NULL, pn544_hci_i2c_irq_thread_fn, 733 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 734 PN544_HCI_I2C_DRIVER_NAME, phy); 735 if (r < 0) { 736 nfc_err(&client->dev, "Unable to register IRQ handler\n"); 737 goto err_rti; 738 } 739 740 r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME, 741 PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM, 742 PN544_HCI_I2C_LLC_MAX_PAYLOAD, 743 pn544_hci_i2c_fw_download, &phy->hdev); 744 if (r < 0) 745 goto err_hci; 746 747 return 0; 748 749 err_hci: 750 free_irq(client->irq, phy); 751 752 err_rti: 753 if (pdata->free_resources != NULL) 754 pdata->free_resources(); 755 756 return r; 757 } 758 759 static int pn544_hci_i2c_remove(struct i2c_client *client) 760 { 761 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 762 struct pn544_nfc_platform_data *pdata = client->dev.platform_data; 763 764 dev_dbg(&client->dev, "%s\n", __func__); 765 766 cancel_work_sync(&phy->fw_work); 767 if (phy->fw_work_state != FW_WORK_STATE_IDLE) 768 pn544_hci_i2c_fw_work_complete(phy, -ENODEV); 769 770 pn544_hci_remove(phy->hdev); 771 772 if (phy->powered) 773 pn544_hci_i2c_disable(phy); 774 775 free_irq(client->irq, phy); 776 if (pdata->free_resources) 777 pdata->free_resources(); 778 779 return 0; 780 } 781 782 static struct i2c_driver pn544_hci_i2c_driver = { 783 .driver = { 784 .name = PN544_HCI_I2C_DRIVER_NAME, 785 }, 786 .probe = pn544_hci_i2c_probe, 787 .id_table = pn544_hci_i2c_id_table, 788 .remove = pn544_hci_i2c_remove, 789 }; 790 791 module_i2c_driver(pn544_hci_i2c_driver); 792 793 MODULE_LICENSE("GPL"); 794 MODULE_DESCRIPTION(DRIVER_DESC); 795