1 /* 2 * I2C Link Layer for PN544 HCI based Driver 3 * 4 * Copyright (C) 2012 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/crc-ccitt.h> 22 #include <linux/module.h> 23 #include <linux/i2c.h> 24 #include <linux/gpio.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_irq.h> 27 #include <linux/miscdevice.h> 28 #include <linux/interrupt.h> 29 #include <linux/delay.h> 30 #include <linux/nfc.h> 31 #include <linux/firmware.h> 32 #include <linux/platform_data/pn544.h> 33 #include <asm/unaligned.h> 34 35 #include <net/nfc/hci.h> 36 #include <net/nfc/llc.h> 37 #include <net/nfc/nfc.h> 38 39 #include "pn544.h" 40 41 #define PN544_I2C_FRAME_HEADROOM 1 42 #define PN544_I2C_FRAME_TAILROOM 2 43 44 /* framing in HCI mode */ 45 #define PN544_HCI_I2C_LLC_LEN 1 46 #define PN544_HCI_I2C_LLC_CRC 2 47 #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \ 48 PN544_HCI_I2C_LLC_CRC) 49 #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC) 50 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29 51 #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \ 52 PN544_HCI_I2C_LLC_MAX_PAYLOAD) 53 54 static struct i2c_device_id pn544_hci_i2c_id_table[] = { 55 {"pn544", 0}, 56 {} 57 }; 58 59 MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table); 60 61 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c" 62 63 /* 64 * Exposed through the 4 most significant bytes 65 * from the HCI SW_VERSION first byte, a.k.a. 66 * SW RomLib. 67 */ 68 #define PN544_HW_VARIANT_C2 0xa 69 #define PN544_HW_VARIANT_C3 0xb 70 71 #define PN544_FW_CMD_RESET 0x01 72 #define PN544_FW_CMD_WRITE 0x08 73 #define PN544_FW_CMD_CHECK 0x06 74 #define PN544_FW_CMD_SECURE_WRITE 0x0C 75 #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D 76 77 struct pn544_i2c_fw_frame_write { 78 u8 cmd; 79 u16 be_length; 80 u8 be_dest_addr[3]; 81 u16 be_datalen; 82 u8 data[]; 83 } __packed; 84 85 struct pn544_i2c_fw_frame_check { 86 u8 cmd; 87 u16 be_length; 88 u8 be_start_addr[3]; 89 u16 be_datalen; 90 u16 be_crc; 91 } __packed; 92 93 struct pn544_i2c_fw_frame_response { 94 u8 status; 95 u16 be_length; 96 } __packed; 97 98 struct pn544_i2c_fw_blob { 99 u32 be_size; 100 u32 be_destaddr; 101 u8 data[]; 102 }; 103 104 struct pn544_i2c_fw_secure_frame { 105 u8 cmd; 106 u16 be_datalen; 107 u8 data[]; 108 } __packed; 109 110 struct pn544_i2c_fw_secure_blob { 111 u64 header; 112 u8 data[]; 113 }; 114 115 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01 116 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02 117 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08 118 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B 119 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11 120 #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13 121 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18 122 #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19 123 #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D 124 #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20 125 #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21 126 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74 127 #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0 128 #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6 129 130 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 131 132 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7 133 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE 134 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8 135 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\ 136 PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\ 137 PN544_FW_WRITE_BUFFER_MAX_LEN) 138 #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3 139 #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\ 140 PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN) 141 #define PN544_FW_SECURE_FRAME_HEADER_LEN 3 142 #define PN544_FW_SECURE_BLOB_HEADER_LEN 8 143 144 #define FW_WORK_STATE_IDLE 1 145 #define FW_WORK_STATE_START 2 146 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3 147 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4 148 #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5 149 150 struct pn544_i2c_phy { 151 struct i2c_client *i2c_dev; 152 struct nfc_hci_dev *hdev; 153 154 unsigned int gpio_en; 155 unsigned int gpio_irq; 156 unsigned int gpio_fw; 157 unsigned int en_polarity; 158 159 u8 hw_variant; 160 161 struct work_struct fw_work; 162 int fw_work_state; 163 char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1]; 164 const struct firmware *fw; 165 u32 fw_blob_dest_addr; 166 size_t fw_blob_size; 167 const u8 *fw_blob_data; 168 size_t fw_written; 169 size_t fw_size; 170 171 int fw_cmd_result; 172 173 int powered; 174 int run_mode; 175 176 int hard_fault; /* 177 * < 0 if hardware error occured (e.g. i2c err) 178 * and prevents normal operation. 179 */ 180 }; 181 182 #define I2C_DUMP_SKB(info, skb) \ 183 do { \ 184 pr_debug("%s:\n", info); \ 185 print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ 186 16, 1, (skb)->data, (skb)->len, 0); \ 187 } while (0) 188 189 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) 190 { 191 int polarity, retry, ret; 192 char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 }; 193 int count = sizeof(rset_cmd); 194 195 nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); 196 197 /* Disable fw download */ 198 gpio_set_value(phy->gpio_fw, 0); 199 200 for (polarity = 0; polarity < 2; polarity++) { 201 phy->en_polarity = polarity; 202 retry = 3; 203 while (retry--) { 204 /* power off */ 205 gpio_set_value(phy->gpio_en, !phy->en_polarity); 206 usleep_range(10000, 15000); 207 208 /* power on */ 209 gpio_set_value(phy->gpio_en, phy->en_polarity); 210 usleep_range(10000, 15000); 211 212 /* send reset */ 213 dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n"); 214 ret = i2c_master_send(phy->i2c_dev, rset_cmd, count); 215 if (ret == count) { 216 nfc_info(&phy->i2c_dev->dev, 217 "nfc_en polarity : active %s\n", 218 (polarity == 0 ? "low" : "high")); 219 goto out; 220 } 221 } 222 } 223 224 nfc_err(&phy->i2c_dev->dev, 225 "Could not detect nfc_en polarity, fallback to active high\n"); 226 227 out: 228 gpio_set_value(phy->gpio_en, !phy->en_polarity); 229 } 230 231 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode) 232 { 233 gpio_set_value(phy->gpio_fw, run_mode == PN544_FW_MODE ? 1 : 0); 234 gpio_set_value(phy->gpio_en, phy->en_polarity); 235 usleep_range(10000, 15000); 236 237 phy->run_mode = run_mode; 238 } 239 240 static int pn544_hci_i2c_enable(void *phy_id) 241 { 242 struct pn544_i2c_phy *phy = phy_id; 243 244 pr_info("%s\n", __func__); 245 246 pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE); 247 248 phy->powered = 1; 249 250 return 0; 251 } 252 253 static void pn544_hci_i2c_disable(void *phy_id) 254 { 255 struct pn544_i2c_phy *phy = phy_id; 256 257 gpio_set_value(phy->gpio_fw, 0); 258 gpio_set_value(phy->gpio_en, !phy->en_polarity); 259 usleep_range(10000, 15000); 260 261 gpio_set_value(phy->gpio_en, phy->en_polarity); 262 usleep_range(10000, 15000); 263 264 gpio_set_value(phy->gpio_en, !phy->en_polarity); 265 usleep_range(10000, 15000); 266 267 phy->powered = 0; 268 } 269 270 static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb) 271 { 272 u16 crc; 273 int len; 274 275 len = skb->len + 2; 276 *skb_push(skb, 1) = len; 277 278 crc = crc_ccitt(0xffff, skb->data, skb->len); 279 crc = ~crc; 280 *skb_put(skb, 1) = crc & 0xff; 281 *skb_put(skb, 1) = crc >> 8; 282 } 283 284 static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb) 285 { 286 skb_pull(skb, PN544_I2C_FRAME_HEADROOM); 287 skb_trim(skb, PN544_I2C_FRAME_TAILROOM); 288 } 289 290 /* 291 * Writing a frame must not return the number of written bytes. 292 * It must return either zero for success, or <0 for error. 293 * In addition, it must not alter the skb 294 */ 295 static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb) 296 { 297 int r; 298 struct pn544_i2c_phy *phy = phy_id; 299 struct i2c_client *client = phy->i2c_dev; 300 301 if (phy->hard_fault != 0) 302 return phy->hard_fault; 303 304 usleep_range(3000, 6000); 305 306 pn544_hci_i2c_add_len_crc(skb); 307 308 I2C_DUMP_SKB("i2c frame written", skb); 309 310 r = i2c_master_send(client, skb->data, skb->len); 311 312 if (r == -EREMOTEIO) { /* Retry, chip was in standby */ 313 usleep_range(6000, 10000); 314 r = i2c_master_send(client, skb->data, skb->len); 315 } 316 317 if (r >= 0) { 318 if (r != skb->len) 319 r = -EREMOTEIO; 320 else 321 r = 0; 322 } 323 324 pn544_hci_i2c_remove_len_crc(skb); 325 326 return r; 327 } 328 329 static int check_crc(u8 *buf, int buflen) 330 { 331 int len; 332 u16 crc; 333 334 len = buf[0] + 1; 335 crc = crc_ccitt(0xffff, buf, len - 2); 336 crc = ~crc; 337 338 if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) { 339 pr_err("CRC error 0x%x != 0x%x 0x%x\n", 340 crc, buf[len - 1], buf[len - 2]); 341 pr_info("%s: BAD CRC\n", __func__); 342 print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE, 343 16, 2, buf, buflen, false); 344 return -EPERM; 345 } 346 return 0; 347 } 348 349 /* 350 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees 351 * that i2c bus will be flushed and that next read will start on a new frame. 352 * returned skb contains only LLC header and payload. 353 * returns: 354 * -EREMOTEIO : i2c read error (fatal) 355 * -EBADMSG : frame was incorrect and discarded 356 * -ENOMEM : cannot allocate skb, frame dropped 357 */ 358 static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb) 359 { 360 int r; 361 u8 len; 362 u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1]; 363 struct i2c_client *client = phy->i2c_dev; 364 365 r = i2c_master_recv(client, &len, 1); 366 if (r != 1) { 367 nfc_err(&client->dev, "cannot read len byte\n"); 368 return -EREMOTEIO; 369 } 370 371 if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) || 372 (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) { 373 nfc_err(&client->dev, "invalid len byte\n"); 374 r = -EBADMSG; 375 goto flush; 376 } 377 378 *skb = alloc_skb(1 + len, GFP_KERNEL); 379 if (*skb == NULL) { 380 r = -ENOMEM; 381 goto flush; 382 } 383 384 *skb_put(*skb, 1) = len; 385 386 r = i2c_master_recv(client, skb_put(*skb, len), len); 387 if (r != len) { 388 kfree_skb(*skb); 389 return -EREMOTEIO; 390 } 391 392 I2C_DUMP_SKB("i2c frame read", *skb); 393 394 r = check_crc((*skb)->data, (*skb)->len); 395 if (r != 0) { 396 kfree_skb(*skb); 397 r = -EBADMSG; 398 goto flush; 399 } 400 401 skb_pull(*skb, 1); 402 skb_trim(*skb, (*skb)->len - 2); 403 404 usleep_range(3000, 6000); 405 406 return 0; 407 408 flush: 409 if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0) 410 r = -EREMOTEIO; 411 412 usleep_range(3000, 6000); 413 414 return r; 415 } 416 417 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy) 418 { 419 int r; 420 struct pn544_i2c_fw_frame_response response; 421 struct i2c_client *client = phy->i2c_dev; 422 423 r = i2c_master_recv(client, (char *) &response, sizeof(response)); 424 if (r != sizeof(response)) { 425 nfc_err(&client->dev, "cannot read fw status\n"); 426 return -EIO; 427 } 428 429 usleep_range(3000, 6000); 430 431 switch (response.status) { 432 case 0: 433 return 0; 434 case PN544_FW_CMD_RESULT_CHUNK_OK: 435 return response.status; 436 case PN544_FW_CMD_RESULT_TIMEOUT: 437 return -ETIMEDOUT; 438 case PN544_FW_CMD_RESULT_BAD_CRC: 439 return -ENODATA; 440 case PN544_FW_CMD_RESULT_ACCESS_DENIED: 441 return -EACCES; 442 case PN544_FW_CMD_RESULT_PROTOCOL_ERROR: 443 return -EPROTO; 444 case PN544_FW_CMD_RESULT_INVALID_PARAMETER: 445 return -EINVAL; 446 case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND: 447 return -ENOTSUPP; 448 case PN544_FW_CMD_RESULT_INVALID_LENGTH: 449 return -EBADMSG; 450 case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR: 451 return -ENOKEY; 452 case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR: 453 return -EINVAL; 454 case PN544_FW_CMD_RESULT_MEMORY_ERROR: 455 return -ENOMEM; 456 case PN544_FW_CMD_RESULT_COMMAND_REJECTED: 457 return -EACCES; 458 case PN544_FW_CMD_RESULT_WRITE_FAILED: 459 case PN544_FW_CMD_RESULT_CHUNK_ERROR: 460 return -EIO; 461 default: 462 return -EIO; 463 } 464 } 465 466 /* 467 * Reads an shdlc frame from the chip. This is not as straightforward as it 468 * seems. There are cases where we could loose the frame start synchronization. 469 * The frame format is len-data-crc, and corruption can occur anywhere while 470 * transiting on i2c bus, such that we could read an invalid len. 471 * In order to recover synchronization with the next frame, we must be sure 472 * to read the real amount of data without using the len byte. We do this by 473 * assuming the following: 474 * - the chip will always present only one single complete frame on the bus 475 * before triggering the interrupt 476 * - the chip will not present a new frame until we have completely read 477 * the previous one (or until we have handled the interrupt). 478 * The tricky case is when we read a corrupted len that is less than the real 479 * len. We must detect this here in order to determine that we need to flush 480 * the bus. This is the reason why we check the crc here. 481 */ 482 static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id) 483 { 484 struct pn544_i2c_phy *phy = phy_id; 485 struct i2c_client *client; 486 struct sk_buff *skb = NULL; 487 int r; 488 489 if (!phy || irq != phy->i2c_dev->irq) { 490 WARN_ON_ONCE(1); 491 return IRQ_NONE; 492 } 493 494 client = phy->i2c_dev; 495 dev_dbg(&client->dev, "IRQ\n"); 496 497 if (phy->hard_fault != 0) 498 return IRQ_HANDLED; 499 500 if (phy->run_mode == PN544_FW_MODE) { 501 phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy); 502 schedule_work(&phy->fw_work); 503 } else { 504 r = pn544_hci_i2c_read(phy, &skb); 505 if (r == -EREMOTEIO) { 506 phy->hard_fault = r; 507 508 nfc_hci_recv_frame(phy->hdev, NULL); 509 510 return IRQ_HANDLED; 511 } else if ((r == -ENOMEM) || (r == -EBADMSG)) { 512 return IRQ_HANDLED; 513 } 514 515 nfc_hci_recv_frame(phy->hdev, skb); 516 } 517 return IRQ_HANDLED; 518 } 519 520 static struct nfc_phy_ops i2c_phy_ops = { 521 .write = pn544_hci_i2c_write, 522 .enable = pn544_hci_i2c_enable, 523 .disable = pn544_hci_i2c_disable, 524 }; 525 526 static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name, 527 u8 hw_variant) 528 { 529 struct pn544_i2c_phy *phy = phy_id; 530 531 pr_info("Starting Firmware Download (%s)\n", firmware_name); 532 533 strcpy(phy->firmware_name, firmware_name); 534 535 phy->hw_variant = hw_variant; 536 phy->fw_work_state = FW_WORK_STATE_START; 537 538 schedule_work(&phy->fw_work); 539 540 return 0; 541 } 542 543 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy, 544 int result) 545 { 546 pr_info("Firmware Download Complete, result=%d\n", result); 547 548 pn544_hci_i2c_disable(phy); 549 550 phy->fw_work_state = FW_WORK_STATE_IDLE; 551 552 if (phy->fw) { 553 release_firmware(phy->fw); 554 phy->fw = NULL; 555 } 556 557 nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result); 558 } 559 560 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr, 561 const u8 *data, u16 datalen) 562 { 563 u8 frame[PN544_FW_I2C_MAX_PAYLOAD]; 564 struct pn544_i2c_fw_frame_write *framep; 565 u16 params_len; 566 int framelen; 567 int r; 568 569 if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN) 570 datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN; 571 572 framep = (struct pn544_i2c_fw_frame_write *) frame; 573 574 params_len = sizeof(framep->be_dest_addr) + 575 sizeof(framep->be_datalen) + datalen; 576 framelen = params_len + sizeof(framep->cmd) + 577 sizeof(framep->be_length); 578 579 framep->cmd = PN544_FW_CMD_WRITE; 580 581 put_unaligned_be16(params_len, &framep->be_length); 582 583 framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16; 584 framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8; 585 framep->be_dest_addr[2] = dest_addr & 0xff; 586 587 put_unaligned_be16(datalen, &framep->be_datalen); 588 589 memcpy(framep->data, data, datalen); 590 591 r = i2c_master_send(client, frame, framelen); 592 593 if (r == framelen) 594 return datalen; 595 else if (r < 0) 596 return r; 597 else 598 return -EIO; 599 } 600 601 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr, 602 const u8 *data, u16 datalen) 603 { 604 struct pn544_i2c_fw_frame_check frame; 605 int r; 606 u16 crc; 607 608 /* calculate local crc for the data we want to check */ 609 crc = crc_ccitt(0xffff, data, datalen); 610 611 frame.cmd = PN544_FW_CMD_CHECK; 612 613 put_unaligned_be16(sizeof(frame.be_start_addr) + 614 sizeof(frame.be_datalen) + sizeof(frame.be_crc), 615 &frame.be_length); 616 617 /* tell the chip the memory region to which our crc applies */ 618 frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16; 619 frame.be_start_addr[1] = (start_addr & 0xff00) >> 8; 620 frame.be_start_addr[2] = start_addr & 0xff; 621 622 put_unaligned_be16(datalen, &frame.be_datalen); 623 624 /* 625 * and give our local crc. Chip will calculate its own crc for the 626 * region and compare with ours. 627 */ 628 put_unaligned_be16(crc, &frame.be_crc); 629 630 r = i2c_master_send(client, (const char *) &frame, sizeof(frame)); 631 632 if (r == sizeof(frame)) 633 return 0; 634 else if (r < 0) 635 return r; 636 else 637 return -EIO; 638 } 639 640 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy) 641 { 642 int r; 643 644 r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev, 645 phy->fw_blob_dest_addr + phy->fw_written, 646 phy->fw_blob_data + phy->fw_written, 647 phy->fw_blob_size - phy->fw_written); 648 if (r < 0) 649 return r; 650 651 phy->fw_written += r; 652 phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER; 653 654 return 0; 655 } 656 657 static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy, 658 const u8 *data, u16 datalen) 659 { 660 u8 buf[PN544_FW_I2C_MAX_PAYLOAD]; 661 struct pn544_i2c_fw_secure_frame *chunk; 662 int chunklen; 663 int r; 664 665 if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN) 666 datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN; 667 668 chunk = (struct pn544_i2c_fw_secure_frame *) buf; 669 670 chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE; 671 672 put_unaligned_be16(datalen, &chunk->be_datalen); 673 674 memcpy(chunk->data, data, datalen); 675 676 chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen; 677 678 r = i2c_master_send(phy->i2c_dev, buf, chunklen); 679 680 if (r == chunklen) 681 return datalen; 682 else if (r < 0) 683 return r; 684 else 685 return -EIO; 686 687 } 688 689 static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy) 690 { 691 struct pn544_i2c_fw_secure_frame *framep; 692 int r; 693 694 framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data; 695 if (phy->fw_written == 0) 696 phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen) 697 + PN544_FW_SECURE_FRAME_HEADER_LEN; 698 699 /* Only secure write command can be chunked*/ 700 if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD && 701 framep->cmd != PN544_FW_CMD_SECURE_WRITE) 702 return -EINVAL; 703 704 /* The firmware also have other commands, we just send them directly */ 705 if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) { 706 r = i2c_master_send(phy->i2c_dev, 707 (const char *) phy->fw_blob_data, phy->fw_blob_size); 708 709 if (r == phy->fw_blob_size) 710 goto exit; 711 else if (r < 0) 712 return r; 713 else 714 return -EIO; 715 } 716 717 r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy, 718 phy->fw_blob_data + phy->fw_written, 719 phy->fw_blob_size - phy->fw_written); 720 if (r < 0) 721 return r; 722 723 exit: 724 phy->fw_written += r; 725 phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER; 726 727 /* SW reset command will not trig any response from PN544 */ 728 if (framep->cmd == PN544_FW_CMD_RESET) { 729 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 730 phy->fw_cmd_result = 0; 731 schedule_work(&phy->fw_work); 732 } 733 734 return 0; 735 } 736 737 static void pn544_hci_i2c_fw_work(struct work_struct *work) 738 { 739 struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy, 740 fw_work); 741 int r; 742 struct pn544_i2c_fw_blob *blob; 743 struct pn544_i2c_fw_secure_blob *secure_blob; 744 745 switch (phy->fw_work_state) { 746 case FW_WORK_STATE_START: 747 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 748 749 r = request_firmware(&phy->fw, phy->firmware_name, 750 &phy->i2c_dev->dev); 751 if (r < 0) 752 goto exit_state_start; 753 754 phy->fw_written = 0; 755 756 switch (phy->hw_variant) { 757 case PN544_HW_VARIANT_C2: 758 blob = (struct pn544_i2c_fw_blob *) phy->fw->data; 759 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 760 phy->fw_blob_dest_addr = get_unaligned_be32( 761 &blob->be_destaddr); 762 phy->fw_blob_data = blob->data; 763 764 r = pn544_hci_i2c_fw_write_chunk(phy); 765 break; 766 case PN544_HW_VARIANT_C3: 767 secure_blob = (struct pn544_i2c_fw_secure_blob *) 768 phy->fw->data; 769 phy->fw_blob_data = secure_blob->data; 770 phy->fw_size = phy->fw->size; 771 r = pn544_hci_i2c_fw_secure_write_frame(phy); 772 break; 773 default: 774 r = -ENOTSUPP; 775 break; 776 } 777 778 exit_state_start: 779 if (r < 0) 780 pn544_hci_i2c_fw_work_complete(phy, r); 781 break; 782 783 case FW_WORK_STATE_WAIT_WRITE_ANSWER: 784 r = phy->fw_cmd_result; 785 if (r < 0) 786 goto exit_state_wait_write_answer; 787 788 if (phy->fw_written == phy->fw_blob_size) { 789 r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev, 790 phy->fw_blob_dest_addr, 791 phy->fw_blob_data, 792 phy->fw_blob_size); 793 if (r < 0) 794 goto exit_state_wait_write_answer; 795 phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER; 796 break; 797 } 798 799 r = pn544_hci_i2c_fw_write_chunk(phy); 800 801 exit_state_wait_write_answer: 802 if (r < 0) 803 pn544_hci_i2c_fw_work_complete(phy, r); 804 break; 805 806 case FW_WORK_STATE_WAIT_CHECK_ANSWER: 807 r = phy->fw_cmd_result; 808 if (r < 0) 809 goto exit_state_wait_check_answer; 810 811 blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data + 812 phy->fw_blob_size); 813 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 814 if (phy->fw_blob_size != 0) { 815 phy->fw_blob_dest_addr = 816 get_unaligned_be32(&blob->be_destaddr); 817 phy->fw_blob_data = blob->data; 818 819 phy->fw_written = 0; 820 r = pn544_hci_i2c_fw_write_chunk(phy); 821 } 822 823 exit_state_wait_check_answer: 824 if (r < 0 || phy->fw_blob_size == 0) 825 pn544_hci_i2c_fw_work_complete(phy, r); 826 break; 827 828 case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER: 829 r = phy->fw_cmd_result; 830 if (r < 0) 831 goto exit_state_wait_secure_write_answer; 832 833 if (r == PN544_FW_CMD_RESULT_CHUNK_OK) { 834 r = pn544_hci_i2c_fw_secure_write_frame(phy); 835 goto exit_state_wait_secure_write_answer; 836 } 837 838 if (phy->fw_written == phy->fw_blob_size) { 839 secure_blob = (struct pn544_i2c_fw_secure_blob *) 840 (phy->fw_blob_data + phy->fw_blob_size); 841 phy->fw_size -= phy->fw_blob_size + 842 PN544_FW_SECURE_BLOB_HEADER_LEN; 843 if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN 844 + PN544_FW_SECURE_FRAME_HEADER_LEN) { 845 phy->fw_blob_data = secure_blob->data; 846 847 phy->fw_written = 0; 848 r = pn544_hci_i2c_fw_secure_write_frame(phy); 849 } 850 } 851 852 exit_state_wait_secure_write_answer: 853 if (r < 0 || phy->fw_size == 0) 854 pn544_hci_i2c_fw_work_complete(phy, r); 855 break; 856 857 default: 858 break; 859 } 860 } 861 862 #ifdef CONFIG_OF 863 864 static int pn544_hci_i2c_of_request_resources(struct i2c_client *client) 865 { 866 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 867 struct device_node *pp; 868 int ret; 869 870 pp = client->dev.of_node; 871 if (!pp) { 872 ret = -ENODEV; 873 goto err_dt; 874 } 875 876 /* Obtention of EN GPIO from device tree */ 877 ret = of_get_named_gpio(pp, "enable-gpios", 0); 878 if (ret < 0) { 879 if (ret != -EPROBE_DEFER) 880 nfc_err(&client->dev, 881 "Failed to get EN gpio, error: %d\n", ret); 882 goto err_dt; 883 } 884 phy->gpio_en = ret; 885 886 /* Configuration of EN GPIO */ 887 ret = gpio_request(phy->gpio_en, "pn544_en"); 888 if (ret) { 889 nfc_err(&client->dev, "Fail EN pin\n"); 890 goto err_dt; 891 } 892 ret = gpio_direction_output(phy->gpio_en, 0); 893 if (ret) { 894 nfc_err(&client->dev, "Fail EN pin direction\n"); 895 goto err_gpio_en; 896 } 897 898 /* Obtention of FW GPIO from device tree */ 899 ret = of_get_named_gpio(pp, "firmware-gpios", 0); 900 if (ret < 0) { 901 if (ret != -EPROBE_DEFER) 902 nfc_err(&client->dev, 903 "Failed to get FW gpio, error: %d\n", ret); 904 goto err_gpio_en; 905 } 906 phy->gpio_fw = ret; 907 908 /* Configuration of FW GPIO */ 909 ret = gpio_request(phy->gpio_fw, "pn544_fw"); 910 if (ret) { 911 nfc_err(&client->dev, "Fail FW pin\n"); 912 goto err_gpio_en; 913 } 914 ret = gpio_direction_output(phy->gpio_fw, 0); 915 if (ret) { 916 nfc_err(&client->dev, "Fail FW pin direction\n"); 917 goto err_gpio_fw; 918 } 919 920 /* IRQ */ 921 ret = irq_of_parse_and_map(pp, 0); 922 if (ret < 0) { 923 nfc_err(&client->dev, 924 "Unable to get irq, error: %d\n", ret); 925 goto err_gpio_fw; 926 } 927 client->irq = ret; 928 929 return 0; 930 931 err_gpio_fw: 932 gpio_free(phy->gpio_fw); 933 err_gpio_en: 934 gpio_free(phy->gpio_en); 935 err_dt: 936 return ret; 937 } 938 939 #else 940 941 static int pn544_hci_i2c_of_request_resources(struct i2c_client *client) 942 { 943 return -ENODEV; 944 } 945 946 #endif 947 948 static int pn544_hci_i2c_probe(struct i2c_client *client, 949 const struct i2c_device_id *id) 950 { 951 struct pn544_i2c_phy *phy; 952 struct pn544_nfc_platform_data *pdata; 953 int r = 0; 954 955 dev_dbg(&client->dev, "%s\n", __func__); 956 dev_dbg(&client->dev, "IRQ: %d\n", client->irq); 957 958 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 959 nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); 960 return -ENODEV; 961 } 962 963 phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy), 964 GFP_KERNEL); 965 if (!phy) { 966 nfc_err(&client->dev, 967 "Cannot allocate memory for pn544 i2c phy.\n"); 968 return -ENOMEM; 969 } 970 971 INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work); 972 phy->fw_work_state = FW_WORK_STATE_IDLE; 973 974 phy->i2c_dev = client; 975 i2c_set_clientdata(client, phy); 976 977 pdata = client->dev.platform_data; 978 979 /* No platform data, using device tree. */ 980 if (!pdata && client->dev.of_node) { 981 r = pn544_hci_i2c_of_request_resources(client); 982 if (r) { 983 nfc_err(&client->dev, "No DT data\n"); 984 return r; 985 } 986 /* Using platform data. */ 987 } else if (pdata) { 988 989 if (pdata->request_resources == NULL) { 990 nfc_err(&client->dev, "request_resources() missing\n"); 991 return -EINVAL; 992 } 993 994 r = pdata->request_resources(client); 995 if (r) { 996 nfc_err(&client->dev, 997 "Cannot get platform resources\n"); 998 return r; 999 } 1000 1001 phy->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE); 1002 phy->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET); 1003 phy->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ); 1004 } else { 1005 nfc_err(&client->dev, "No platform data\n"); 1006 return -EINVAL; 1007 } 1008 1009 pn544_hci_i2c_platform_init(phy); 1010 1011 r = request_threaded_irq(client->irq, NULL, pn544_hci_i2c_irq_thread_fn, 1012 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1013 PN544_HCI_I2C_DRIVER_NAME, phy); 1014 if (r < 0) { 1015 nfc_err(&client->dev, "Unable to register IRQ handler\n"); 1016 goto err_rti; 1017 } 1018 1019 r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME, 1020 PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM, 1021 PN544_HCI_I2C_LLC_MAX_PAYLOAD, 1022 pn544_hci_i2c_fw_download, &phy->hdev); 1023 if (r < 0) 1024 goto err_hci; 1025 1026 return 0; 1027 1028 err_hci: 1029 free_irq(client->irq, phy); 1030 1031 err_rti: 1032 if (!pdata) { 1033 gpio_free(phy->gpio_en); 1034 gpio_free(phy->gpio_fw); 1035 } else if (pdata->free_resources) { 1036 pdata->free_resources(); 1037 } 1038 1039 return r; 1040 } 1041 1042 static int pn544_hci_i2c_remove(struct i2c_client *client) 1043 { 1044 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 1045 struct pn544_nfc_platform_data *pdata = client->dev.platform_data; 1046 1047 dev_dbg(&client->dev, "%s\n", __func__); 1048 1049 cancel_work_sync(&phy->fw_work); 1050 if (phy->fw_work_state != FW_WORK_STATE_IDLE) 1051 pn544_hci_i2c_fw_work_complete(phy, -ENODEV); 1052 1053 pn544_hci_remove(phy->hdev); 1054 1055 if (phy->powered) 1056 pn544_hci_i2c_disable(phy); 1057 1058 free_irq(client->irq, phy); 1059 1060 /* No platform data, GPIOs have been requested by this driver */ 1061 if (!pdata) { 1062 gpio_free(phy->gpio_en); 1063 gpio_free(phy->gpio_fw); 1064 /* Using platform data */ 1065 } else if (pdata->free_resources) { 1066 pdata->free_resources(); 1067 } 1068 1069 return 0; 1070 } 1071 1072 static const struct of_device_id of_pn544_i2c_match[] = { 1073 { .compatible = "nxp,pn544-i2c", }, 1074 {}, 1075 }; 1076 MODULE_DEVICE_TABLE(of, of_pn544_i2c_match); 1077 1078 static struct i2c_driver pn544_hci_i2c_driver = { 1079 .driver = { 1080 .name = PN544_HCI_I2C_DRIVER_NAME, 1081 .owner = THIS_MODULE, 1082 .of_match_table = of_match_ptr(of_pn544_i2c_match), 1083 }, 1084 .probe = pn544_hci_i2c_probe, 1085 .id_table = pn544_hci_i2c_id_table, 1086 .remove = pn544_hci_i2c_remove, 1087 }; 1088 1089 module_i2c_driver(pn544_hci_i2c_driver); 1090 1091 MODULE_LICENSE("GPL"); 1092 MODULE_DESCRIPTION(DRIVER_DESC); 1093