1 /* 2 * I2C Link Layer for PN544 HCI based Driver 3 * 4 * Copyright (C) 2012 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the 17 * Free Software Foundation, Inc., 18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/crc-ccitt.h> 24 #include <linux/module.h> 25 #include <linux/i2c.h> 26 #include <linux/gpio.h> 27 #include <linux/miscdevice.h> 28 #include <linux/interrupt.h> 29 #include <linux/delay.h> 30 #include <linux/nfc.h> 31 #include <linux/firmware.h> 32 #include <linux/unaligned/access_ok.h> 33 #include <linux/platform_data/pn544.h> 34 35 #include <net/nfc/hci.h> 36 #include <net/nfc/llc.h> 37 #include <net/nfc/nfc.h> 38 39 #include "pn544.h" 40 41 #define PN544_I2C_FRAME_HEADROOM 1 42 #define PN544_I2C_FRAME_TAILROOM 2 43 44 /* framing in HCI mode */ 45 #define PN544_HCI_I2C_LLC_LEN 1 46 #define PN544_HCI_I2C_LLC_CRC 2 47 #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \ 48 PN544_HCI_I2C_LLC_CRC) 49 #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC) 50 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29 51 #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \ 52 PN544_HCI_I2C_LLC_MAX_PAYLOAD) 53 54 static struct i2c_device_id pn544_hci_i2c_id_table[] = { 55 {"pn544", 0}, 56 {} 57 }; 58 59 MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table); 60 61 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c" 62 63 #define PN544_FW_CMD_WRITE 0x08 64 #define PN544_FW_CMD_CHECK 0x06 65 66 struct pn544_i2c_fw_frame_write { 67 u8 cmd; 68 u16 be_length; 69 u8 be_dest_addr[3]; 70 u16 be_datalen; 71 u8 data[]; 72 } __packed; 73 74 struct pn544_i2c_fw_frame_check { 75 u8 cmd; 76 u16 be_length; 77 u8 be_start_addr[3]; 78 u16 be_datalen; 79 u16 be_crc; 80 } __packed; 81 82 struct pn544_i2c_fw_frame_response { 83 u8 status; 84 u16 be_length; 85 } __packed; 86 87 struct pn544_i2c_fw_blob { 88 u32 be_size; 89 u32 be_destaddr; 90 u8 data[]; 91 }; 92 93 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01 94 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02 95 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08 96 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B 97 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11 98 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18 99 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74 100 101 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 102 103 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7 104 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE 105 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8 106 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\ 107 PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\ 108 PN544_FW_WRITE_BUFFER_MAX_LEN) 109 110 #define FW_WORK_STATE_IDLE 1 111 #define FW_WORK_STATE_START 2 112 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3 113 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4 114 115 struct pn544_i2c_phy { 116 struct i2c_client *i2c_dev; 117 struct nfc_hci_dev *hdev; 118 119 unsigned int gpio_en; 120 unsigned int gpio_irq; 121 unsigned int gpio_fw; 122 unsigned int en_polarity; 123 124 struct work_struct fw_work; 125 int fw_work_state; 126 char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1]; 127 const struct firmware *fw; 128 u32 fw_blob_dest_addr; 129 size_t fw_blob_size; 130 const u8 *fw_blob_data; 131 size_t fw_written; 132 int fw_cmd_result; 133 134 int powered; 135 int run_mode; 136 137 int hard_fault; /* 138 * < 0 if hardware error occured (e.g. i2c err) 139 * and prevents normal operation. 140 */ 141 }; 142 143 #define I2C_DUMP_SKB(info, skb) \ 144 do { \ 145 pr_debug("%s:\n", info); \ 146 print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ 147 16, 1, (skb)->data, (skb)->len, 0); \ 148 } while (0) 149 150 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) 151 { 152 int polarity, retry, ret; 153 char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 }; 154 int count = sizeof(rset_cmd); 155 156 nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); 157 158 /* Disable fw download */ 159 gpio_set_value(phy->gpio_fw, 0); 160 161 for (polarity = 0; polarity < 2; polarity++) { 162 phy->en_polarity = polarity; 163 retry = 3; 164 while (retry--) { 165 /* power off */ 166 gpio_set_value(phy->gpio_en, !phy->en_polarity); 167 usleep_range(10000, 15000); 168 169 /* power on */ 170 gpio_set_value(phy->gpio_en, phy->en_polarity); 171 usleep_range(10000, 15000); 172 173 /* send reset */ 174 dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n"); 175 ret = i2c_master_send(phy->i2c_dev, rset_cmd, count); 176 if (ret == count) { 177 nfc_info(&phy->i2c_dev->dev, 178 "nfc_en polarity : active %s\n", 179 (polarity == 0 ? "low" : "high")); 180 goto out; 181 } 182 } 183 } 184 185 nfc_err(&phy->i2c_dev->dev, 186 "Could not detect nfc_en polarity, fallback to active high\n"); 187 188 out: 189 gpio_set_value(phy->gpio_en, !phy->en_polarity); 190 } 191 192 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode) 193 { 194 gpio_set_value(phy->gpio_fw, run_mode == PN544_FW_MODE ? 1 : 0); 195 gpio_set_value(phy->gpio_en, phy->en_polarity); 196 usleep_range(10000, 15000); 197 198 phy->run_mode = run_mode; 199 } 200 201 static int pn544_hci_i2c_enable(void *phy_id) 202 { 203 struct pn544_i2c_phy *phy = phy_id; 204 205 pr_info("%s\n", __func__); 206 207 pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE); 208 209 phy->powered = 1; 210 211 return 0; 212 } 213 214 static void pn544_hci_i2c_disable(void *phy_id) 215 { 216 struct pn544_i2c_phy *phy = phy_id; 217 218 gpio_set_value(phy->gpio_fw, 0); 219 gpio_set_value(phy->gpio_en, !phy->en_polarity); 220 usleep_range(10000, 15000); 221 222 gpio_set_value(phy->gpio_en, phy->en_polarity); 223 usleep_range(10000, 15000); 224 225 gpio_set_value(phy->gpio_en, !phy->en_polarity); 226 usleep_range(10000, 15000); 227 228 phy->powered = 0; 229 } 230 231 static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb) 232 { 233 u16 crc; 234 int len; 235 236 len = skb->len + 2; 237 *skb_push(skb, 1) = len; 238 239 crc = crc_ccitt(0xffff, skb->data, skb->len); 240 crc = ~crc; 241 *skb_put(skb, 1) = crc & 0xff; 242 *skb_put(skb, 1) = crc >> 8; 243 } 244 245 static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb) 246 { 247 skb_pull(skb, PN544_I2C_FRAME_HEADROOM); 248 skb_trim(skb, PN544_I2C_FRAME_TAILROOM); 249 } 250 251 /* 252 * Writing a frame must not return the number of written bytes. 253 * It must return either zero for success, or <0 for error. 254 * In addition, it must not alter the skb 255 */ 256 static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb) 257 { 258 int r; 259 struct pn544_i2c_phy *phy = phy_id; 260 struct i2c_client *client = phy->i2c_dev; 261 262 if (phy->hard_fault != 0) 263 return phy->hard_fault; 264 265 usleep_range(3000, 6000); 266 267 pn544_hci_i2c_add_len_crc(skb); 268 269 I2C_DUMP_SKB("i2c frame written", skb); 270 271 r = i2c_master_send(client, skb->data, skb->len); 272 273 if (r == -EREMOTEIO) { /* Retry, chip was in standby */ 274 usleep_range(6000, 10000); 275 r = i2c_master_send(client, skb->data, skb->len); 276 } 277 278 if (r >= 0) { 279 if (r != skb->len) 280 r = -EREMOTEIO; 281 else 282 r = 0; 283 } 284 285 pn544_hci_i2c_remove_len_crc(skb); 286 287 return r; 288 } 289 290 static int check_crc(u8 *buf, int buflen) 291 { 292 int len; 293 u16 crc; 294 295 len = buf[0] + 1; 296 crc = crc_ccitt(0xffff, buf, len - 2); 297 crc = ~crc; 298 299 if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) { 300 pr_err("CRC error 0x%x != 0x%x 0x%x\n", 301 crc, buf[len - 1], buf[len - 2]); 302 pr_info("%s: BAD CRC\n", __func__); 303 print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE, 304 16, 2, buf, buflen, false); 305 return -EPERM; 306 } 307 return 0; 308 } 309 310 /* 311 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees 312 * that i2c bus will be flushed and that next read will start on a new frame. 313 * returned skb contains only LLC header and payload. 314 * returns: 315 * -EREMOTEIO : i2c read error (fatal) 316 * -EBADMSG : frame was incorrect and discarded 317 * -ENOMEM : cannot allocate skb, frame dropped 318 */ 319 static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb) 320 { 321 int r; 322 u8 len; 323 u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1]; 324 struct i2c_client *client = phy->i2c_dev; 325 326 r = i2c_master_recv(client, &len, 1); 327 if (r != 1) { 328 nfc_err(&client->dev, "cannot read len byte\n"); 329 return -EREMOTEIO; 330 } 331 332 if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) || 333 (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) { 334 nfc_err(&client->dev, "invalid len byte\n"); 335 r = -EBADMSG; 336 goto flush; 337 } 338 339 *skb = alloc_skb(1 + len, GFP_KERNEL); 340 if (*skb == NULL) { 341 r = -ENOMEM; 342 goto flush; 343 } 344 345 *skb_put(*skb, 1) = len; 346 347 r = i2c_master_recv(client, skb_put(*skb, len), len); 348 if (r != len) { 349 kfree_skb(*skb); 350 return -EREMOTEIO; 351 } 352 353 I2C_DUMP_SKB("i2c frame read", *skb); 354 355 r = check_crc((*skb)->data, (*skb)->len); 356 if (r != 0) { 357 kfree_skb(*skb); 358 r = -EBADMSG; 359 goto flush; 360 } 361 362 skb_pull(*skb, 1); 363 skb_trim(*skb, (*skb)->len - 2); 364 365 usleep_range(3000, 6000); 366 367 return 0; 368 369 flush: 370 if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0) 371 r = -EREMOTEIO; 372 373 usleep_range(3000, 6000); 374 375 return r; 376 } 377 378 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy) 379 { 380 int r; 381 struct pn544_i2c_fw_frame_response response; 382 struct i2c_client *client = phy->i2c_dev; 383 384 r = i2c_master_recv(client, (char *) &response, sizeof(response)); 385 if (r != sizeof(response)) { 386 nfc_err(&client->dev, "cannot read fw status\n"); 387 return -EIO; 388 } 389 390 usleep_range(3000, 6000); 391 392 switch (response.status) { 393 case 0: 394 return 0; 395 case PN544_FW_CMD_RESULT_TIMEOUT: 396 return -ETIMEDOUT; 397 case PN544_FW_CMD_RESULT_BAD_CRC: 398 return -ENODATA; 399 case PN544_FW_CMD_RESULT_ACCESS_DENIED: 400 return -EACCES; 401 case PN544_FW_CMD_RESULT_PROTOCOL_ERROR: 402 return -EPROTO; 403 case PN544_FW_CMD_RESULT_INVALID_PARAMETER: 404 return -EINVAL; 405 case PN544_FW_CMD_RESULT_INVALID_LENGTH: 406 return -EBADMSG; 407 case PN544_FW_CMD_RESULT_WRITE_FAILED: 408 return -EIO; 409 default: 410 return -EIO; 411 } 412 } 413 414 /* 415 * Reads an shdlc frame from the chip. This is not as straightforward as it 416 * seems. There are cases where we could loose the frame start synchronization. 417 * The frame format is len-data-crc, and corruption can occur anywhere while 418 * transiting on i2c bus, such that we could read an invalid len. 419 * In order to recover synchronization with the next frame, we must be sure 420 * to read the real amount of data without using the len byte. We do this by 421 * assuming the following: 422 * - the chip will always present only one single complete frame on the bus 423 * before triggering the interrupt 424 * - the chip will not present a new frame until we have completely read 425 * the previous one (or until we have handled the interrupt). 426 * The tricky case is when we read a corrupted len that is less than the real 427 * len. We must detect this here in order to determine that we need to flush 428 * the bus. This is the reason why we check the crc here. 429 */ 430 static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id) 431 { 432 struct pn544_i2c_phy *phy = phy_id; 433 struct i2c_client *client; 434 struct sk_buff *skb = NULL; 435 int r; 436 437 if (!phy || irq != phy->i2c_dev->irq) { 438 WARN_ON_ONCE(1); 439 return IRQ_NONE; 440 } 441 442 client = phy->i2c_dev; 443 dev_dbg(&client->dev, "IRQ\n"); 444 445 if (phy->hard_fault != 0) 446 return IRQ_HANDLED; 447 448 if (phy->run_mode == PN544_FW_MODE) { 449 phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy); 450 schedule_work(&phy->fw_work); 451 } else { 452 r = pn544_hci_i2c_read(phy, &skb); 453 if (r == -EREMOTEIO) { 454 phy->hard_fault = r; 455 456 nfc_hci_recv_frame(phy->hdev, NULL); 457 458 return IRQ_HANDLED; 459 } else if ((r == -ENOMEM) || (r == -EBADMSG)) { 460 return IRQ_HANDLED; 461 } 462 463 nfc_hci_recv_frame(phy->hdev, skb); 464 } 465 return IRQ_HANDLED; 466 } 467 468 static struct nfc_phy_ops i2c_phy_ops = { 469 .write = pn544_hci_i2c_write, 470 .enable = pn544_hci_i2c_enable, 471 .disable = pn544_hci_i2c_disable, 472 }; 473 474 static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name) 475 { 476 struct pn544_i2c_phy *phy = phy_id; 477 478 pr_info("Starting Firmware Download (%s)\n", firmware_name); 479 480 strcpy(phy->firmware_name, firmware_name); 481 482 phy->fw_work_state = FW_WORK_STATE_START; 483 484 schedule_work(&phy->fw_work); 485 486 return 0; 487 } 488 489 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy, 490 int result) 491 { 492 pr_info("Firmware Download Complete, result=%d\n", result); 493 494 pn544_hci_i2c_disable(phy); 495 496 phy->fw_work_state = FW_WORK_STATE_IDLE; 497 498 if (phy->fw) { 499 release_firmware(phy->fw); 500 phy->fw = NULL; 501 } 502 503 nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result); 504 } 505 506 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr, 507 const u8 *data, u16 datalen) 508 { 509 u8 frame[PN544_FW_I2C_MAX_PAYLOAD]; 510 struct pn544_i2c_fw_frame_write *framep; 511 u16 params_len; 512 int framelen; 513 int r; 514 515 if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN) 516 datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN; 517 518 framep = (struct pn544_i2c_fw_frame_write *) frame; 519 520 params_len = sizeof(framep->be_dest_addr) + 521 sizeof(framep->be_datalen) + datalen; 522 framelen = params_len + sizeof(framep->cmd) + 523 sizeof(framep->be_length); 524 525 framep->cmd = PN544_FW_CMD_WRITE; 526 527 put_unaligned_be16(params_len, &framep->be_length); 528 529 framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16; 530 framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8; 531 framep->be_dest_addr[2] = dest_addr & 0xff; 532 533 put_unaligned_be16(datalen, &framep->be_datalen); 534 535 memcpy(framep->data, data, datalen); 536 537 r = i2c_master_send(client, frame, framelen); 538 539 if (r == framelen) 540 return datalen; 541 else if (r < 0) 542 return r; 543 else 544 return -EIO; 545 } 546 547 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr, 548 const u8 *data, u16 datalen) 549 { 550 struct pn544_i2c_fw_frame_check frame; 551 int r; 552 u16 crc; 553 554 /* calculate local crc for the data we want to check */ 555 crc = crc_ccitt(0xffff, data, datalen); 556 557 frame.cmd = PN544_FW_CMD_CHECK; 558 559 put_unaligned_be16(sizeof(frame.be_start_addr) + 560 sizeof(frame.be_datalen) + sizeof(frame.be_crc), 561 &frame.be_length); 562 563 /* tell the chip the memory region to which our crc applies */ 564 frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16; 565 frame.be_start_addr[1] = (start_addr & 0xff00) >> 8; 566 frame.be_start_addr[2] = start_addr & 0xff; 567 568 put_unaligned_be16(datalen, &frame.be_datalen); 569 570 /* 571 * and give our local crc. Chip will calculate its own crc for the 572 * region and compare with ours. 573 */ 574 put_unaligned_be16(crc, &frame.be_crc); 575 576 r = i2c_master_send(client, (const char *) &frame, sizeof(frame)); 577 578 if (r == sizeof(frame)) 579 return 0; 580 else if (r < 0) 581 return r; 582 else 583 return -EIO; 584 } 585 586 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy) 587 { 588 int r; 589 590 r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev, 591 phy->fw_blob_dest_addr + phy->fw_written, 592 phy->fw_blob_data + phy->fw_written, 593 phy->fw_blob_size - phy->fw_written); 594 if (r < 0) 595 return r; 596 597 phy->fw_written += r; 598 phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER; 599 600 return 0; 601 } 602 603 static void pn544_hci_i2c_fw_work(struct work_struct *work) 604 { 605 struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy, 606 fw_work); 607 int r; 608 struct pn544_i2c_fw_blob *blob; 609 610 switch (phy->fw_work_state) { 611 case FW_WORK_STATE_START: 612 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 613 614 r = request_firmware(&phy->fw, phy->firmware_name, 615 &phy->i2c_dev->dev); 616 if (r < 0) 617 goto exit_state_start; 618 619 blob = (struct pn544_i2c_fw_blob *) phy->fw->data; 620 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 621 phy->fw_blob_dest_addr = get_unaligned_be32(&blob->be_destaddr); 622 phy->fw_blob_data = blob->data; 623 624 phy->fw_written = 0; 625 r = pn544_hci_i2c_fw_write_chunk(phy); 626 627 exit_state_start: 628 if (r < 0) 629 pn544_hci_i2c_fw_work_complete(phy, r); 630 break; 631 632 case FW_WORK_STATE_WAIT_WRITE_ANSWER: 633 r = phy->fw_cmd_result; 634 if (r < 0) 635 goto exit_state_wait_write_answer; 636 637 if (phy->fw_written == phy->fw_blob_size) { 638 r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev, 639 phy->fw_blob_dest_addr, 640 phy->fw_blob_data, 641 phy->fw_blob_size); 642 if (r < 0) 643 goto exit_state_wait_write_answer; 644 phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER; 645 break; 646 } 647 648 r = pn544_hci_i2c_fw_write_chunk(phy); 649 650 exit_state_wait_write_answer: 651 if (r < 0) 652 pn544_hci_i2c_fw_work_complete(phy, r); 653 break; 654 655 case FW_WORK_STATE_WAIT_CHECK_ANSWER: 656 r = phy->fw_cmd_result; 657 if (r < 0) 658 goto exit_state_wait_check_answer; 659 660 blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data + 661 phy->fw_blob_size); 662 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 663 if (phy->fw_blob_size != 0) { 664 phy->fw_blob_dest_addr = 665 get_unaligned_be32(&blob->be_destaddr); 666 phy->fw_blob_data = blob->data; 667 668 phy->fw_written = 0; 669 r = pn544_hci_i2c_fw_write_chunk(phy); 670 } 671 672 exit_state_wait_check_answer: 673 if (r < 0 || phy->fw_blob_size == 0) 674 pn544_hci_i2c_fw_work_complete(phy, r); 675 break; 676 677 default: 678 break; 679 } 680 } 681 682 static int pn544_hci_i2c_probe(struct i2c_client *client, 683 const struct i2c_device_id *id) 684 { 685 struct pn544_i2c_phy *phy; 686 struct pn544_nfc_platform_data *pdata; 687 int r = 0; 688 689 dev_dbg(&client->dev, "%s\n", __func__); 690 dev_dbg(&client->dev, "IRQ: %d\n", client->irq); 691 692 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 693 nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); 694 return -ENODEV; 695 } 696 697 phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy), 698 GFP_KERNEL); 699 if (!phy) { 700 nfc_err(&client->dev, 701 "Cannot allocate memory for pn544 i2c phy.\n"); 702 return -ENOMEM; 703 } 704 705 INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work); 706 phy->fw_work_state = FW_WORK_STATE_IDLE; 707 708 phy->i2c_dev = client; 709 i2c_set_clientdata(client, phy); 710 711 pdata = client->dev.platform_data; 712 if (pdata == NULL) { 713 nfc_err(&client->dev, "No platform data\n"); 714 return -EINVAL; 715 } 716 717 if (pdata->request_resources == NULL) { 718 nfc_err(&client->dev, "request_resources() missing\n"); 719 return -EINVAL; 720 } 721 722 r = pdata->request_resources(client); 723 if (r) { 724 nfc_err(&client->dev, "Cannot get platform resources\n"); 725 return r; 726 } 727 728 phy->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE); 729 phy->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET); 730 phy->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ); 731 732 pn544_hci_i2c_platform_init(phy); 733 734 r = request_threaded_irq(client->irq, NULL, pn544_hci_i2c_irq_thread_fn, 735 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 736 PN544_HCI_I2C_DRIVER_NAME, phy); 737 if (r < 0) { 738 nfc_err(&client->dev, "Unable to register IRQ handler\n"); 739 goto err_rti; 740 } 741 742 r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME, 743 PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM, 744 PN544_HCI_I2C_LLC_MAX_PAYLOAD, 745 pn544_hci_i2c_fw_download, &phy->hdev); 746 if (r < 0) 747 goto err_hci; 748 749 return 0; 750 751 err_hci: 752 free_irq(client->irq, phy); 753 754 err_rti: 755 if (pdata->free_resources != NULL) 756 pdata->free_resources(); 757 758 return r; 759 } 760 761 static int pn544_hci_i2c_remove(struct i2c_client *client) 762 { 763 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 764 struct pn544_nfc_platform_data *pdata = client->dev.platform_data; 765 766 dev_dbg(&client->dev, "%s\n", __func__); 767 768 cancel_work_sync(&phy->fw_work); 769 if (phy->fw_work_state != FW_WORK_STATE_IDLE) 770 pn544_hci_i2c_fw_work_complete(phy, -ENODEV); 771 772 pn544_hci_remove(phy->hdev); 773 774 if (phy->powered) 775 pn544_hci_i2c_disable(phy); 776 777 free_irq(client->irq, phy); 778 if (pdata->free_resources) 779 pdata->free_resources(); 780 781 return 0; 782 } 783 784 static struct i2c_driver pn544_hci_i2c_driver = { 785 .driver = { 786 .name = PN544_HCI_I2C_DRIVER_NAME, 787 }, 788 .probe = pn544_hci_i2c_probe, 789 .id_table = pn544_hci_i2c_id_table, 790 .remove = pn544_hci_i2c_remove, 791 }; 792 793 module_i2c_driver(pn544_hci_i2c_driver); 794 795 MODULE_LICENSE("GPL"); 796 MODULE_DESCRIPTION(DRIVER_DESC); 797