1 /* 2 * I2C Link Layer for PN544 HCI based Driver 3 * 4 * Copyright (C) 2012 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/crc-ccitt.h> 22 #include <linux/module.h> 23 #include <linux/i2c.h> 24 #include <linux/gpio.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_irq.h> 27 #include <linux/acpi.h> 28 #include <linux/miscdevice.h> 29 #include <linux/interrupt.h> 30 #include <linux/delay.h> 31 #include <linux/nfc.h> 32 #include <linux/firmware.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/platform_data/pn544.h> 35 #include <asm/unaligned.h> 36 37 #include <net/nfc/hci.h> 38 #include <net/nfc/llc.h> 39 #include <net/nfc/nfc.h> 40 41 #include "pn544.h" 42 43 #define PN544_I2C_FRAME_HEADROOM 1 44 #define PN544_I2C_FRAME_TAILROOM 2 45 46 /* GPIO names */ 47 #define PN544_GPIO_NAME_IRQ "pn544_irq" 48 #define PN544_GPIO_NAME_FW "pn544_fw" 49 #define PN544_GPIO_NAME_EN "pn544_en" 50 51 /* framing in HCI mode */ 52 #define PN544_HCI_I2C_LLC_LEN 1 53 #define PN544_HCI_I2C_LLC_CRC 2 54 #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \ 55 PN544_HCI_I2C_LLC_CRC) 56 #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC) 57 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29 58 #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \ 59 PN544_HCI_I2C_LLC_MAX_PAYLOAD) 60 61 static struct i2c_device_id pn544_hci_i2c_id_table[] = { 62 {"pn544", 0}, 63 {} 64 }; 65 66 MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table); 67 68 static const struct acpi_device_id pn544_hci_i2c_acpi_match[] = { 69 {"NXP5440", 0}, 70 {} 71 }; 72 73 MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match); 74 75 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c" 76 77 /* 78 * Exposed through the 4 most significant bytes 79 * from the HCI SW_VERSION first byte, a.k.a. 80 * SW RomLib. 81 */ 82 #define PN544_HW_VARIANT_C2 0xa 83 #define PN544_HW_VARIANT_C3 0xb 84 85 #define PN544_FW_CMD_RESET 0x01 86 #define PN544_FW_CMD_WRITE 0x08 87 #define PN544_FW_CMD_CHECK 0x06 88 #define PN544_FW_CMD_SECURE_WRITE 0x0C 89 #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D 90 91 struct pn544_i2c_fw_frame_write { 92 u8 cmd; 93 u16 be_length; 94 u8 be_dest_addr[3]; 95 u16 be_datalen; 96 u8 data[]; 97 } __packed; 98 99 struct pn544_i2c_fw_frame_check { 100 u8 cmd; 101 u16 be_length; 102 u8 be_start_addr[3]; 103 u16 be_datalen; 104 u16 be_crc; 105 } __packed; 106 107 struct pn544_i2c_fw_frame_response { 108 u8 status; 109 u16 be_length; 110 } __packed; 111 112 struct pn544_i2c_fw_blob { 113 u32 be_size; 114 u32 be_destaddr; 115 u8 data[]; 116 }; 117 118 struct pn544_i2c_fw_secure_frame { 119 u8 cmd; 120 u16 be_datalen; 121 u8 data[]; 122 } __packed; 123 124 struct pn544_i2c_fw_secure_blob { 125 u64 header; 126 u8 data[]; 127 }; 128 129 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01 130 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02 131 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08 132 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B 133 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11 134 #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13 135 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18 136 #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19 137 #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D 138 #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20 139 #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21 140 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74 141 #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0 142 #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6 143 144 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 145 146 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7 147 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE 148 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8 149 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\ 150 PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\ 151 PN544_FW_WRITE_BUFFER_MAX_LEN) 152 #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3 153 #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\ 154 PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN) 155 #define PN544_FW_SECURE_FRAME_HEADER_LEN 3 156 #define PN544_FW_SECURE_BLOB_HEADER_LEN 8 157 158 #define FW_WORK_STATE_IDLE 1 159 #define FW_WORK_STATE_START 2 160 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3 161 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4 162 #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5 163 164 struct pn544_i2c_phy { 165 struct i2c_client *i2c_dev; 166 struct nfc_hci_dev *hdev; 167 168 unsigned int gpio_en; 169 unsigned int gpio_irq; 170 unsigned int gpio_fw; 171 unsigned int en_polarity; 172 173 u8 hw_variant; 174 175 struct work_struct fw_work; 176 int fw_work_state; 177 char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1]; 178 const struct firmware *fw; 179 u32 fw_blob_dest_addr; 180 size_t fw_blob_size; 181 const u8 *fw_blob_data; 182 size_t fw_written; 183 size_t fw_size; 184 185 int fw_cmd_result; 186 187 int powered; 188 int run_mode; 189 190 int hard_fault; /* 191 * < 0 if hardware error occured (e.g. i2c err) 192 * and prevents normal operation. 193 */ 194 }; 195 196 #define I2C_DUMP_SKB(info, skb) \ 197 do { \ 198 pr_debug("%s:\n", info); \ 199 print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ 200 16, 1, (skb)->data, (skb)->len, 0); \ 201 } while (0) 202 203 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) 204 { 205 int polarity, retry, ret; 206 char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 }; 207 int count = sizeof(rset_cmd); 208 209 nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); 210 211 /* Disable fw download */ 212 gpio_set_value_cansleep(phy->gpio_fw, 0); 213 214 for (polarity = 0; polarity < 2; polarity++) { 215 phy->en_polarity = polarity; 216 retry = 3; 217 while (retry--) { 218 /* power off */ 219 gpio_set_value_cansleep(phy->gpio_en, 220 !phy->en_polarity); 221 usleep_range(10000, 15000); 222 223 /* power on */ 224 gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); 225 usleep_range(10000, 15000); 226 227 /* send reset */ 228 dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n"); 229 ret = i2c_master_send(phy->i2c_dev, rset_cmd, count); 230 if (ret == count) { 231 nfc_info(&phy->i2c_dev->dev, 232 "nfc_en polarity : active %s\n", 233 (polarity == 0 ? "low" : "high")); 234 goto out; 235 } 236 } 237 } 238 239 nfc_err(&phy->i2c_dev->dev, 240 "Could not detect nfc_en polarity, fallback to active high\n"); 241 242 out: 243 gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); 244 } 245 246 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode) 247 { 248 gpio_set_value_cansleep(phy->gpio_fw, 249 run_mode == PN544_FW_MODE ? 1 : 0); 250 gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); 251 usleep_range(10000, 15000); 252 253 phy->run_mode = run_mode; 254 } 255 256 static int pn544_hci_i2c_enable(void *phy_id) 257 { 258 struct pn544_i2c_phy *phy = phy_id; 259 260 pr_info("%s\n", __func__); 261 262 pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE); 263 264 phy->powered = 1; 265 266 return 0; 267 } 268 269 static void pn544_hci_i2c_disable(void *phy_id) 270 { 271 struct pn544_i2c_phy *phy = phy_id; 272 273 gpio_set_value_cansleep(phy->gpio_fw, 0); 274 gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); 275 usleep_range(10000, 15000); 276 277 gpio_set_value_cansleep(phy->gpio_en, phy->en_polarity); 278 usleep_range(10000, 15000); 279 280 gpio_set_value_cansleep(phy->gpio_en, !phy->en_polarity); 281 usleep_range(10000, 15000); 282 283 phy->powered = 0; 284 } 285 286 static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb) 287 { 288 u16 crc; 289 int len; 290 291 len = skb->len + 2; 292 *skb_push(skb, 1) = len; 293 294 crc = crc_ccitt(0xffff, skb->data, skb->len); 295 crc = ~crc; 296 *skb_put(skb, 1) = crc & 0xff; 297 *skb_put(skb, 1) = crc >> 8; 298 } 299 300 static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb) 301 { 302 skb_pull(skb, PN544_I2C_FRAME_HEADROOM); 303 skb_trim(skb, PN544_I2C_FRAME_TAILROOM); 304 } 305 306 /* 307 * Writing a frame must not return the number of written bytes. 308 * It must return either zero for success, or <0 for error. 309 * In addition, it must not alter the skb 310 */ 311 static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb) 312 { 313 int r; 314 struct pn544_i2c_phy *phy = phy_id; 315 struct i2c_client *client = phy->i2c_dev; 316 317 if (phy->hard_fault != 0) 318 return phy->hard_fault; 319 320 usleep_range(3000, 6000); 321 322 pn544_hci_i2c_add_len_crc(skb); 323 324 I2C_DUMP_SKB("i2c frame written", skb); 325 326 r = i2c_master_send(client, skb->data, skb->len); 327 328 if (r == -EREMOTEIO) { /* Retry, chip was in standby */ 329 usleep_range(6000, 10000); 330 r = i2c_master_send(client, skb->data, skb->len); 331 } 332 333 if (r >= 0) { 334 if (r != skb->len) 335 r = -EREMOTEIO; 336 else 337 r = 0; 338 } 339 340 pn544_hci_i2c_remove_len_crc(skb); 341 342 return r; 343 } 344 345 static int check_crc(u8 *buf, int buflen) 346 { 347 int len; 348 u16 crc; 349 350 len = buf[0] + 1; 351 crc = crc_ccitt(0xffff, buf, len - 2); 352 crc = ~crc; 353 354 if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) { 355 pr_err("CRC error 0x%x != 0x%x 0x%x\n", 356 crc, buf[len - 1], buf[len - 2]); 357 pr_info("%s: BAD CRC\n", __func__); 358 print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE, 359 16, 2, buf, buflen, false); 360 return -EPERM; 361 } 362 return 0; 363 } 364 365 /* 366 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees 367 * that i2c bus will be flushed and that next read will start on a new frame. 368 * returned skb contains only LLC header and payload. 369 * returns: 370 * -EREMOTEIO : i2c read error (fatal) 371 * -EBADMSG : frame was incorrect and discarded 372 * -ENOMEM : cannot allocate skb, frame dropped 373 */ 374 static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb) 375 { 376 int r; 377 u8 len; 378 u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1]; 379 struct i2c_client *client = phy->i2c_dev; 380 381 r = i2c_master_recv(client, &len, 1); 382 if (r != 1) { 383 nfc_err(&client->dev, "cannot read len byte\n"); 384 return -EREMOTEIO; 385 } 386 387 if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) || 388 (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) { 389 nfc_err(&client->dev, "invalid len byte\n"); 390 r = -EBADMSG; 391 goto flush; 392 } 393 394 *skb = alloc_skb(1 + len, GFP_KERNEL); 395 if (*skb == NULL) { 396 r = -ENOMEM; 397 goto flush; 398 } 399 400 *skb_put(*skb, 1) = len; 401 402 r = i2c_master_recv(client, skb_put(*skb, len), len); 403 if (r != len) { 404 kfree_skb(*skb); 405 return -EREMOTEIO; 406 } 407 408 I2C_DUMP_SKB("i2c frame read", *skb); 409 410 r = check_crc((*skb)->data, (*skb)->len); 411 if (r != 0) { 412 kfree_skb(*skb); 413 r = -EBADMSG; 414 goto flush; 415 } 416 417 skb_pull(*skb, 1); 418 skb_trim(*skb, (*skb)->len - 2); 419 420 usleep_range(3000, 6000); 421 422 return 0; 423 424 flush: 425 if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0) 426 r = -EREMOTEIO; 427 428 usleep_range(3000, 6000); 429 430 return r; 431 } 432 433 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy) 434 { 435 int r; 436 struct pn544_i2c_fw_frame_response response; 437 struct i2c_client *client = phy->i2c_dev; 438 439 r = i2c_master_recv(client, (char *) &response, sizeof(response)); 440 if (r != sizeof(response)) { 441 nfc_err(&client->dev, "cannot read fw status\n"); 442 return -EIO; 443 } 444 445 usleep_range(3000, 6000); 446 447 switch (response.status) { 448 case 0: 449 return 0; 450 case PN544_FW_CMD_RESULT_CHUNK_OK: 451 return response.status; 452 case PN544_FW_CMD_RESULT_TIMEOUT: 453 return -ETIMEDOUT; 454 case PN544_FW_CMD_RESULT_BAD_CRC: 455 return -ENODATA; 456 case PN544_FW_CMD_RESULT_ACCESS_DENIED: 457 return -EACCES; 458 case PN544_FW_CMD_RESULT_PROTOCOL_ERROR: 459 return -EPROTO; 460 case PN544_FW_CMD_RESULT_INVALID_PARAMETER: 461 return -EINVAL; 462 case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND: 463 return -ENOTSUPP; 464 case PN544_FW_CMD_RESULT_INVALID_LENGTH: 465 return -EBADMSG; 466 case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR: 467 return -ENOKEY; 468 case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR: 469 return -EINVAL; 470 case PN544_FW_CMD_RESULT_MEMORY_ERROR: 471 return -ENOMEM; 472 case PN544_FW_CMD_RESULT_COMMAND_REJECTED: 473 return -EACCES; 474 case PN544_FW_CMD_RESULT_WRITE_FAILED: 475 case PN544_FW_CMD_RESULT_CHUNK_ERROR: 476 return -EIO; 477 default: 478 return -EIO; 479 } 480 } 481 482 /* 483 * Reads an shdlc frame from the chip. This is not as straightforward as it 484 * seems. There are cases where we could loose the frame start synchronization. 485 * The frame format is len-data-crc, and corruption can occur anywhere while 486 * transiting on i2c bus, such that we could read an invalid len. 487 * In order to recover synchronization with the next frame, we must be sure 488 * to read the real amount of data without using the len byte. We do this by 489 * assuming the following: 490 * - the chip will always present only one single complete frame on the bus 491 * before triggering the interrupt 492 * - the chip will not present a new frame until we have completely read 493 * the previous one (or until we have handled the interrupt). 494 * The tricky case is when we read a corrupted len that is less than the real 495 * len. We must detect this here in order to determine that we need to flush 496 * the bus. This is the reason why we check the crc here. 497 */ 498 static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id) 499 { 500 struct pn544_i2c_phy *phy = phy_id; 501 struct i2c_client *client; 502 struct sk_buff *skb = NULL; 503 int r; 504 505 if (!phy || irq != phy->i2c_dev->irq) { 506 WARN_ON_ONCE(1); 507 return IRQ_NONE; 508 } 509 510 client = phy->i2c_dev; 511 dev_dbg(&client->dev, "IRQ\n"); 512 513 if (phy->hard_fault != 0) 514 return IRQ_HANDLED; 515 516 if (phy->run_mode == PN544_FW_MODE) { 517 phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy); 518 schedule_work(&phy->fw_work); 519 } else { 520 r = pn544_hci_i2c_read(phy, &skb); 521 if (r == -EREMOTEIO) { 522 phy->hard_fault = r; 523 524 nfc_hci_recv_frame(phy->hdev, NULL); 525 526 return IRQ_HANDLED; 527 } else if ((r == -ENOMEM) || (r == -EBADMSG)) { 528 return IRQ_HANDLED; 529 } 530 531 nfc_hci_recv_frame(phy->hdev, skb); 532 } 533 return IRQ_HANDLED; 534 } 535 536 static struct nfc_phy_ops i2c_phy_ops = { 537 .write = pn544_hci_i2c_write, 538 .enable = pn544_hci_i2c_enable, 539 .disable = pn544_hci_i2c_disable, 540 }; 541 542 static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name, 543 u8 hw_variant) 544 { 545 struct pn544_i2c_phy *phy = phy_id; 546 547 pr_info("Starting Firmware Download (%s)\n", firmware_name); 548 549 strcpy(phy->firmware_name, firmware_name); 550 551 phy->hw_variant = hw_variant; 552 phy->fw_work_state = FW_WORK_STATE_START; 553 554 schedule_work(&phy->fw_work); 555 556 return 0; 557 } 558 559 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy, 560 int result) 561 { 562 pr_info("Firmware Download Complete, result=%d\n", result); 563 564 pn544_hci_i2c_disable(phy); 565 566 phy->fw_work_state = FW_WORK_STATE_IDLE; 567 568 if (phy->fw) { 569 release_firmware(phy->fw); 570 phy->fw = NULL; 571 } 572 573 nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result); 574 } 575 576 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr, 577 const u8 *data, u16 datalen) 578 { 579 u8 frame[PN544_FW_I2C_MAX_PAYLOAD]; 580 struct pn544_i2c_fw_frame_write *framep; 581 u16 params_len; 582 int framelen; 583 int r; 584 585 if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN) 586 datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN; 587 588 framep = (struct pn544_i2c_fw_frame_write *) frame; 589 590 params_len = sizeof(framep->be_dest_addr) + 591 sizeof(framep->be_datalen) + datalen; 592 framelen = params_len + sizeof(framep->cmd) + 593 sizeof(framep->be_length); 594 595 framep->cmd = PN544_FW_CMD_WRITE; 596 597 put_unaligned_be16(params_len, &framep->be_length); 598 599 framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16; 600 framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8; 601 framep->be_dest_addr[2] = dest_addr & 0xff; 602 603 put_unaligned_be16(datalen, &framep->be_datalen); 604 605 memcpy(framep->data, data, datalen); 606 607 r = i2c_master_send(client, frame, framelen); 608 609 if (r == framelen) 610 return datalen; 611 else if (r < 0) 612 return r; 613 else 614 return -EIO; 615 } 616 617 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr, 618 const u8 *data, u16 datalen) 619 { 620 struct pn544_i2c_fw_frame_check frame; 621 int r; 622 u16 crc; 623 624 /* calculate local crc for the data we want to check */ 625 crc = crc_ccitt(0xffff, data, datalen); 626 627 frame.cmd = PN544_FW_CMD_CHECK; 628 629 put_unaligned_be16(sizeof(frame.be_start_addr) + 630 sizeof(frame.be_datalen) + sizeof(frame.be_crc), 631 &frame.be_length); 632 633 /* tell the chip the memory region to which our crc applies */ 634 frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16; 635 frame.be_start_addr[1] = (start_addr & 0xff00) >> 8; 636 frame.be_start_addr[2] = start_addr & 0xff; 637 638 put_unaligned_be16(datalen, &frame.be_datalen); 639 640 /* 641 * and give our local crc. Chip will calculate its own crc for the 642 * region and compare with ours. 643 */ 644 put_unaligned_be16(crc, &frame.be_crc); 645 646 r = i2c_master_send(client, (const char *) &frame, sizeof(frame)); 647 648 if (r == sizeof(frame)) 649 return 0; 650 else if (r < 0) 651 return r; 652 else 653 return -EIO; 654 } 655 656 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy) 657 { 658 int r; 659 660 r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev, 661 phy->fw_blob_dest_addr + phy->fw_written, 662 phy->fw_blob_data + phy->fw_written, 663 phy->fw_blob_size - phy->fw_written); 664 if (r < 0) 665 return r; 666 667 phy->fw_written += r; 668 phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER; 669 670 return 0; 671 } 672 673 static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy, 674 const u8 *data, u16 datalen) 675 { 676 u8 buf[PN544_FW_I2C_MAX_PAYLOAD]; 677 struct pn544_i2c_fw_secure_frame *chunk; 678 int chunklen; 679 int r; 680 681 if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN) 682 datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN; 683 684 chunk = (struct pn544_i2c_fw_secure_frame *) buf; 685 686 chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE; 687 688 put_unaligned_be16(datalen, &chunk->be_datalen); 689 690 memcpy(chunk->data, data, datalen); 691 692 chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen; 693 694 r = i2c_master_send(phy->i2c_dev, buf, chunklen); 695 696 if (r == chunklen) 697 return datalen; 698 else if (r < 0) 699 return r; 700 else 701 return -EIO; 702 703 } 704 705 static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy) 706 { 707 struct pn544_i2c_fw_secure_frame *framep; 708 int r; 709 710 framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data; 711 if (phy->fw_written == 0) 712 phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen) 713 + PN544_FW_SECURE_FRAME_HEADER_LEN; 714 715 /* Only secure write command can be chunked*/ 716 if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD && 717 framep->cmd != PN544_FW_CMD_SECURE_WRITE) 718 return -EINVAL; 719 720 /* The firmware also have other commands, we just send them directly */ 721 if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) { 722 r = i2c_master_send(phy->i2c_dev, 723 (const char *) phy->fw_blob_data, phy->fw_blob_size); 724 725 if (r == phy->fw_blob_size) 726 goto exit; 727 else if (r < 0) 728 return r; 729 else 730 return -EIO; 731 } 732 733 r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy, 734 phy->fw_blob_data + phy->fw_written, 735 phy->fw_blob_size - phy->fw_written); 736 if (r < 0) 737 return r; 738 739 exit: 740 phy->fw_written += r; 741 phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER; 742 743 /* SW reset command will not trig any response from PN544 */ 744 if (framep->cmd == PN544_FW_CMD_RESET) { 745 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 746 phy->fw_cmd_result = 0; 747 schedule_work(&phy->fw_work); 748 } 749 750 return 0; 751 } 752 753 static void pn544_hci_i2c_fw_work(struct work_struct *work) 754 { 755 struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy, 756 fw_work); 757 int r; 758 struct pn544_i2c_fw_blob *blob; 759 struct pn544_i2c_fw_secure_blob *secure_blob; 760 761 switch (phy->fw_work_state) { 762 case FW_WORK_STATE_START: 763 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 764 765 r = request_firmware(&phy->fw, phy->firmware_name, 766 &phy->i2c_dev->dev); 767 if (r < 0) 768 goto exit_state_start; 769 770 phy->fw_written = 0; 771 772 switch (phy->hw_variant) { 773 case PN544_HW_VARIANT_C2: 774 blob = (struct pn544_i2c_fw_blob *) phy->fw->data; 775 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 776 phy->fw_blob_dest_addr = get_unaligned_be32( 777 &blob->be_destaddr); 778 phy->fw_blob_data = blob->data; 779 780 r = pn544_hci_i2c_fw_write_chunk(phy); 781 break; 782 case PN544_HW_VARIANT_C3: 783 secure_blob = (struct pn544_i2c_fw_secure_blob *) 784 phy->fw->data; 785 phy->fw_blob_data = secure_blob->data; 786 phy->fw_size = phy->fw->size; 787 r = pn544_hci_i2c_fw_secure_write_frame(phy); 788 break; 789 default: 790 r = -ENOTSUPP; 791 break; 792 } 793 794 exit_state_start: 795 if (r < 0) 796 pn544_hci_i2c_fw_work_complete(phy, r); 797 break; 798 799 case FW_WORK_STATE_WAIT_WRITE_ANSWER: 800 r = phy->fw_cmd_result; 801 if (r < 0) 802 goto exit_state_wait_write_answer; 803 804 if (phy->fw_written == phy->fw_blob_size) { 805 r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev, 806 phy->fw_blob_dest_addr, 807 phy->fw_blob_data, 808 phy->fw_blob_size); 809 if (r < 0) 810 goto exit_state_wait_write_answer; 811 phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER; 812 break; 813 } 814 815 r = pn544_hci_i2c_fw_write_chunk(phy); 816 817 exit_state_wait_write_answer: 818 if (r < 0) 819 pn544_hci_i2c_fw_work_complete(phy, r); 820 break; 821 822 case FW_WORK_STATE_WAIT_CHECK_ANSWER: 823 r = phy->fw_cmd_result; 824 if (r < 0) 825 goto exit_state_wait_check_answer; 826 827 blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data + 828 phy->fw_blob_size); 829 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 830 if (phy->fw_blob_size != 0) { 831 phy->fw_blob_dest_addr = 832 get_unaligned_be32(&blob->be_destaddr); 833 phy->fw_blob_data = blob->data; 834 835 phy->fw_written = 0; 836 r = pn544_hci_i2c_fw_write_chunk(phy); 837 } 838 839 exit_state_wait_check_answer: 840 if (r < 0 || phy->fw_blob_size == 0) 841 pn544_hci_i2c_fw_work_complete(phy, r); 842 break; 843 844 case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER: 845 r = phy->fw_cmd_result; 846 if (r < 0) 847 goto exit_state_wait_secure_write_answer; 848 849 if (r == PN544_FW_CMD_RESULT_CHUNK_OK) { 850 r = pn544_hci_i2c_fw_secure_write_frame(phy); 851 goto exit_state_wait_secure_write_answer; 852 } 853 854 if (phy->fw_written == phy->fw_blob_size) { 855 secure_blob = (struct pn544_i2c_fw_secure_blob *) 856 (phy->fw_blob_data + phy->fw_blob_size); 857 phy->fw_size -= phy->fw_blob_size + 858 PN544_FW_SECURE_BLOB_HEADER_LEN; 859 if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN 860 + PN544_FW_SECURE_FRAME_HEADER_LEN) { 861 phy->fw_blob_data = secure_blob->data; 862 863 phy->fw_written = 0; 864 r = pn544_hci_i2c_fw_secure_write_frame(phy); 865 } 866 } 867 868 exit_state_wait_secure_write_answer: 869 if (r < 0 || phy->fw_size == 0) 870 pn544_hci_i2c_fw_work_complete(phy, r); 871 break; 872 873 default: 874 break; 875 } 876 } 877 878 static int pn544_hci_i2c_acpi_request_resources(struct i2c_client *client) 879 { 880 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 881 const struct acpi_device_id *id; 882 struct gpio_desc *gpiod_en, *gpiod_irq, *gpiod_fw; 883 struct device *dev; 884 int ret; 885 886 if (!client) 887 return -EINVAL; 888 889 dev = &client->dev; 890 891 /* Match the struct device against a given list of ACPI IDs */ 892 id = acpi_match_device(dev->driver->acpi_match_table, dev); 893 894 if (!id) 895 return -ENODEV; 896 897 /* Get EN GPIO from ACPI */ 898 gpiod_en = devm_gpiod_get_index(dev, PN544_GPIO_NAME_EN, 1); 899 if (IS_ERR(gpiod_en)) { 900 nfc_err(dev, 901 "Unable to get EN GPIO\n"); 902 return -ENODEV; 903 } 904 905 phy->gpio_en = desc_to_gpio(gpiod_en); 906 907 /* Configuration EN GPIO */ 908 ret = gpiod_direction_output(gpiod_en, 0); 909 if (ret) { 910 nfc_err(dev, "Fail EN pin direction\n"); 911 return ret; 912 } 913 914 /* Get FW GPIO from ACPI */ 915 gpiod_fw = devm_gpiod_get_index(dev, PN544_GPIO_NAME_FW, 2); 916 if (IS_ERR(gpiod_fw)) { 917 nfc_err(dev, 918 "Unable to get FW GPIO\n"); 919 return -ENODEV; 920 } 921 922 phy->gpio_fw = desc_to_gpio(gpiod_fw); 923 924 /* Configuration FW GPIO */ 925 ret = gpiod_direction_output(gpiod_fw, 0); 926 if (ret) { 927 nfc_err(dev, "Fail FW pin direction\n"); 928 return ret; 929 } 930 931 /* Get IRQ GPIO */ 932 gpiod_irq = devm_gpiod_get_index(dev, PN544_GPIO_NAME_IRQ, 0); 933 if (IS_ERR(gpiod_irq)) { 934 nfc_err(dev, 935 "Unable to get IRQ GPIO\n"); 936 return -ENODEV; 937 } 938 939 phy->gpio_irq = desc_to_gpio(gpiod_irq); 940 941 /* Configure IRQ GPIO */ 942 ret = gpiod_direction_input(gpiod_irq); 943 if (ret) { 944 nfc_err(dev, "Fail IRQ pin direction\n"); 945 return ret; 946 } 947 948 /* Map the pin to an IRQ */ 949 ret = gpiod_to_irq(gpiod_irq); 950 if (ret < 0) { 951 nfc_err(dev, "Fail pin IRQ mapping\n"); 952 return ret; 953 } 954 955 nfc_info(dev, "GPIO resource, no:%d irq:%d\n", 956 desc_to_gpio(gpiod_irq), ret); 957 client->irq = ret; 958 959 return 0; 960 } 961 962 #ifdef CONFIG_OF 963 964 static int pn544_hci_i2c_of_request_resources(struct i2c_client *client) 965 { 966 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 967 struct device_node *pp; 968 int ret; 969 970 pp = client->dev.of_node; 971 if (!pp) { 972 ret = -ENODEV; 973 goto err_dt; 974 } 975 976 /* Obtention of EN GPIO from device tree */ 977 ret = of_get_named_gpio(pp, "enable-gpios", 0); 978 if (ret < 0) { 979 if (ret != -EPROBE_DEFER) 980 nfc_err(&client->dev, 981 "Failed to get EN gpio, error: %d\n", ret); 982 goto err_dt; 983 } 984 phy->gpio_en = ret; 985 986 /* Configuration of EN GPIO */ 987 ret = gpio_request(phy->gpio_en, PN544_GPIO_NAME_EN); 988 if (ret) { 989 nfc_err(&client->dev, "Fail EN pin\n"); 990 goto err_dt; 991 } 992 ret = gpio_direction_output(phy->gpio_en, 0); 993 if (ret) { 994 nfc_err(&client->dev, "Fail EN pin direction\n"); 995 goto err_gpio_en; 996 } 997 998 /* Obtention of FW GPIO from device tree */ 999 ret = of_get_named_gpio(pp, "firmware-gpios", 0); 1000 if (ret < 0) { 1001 if (ret != -EPROBE_DEFER) 1002 nfc_err(&client->dev, 1003 "Failed to get FW gpio, error: %d\n", ret); 1004 goto err_gpio_en; 1005 } 1006 phy->gpio_fw = ret; 1007 1008 /* Configuration of FW GPIO */ 1009 ret = gpio_request(phy->gpio_fw, PN544_GPIO_NAME_FW); 1010 if (ret) { 1011 nfc_err(&client->dev, "Fail FW pin\n"); 1012 goto err_gpio_en; 1013 } 1014 ret = gpio_direction_output(phy->gpio_fw, 0); 1015 if (ret) { 1016 nfc_err(&client->dev, "Fail FW pin direction\n"); 1017 goto err_gpio_fw; 1018 } 1019 1020 /* IRQ */ 1021 ret = irq_of_parse_and_map(pp, 0); 1022 if (ret < 0) { 1023 nfc_err(&client->dev, 1024 "Unable to get irq, error: %d\n", ret); 1025 goto err_gpio_fw; 1026 } 1027 client->irq = ret; 1028 1029 return 0; 1030 1031 err_gpio_fw: 1032 gpio_free(phy->gpio_fw); 1033 err_gpio_en: 1034 gpio_free(phy->gpio_en); 1035 err_dt: 1036 return ret; 1037 } 1038 1039 #else 1040 1041 static int pn544_hci_i2c_of_request_resources(struct i2c_client *client) 1042 { 1043 return -ENODEV; 1044 } 1045 1046 #endif 1047 1048 static int pn544_hci_i2c_probe(struct i2c_client *client, 1049 const struct i2c_device_id *id) 1050 { 1051 struct pn544_i2c_phy *phy; 1052 struct pn544_nfc_platform_data *pdata; 1053 int r = 0; 1054 1055 dev_dbg(&client->dev, "%s\n", __func__); 1056 dev_dbg(&client->dev, "IRQ: %d\n", client->irq); 1057 1058 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1059 nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); 1060 return -ENODEV; 1061 } 1062 1063 phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy), 1064 GFP_KERNEL); 1065 if (!phy) 1066 return -ENOMEM; 1067 1068 INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work); 1069 phy->fw_work_state = FW_WORK_STATE_IDLE; 1070 1071 phy->i2c_dev = client; 1072 i2c_set_clientdata(client, phy); 1073 1074 pdata = client->dev.platform_data; 1075 1076 /* No platform data, using device tree. */ 1077 if (!pdata && client->dev.of_node) { 1078 r = pn544_hci_i2c_of_request_resources(client); 1079 if (r) { 1080 nfc_err(&client->dev, "No DT data\n"); 1081 return r; 1082 } 1083 /* Using platform data. */ 1084 } else if (pdata) { 1085 1086 if (pdata->request_resources == NULL) { 1087 nfc_err(&client->dev, "request_resources() missing\n"); 1088 return -EINVAL; 1089 } 1090 1091 r = pdata->request_resources(client); 1092 if (r) { 1093 nfc_err(&client->dev, 1094 "Cannot get platform resources\n"); 1095 return r; 1096 } 1097 1098 phy->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE); 1099 phy->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET); 1100 phy->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ); 1101 /* Using ACPI */ 1102 } else if (ACPI_HANDLE(&client->dev)) { 1103 r = pn544_hci_i2c_acpi_request_resources(client); 1104 if (r) { 1105 nfc_err(&client->dev, 1106 "Cannot get ACPI data\n"); 1107 return r; 1108 } 1109 } else { 1110 nfc_err(&client->dev, "No platform data\n"); 1111 return -EINVAL; 1112 } 1113 1114 pn544_hci_i2c_platform_init(phy); 1115 1116 r = request_threaded_irq(client->irq, NULL, pn544_hci_i2c_irq_thread_fn, 1117 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1118 PN544_HCI_I2C_DRIVER_NAME, phy); 1119 if (r < 0) { 1120 nfc_err(&client->dev, "Unable to register IRQ handler\n"); 1121 goto err_rti; 1122 } 1123 1124 r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME, 1125 PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM, 1126 PN544_HCI_I2C_LLC_MAX_PAYLOAD, 1127 pn544_hci_i2c_fw_download, &phy->hdev); 1128 if (r < 0) 1129 goto err_hci; 1130 1131 return 0; 1132 1133 err_hci: 1134 free_irq(client->irq, phy); 1135 1136 err_rti: 1137 if (!pdata) { 1138 gpio_free(phy->gpio_en); 1139 gpio_free(phy->gpio_fw); 1140 } else if (pdata->free_resources) { 1141 pdata->free_resources(); 1142 } 1143 1144 return r; 1145 } 1146 1147 static int pn544_hci_i2c_remove(struct i2c_client *client) 1148 { 1149 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 1150 struct pn544_nfc_platform_data *pdata = client->dev.platform_data; 1151 1152 dev_dbg(&client->dev, "%s\n", __func__); 1153 1154 cancel_work_sync(&phy->fw_work); 1155 if (phy->fw_work_state != FW_WORK_STATE_IDLE) 1156 pn544_hci_i2c_fw_work_complete(phy, -ENODEV); 1157 1158 pn544_hci_remove(phy->hdev); 1159 1160 if (phy->powered) 1161 pn544_hci_i2c_disable(phy); 1162 1163 free_irq(client->irq, phy); 1164 1165 /* No platform data, GPIOs have been requested by this driver */ 1166 if (!pdata) { 1167 gpio_free(phy->gpio_en); 1168 gpio_free(phy->gpio_fw); 1169 /* Using platform data */ 1170 } else if (pdata->free_resources) { 1171 pdata->free_resources(); 1172 } 1173 1174 return 0; 1175 } 1176 1177 static const struct of_device_id of_pn544_i2c_match[] = { 1178 { .compatible = "nxp,pn544-i2c", }, 1179 {}, 1180 }; 1181 MODULE_DEVICE_TABLE(of, of_pn544_i2c_match); 1182 1183 static struct i2c_driver pn544_hci_i2c_driver = { 1184 .driver = { 1185 .name = PN544_HCI_I2C_DRIVER_NAME, 1186 .owner = THIS_MODULE, 1187 .of_match_table = of_match_ptr(of_pn544_i2c_match), 1188 .acpi_match_table = ACPI_PTR(pn544_hci_i2c_acpi_match), 1189 }, 1190 .probe = pn544_hci_i2c_probe, 1191 .id_table = pn544_hci_i2c_id_table, 1192 .remove = pn544_hci_i2c_remove, 1193 }; 1194 1195 module_i2c_driver(pn544_hci_i2c_driver); 1196 1197 MODULE_LICENSE("GPL"); 1198 MODULE_DESCRIPTION(DRIVER_DESC); 1199