113e920d9SHaijun Liu /* SPDX-License-Identifier: GPL-2.0-only 213e920d9SHaijun Liu * 313e920d9SHaijun Liu * Copyright (c) 2021, MediaTek Inc. 413e920d9SHaijun Liu * Copyright (c) 2021-2022, Intel Corporation. 513e920d9SHaijun Liu * 613e920d9SHaijun Liu * Authors: 713e920d9SHaijun Liu * Haijun Liu <haijun.liu@mediatek.com> 813e920d9SHaijun Liu * Ricardo Martinez <ricardo.martinez@linux.intel.com> 913e920d9SHaijun Liu * Sreehari Kancharla <sreehari.kancharla@intel.com> 1013e920d9SHaijun Liu * 1113e920d9SHaijun Liu * Contributors: 1213e920d9SHaijun Liu * Amir Hanania <amir.hanania@intel.com> 1313e920d9SHaijun Liu * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> 1413e920d9SHaijun Liu * Moises Veleta <moises.veleta@intel.com> 1513e920d9SHaijun Liu */ 1613e920d9SHaijun Liu 1713e920d9SHaijun Liu #ifndef __T7XX_PCI_H__ 1813e920d9SHaijun Liu #define __T7XX_PCI_H__ 1913e920d9SHaijun Liu 2046e8f49eSHaijun Liu #include <linux/completion.h> 2113e920d9SHaijun Liu #include <linux/irqreturn.h> 2246e8f49eSHaijun Liu #include <linux/mutex.h> 2313e920d9SHaijun Liu #include <linux/pci.h> 24de49ea38SHaijun Liu #include <linux/spinlock.h> 2513e920d9SHaijun Liu #include <linux/types.h> 2613e920d9SHaijun Liu 2713e920d9SHaijun Liu #include "t7xx_reg.h" 2813e920d9SHaijun Liu 2913e920d9SHaijun Liu /* struct t7xx_addr_base - holds base addresses 3013e920d9SHaijun Liu * @pcie_mac_ireg_base: PCIe MAC register base 3113e920d9SHaijun Liu * @pcie_ext_reg_base: used to calculate base addresses for CLDMA, DPMA and MHCCIF registers 3213e920d9SHaijun Liu * @pcie_dev_reg_trsl_addr: used to calculate the register base address 3313e920d9SHaijun Liu * @infracfg_ao_base: base address used in CLDMA reset operations 3413e920d9SHaijun Liu * @mhccif_rc_base: host view of MHCCIF rc base addr 3513e920d9SHaijun Liu */ 3613e920d9SHaijun Liu struct t7xx_addr_base { 3713e920d9SHaijun Liu void __iomem *pcie_mac_ireg_base; 3813e920d9SHaijun Liu void __iomem *pcie_ext_reg_base; 3913e920d9SHaijun Liu u32 pcie_dev_reg_trsl_addr; 4013e920d9SHaijun Liu void __iomem *infracfg_ao_base; 4113e920d9SHaijun Liu void __iomem *mhccif_rc_base; 4213e920d9SHaijun Liu }; 4313e920d9SHaijun Liu 4413e920d9SHaijun Liu typedef irqreturn_t (*t7xx_intr_callback)(int irq, void *param); 4513e920d9SHaijun Liu 4613e920d9SHaijun Liu /* struct t7xx_pci_dev - MTK device context structure 4713e920d9SHaijun Liu * @intr_handler: array of handler function for request_threaded_irq 4813e920d9SHaijun Liu * @intr_thread: array of thread_fn for request_threaded_irq 4913e920d9SHaijun Liu * @callback_param: array of cookie passed back to interrupt functions 5013e920d9SHaijun Liu * @pdev: PCI device 5113e920d9SHaijun Liu * @base_addr: memory base addresses of HW components 5213e920d9SHaijun Liu * @md: modem interface 5313e920d9SHaijun Liu * @ccmni_ctlb: context structure used to control the network data path 5413e920d9SHaijun Liu * @rgu_pci_irq_en: RGU callback ISR registered and active 5546e8f49eSHaijun Liu * @md_pm_entities: list of pm entities 5646e8f49eSHaijun Liu * @md_pm_entity_mtx: protects md_pm_entities list 5746e8f49eSHaijun Liu * @pm_sr_ack: ack from the device when went to sleep or woke up 5846e8f49eSHaijun Liu * @md_pm_state: state for resume/suspend 59de49ea38SHaijun Liu * @md_pm_lock: protects PCIe sleep lock 60de49ea38SHaijun Liu * @sleep_disable_count: PCIe L1.2 lock counter 61de49ea38SHaijun Liu * @sleep_lock_acquire: indicates that sleep has been disabled 6213e920d9SHaijun Liu */ 6313e920d9SHaijun Liu struct t7xx_pci_dev { 6413e920d9SHaijun Liu t7xx_intr_callback intr_handler[EXT_INT_NUM]; 6513e920d9SHaijun Liu t7xx_intr_callback intr_thread[EXT_INT_NUM]; 6613e920d9SHaijun Liu void *callback_param[EXT_INT_NUM]; 6713e920d9SHaijun Liu struct pci_dev *pdev; 6813e920d9SHaijun Liu struct t7xx_addr_base base_addr; 6913e920d9SHaijun Liu struct t7xx_modem *md; 7013e920d9SHaijun Liu struct t7xx_ccmni_ctrl *ccmni_ctlb; 7113e920d9SHaijun Liu bool rgu_pci_irq_en; 72*ab87603bSKai-Heng Feng struct completion init_done; 7346e8f49eSHaijun Liu 7446e8f49eSHaijun Liu /* Low Power Items */ 7546e8f49eSHaijun Liu struct list_head md_pm_entities; 7646e8f49eSHaijun Liu struct mutex md_pm_entity_mtx; /* Protects MD PM entities list */ 7746e8f49eSHaijun Liu struct completion pm_sr_ack; 7846e8f49eSHaijun Liu atomic_t md_pm_state; 79de49ea38SHaijun Liu spinlock_t md_pm_lock; /* Protects PCI resource lock */ 80de49ea38SHaijun Liu unsigned int sleep_disable_count; 81de49ea38SHaijun Liu struct completion sleep_lock_acquire; 823349e4a4SM Chetan Kumar #ifdef CONFIG_WWAN_DEBUGFS 833349e4a4SM Chetan Kumar struct dentry *debugfs_dir; 843349e4a4SM Chetan Kumar #endif 8513e920d9SHaijun Liu }; 8613e920d9SHaijun Liu 8746e8f49eSHaijun Liu enum t7xx_pm_id { 8846e8f49eSHaijun Liu PM_ENTITY_ID_CTRL1, 8946e8f49eSHaijun Liu PM_ENTITY_ID_CTRL2, 9046e8f49eSHaijun Liu PM_ENTITY_ID_DATA, 9146e8f49eSHaijun Liu PM_ENTITY_ID_INVALID 9246e8f49eSHaijun Liu }; 9346e8f49eSHaijun Liu 9446e8f49eSHaijun Liu /* struct md_pm_entity - device power management entity 9546e8f49eSHaijun Liu * @entity: list of PM Entities 9646e8f49eSHaijun Liu * @suspend: callback invoked before sending D3 request to device 9746e8f49eSHaijun Liu * @suspend_late: callback invoked after getting D3 ACK from device 9846e8f49eSHaijun Liu * @resume_early: callback invoked before sending the resume request to device 9946e8f49eSHaijun Liu * @resume: callback invoked after getting resume ACK from device 10046e8f49eSHaijun Liu * @id: unique PM entity identifier 10146e8f49eSHaijun Liu * @entity_param: parameter passed to the registered callbacks 10246e8f49eSHaijun Liu * 10346e8f49eSHaijun Liu * This structure is used to indicate PM operations required by internal 10446e8f49eSHaijun Liu * HW modules such as CLDMA and DPMA. 10546e8f49eSHaijun Liu */ 10646e8f49eSHaijun Liu struct md_pm_entity { 10746e8f49eSHaijun Liu struct list_head entity; 10846e8f49eSHaijun Liu int (*suspend)(struct t7xx_pci_dev *t7xx_dev, void *entity_param); 10946e8f49eSHaijun Liu void (*suspend_late)(struct t7xx_pci_dev *t7xx_dev, void *entity_param); 11046e8f49eSHaijun Liu void (*resume_early)(struct t7xx_pci_dev *t7xx_dev, void *entity_param); 11146e8f49eSHaijun Liu int (*resume)(struct t7xx_pci_dev *t7xx_dev, void *entity_param); 11246e8f49eSHaijun Liu enum t7xx_pm_id id; 11346e8f49eSHaijun Liu void *entity_param; 11446e8f49eSHaijun Liu }; 11546e8f49eSHaijun Liu 116de49ea38SHaijun Liu void t7xx_pci_disable_sleep(struct t7xx_pci_dev *t7xx_dev); 117de49ea38SHaijun Liu void t7xx_pci_enable_sleep(struct t7xx_pci_dev *t7xx_dev); 118de49ea38SHaijun Liu int t7xx_pci_sleep_disable_complete(struct t7xx_pci_dev *t7xx_dev); 11946e8f49eSHaijun Liu int t7xx_pci_pm_entity_register(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity); 12046e8f49eSHaijun Liu int t7xx_pci_pm_entity_unregister(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity); 12146e8f49eSHaijun Liu void t7xx_pci_pm_init_late(struct t7xx_pci_dev *t7xx_dev); 12246e8f49eSHaijun Liu void t7xx_pci_pm_exp_detected(struct t7xx_pci_dev *t7xx_dev); 12346e8f49eSHaijun Liu 12413e920d9SHaijun Liu #endif /* __T7XX_PCI_H__ */ 125