1*39d43904SHaijun Liu /* SPDX-License-Identifier: GPL-2.0-only 2*39d43904SHaijun Liu * 3*39d43904SHaijun Liu * Copyright (c) 2021, MediaTek Inc. 4*39d43904SHaijun Liu * Copyright (c) 2021-2022, Intel Corporation. 5*39d43904SHaijun Liu * 6*39d43904SHaijun Liu * Authors: 7*39d43904SHaijun Liu * Haijun Liu <haijun.liu@mediatek.com> 8*39d43904SHaijun Liu * Moises Veleta <moises.veleta@intel.com> 9*39d43904SHaijun Liu * Ricardo Martinez <ricardo.martinez@linux.intel.com> 10*39d43904SHaijun Liu * 11*39d43904SHaijun Liu * Contributors: 12*39d43904SHaijun Liu * Amir Hanania <amir.hanania@intel.com> 13*39d43904SHaijun Liu * Andy Shevchenko <andriy.shevchenko@linux.intel.com> 14*39d43904SHaijun Liu * Sreehari Kancharla <sreehari.kancharla@intel.com> 15*39d43904SHaijun Liu */ 16*39d43904SHaijun Liu 17*39d43904SHaijun Liu #ifndef __T7XX_CLDMA_H__ 18*39d43904SHaijun Liu #define __T7XX_CLDMA_H__ 19*39d43904SHaijun Liu 20*39d43904SHaijun Liu #include <linux/bits.h> 21*39d43904SHaijun Liu #include <linux/types.h> 22*39d43904SHaijun Liu 23*39d43904SHaijun Liu #define CLDMA_TXQ_NUM 8 24*39d43904SHaijun Liu #define CLDMA_RXQ_NUM 8 25*39d43904SHaijun Liu #define CLDMA_ALL_Q GENMASK(7, 0) 26*39d43904SHaijun Liu 27*39d43904SHaijun Liu /* Interrupt status bits */ 28*39d43904SHaijun Liu #define EMPTY_STATUS_BITMASK GENMASK(15, 8) 29*39d43904SHaijun Liu #define TXRX_STATUS_BITMASK GENMASK(7, 0) 30*39d43904SHaijun Liu #define EQ_STA_BIT_OFFSET 8 31*39d43904SHaijun Liu #define L2_INT_BIT_COUNT 16 32*39d43904SHaijun Liu #define EQ_STA_BIT(index) (BIT((index) + EQ_STA_BIT_OFFSET) & EMPTY_STATUS_BITMASK) 33*39d43904SHaijun Liu 34*39d43904SHaijun Liu #define TQ_ERR_INT_BITMASK GENMASK(23, 16) 35*39d43904SHaijun Liu #define TQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24) 36*39d43904SHaijun Liu 37*39d43904SHaijun Liu #define RQ_ERR_INT_BITMASK GENMASK(23, 16) 38*39d43904SHaijun Liu #define RQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24) 39*39d43904SHaijun Liu 40*39d43904SHaijun Liu #define CLDMA0_AO_BASE 0x10049000 41*39d43904SHaijun Liu #define CLDMA0_PD_BASE 0x1021d000 42*39d43904SHaijun Liu #define CLDMA1_AO_BASE 0x1004b000 43*39d43904SHaijun Liu #define CLDMA1_PD_BASE 0x1021f000 44*39d43904SHaijun Liu 45*39d43904SHaijun Liu #define CLDMA_R_AO_BASE 0x10023000 46*39d43904SHaijun Liu #define CLDMA_R_PD_BASE 0x1023d000 47*39d43904SHaijun Liu 48*39d43904SHaijun Liu /* CLDMA TX */ 49*39d43904SHaijun Liu #define REG_CLDMA_UL_START_ADDRL_0 0x0004 50*39d43904SHaijun Liu #define REG_CLDMA_UL_START_ADDRH_0 0x0008 51*39d43904SHaijun Liu #define REG_CLDMA_UL_CURRENT_ADDRL_0 0x0044 52*39d43904SHaijun Liu #define REG_CLDMA_UL_CURRENT_ADDRH_0 0x0048 53*39d43904SHaijun Liu #define REG_CLDMA_UL_STATUS 0x0084 54*39d43904SHaijun Liu #define REG_CLDMA_UL_START_CMD 0x0088 55*39d43904SHaijun Liu #define REG_CLDMA_UL_RESUME_CMD 0x008c 56*39d43904SHaijun Liu #define REG_CLDMA_UL_STOP_CMD 0x0090 57*39d43904SHaijun Liu #define REG_CLDMA_UL_ERROR 0x0094 58*39d43904SHaijun Liu #define REG_CLDMA_UL_CFG 0x0098 59*39d43904SHaijun Liu #define UL_CFG_BIT_MODE_36 BIT(5) 60*39d43904SHaijun Liu #define UL_CFG_BIT_MODE_40 BIT(6) 61*39d43904SHaijun Liu #define UL_CFG_BIT_MODE_64 BIT(7) 62*39d43904SHaijun Liu #define UL_CFG_BIT_MODE_MASK GENMASK(7, 5) 63*39d43904SHaijun Liu 64*39d43904SHaijun Liu #define REG_CLDMA_UL_MEM 0x009c 65*39d43904SHaijun Liu #define UL_MEM_CHECK_DIS BIT(0) 66*39d43904SHaijun Liu 67*39d43904SHaijun Liu /* CLDMA RX */ 68*39d43904SHaijun Liu #define REG_CLDMA_DL_START_CMD 0x05bc 69*39d43904SHaijun Liu #define REG_CLDMA_DL_RESUME_CMD 0x05c0 70*39d43904SHaijun Liu #define REG_CLDMA_DL_STOP_CMD 0x05c4 71*39d43904SHaijun Liu #define REG_CLDMA_DL_MEM 0x0508 72*39d43904SHaijun Liu #define DL_MEM_CHECK_DIS BIT(0) 73*39d43904SHaijun Liu 74*39d43904SHaijun Liu #define REG_CLDMA_DL_CFG 0x0404 75*39d43904SHaijun Liu #define DL_CFG_UP_HW_LAST BIT(2) 76*39d43904SHaijun Liu #define DL_CFG_BIT_MODE_36 BIT(10) 77*39d43904SHaijun Liu #define DL_CFG_BIT_MODE_40 BIT(11) 78*39d43904SHaijun Liu #define DL_CFG_BIT_MODE_64 BIT(12) 79*39d43904SHaijun Liu #define DL_CFG_BIT_MODE_MASK GENMASK(12, 10) 80*39d43904SHaijun Liu 81*39d43904SHaijun Liu #define REG_CLDMA_DL_START_ADDRL_0 0x0478 82*39d43904SHaijun Liu #define REG_CLDMA_DL_START_ADDRH_0 0x047c 83*39d43904SHaijun Liu #define REG_CLDMA_DL_CURRENT_ADDRL_0 0x04b8 84*39d43904SHaijun Liu #define REG_CLDMA_DL_CURRENT_ADDRH_0 0x04bc 85*39d43904SHaijun Liu #define REG_CLDMA_DL_STATUS 0x04f8 86*39d43904SHaijun Liu 87*39d43904SHaijun Liu /* CLDMA MISC */ 88*39d43904SHaijun Liu #define REG_CLDMA_L2TISAR0 0x0810 89*39d43904SHaijun Liu #define REG_CLDMA_L2TISAR1 0x0814 90*39d43904SHaijun Liu #define REG_CLDMA_L2TIMR0 0x0818 91*39d43904SHaijun Liu #define REG_CLDMA_L2TIMR1 0x081c 92*39d43904SHaijun Liu #define REG_CLDMA_L2TIMCR0 0x0820 93*39d43904SHaijun Liu #define REG_CLDMA_L2TIMCR1 0x0824 94*39d43904SHaijun Liu #define REG_CLDMA_L2TIMSR0 0x0828 95*39d43904SHaijun Liu #define REG_CLDMA_L2TIMSR1 0x082c 96*39d43904SHaijun Liu #define REG_CLDMA_L3TISAR0 0x0830 97*39d43904SHaijun Liu #define REG_CLDMA_L3TISAR1 0x0834 98*39d43904SHaijun Liu #define REG_CLDMA_L2RISAR0 0x0850 99*39d43904SHaijun Liu #define REG_CLDMA_L2RISAR1 0x0854 100*39d43904SHaijun Liu #define REG_CLDMA_L3RISAR0 0x0870 101*39d43904SHaijun Liu #define REG_CLDMA_L3RISAR1 0x0874 102*39d43904SHaijun Liu #define REG_CLDMA_IP_BUSY 0x08b4 103*39d43904SHaijun Liu #define IP_BUSY_WAKEUP BIT(0) 104*39d43904SHaijun Liu #define CLDMA_L2TISAR0_ALL_INT_MASK GENMASK(15, 0) 105*39d43904SHaijun Liu #define CLDMA_L2RISAR0_ALL_INT_MASK GENMASK(15, 0) 106*39d43904SHaijun Liu 107*39d43904SHaijun Liu /* CLDMA MISC */ 108*39d43904SHaijun Liu #define REG_CLDMA_L2RIMR0 0x0858 109*39d43904SHaijun Liu #define REG_CLDMA_L2RIMR1 0x085c 110*39d43904SHaijun Liu #define REG_CLDMA_L2RIMCR0 0x0860 111*39d43904SHaijun Liu #define REG_CLDMA_L2RIMCR1 0x0864 112*39d43904SHaijun Liu #define REG_CLDMA_L2RIMSR0 0x0868 113*39d43904SHaijun Liu #define REG_CLDMA_L2RIMSR1 0x086c 114*39d43904SHaijun Liu #define REG_CLDMA_BUSY_MASK 0x0954 115*39d43904SHaijun Liu #define BUSY_MASK_PCIE BIT(0) 116*39d43904SHaijun Liu #define BUSY_MASK_AP BIT(1) 117*39d43904SHaijun Liu #define BUSY_MASK_MD BIT(2) 118*39d43904SHaijun Liu 119*39d43904SHaijun Liu #define REG_CLDMA_INT_MASK 0x0960 120*39d43904SHaijun Liu 121*39d43904SHaijun Liu /* CLDMA RESET */ 122*39d43904SHaijun Liu #define REG_INFRA_RST4_SET 0x0730 123*39d43904SHaijun Liu #define RST4_CLDMA1_SW_RST_SET BIT(20) 124*39d43904SHaijun Liu 125*39d43904SHaijun Liu #define REG_INFRA_RST4_CLR 0x0734 126*39d43904SHaijun Liu #define RST4_CLDMA1_SW_RST_CLR BIT(20) 127*39d43904SHaijun Liu 128*39d43904SHaijun Liu #define REG_INFRA_RST2_SET 0x0140 129*39d43904SHaijun Liu #define RST2_PMIC_SW_RST_SET BIT(18) 130*39d43904SHaijun Liu 131*39d43904SHaijun Liu #define REG_INFRA_RST2_CLR 0x0144 132*39d43904SHaijun Liu #define RST2_PMIC_SW_RST_CLR BIT(18) 133*39d43904SHaijun Liu 134*39d43904SHaijun Liu enum mtk_txrx { 135*39d43904SHaijun Liu MTK_TX, 136*39d43904SHaijun Liu MTK_RX, 137*39d43904SHaijun Liu }; 138*39d43904SHaijun Liu 139*39d43904SHaijun Liu enum t7xx_hw_mode { 140*39d43904SHaijun Liu MODE_BIT_32, 141*39d43904SHaijun Liu MODE_BIT_36, 142*39d43904SHaijun Liu MODE_BIT_40, 143*39d43904SHaijun Liu MODE_BIT_64, 144*39d43904SHaijun Liu }; 145*39d43904SHaijun Liu 146*39d43904SHaijun Liu struct t7xx_cldma_hw { 147*39d43904SHaijun Liu enum t7xx_hw_mode hw_mode; 148*39d43904SHaijun Liu void __iomem *ap_ao_base; 149*39d43904SHaijun Liu void __iomem *ap_pdn_base; 150*39d43904SHaijun Liu u32 phy_interrupt_id; 151*39d43904SHaijun Liu }; 152*39d43904SHaijun Liu 153*39d43904SHaijun Liu void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno, 154*39d43904SHaijun Liu enum mtk_txrx tx_rx); 155*39d43904SHaijun Liu void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, 156*39d43904SHaijun Liu enum mtk_txrx tx_rx); 157*39d43904SHaijun Liu void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno, 158*39d43904SHaijun Liu enum mtk_txrx tx_rx); 159*39d43904SHaijun Liu void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx); 160*39d43904SHaijun Liu unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno, 161*39d43904SHaijun Liu enum mtk_txrx tx_rx); 162*39d43904SHaijun Liu void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info); 163*39d43904SHaijun Liu void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno, 164*39d43904SHaijun Liu enum mtk_txrx tx_rx); 165*39d43904SHaijun Liu void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info); 166*39d43904SHaijun Liu void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno, 167*39d43904SHaijun Liu enum mtk_txrx tx_rx); 168*39d43904SHaijun Liu void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask); 169*39d43904SHaijun Liu void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask); 170*39d43904SHaijun Liu void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx); 171*39d43904SHaijun Liu void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info, 172*39d43904SHaijun Liu unsigned int qno, u64 address, enum mtk_txrx tx_rx); 173*39d43904SHaijun Liu void t7xx_cldma_hw_reset(void __iomem *ao_base); 174*39d43904SHaijun Liu void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx); 175*39d43904SHaijun Liu unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask, 176*39d43904SHaijun Liu enum mtk_txrx tx_rx); 177*39d43904SHaijun Liu void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info); 178*39d43904SHaijun Liu void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info); 179*39d43904SHaijun Liu bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno); 180*39d43904SHaijun Liu #endif 181