1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright (C) 2020-21 Intel Corporation. 4 */ 5 6 #ifndef IOSM_IPC_MMIO_H 7 #define IOSM_IPC_MMIO_H 8 9 /* Minimal IOSM CP VERSION which has valid CP_CAPABILITIES field */ 10 #define IOSM_CP_VERSION 0x0100UL 11 12 /* DL dir Aggregation support mask */ 13 #define DL_AGGR BIT(9) 14 15 /* UL dir Aggregation support mask */ 16 #define UL_AGGR BIT(8) 17 18 /* UL flow credit support mask */ 19 #define UL_FLOW_CREDIT BIT(21) 20 21 /* Possible states of the IPC finite state machine. */ 22 enum ipc_mem_device_ipc_state { 23 IPC_MEM_DEVICE_IPC_UNINIT, 24 IPC_MEM_DEVICE_IPC_INIT, 25 IPC_MEM_DEVICE_IPC_RUNNING, 26 IPC_MEM_DEVICE_IPC_RECOVERY, 27 IPC_MEM_DEVICE_IPC_ERROR, 28 IPC_MEM_DEVICE_IPC_DONT_CARE, 29 IPC_MEM_DEVICE_IPC_INVALID = -1 30 }; 31 32 /* Boot ROM exit status. */ 33 enum rom_exit_code { 34 IMEM_ROM_EXIT_OPEN_EXT = 0x01, 35 IMEM_ROM_EXIT_OPEN_MEM = 0x02, 36 IMEM_ROM_EXIT_CERT_EXT = 0x10, 37 IMEM_ROM_EXIT_CERT_MEM = 0x20, 38 IMEM_ROM_EXIT_FAIL = 0xFF 39 }; 40 41 /* Boot stages */ 42 enum ipc_mem_exec_stage { 43 IPC_MEM_EXEC_STAGE_RUN = 0x600DF00D, 44 IPC_MEM_EXEC_STAGE_CRASH = 0x8BADF00D, 45 IPC_MEM_EXEC_STAGE_CD_READY = 0xBADC0DED, 46 IPC_MEM_EXEC_STAGE_BOOT = 0xFEEDB007, 47 IPC_MEM_EXEC_STAGE_PSI = 0xFEEDBEEF, 48 IPC_MEM_EXEC_STAGE_EBL = 0xFEEDCAFE, 49 IPC_MEM_EXEC_STAGE_INVALID = 0xFFFFFFFF 50 }; 51 52 /* mmio scratchpad info */ 53 struct mmio_offset { 54 int exec_stage; 55 int chip_info; 56 int rom_exit_code; 57 int psi_address; 58 int psi_size; 59 int ipc_status; 60 int context_info; 61 int ap_win_base; 62 int ap_win_end; 63 int cp_version; 64 int cp_capability; 65 }; 66 67 /** 68 * struct iosm_mmio - MMIO region mapped to the doorbell scratchpad. 69 * @base: Base address of MMIO region 70 * @dev: Pointer to device structure 71 * @offset: Start offset 72 * @context_info_addr: Physical base address of context info structure 73 * @chip_info_version: Version of chip info structure 74 * @chip_info_size: Size of chip info structure 75 * @mux_protocol: mux protocol 76 * @has_ul_flow_credit: Ul flow credit support 77 * @has_slp_no_prot: Device sleep no protocol support 78 * @has_mcr_support: Usage of mcr support 79 */ 80 struct iosm_mmio { 81 unsigned char __iomem *base; 82 struct device *dev; 83 struct mmio_offset offset; 84 phys_addr_t context_info_addr; 85 unsigned int chip_info_version; 86 unsigned int chip_info_size; 87 u32 mux_protocol; 88 u8 has_ul_flow_credit:1, 89 has_slp_no_prot:1, 90 has_mcr_support:1; 91 }; 92 93 /** 94 * ipc_mmio_init - Allocate mmio instance data 95 * @mmio_addr: Mapped AP base address of the MMIO area. 96 * @dev: Pointer to device structure 97 * 98 * Returns: address of mmio instance data or NULL if fails. 99 */ 100 struct iosm_mmio *ipc_mmio_init(void __iomem *mmio_addr, struct device *dev); 101 102 /** 103 * ipc_mmio_set_psi_addr_and_size - Set start address and size of the 104 * primary system image (PSI) for the 105 * FW dowload. 106 * @ipc_mmio: Pointer to mmio instance 107 * @addr: PSI address 108 * @size: PSI immage size 109 */ 110 void ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr, 111 u32 size); 112 113 /** 114 * ipc_mmio_set_contex_info_addr - Stores the Context Info Address in 115 * MMIO instance to share it with CP during 116 * mmio_init. 117 * @ipc_mmio: Pointer to mmio instance 118 * @addr: 64-bit address of AP context information. 119 */ 120 void ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio, 121 phys_addr_t addr); 122 123 /** 124 * ipc_mmio_get_cp_version - Get the CP IPC version 125 * @ipc_mmio: Pointer to mmio instance 126 * 127 * Returns: version number on success and failure value on error. 128 */ 129 int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio); 130 131 /** 132 * ipc_mmio_get_rom_exit_code - Get exit code from CP boot rom download app 133 * @ipc_mmio: Pointer to mmio instance 134 * 135 * Returns: exit code from CP boot rom download APP 136 */ 137 enum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio); 138 139 /** 140 * ipc_mmio_get_exec_stage - Query CP execution stage 141 * @ipc_mmio: Pointer to mmio instance 142 * 143 * Returns: CP execution stage 144 */ 145 enum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio); 146 147 /** 148 * ipc_mmio_get_ipc_state - Query CP IPC state 149 * @ipc_mmio: Pointer to mmio instance 150 * 151 * Returns: CP IPC state 152 */ 153 enum ipc_mem_device_ipc_state 154 ipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio); 155 156 /** 157 * ipc_mmio_copy_chip_info - Copy size bytes of CP chip info structure 158 * into caller provided buffer 159 * @ipc_mmio: Pointer to mmio instance 160 * @dest: Pointer to caller provided buff 161 * @size: Number of bytes to copy 162 */ 163 void ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest, 164 size_t size); 165 166 /** 167 * ipc_mmio_config - Write context info and AP memory range addresses. 168 * This needs to be called when CP is in 169 * IPC_MEM_DEVICE_IPC_INIT state 170 * 171 * @ipc_mmio: Pointer to mmio instance 172 */ 173 void ipc_mmio_config(struct iosm_mmio *ipc_mmio); 174 175 /** 176 * ipc_mmio_update_cp_capability - Read and update modem capability, from mmio 177 * capability offset 178 * 179 * @ipc_mmio: Pointer to mmio instance 180 */ 181 void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio); 182 183 #endif 184