1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright (C) 2020-21 Intel Corporation. 4 */ 5 6 #ifndef IOSM_IPC_IMEM_H 7 #define IOSM_IPC_IMEM_H 8 9 #include <linux/skbuff.h> 10 11 #include "iosm_ipc_mmio.h" 12 #include "iosm_ipc_pcie.h" 13 #include "iosm_ipc_uevent.h" 14 #include "iosm_ipc_wwan.h" 15 #include "iosm_ipc_task_queue.h" 16 17 struct ipc_chnl_cfg; 18 19 /* IRQ moderation in usec */ 20 #define IRQ_MOD_OFF 0 21 #define IRQ_MOD_NET 1000 22 #define IRQ_MOD_TRC 4000 23 24 /* Either the PSI image is accepted by CP or the suspended flash tool is waken, 25 * informed that the CP ROM driver is not ready to process the PSI image. 26 * unit : milliseconds 27 */ 28 #define IPC_PSI_TRANSFER_TIMEOUT 3000 29 30 /* Timeout in 20 msec to wait for the modem to boot up to 31 * IPC_MEM_DEVICE_IPC_INIT state. 32 * unit : milliseconds (500 * ipc_util_msleep(20)) 33 */ 34 #define IPC_MODEM_BOOT_TIMEOUT 500 35 36 /* Wait timeout for ipc status reflects IPC_MEM_DEVICE_IPC_UNINIT 37 * unit : milliseconds 38 */ 39 #define IPC_MODEM_UNINIT_TIMEOUT_MS 30 40 41 /* Pending time for processing data. 42 * unit : milliseconds 43 */ 44 #define IPC_PEND_DATA_TIMEOUT 500 45 46 /* The timeout in milliseconds for application to wait for remote time. */ 47 #define IPC_REMOTE_TS_TIMEOUT_MS 10 48 49 /* Timeout for TD allocation retry. 50 * unit : milliseconds 51 */ 52 #define IPC_TD_ALLOC_TIMER_PERIOD_MS 100 53 54 /* Host sleep target is host */ 55 #define IPC_HOST_SLEEP_HOST 0 56 57 /* Host sleep target is device */ 58 #define IPC_HOST_SLEEP_DEVICE 1 59 60 /* Sleep message, target host: AP enters sleep / target device: CP is 61 * allowed to enter sleep and shall use the host sleep protocol 62 */ 63 #define IPC_HOST_SLEEP_ENTER_SLEEP 0 64 65 /* Sleep_message, target host: AP exits sleep / target device: CP is 66 * NOT allowed to enter sleep 67 */ 68 #define IPC_HOST_SLEEP_EXIT_SLEEP 1 69 70 #define IMEM_IRQ_DONT_CARE (-1) 71 72 #define IPC_MEM_MAX_CHANNELS 7 73 74 #define IPC_MEM_MUX_IP_SESSION_ENTRIES 8 75 76 #define IPC_MEM_MUX_IP_CH_IF_ID 0 77 78 #define TD_UPDATE_DEFAULT_TIMEOUT_USEC 1900 79 80 #define FORCE_UPDATE_DEFAULT_TIMEOUT_USEC 500 81 82 /* Sleep_message, target host: not applicable / target device: CP is 83 * allowed to enter sleep and shall NOT use the device sleep protocol 84 */ 85 #define IPC_HOST_SLEEP_ENTER_SLEEP_NO_PROTOCOL 2 86 87 /* in_band_crash_signal IPC_MEM_INBAND_CRASH_SIG 88 * Modem crash notification configuration. If this value is non-zero then 89 * FEATURE_SET message will be sent to the Modem as a result the Modem will 90 * signal Crash via Execution Stage register. If this value is zero then Modem 91 * will use out-of-band method to notify about it's Crash. 92 */ 93 #define IPC_MEM_INBAND_CRASH_SIG 1 94 95 /* Extra headroom to be allocated for DL SKBs to allow addition of Ethernet 96 * header 97 */ 98 #define IPC_MEM_DL_ETH_OFFSET 16 99 100 #define IPC_CB(skb) ((struct ipc_skb_cb *)((skb)->cb)) 101 102 #define FULLY_FUNCTIONAL 0 103 104 /* List of the supported UL/DL pipes. */ 105 enum ipc_mem_pipes { 106 IPC_MEM_PIPE_0 = 0, 107 IPC_MEM_PIPE_1, 108 IPC_MEM_PIPE_2, 109 IPC_MEM_PIPE_3, 110 IPC_MEM_PIPE_4, 111 IPC_MEM_PIPE_5, 112 IPC_MEM_PIPE_6, 113 IPC_MEM_PIPE_7, 114 IPC_MEM_PIPE_8, 115 IPC_MEM_PIPE_9, 116 IPC_MEM_PIPE_10, 117 IPC_MEM_PIPE_11, 118 IPC_MEM_PIPE_12, 119 IPC_MEM_PIPE_13, 120 IPC_MEM_PIPE_14, 121 IPC_MEM_PIPE_15, 122 IPC_MEM_PIPE_16, 123 IPC_MEM_PIPE_17, 124 IPC_MEM_PIPE_18, 125 IPC_MEM_PIPE_19, 126 IPC_MEM_PIPE_20, 127 IPC_MEM_PIPE_21, 128 IPC_MEM_PIPE_22, 129 IPC_MEM_PIPE_23, 130 IPC_MEM_MAX_PIPES 131 }; 132 133 /* Enum defining channel states. */ 134 enum ipc_channel_state { 135 IMEM_CHANNEL_FREE, 136 IMEM_CHANNEL_RESERVED, 137 IMEM_CHANNEL_ACTIVE, 138 IMEM_CHANNEL_CLOSING, 139 }; 140 141 /* Time Unit */ 142 enum ipc_time_unit { 143 IPC_SEC = 0, 144 IPC_MILLI_SEC = 1, 145 IPC_MICRO_SEC = 2, 146 IPC_NANO_SEC = 3, 147 IPC_PICO_SEC = 4, 148 IPC_FEMTO_SEC = 5, 149 IPC_ATTO_SEC = 6, 150 }; 151 152 /** 153 * enum ipc_ctype - Enum defining supported channel type needed for control 154 * /IP traffic. 155 * @IPC_CTYPE_WWAN: Used for IP traffic 156 * @IPC_CTYPE_CTRL: Used for Control Communication 157 */ 158 enum ipc_ctype { 159 IPC_CTYPE_WWAN, 160 IPC_CTYPE_CTRL, 161 }; 162 163 /* Pipe direction. */ 164 enum ipc_mem_pipe_dir { 165 IPC_MEM_DIR_UL, 166 IPC_MEM_DIR_DL, 167 }; 168 169 /* HP update identifier. To be used as data for ipc_cp_irq_hpda_update() */ 170 enum ipc_hp_identifier { 171 IPC_HP_MR = 0, 172 IPC_HP_PM_TRIGGER, 173 IPC_HP_WAKEUP_SPEC_TMR, 174 IPC_HP_TD_UPD_TMR_START, 175 IPC_HP_TD_UPD_TMR, 176 IPC_HP_FAST_TD_UPD_TMR, 177 IPC_HP_UL_WRITE_TD, 178 IPC_HP_DL_PROCESS, 179 IPC_HP_NET_CHANNEL_INIT, 180 IPC_HP_CDEV_OPEN, 181 }; 182 183 /** 184 * struct ipc_pipe - Structure for Pipe. 185 * @tdr_start: Ipc private protocol Transfer Descriptor Ring 186 * @channel: Id of the sio device, set by imem_sio_open, 187 * needed to pass DL char to the user terminal 188 * @skbr_start: Circular buffer for skbuf and the buffer 189 * reference in a tdr_start entry. 190 * @phy_tdr_start: Transfer descriptor start address 191 * @old_head: last head pointer reported to CP. 192 * @old_tail: AP read position before CP moves the read 193 * position to write/head. If CP has consumed the 194 * buffers, AP has to freed the skbuf starting at 195 * tdr_start[old_tail]. 196 * @nr_of_entries: Number of elements of skb_start and tdr_start. 197 * @max_nr_of_queued_entries: Maximum number of queued entries in TDR 198 * @accumulation_backoff: Accumulation in usec for accumulation 199 * backoff (0 = no acc backoff) 200 * @irq_moderation: timer in usec for irq_moderation 201 * (0=no irq moderation) 202 * @pipe_nr: Pipe identification number 203 * @irq: Interrupt vector 204 * @dir: Direction of data stream in pipe 205 * @td_tag: Unique tag of the buffer queued 206 * @buf_size: Buffer size (in bytes) for preallocated 207 * buffers (for DL pipes) 208 * @nr_of_queued_entries: Aueued number of entries 209 * @is_open: Check for open pipe status 210 */ 211 struct ipc_pipe { 212 struct ipc_protocol_td *tdr_start; 213 struct ipc_mem_channel *channel; 214 struct sk_buff **skbr_start; 215 dma_addr_t phy_tdr_start; 216 u32 old_head; 217 u32 old_tail; 218 u32 nr_of_entries; 219 u32 max_nr_of_queued_entries; 220 u32 accumulation_backoff; 221 u32 irq_moderation; 222 u32 pipe_nr; 223 u32 irq; 224 enum ipc_mem_pipe_dir dir; 225 u32 td_tag; 226 u32 buf_size; 227 u16 nr_of_queued_entries; 228 u8 is_open:1; 229 }; 230 231 /** 232 * struct ipc_mem_channel - Structure for Channel. 233 * @channel_id: Instance of the channel list and is return to the user 234 * at the end of the open operation. 235 * @ctype: Control or netif channel. 236 * @index: unique index per ctype 237 * @ul_pipe: pipe objects 238 * @dl_pipe: pipe objects 239 * @if_id: Interface ID 240 * @net_err_count: Number of downlink errors returned by ipc_wwan_receive 241 * interface at the entry point of the IP stack. 242 * @state: Free, reserved or busy (in use). 243 * @ul_sem: Needed for the blocking write or uplink transfer. 244 * @ul_list: Uplink accumulator which is filled by the uplink 245 * char app or IP stack. The socket buffer pointer are 246 * added to the descriptor list in the kthread context. 247 */ 248 struct ipc_mem_channel { 249 int channel_id; 250 enum ipc_ctype ctype; 251 int index; 252 struct ipc_pipe ul_pipe; 253 struct ipc_pipe dl_pipe; 254 int if_id; 255 u32 net_err_count; 256 enum ipc_channel_state state; 257 struct completion ul_sem; 258 struct sk_buff_head ul_list; 259 }; 260 261 /** 262 * enum ipc_phase - Different AP and CP phases. 263 * The enums defined after "IPC_P_ROM" and before 264 * "IPC_P_RUN" indicates the operating state where CP can 265 * respond to any requests. So while introducing new phase 266 * this shall be taken into consideration. 267 * @IPC_P_OFF: On host PC, the PCIe device link settings are known 268 * about the combined power on. PC is running, the driver 269 * is loaded and CP is in power off mode. The PCIe bus 270 * driver call the device power mode D3hot. In this phase 271 * the driver the polls the device, until the device is in 272 * the power on state and signals the power mode D0. 273 * @IPC_P_OFF_REQ: The intermediate phase between cleanup activity starts 274 * and ends. 275 * @IPC_P_CRASH: The phase indicating CP crash 276 * @IPC_P_CD_READY: The phase indicating CP core dump is ready 277 * @IPC_P_ROM: After power on, CP starts in ROM mode and the IPC ROM 278 * driver is waiting 150 ms for the AP active notification 279 * saved in the PCI link status register. 280 * @IPC_P_PSI: Primary signed image download phase 281 * @IPC_P_EBL: Extended bootloader pahse 282 * @IPC_P_RUN: The phase after flashing to RAM is the RUNTIME phase. 283 */ 284 enum ipc_phase { 285 IPC_P_OFF, 286 IPC_P_OFF_REQ, 287 IPC_P_CRASH, 288 IPC_P_CD_READY, 289 IPC_P_ROM, 290 IPC_P_PSI, 291 IPC_P_EBL, 292 IPC_P_RUN, 293 }; 294 295 /** 296 * struct iosm_imem - Current state of the IPC shared memory. 297 * @mmio: mmio instance to access CP MMIO area / 298 * doorbell scratchpad. 299 * @ipc_protocol: IPC Protocol instance 300 * @ipc_task: Task for entry into ipc task queue 301 * @wwan: WWAN device pointer 302 * @mux: IP Data multiplexing state. 303 * @sio: IPC SIO data structure pointer 304 * @ipc_port: IPC PORT data structure pointer 305 * @pcie: IPC PCIe 306 * @dev: Pointer to device structure 307 * @flash_channel_id: Reserved channel id for flashing to RAM. 308 * @ipc_requested_state: Expected IPC state on CP. 309 * @channels: Channel list with UL/DL pipe pairs. 310 * @ipc_status: local ipc_status 311 * @nr_of_channels: number of configured channels 312 * @startup_timer: startup timer for NAND support. 313 * @hrtimer_period: Hr timer period 314 * @tdupdate_timer: Delay the TD update doorbell. 315 * @fast_update_timer: forced head pointer update delay timer. 316 * @td_alloc_timer: Timer for DL pipe TD allocation retry 317 * @rom_exit_code: Mapped boot rom exit code. 318 * @enter_runtime: 1 means the transition to runtime phase was 319 * executed. 320 * @ul_pend_sem: Semaphore to wait/complete of UL TDs 321 * before closing pipe. 322 * @app_notify_ul_pend: Signal app if UL TD is pending 323 * @dl_pend_sem: Semaphore to wait/complete of DL TDs 324 * before closing pipe. 325 * @app_notify_dl_pend: Signal app if DL TD is pending 326 * @phase: Operating phase like runtime. 327 * @pci_device_id: Device ID 328 * @cp_version: CP version 329 * @device_sleep: Device sleep state 330 * @run_state_worker: Pointer to worker component for device 331 * setup operations to be called when modem 332 * reaches RUN state 333 * @ev_irq_pending: 0 means inform the IPC tasklet to 334 * process the irq actions. 335 * @flag: Flag to monitor the state of driver 336 * @td_update_timer_suspended: if true then td update timer suspend 337 * @ev_cdev_write_pending: 0 means inform the IPC tasklet to pass 338 * the accumulated uplink buffers to CP. 339 * @ev_mux_net_transmit_pending:0 means inform the IPC tasklet to pass 340 * @reset_det_n: Reset detect flag 341 * @pcie_wake_n: Pcie wake flag 342 */ 343 struct iosm_imem { 344 struct iosm_mmio *mmio; 345 struct iosm_protocol *ipc_protocol; 346 struct ipc_task *ipc_task; 347 struct iosm_wwan *wwan; 348 struct iosm_mux *mux; 349 struct iosm_cdev *ipc_port[IPC_MEM_MAX_CHANNELS]; 350 struct iosm_pcie *pcie; 351 struct device *dev; 352 int flash_channel_id; 353 enum ipc_mem_device_ipc_state ipc_requested_state; 354 struct ipc_mem_channel channels[IPC_MEM_MAX_CHANNELS]; 355 u32 ipc_status; 356 u32 nr_of_channels; 357 struct hrtimer startup_timer; 358 ktime_t hrtimer_period; 359 struct hrtimer tdupdate_timer; 360 struct hrtimer fast_update_timer; 361 struct hrtimer td_alloc_timer; 362 enum rom_exit_code rom_exit_code; 363 u32 enter_runtime; 364 struct completion ul_pend_sem; 365 u32 app_notify_ul_pend; 366 struct completion dl_pend_sem; 367 u32 app_notify_dl_pend; 368 enum ipc_phase phase; 369 u16 pci_device_id; 370 int cp_version; 371 int device_sleep; 372 struct work_struct run_state_worker; 373 u8 ev_irq_pending[IPC_IRQ_VECTORS]; 374 unsigned long flag; 375 u8 td_update_timer_suspended:1, 376 ev_cdev_write_pending:1, 377 ev_mux_net_transmit_pending:1, 378 reset_det_n:1, 379 pcie_wake_n:1; 380 }; 381 382 /** 383 * ipc_imem_init - Initialize the shared memory region 384 * @pcie: Pointer to core driver data-struct 385 * @device_id: PCI device ID 386 * @mmio: Pointer to the mmio area 387 * @dev: Pointer to device structure 388 * 389 * Returns: Initialized imem pointer on success else NULL 390 */ 391 struct iosm_imem *ipc_imem_init(struct iosm_pcie *pcie, unsigned int device_id, 392 void __iomem *mmio, struct device *dev); 393 394 /** 395 * ipc_imem_pm_s2idle_sleep - Set PM variables to sleep/active for 396 * s2idle sleep/active 397 * @ipc_imem: Pointer to imem data-struct 398 * @sleep: Set PM Variable to sleep/active 399 */ 400 void ipc_imem_pm_s2idle_sleep(struct iosm_imem *ipc_imem, bool sleep); 401 402 /** 403 * ipc_imem_pm_suspend - The HAL shall ask the shared memory layer 404 * whether D3 is allowed. 405 * @ipc_imem: Pointer to imem data-struct 406 */ 407 void ipc_imem_pm_suspend(struct iosm_imem *ipc_imem); 408 409 /** 410 * ipc_imem_pm_resume - The HAL shall inform the shared memory layer 411 * that the device is active. 412 * @ipc_imem: Pointer to imem data-struct 413 */ 414 void ipc_imem_pm_resume(struct iosm_imem *ipc_imem); 415 416 /** 417 * ipc_imem_cleanup - Inform CP and free the shared memory resources. 418 * @ipc_imem: Pointer to imem data-struct 419 */ 420 void ipc_imem_cleanup(struct iosm_imem *ipc_imem); 421 422 /** 423 * ipc_imem_irq_process - Shift the IRQ actions to the IPC thread. 424 * @ipc_imem: Pointer to imem data-struct 425 * @irq: Irq number 426 */ 427 void ipc_imem_irq_process(struct iosm_imem *ipc_imem, int irq); 428 429 /** 430 * imem_get_device_sleep_state - Get the device sleep state value. 431 * @ipc_imem: Pointer to imem instance 432 * 433 * Returns: device sleep state 434 */ 435 int imem_get_device_sleep_state(struct iosm_imem *ipc_imem); 436 437 /** 438 * ipc_imem_td_update_timer_suspend - Updates the TD Update Timer suspend flag. 439 * @ipc_imem: Pointer to imem data-struct 440 * @suspend: Flag to update. If TRUE then HP update doorbell is triggered to 441 * device without any wait. If FALSE then HP update doorbell is 442 * delayed until timeout. 443 */ 444 void ipc_imem_td_update_timer_suspend(struct iosm_imem *ipc_imem, bool suspend); 445 446 /** 447 * ipc_imem_channel_close - Release the channel resources. 448 * @ipc_imem: Pointer to imem data-struct 449 * @channel_id: Channel ID to be cleaned up. 450 */ 451 void ipc_imem_channel_close(struct iosm_imem *ipc_imem, int channel_id); 452 453 /** 454 * ipc_imem_channel_alloc - Reserves a channel 455 * @ipc_imem: Pointer to imem data-struct 456 * @index: ID to lookup from the preallocated list. 457 * @ctype: Channel type. 458 * 459 * Returns: Index on success and failure value on error 460 */ 461 int ipc_imem_channel_alloc(struct iosm_imem *ipc_imem, int index, 462 enum ipc_ctype ctype); 463 464 /** 465 * ipc_imem_channel_open - Establish the pipes. 466 * @ipc_imem: Pointer to imem data-struct 467 * @channel_id: Channel ID returned during alloc. 468 * @db_id: Doorbell ID for trigger identifier. 469 * 470 * Returns: Pointer of ipc_mem_channel on success and NULL on failure. 471 */ 472 struct ipc_mem_channel *ipc_imem_channel_open(struct iosm_imem *ipc_imem, 473 int channel_id, u32 db_id); 474 475 /** 476 * ipc_imem_td_update_timer_start - Starts the TD Update Timer if not running. 477 * @ipc_imem: Pointer to imem data-struct 478 */ 479 void ipc_imem_td_update_timer_start(struct iosm_imem *ipc_imem); 480 481 /** 482 * ipc_imem_ul_write_td - Pass the channel UL list to protocol layer for TD 483 * preparation and sending them to the device. 484 * @ipc_imem: Pointer to imem data-struct 485 * 486 * Returns: TRUE of HP Doorbell trigger is pending. FALSE otherwise. 487 */ 488 bool ipc_imem_ul_write_td(struct iosm_imem *ipc_imem); 489 490 /** 491 * ipc_imem_ul_send - Dequeue SKB from channel list and start with 492 * the uplink transfer.If HP Doorbell is pending to be 493 * triggered then starts the TD Update Timer. 494 * @ipc_imem: Pointer to imem data-struct 495 */ 496 void ipc_imem_ul_send(struct iosm_imem *ipc_imem); 497 498 /** 499 * ipc_imem_channel_update - Set or modify pipe config of an existing channel 500 * @ipc_imem: Pointer to imem data-struct 501 * @id: Channel config index 502 * @chnl_cfg: Channel config struct 503 * @irq_moderation: Timer in usec for irq_moderation 504 */ 505 void ipc_imem_channel_update(struct iosm_imem *ipc_imem, int id, 506 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 507 508 /** 509 * ipc_imem_channel_free -Free an IPC channel. 510 * @channel: Channel to be freed 511 */ 512 void ipc_imem_channel_free(struct ipc_mem_channel *channel); 513 514 /** 515 * ipc_imem_hrtimer_stop - Stop the hrtimer 516 * @hr_timer: Pointer to hrtimer instance 517 */ 518 void ipc_imem_hrtimer_stop(struct hrtimer *hr_timer); 519 520 /** 521 * ipc_imem_pipe_cleanup - Reset volatile pipe content for all channels 522 * @ipc_imem: Pointer to imem data-struct 523 * @pipe: Pipe to cleaned up 524 */ 525 void ipc_imem_pipe_cleanup(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 526 527 /** 528 * ipc_imem_pipe_close - Send msg to device to close pipe 529 * @ipc_imem: Pointer to imem data-struct 530 * @pipe: Pipe to be closed 531 */ 532 void ipc_imem_pipe_close(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 533 534 /** 535 * ipc_imem_phase_update - Get the CP execution state 536 * and map it to the AP phase. 537 * @ipc_imem: Pointer to imem data-struct 538 * 539 * Returns: Current ap updated phase 540 */ 541 enum ipc_phase ipc_imem_phase_update(struct iosm_imem *ipc_imem); 542 543 /** 544 * ipc_imem_phase_get_string - Return the current operation 545 * phase as string. 546 * @phase: AP phase 547 * 548 * Returns: AP phase string 549 */ 550 const char *ipc_imem_phase_get_string(enum ipc_phase phase); 551 552 /** 553 * ipc_imem_msg_send_feature_set - Send feature set message to modem 554 * @ipc_imem: Pointer to imem data-struct 555 * @reset_enable: 0 = out-of-band, 1 = in-band-crash notification 556 * @atomic_ctx: if disabled call in tasklet context 557 * 558 */ 559 void ipc_imem_msg_send_feature_set(struct iosm_imem *ipc_imem, 560 unsigned int reset_enable, bool atomic_ctx); 561 562 /** 563 * ipc_imem_ipc_init_check - Send the init event to CP, wait a certain time and 564 * set CP to runtime with the context information 565 * @ipc_imem: Pointer to imem data-struct 566 */ 567 void ipc_imem_ipc_init_check(struct iosm_imem *ipc_imem); 568 569 /** 570 * ipc_imem_channel_init - Initialize the channel list with UL/DL pipe pairs. 571 * @ipc_imem: Pointer to imem data-struct 572 * @ctype: Channel type 573 * @chnl_cfg: Channel configuration struct 574 * @irq_moderation: Timer in usec for irq_moderation 575 */ 576 void ipc_imem_channel_init(struct iosm_imem *ipc_imem, enum ipc_ctype ctype, 577 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 578 #endif 579