1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright (C) 2020-21 Intel Corporation. 4 */ 5 6 #ifndef IOSM_IPC_IMEM_H 7 #define IOSM_IPC_IMEM_H 8 9 #include <linux/skbuff.h> 10 11 #include "iosm_ipc_mmio.h" 12 #include "iosm_ipc_pcie.h" 13 #include "iosm_ipc_uevent.h" 14 #include "iosm_ipc_wwan.h" 15 #include "iosm_ipc_task_queue.h" 16 17 struct ipc_chnl_cfg; 18 19 /* IRQ moderation in usec */ 20 #define IRQ_MOD_OFF 0 21 #define IRQ_MOD_NET 1000 22 #define IRQ_MOD_TRC 4000 23 24 /* Either the PSI image is accepted by CP or the suspended flash tool is waken, 25 * informed that the CP ROM driver is not ready to process the PSI image. 26 * unit : milliseconds 27 */ 28 #define IPC_PSI_TRANSFER_TIMEOUT 3000 29 30 /* Timeout in 20 msec to wait for the modem to boot up to 31 * IPC_MEM_DEVICE_IPC_INIT state. 32 * unit : milliseconds (500 * ipc_util_msleep(20)) 33 */ 34 #define IPC_MODEM_BOOT_TIMEOUT 500 35 36 /* Wait timeout for ipc status reflects IPC_MEM_DEVICE_IPC_UNINIT 37 * unit : milliseconds 38 */ 39 #define IPC_MODEM_UNINIT_TIMEOUT_MS 30 40 41 /* Pending time for processing data. 42 * unit : milliseconds 43 */ 44 #define IPC_PEND_DATA_TIMEOUT 500 45 46 /* The timeout in milliseconds for application to wait for remote time. */ 47 #define IPC_REMOTE_TS_TIMEOUT_MS 10 48 49 /* Timeout for TD allocation retry. 50 * unit : milliseconds 51 */ 52 #define IPC_TD_ALLOC_TIMER_PERIOD_MS 100 53 54 /* Host sleep target is host */ 55 #define IPC_HOST_SLEEP_HOST 0 56 57 /* Host sleep target is device */ 58 #define IPC_HOST_SLEEP_DEVICE 1 59 60 /* Sleep message, target host: AP enters sleep / target device: CP is 61 * allowed to enter sleep and shall use the host sleep protocol 62 */ 63 #define IPC_HOST_SLEEP_ENTER_SLEEP 0 64 65 /* Sleep_message, target host: AP exits sleep / target device: CP is 66 * NOT allowed to enter sleep 67 */ 68 #define IPC_HOST_SLEEP_EXIT_SLEEP 1 69 70 #define IMEM_IRQ_DONT_CARE (-1) 71 72 #define IPC_MEM_MAX_CHANNELS 8 73 74 #define IPC_MEM_MUX_IP_SESSION_ENTRIES 8 75 76 #define IPC_MEM_MUX_IP_CH_IF_ID 0 77 78 #define TD_UPDATE_DEFAULT_TIMEOUT_USEC 1900 79 80 #define FORCE_UPDATE_DEFAULT_TIMEOUT_USEC 500 81 82 /* Sleep_message, target host: not applicable / target device: CP is 83 * allowed to enter sleep and shall NOT use the device sleep protocol 84 */ 85 #define IPC_HOST_SLEEP_ENTER_SLEEP_NO_PROTOCOL 2 86 87 /* in_band_crash_signal IPC_MEM_INBAND_CRASH_SIG 88 * Modem crash notification configuration. If this value is non-zero then 89 * FEATURE_SET message will be sent to the Modem as a result the Modem will 90 * signal Crash via Execution Stage register. If this value is zero then Modem 91 * will use out-of-band method to notify about it's Crash. 92 */ 93 #define IPC_MEM_INBAND_CRASH_SIG 1 94 95 /* Extra headroom to be allocated for DL SKBs to allow addition of Ethernet 96 * header 97 */ 98 #define IPC_MEM_DL_ETH_OFFSET 16 99 100 #define IPC_CB(skb) ((struct ipc_skb_cb *)((skb)->cb)) 101 #define IOSM_CHIP_INFO_SIZE_MAX 100 102 103 #define FULLY_FUNCTIONAL 0 104 #define IOSM_DEVLINK_INIT 1 105 106 /* List of the supported UL/DL pipes. */ 107 enum ipc_mem_pipes { 108 IPC_MEM_PIPE_0 = 0, 109 IPC_MEM_PIPE_1, 110 IPC_MEM_PIPE_2, 111 IPC_MEM_PIPE_3, 112 IPC_MEM_PIPE_4, 113 IPC_MEM_PIPE_5, 114 IPC_MEM_PIPE_6, 115 IPC_MEM_PIPE_7, 116 IPC_MEM_PIPE_8, 117 IPC_MEM_PIPE_9, 118 IPC_MEM_PIPE_10, 119 IPC_MEM_PIPE_11, 120 IPC_MEM_PIPE_12, 121 IPC_MEM_PIPE_13, 122 IPC_MEM_PIPE_14, 123 IPC_MEM_PIPE_15, 124 IPC_MEM_PIPE_16, 125 IPC_MEM_PIPE_17, 126 IPC_MEM_PIPE_18, 127 IPC_MEM_PIPE_19, 128 IPC_MEM_PIPE_20, 129 IPC_MEM_PIPE_21, 130 IPC_MEM_PIPE_22, 131 IPC_MEM_PIPE_23, 132 IPC_MEM_MAX_PIPES 133 }; 134 135 /* Enum defining channel states. */ 136 enum ipc_channel_state { 137 IMEM_CHANNEL_FREE, 138 IMEM_CHANNEL_RESERVED, 139 IMEM_CHANNEL_ACTIVE, 140 IMEM_CHANNEL_CLOSING, 141 }; 142 143 /* Time Unit */ 144 enum ipc_time_unit { 145 IPC_SEC = 0, 146 IPC_MILLI_SEC = 1, 147 IPC_MICRO_SEC = 2, 148 IPC_NANO_SEC = 3, 149 IPC_PICO_SEC = 4, 150 IPC_FEMTO_SEC = 5, 151 IPC_ATTO_SEC = 6, 152 }; 153 154 /** 155 * enum ipc_ctype - Enum defining supported channel type needed for control 156 * /IP traffic. 157 * @IPC_CTYPE_WWAN: Used for IP traffic 158 * @IPC_CTYPE_CTRL: Used for Control Communication 159 */ 160 enum ipc_ctype { 161 IPC_CTYPE_WWAN, 162 IPC_CTYPE_CTRL, 163 }; 164 165 /* Pipe direction. */ 166 enum ipc_mem_pipe_dir { 167 IPC_MEM_DIR_UL, 168 IPC_MEM_DIR_DL, 169 }; 170 171 /* HP update identifier. To be used as data for ipc_cp_irq_hpda_update() */ 172 enum ipc_hp_identifier { 173 IPC_HP_MR = 0, 174 IPC_HP_PM_TRIGGER, 175 IPC_HP_WAKEUP_SPEC_TMR, 176 IPC_HP_TD_UPD_TMR_START, 177 IPC_HP_TD_UPD_TMR, 178 IPC_HP_FAST_TD_UPD_TMR, 179 IPC_HP_UL_WRITE_TD, 180 IPC_HP_DL_PROCESS, 181 IPC_HP_NET_CHANNEL_INIT, 182 IPC_HP_CDEV_OPEN, 183 }; 184 185 /** 186 * struct ipc_pipe - Structure for Pipe. 187 * @tdr_start: Ipc private protocol Transfer Descriptor Ring 188 * @channel: Id of the sio device, set by imem_sio_open, 189 * needed to pass DL char to the user terminal 190 * @skbr_start: Circular buffer for skbuf and the buffer 191 * reference in a tdr_start entry. 192 * @phy_tdr_start: Transfer descriptor start address 193 * @old_head: last head pointer reported to CP. 194 * @old_tail: AP read position before CP moves the read 195 * position to write/head. If CP has consumed the 196 * buffers, AP has to freed the skbuf starting at 197 * tdr_start[old_tail]. 198 * @nr_of_entries: Number of elements of skb_start and tdr_start. 199 * @max_nr_of_queued_entries: Maximum number of queued entries in TDR 200 * @accumulation_backoff: Accumulation in usec for accumulation 201 * backoff (0 = no acc backoff) 202 * @irq_moderation: timer in usec for irq_moderation 203 * (0=no irq moderation) 204 * @pipe_nr: Pipe identification number 205 * @irq: Interrupt vector 206 * @dir: Direction of data stream in pipe 207 * @td_tag: Unique tag of the buffer queued 208 * @buf_size: Buffer size (in bytes) for preallocated 209 * buffers (for DL pipes) 210 * @nr_of_queued_entries: Aueued number of entries 211 * @is_open: Check for open pipe status 212 */ 213 struct ipc_pipe { 214 struct ipc_protocol_td *tdr_start; 215 struct ipc_mem_channel *channel; 216 struct sk_buff **skbr_start; 217 dma_addr_t phy_tdr_start; 218 u32 old_head; 219 u32 old_tail; 220 u32 nr_of_entries; 221 u32 max_nr_of_queued_entries; 222 u32 accumulation_backoff; 223 u32 irq_moderation; 224 u32 pipe_nr; 225 u32 irq; 226 enum ipc_mem_pipe_dir dir; 227 u32 td_tag; 228 u32 buf_size; 229 u16 nr_of_queued_entries; 230 u8 is_open:1; 231 }; 232 233 /** 234 * struct ipc_mem_channel - Structure for Channel. 235 * @channel_id: Instance of the channel list and is return to the user 236 * at the end of the open operation. 237 * @ctype: Control or netif channel. 238 * @index: unique index per ctype 239 * @ul_pipe: pipe objects 240 * @dl_pipe: pipe objects 241 * @if_id: Interface ID 242 * @net_err_count: Number of downlink errors returned by ipc_wwan_receive 243 * interface at the entry point of the IP stack. 244 * @state: Free, reserved or busy (in use). 245 * @ul_sem: Needed for the blocking write or uplink transfer. 246 * @ul_list: Uplink accumulator which is filled by the uplink 247 * char app or IP stack. The socket buffer pointer are 248 * added to the descriptor list in the kthread context. 249 */ 250 struct ipc_mem_channel { 251 int channel_id; 252 enum ipc_ctype ctype; 253 int index; 254 struct ipc_pipe ul_pipe; 255 struct ipc_pipe dl_pipe; 256 int if_id; 257 u32 net_err_count; 258 enum ipc_channel_state state; 259 struct completion ul_sem; 260 struct sk_buff_head ul_list; 261 }; 262 263 /** 264 * enum ipc_phase - Different AP and CP phases. 265 * The enums defined after "IPC_P_ROM" and before 266 * "IPC_P_RUN" indicates the operating state where CP can 267 * respond to any requests. So while introducing new phase 268 * this shall be taken into consideration. 269 * @IPC_P_OFF: On host PC, the PCIe device link settings are known 270 * about the combined power on. PC is running, the driver 271 * is loaded and CP is in power off mode. The PCIe bus 272 * driver call the device power mode D3hot. In this phase 273 * the driver the polls the device, until the device is in 274 * the power on state and signals the power mode D0. 275 * @IPC_P_OFF_REQ: The intermediate phase between cleanup activity starts 276 * and ends. 277 * @IPC_P_CRASH: The phase indicating CP crash 278 * @IPC_P_CD_READY: The phase indicating CP core dump is ready 279 * @IPC_P_ROM: After power on, CP starts in ROM mode and the IPC ROM 280 * driver is waiting 150 ms for the AP active notification 281 * saved in the PCI link status register. 282 * @IPC_P_PSI: Primary signed image download phase 283 * @IPC_P_EBL: Extended bootloader pahse 284 * @IPC_P_RUN: The phase after flashing to RAM is the RUNTIME phase. 285 */ 286 enum ipc_phase { 287 IPC_P_OFF, 288 IPC_P_OFF_REQ, 289 IPC_P_CRASH, 290 IPC_P_CD_READY, 291 IPC_P_ROM, 292 IPC_P_PSI, 293 IPC_P_EBL, 294 IPC_P_RUN, 295 }; 296 297 /** 298 * struct iosm_imem - Current state of the IPC shared memory. 299 * @mmio: mmio instance to access CP MMIO area / 300 * doorbell scratchpad. 301 * @ipc_protocol: IPC Protocol instance 302 * @ipc_task: Task for entry into ipc task queue 303 * @wwan: WWAN device pointer 304 * @mux: IP Data multiplexing state. 305 * @sio: IPC SIO data structure pointer 306 * @ipc_port: IPC PORT data structure pointer 307 * @pcie: IPC PCIe 308 * @trace: IPC trace data structure pointer 309 * @dev: Pointer to device structure 310 * @ipc_requested_state: Expected IPC state on CP. 311 * @channels: Channel list with UL/DL pipe pairs. 312 * @ipc_devlink: IPC Devlink data structure pointer 313 * @ipc_status: local ipc_status 314 * @nr_of_channels: number of configured channels 315 * @startup_timer: startup timer for NAND support. 316 * @hrtimer_period: Hr timer period 317 * @tdupdate_timer: Delay the TD update doorbell. 318 * @fast_update_timer: forced head pointer update delay timer. 319 * @td_alloc_timer: Timer for DL pipe TD allocation retry 320 * @rom_exit_code: Mapped boot rom exit code. 321 * @enter_runtime: 1 means the transition to runtime phase was 322 * executed. 323 * @ul_pend_sem: Semaphore to wait/complete of UL TDs 324 * before closing pipe. 325 * @app_notify_ul_pend: Signal app if UL TD is pending 326 * @dl_pend_sem: Semaphore to wait/complete of DL TDs 327 * before closing pipe. 328 * @app_notify_dl_pend: Signal app if DL TD is pending 329 * @phase: Operating phase like runtime. 330 * @pci_device_id: Device ID 331 * @cp_version: CP version 332 * @device_sleep: Device sleep state 333 * @run_state_worker: Pointer to worker component for device 334 * setup operations to be called when modem 335 * reaches RUN state 336 * @ev_irq_pending: 0 means inform the IPC tasklet to 337 * process the irq actions. 338 * @flag: Flag to monitor the state of driver 339 * @td_update_timer_suspended: if true then td update timer suspend 340 * @ev_mux_net_transmit_pending:0 means inform the IPC tasklet to pass 341 * @reset_det_n: Reset detect flag 342 * @pcie_wake_n: Pcie wake flag 343 * @debugfs_dir: Debug FS directory for driver-specific entries 344 */ 345 struct iosm_imem { 346 struct iosm_mmio *mmio; 347 struct iosm_protocol *ipc_protocol; 348 struct ipc_task *ipc_task; 349 struct iosm_wwan *wwan; 350 struct iosm_mux *mux; 351 struct iosm_cdev *ipc_port[IPC_MEM_MAX_CHANNELS]; 352 struct iosm_pcie *pcie; 353 #ifdef CONFIG_WWAN_DEBUGFS 354 struct iosm_trace *trace; 355 #endif 356 struct device *dev; 357 enum ipc_mem_device_ipc_state ipc_requested_state; 358 struct ipc_mem_channel channels[IPC_MEM_MAX_CHANNELS]; 359 struct iosm_devlink *ipc_devlink; 360 u32 ipc_status; 361 u32 nr_of_channels; 362 struct hrtimer startup_timer; 363 ktime_t hrtimer_period; 364 struct hrtimer tdupdate_timer; 365 struct hrtimer fast_update_timer; 366 struct hrtimer td_alloc_timer; 367 enum rom_exit_code rom_exit_code; 368 u32 enter_runtime; 369 struct completion ul_pend_sem; 370 u32 app_notify_ul_pend; 371 struct completion dl_pend_sem; 372 u32 app_notify_dl_pend; 373 enum ipc_phase phase; 374 u16 pci_device_id; 375 int cp_version; 376 int device_sleep; 377 struct work_struct run_state_worker; 378 u8 ev_irq_pending[IPC_IRQ_VECTORS]; 379 unsigned long flag; 380 u8 td_update_timer_suspended:1, 381 ev_mux_net_transmit_pending:1, 382 reset_det_n:1, 383 pcie_wake_n:1; 384 #ifdef CONFIG_WWAN_DEBUGFS 385 struct dentry *debugfs_dir; 386 #endif 387 }; 388 389 /** 390 * ipc_imem_init - Initialize the shared memory region 391 * @pcie: Pointer to core driver data-struct 392 * @device_id: PCI device ID 393 * @mmio: Pointer to the mmio area 394 * @dev: Pointer to device structure 395 * 396 * Returns: Initialized imem pointer on success else NULL 397 */ 398 struct iosm_imem *ipc_imem_init(struct iosm_pcie *pcie, unsigned int device_id, 399 void __iomem *mmio, struct device *dev); 400 401 /** 402 * ipc_imem_pm_s2idle_sleep - Set PM variables to sleep/active for 403 * s2idle sleep/active 404 * @ipc_imem: Pointer to imem data-struct 405 * @sleep: Set PM Variable to sleep/active 406 */ 407 void ipc_imem_pm_s2idle_sleep(struct iosm_imem *ipc_imem, bool sleep); 408 409 /** 410 * ipc_imem_pm_suspend - The HAL shall ask the shared memory layer 411 * whether D3 is allowed. 412 * @ipc_imem: Pointer to imem data-struct 413 */ 414 void ipc_imem_pm_suspend(struct iosm_imem *ipc_imem); 415 416 /** 417 * ipc_imem_pm_resume - The HAL shall inform the shared memory layer 418 * that the device is active. 419 * @ipc_imem: Pointer to imem data-struct 420 */ 421 void ipc_imem_pm_resume(struct iosm_imem *ipc_imem); 422 423 /** 424 * ipc_imem_cleanup - Inform CP and free the shared memory resources. 425 * @ipc_imem: Pointer to imem data-struct 426 */ 427 void ipc_imem_cleanup(struct iosm_imem *ipc_imem); 428 429 /** 430 * ipc_imem_irq_process - Shift the IRQ actions to the IPC thread. 431 * @ipc_imem: Pointer to imem data-struct 432 * @irq: Irq number 433 */ 434 void ipc_imem_irq_process(struct iosm_imem *ipc_imem, int irq); 435 436 /** 437 * imem_get_device_sleep_state - Get the device sleep state value. 438 * @ipc_imem: Pointer to imem instance 439 * 440 * Returns: device sleep state 441 */ 442 int imem_get_device_sleep_state(struct iosm_imem *ipc_imem); 443 444 /** 445 * ipc_imem_td_update_timer_suspend - Updates the TD Update Timer suspend flag. 446 * @ipc_imem: Pointer to imem data-struct 447 * @suspend: Flag to update. If TRUE then HP update doorbell is triggered to 448 * device without any wait. If FALSE then HP update doorbell is 449 * delayed until timeout. 450 */ 451 void ipc_imem_td_update_timer_suspend(struct iosm_imem *ipc_imem, bool suspend); 452 453 /** 454 * ipc_imem_channel_close - Release the channel resources. 455 * @ipc_imem: Pointer to imem data-struct 456 * @channel_id: Channel ID to be cleaned up. 457 */ 458 void ipc_imem_channel_close(struct iosm_imem *ipc_imem, int channel_id); 459 460 /** 461 * ipc_imem_channel_alloc - Reserves a channel 462 * @ipc_imem: Pointer to imem data-struct 463 * @index: ID to lookup from the preallocated list. 464 * @ctype: Channel type. 465 * 466 * Returns: Index on success and failure value on error 467 */ 468 int ipc_imem_channel_alloc(struct iosm_imem *ipc_imem, int index, 469 enum ipc_ctype ctype); 470 471 /** 472 * ipc_imem_channel_open - Establish the pipes. 473 * @ipc_imem: Pointer to imem data-struct 474 * @channel_id: Channel ID returned during alloc. 475 * @db_id: Doorbell ID for trigger identifier. 476 * 477 * Returns: Pointer of ipc_mem_channel on success and NULL on failure. 478 */ 479 struct ipc_mem_channel *ipc_imem_channel_open(struct iosm_imem *ipc_imem, 480 int channel_id, u32 db_id); 481 482 /** 483 * ipc_imem_td_update_timer_start - Starts the TD Update Timer if not running. 484 * @ipc_imem: Pointer to imem data-struct 485 */ 486 void ipc_imem_td_update_timer_start(struct iosm_imem *ipc_imem); 487 488 /** 489 * ipc_imem_ul_write_td - Pass the channel UL list to protocol layer for TD 490 * preparation and sending them to the device. 491 * @ipc_imem: Pointer to imem data-struct 492 * 493 * Returns: TRUE of HP Doorbell trigger is pending. FALSE otherwise. 494 */ 495 bool ipc_imem_ul_write_td(struct iosm_imem *ipc_imem); 496 497 /** 498 * ipc_imem_ul_send - Dequeue SKB from channel list and start with 499 * the uplink transfer.If HP Doorbell is pending to be 500 * triggered then starts the TD Update Timer. 501 * @ipc_imem: Pointer to imem data-struct 502 */ 503 void ipc_imem_ul_send(struct iosm_imem *ipc_imem); 504 505 /** 506 * ipc_imem_channel_update - Set or modify pipe config of an existing channel 507 * @ipc_imem: Pointer to imem data-struct 508 * @id: Channel config index 509 * @chnl_cfg: Channel config struct 510 * @irq_moderation: Timer in usec for irq_moderation 511 */ 512 void ipc_imem_channel_update(struct iosm_imem *ipc_imem, int id, 513 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 514 515 /** 516 * ipc_imem_channel_free -Free an IPC channel. 517 * @channel: Channel to be freed 518 */ 519 void ipc_imem_channel_free(struct ipc_mem_channel *channel); 520 521 /** 522 * ipc_imem_hrtimer_stop - Stop the hrtimer 523 * @hr_timer: Pointer to hrtimer instance 524 */ 525 void ipc_imem_hrtimer_stop(struct hrtimer *hr_timer); 526 527 /** 528 * ipc_imem_pipe_cleanup - Reset volatile pipe content for all channels 529 * @ipc_imem: Pointer to imem data-struct 530 * @pipe: Pipe to cleaned up 531 */ 532 void ipc_imem_pipe_cleanup(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 533 534 /** 535 * ipc_imem_pipe_close - Send msg to device to close pipe 536 * @ipc_imem: Pointer to imem data-struct 537 * @pipe: Pipe to be closed 538 */ 539 void ipc_imem_pipe_close(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 540 541 /** 542 * ipc_imem_phase_update - Get the CP execution state 543 * and map it to the AP phase. 544 * @ipc_imem: Pointer to imem data-struct 545 * 546 * Returns: Current ap updated phase 547 */ 548 enum ipc_phase ipc_imem_phase_update(struct iosm_imem *ipc_imem); 549 550 /** 551 * ipc_imem_phase_get_string - Return the current operation 552 * phase as string. 553 * @phase: AP phase 554 * 555 * Returns: AP phase string 556 */ 557 const char *ipc_imem_phase_get_string(enum ipc_phase phase); 558 559 /** 560 * ipc_imem_msg_send_feature_set - Send feature set message to modem 561 * @ipc_imem: Pointer to imem data-struct 562 * @reset_enable: 0 = out-of-band, 1 = in-band-crash notification 563 * @atomic_ctx: if disabled call in tasklet context 564 * 565 */ 566 void ipc_imem_msg_send_feature_set(struct iosm_imem *ipc_imem, 567 unsigned int reset_enable, bool atomic_ctx); 568 569 /** 570 * ipc_imem_ipc_init_check - Send the init event to CP, wait a certain time and 571 * set CP to runtime with the context information 572 * @ipc_imem: Pointer to imem data-struct 573 */ 574 void ipc_imem_ipc_init_check(struct iosm_imem *ipc_imem); 575 576 /** 577 * ipc_imem_channel_init - Initialize the channel list with UL/DL pipe pairs. 578 * @ipc_imem: Pointer to imem data-struct 579 * @ctype: Channel type 580 * @chnl_cfg: Channel configuration struct 581 * @irq_moderation: Timer in usec for irq_moderation 582 */ 583 void ipc_imem_channel_init(struct iosm_imem *ipc_imem, enum ipc_ctype ctype, 584 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 585 586 /** 587 * ipc_imem_devlink_trigger_chip_info - Inform devlink that the chip 588 * information are available if the 589 * flashing to RAM interworking shall be 590 * executed. 591 * @ipc_imem: Pointer to imem structure 592 * 593 * Returns: 0 on success, -1 on failure 594 */ 595 int ipc_imem_devlink_trigger_chip_info(struct iosm_imem *ipc_imem); 596 #endif 597