1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright (C) 2020-21 Intel Corporation. 4 */ 5 6 #ifndef IOSM_IPC_IMEM_H 7 #define IOSM_IPC_IMEM_H 8 9 #include <linux/skbuff.h> 10 11 #include "iosm_ipc_mmio.h" 12 #include "iosm_ipc_pcie.h" 13 #include "iosm_ipc_uevent.h" 14 #include "iosm_ipc_wwan.h" 15 #include "iosm_ipc_task_queue.h" 16 17 struct ipc_chnl_cfg; 18 19 /* IRQ moderation in usec */ 20 #define IRQ_MOD_OFF 0 21 #define IRQ_MOD_NET 1000 22 #define IRQ_MOD_TRC 4000 23 24 /* Either the PSI image is accepted by CP or the suspended flash tool is waken, 25 * informed that the CP ROM driver is not ready to process the PSI image. 26 * unit : milliseconds 27 */ 28 #define IPC_PSI_TRANSFER_TIMEOUT 3000 29 30 /* Timeout in 20 msec to wait for the modem to boot up to 31 * IPC_MEM_DEVICE_IPC_INIT state. 32 * unit : milliseconds (500 * ipc_util_msleep(20)) 33 */ 34 #define IPC_MODEM_BOOT_TIMEOUT 500 35 36 /* Wait timeout for ipc status reflects IPC_MEM_DEVICE_IPC_UNINIT 37 * unit : milliseconds 38 */ 39 #define IPC_MODEM_UNINIT_TIMEOUT_MS 30 40 41 /* Pending time for processing data. 42 * unit : milliseconds 43 */ 44 #define IPC_PEND_DATA_TIMEOUT 500 45 46 /* The timeout in milliseconds for application to wait for remote time. */ 47 #define IPC_REMOTE_TS_TIMEOUT_MS 10 48 49 /* Timeout for TD allocation retry. 50 * unit : milliseconds 51 */ 52 #define IPC_TD_ALLOC_TIMER_PERIOD_MS 100 53 54 /* Host sleep target is host */ 55 #define IPC_HOST_SLEEP_HOST 0 56 57 /* Host sleep target is device */ 58 #define IPC_HOST_SLEEP_DEVICE 1 59 60 /* Sleep message, target host: AP enters sleep / target device: CP is 61 * allowed to enter sleep and shall use the host sleep protocol 62 */ 63 #define IPC_HOST_SLEEP_ENTER_SLEEP 0 64 65 /* Sleep_message, target host: AP exits sleep / target device: CP is 66 * NOT allowed to enter sleep 67 */ 68 #define IPC_HOST_SLEEP_EXIT_SLEEP 1 69 70 #define IMEM_IRQ_DONT_CARE (-1) 71 72 #define IPC_MEM_MAX_CHANNELS 8 73 74 #define IPC_MEM_MUX_IP_SESSION_ENTRIES 8 75 76 #define IPC_MEM_MUX_IP_CH_IF_ID 0 77 78 #define TD_UPDATE_DEFAULT_TIMEOUT_USEC 1900 79 80 #define FORCE_UPDATE_DEFAULT_TIMEOUT_USEC 500 81 82 /* Sleep_message, target host: not applicable / target device: CP is 83 * allowed to enter sleep and shall NOT use the device sleep protocol 84 */ 85 #define IPC_HOST_SLEEP_ENTER_SLEEP_NO_PROTOCOL 2 86 87 /* in_band_crash_signal IPC_MEM_INBAND_CRASH_SIG 88 * Modem crash notification configuration. If this value is non-zero then 89 * FEATURE_SET message will be sent to the Modem as a result the Modem will 90 * signal Crash via Execution Stage register. If this value is zero then Modem 91 * will use out-of-band method to notify about it's Crash. 92 */ 93 #define IPC_MEM_INBAND_CRASH_SIG 1 94 95 /* Extra headroom to be allocated for DL SKBs to allow addition of Ethernet 96 * header 97 */ 98 #define IPC_MEM_DL_ETH_OFFSET 16 99 100 #define IPC_CB(skb) ((struct ipc_skb_cb *)((skb)->cb)) 101 #define IOSM_CHIP_INFO_SIZE_MAX 100 102 103 #define FULLY_FUNCTIONAL 0 104 #define IOSM_DEVLINK_INIT 1 105 106 #define IPC_MEM_AUTO_SUSPEND_DELAY_MS 5000 107 108 /* List of the supported UL/DL pipes. */ 109 enum ipc_mem_pipes { 110 IPC_MEM_PIPE_0 = 0, 111 IPC_MEM_PIPE_1, 112 IPC_MEM_PIPE_2, 113 IPC_MEM_PIPE_3, 114 IPC_MEM_PIPE_4, 115 IPC_MEM_PIPE_5, 116 IPC_MEM_PIPE_6, 117 IPC_MEM_PIPE_7, 118 IPC_MEM_PIPE_8, 119 IPC_MEM_PIPE_9, 120 IPC_MEM_PIPE_10, 121 IPC_MEM_PIPE_11, 122 IPC_MEM_PIPE_12, 123 IPC_MEM_PIPE_13, 124 IPC_MEM_PIPE_14, 125 IPC_MEM_PIPE_15, 126 IPC_MEM_PIPE_16, 127 IPC_MEM_PIPE_17, 128 IPC_MEM_PIPE_18, 129 IPC_MEM_PIPE_19, 130 IPC_MEM_PIPE_20, 131 IPC_MEM_PIPE_21, 132 IPC_MEM_PIPE_22, 133 IPC_MEM_PIPE_23, 134 IPC_MEM_MAX_PIPES 135 }; 136 137 /* Enum defining channel states. */ 138 enum ipc_channel_state { 139 IMEM_CHANNEL_FREE, 140 IMEM_CHANNEL_RESERVED, 141 IMEM_CHANNEL_ACTIVE, 142 IMEM_CHANNEL_CLOSING, 143 }; 144 145 /** 146 * enum ipc_ctype - Enum defining supported channel type needed for control 147 * /IP traffic. 148 * @IPC_CTYPE_WWAN: Used for IP traffic 149 * @IPC_CTYPE_CTRL: Used for Control Communication 150 */ 151 enum ipc_ctype { 152 IPC_CTYPE_WWAN, 153 IPC_CTYPE_CTRL, 154 }; 155 156 /* Pipe direction. */ 157 enum ipc_mem_pipe_dir { 158 IPC_MEM_DIR_UL, 159 IPC_MEM_DIR_DL, 160 }; 161 162 /* HP update identifier. To be used as data for ipc_cp_irq_hpda_update() */ 163 enum ipc_hp_identifier { 164 IPC_HP_MR = 0, 165 IPC_HP_PM_TRIGGER, 166 IPC_HP_WAKEUP_SPEC_TMR, 167 IPC_HP_TD_UPD_TMR_START, 168 IPC_HP_TD_UPD_TMR, 169 IPC_HP_FAST_TD_UPD_TMR, 170 IPC_HP_UL_WRITE_TD, 171 IPC_HP_DL_PROCESS, 172 IPC_HP_NET_CHANNEL_INIT, 173 IPC_HP_CDEV_OPEN, 174 }; 175 176 /** 177 * struct ipc_pipe - Structure for Pipe. 178 * @tdr_start: Ipc private protocol Transfer Descriptor Ring 179 * @channel: Id of the sio device, set by imem_sio_open, 180 * needed to pass DL char to the user terminal 181 * @skbr_start: Circular buffer for skbuf and the buffer 182 * reference in a tdr_start entry. 183 * @phy_tdr_start: Transfer descriptor start address 184 * @old_head: last head pointer reported to CP. 185 * @old_tail: AP read position before CP moves the read 186 * position to write/head. If CP has consumed the 187 * buffers, AP has to freed the skbuf starting at 188 * tdr_start[old_tail]. 189 * @nr_of_entries: Number of elements of skb_start and tdr_start. 190 * @max_nr_of_queued_entries: Maximum number of queued entries in TDR 191 * @accumulation_backoff: Accumulation in usec for accumulation 192 * backoff (0 = no acc backoff) 193 * @irq_moderation: timer in usec for irq_moderation 194 * (0=no irq moderation) 195 * @pipe_nr: Pipe identification number 196 * @irq: Interrupt vector 197 * @dir: Direction of data stream in pipe 198 * @buf_size: Buffer size (in bytes) for preallocated 199 * buffers (for DL pipes) 200 * @nr_of_queued_entries: Aueued number of entries 201 * @is_open: Check for open pipe status 202 */ 203 struct ipc_pipe { 204 struct ipc_protocol_td *tdr_start; 205 struct ipc_mem_channel *channel; 206 struct sk_buff **skbr_start; 207 dma_addr_t phy_tdr_start; 208 u32 old_head; 209 u32 old_tail; 210 u32 nr_of_entries; 211 u32 max_nr_of_queued_entries; 212 u32 accumulation_backoff; 213 u32 irq_moderation; 214 u32 pipe_nr; 215 u32 irq; 216 enum ipc_mem_pipe_dir dir; 217 u32 buf_size; 218 u16 nr_of_queued_entries; 219 u8 is_open:1; 220 }; 221 222 /** 223 * struct ipc_mem_channel - Structure for Channel. 224 * @channel_id: Instance of the channel list and is return to the user 225 * at the end of the open operation. 226 * @ctype: Control or netif channel. 227 * @index: unique index per ctype 228 * @ul_pipe: pipe objects 229 * @dl_pipe: pipe objects 230 * @if_id: Interface ID 231 * @net_err_count: Number of downlink errors returned by ipc_wwan_receive 232 * interface at the entry point of the IP stack. 233 * @state: Free, reserved or busy (in use). 234 * @ul_sem: Needed for the blocking write or uplink transfer. 235 * @ul_list: Uplink accumulator which is filled by the uplink 236 * char app or IP stack. The socket buffer pointer are 237 * added to the descriptor list in the kthread context. 238 */ 239 struct ipc_mem_channel { 240 int channel_id; 241 enum ipc_ctype ctype; 242 int index; 243 struct ipc_pipe ul_pipe; 244 struct ipc_pipe dl_pipe; 245 int if_id; 246 u32 net_err_count; 247 enum ipc_channel_state state; 248 struct completion ul_sem; 249 struct sk_buff_head ul_list; 250 }; 251 252 /** 253 * enum ipc_phase - Different AP and CP phases. 254 * The enums defined after "IPC_P_ROM" and before 255 * "IPC_P_RUN" indicates the operating state where CP can 256 * respond to any requests. So while introducing new phase 257 * this shall be taken into consideration. 258 * @IPC_P_OFF: On host PC, the PCIe device link settings are known 259 * about the combined power on. PC is running, the driver 260 * is loaded and CP is in power off mode. The PCIe bus 261 * driver call the device power mode D3hot. In this phase 262 * the driver the polls the device, until the device is in 263 * the power on state and signals the power mode D0. 264 * @IPC_P_OFF_REQ: The intermediate phase between cleanup activity starts 265 * and ends. 266 * @IPC_P_CRASH: The phase indicating CP crash 267 * @IPC_P_CD_READY: The phase indicating CP core dump is ready 268 * @IPC_P_ROM: After power on, CP starts in ROM mode and the IPC ROM 269 * driver is waiting 150 ms for the AP active notification 270 * saved in the PCI link status register. 271 * @IPC_P_PSI: Primary signed image download phase 272 * @IPC_P_EBL: Extended bootloader pahse 273 * @IPC_P_RUN: The phase after flashing to RAM is the RUNTIME phase. 274 */ 275 enum ipc_phase { 276 IPC_P_OFF, 277 IPC_P_OFF_REQ, 278 IPC_P_CRASH, 279 IPC_P_CD_READY, 280 IPC_P_ROM, 281 IPC_P_PSI, 282 IPC_P_EBL, 283 IPC_P_RUN, 284 }; 285 286 /** 287 * struct iosm_imem - Current state of the IPC shared memory. 288 * @mmio: mmio instance to access CP MMIO area / 289 * doorbell scratchpad. 290 * @ipc_protocol: IPC Protocol instance 291 * @ipc_task: Task for entry into ipc task queue 292 * @wwan: WWAN device pointer 293 * @mux: IP Data multiplexing state. 294 * @sio: IPC SIO data structure pointer 295 * @ipc_port: IPC PORT data structure pointer 296 * @pcie: IPC PCIe 297 * @trace: IPC trace data structure pointer 298 * @dev: Pointer to device structure 299 * @ipc_requested_state: Expected IPC state on CP. 300 * @channels: Channel list with UL/DL pipe pairs. 301 * @ipc_devlink: IPC Devlink data structure pointer 302 * @ipc_status: local ipc_status 303 * @nr_of_channels: number of configured channels 304 * @startup_timer: startup timer for NAND support. 305 * @hrtimer_period: Hr timer period 306 * @tdupdate_timer: Delay the TD update doorbell. 307 * @fast_update_timer: forced head pointer update delay timer. 308 * @td_alloc_timer: Timer for DL pipe TD allocation retry 309 * @adb_timer: Timer for finishing the ADB. 310 * @rom_exit_code: Mapped boot rom exit code. 311 * @enter_runtime: 1 means the transition to runtime phase was 312 * executed. 313 * @ul_pend_sem: Semaphore to wait/complete of UL TDs 314 * before closing pipe. 315 * @app_notify_ul_pend: Signal app if UL TD is pending 316 * @dl_pend_sem: Semaphore to wait/complete of DL TDs 317 * before closing pipe. 318 * @app_notify_dl_pend: Signal app if DL TD is pending 319 * @phase: Operating phase like runtime. 320 * @pci_device_id: Device ID 321 * @cp_version: CP version 322 * @device_sleep: Device sleep state 323 * @run_state_worker: Pointer to worker component for device 324 * setup operations to be called when modem 325 * reaches RUN state 326 * @ev_irq_pending: 0 means inform the IPC tasklet to 327 * process the irq actions. 328 * @flag: Flag to monitor the state of driver 329 * @td_update_timer_suspended: if true then td update timer suspend 330 * @ev_mux_net_transmit_pending:0 means inform the IPC tasklet to pass 331 * @reset_det_n: Reset detect flag 332 * @pcie_wake_n: Pcie wake flag 333 * @debugfs_wwan_dir: WWAN Debug FS directory entry 334 * @debugfs_dir: Debug FS directory for driver-specific entries 335 */ 336 struct iosm_imem { 337 struct iosm_mmio *mmio; 338 struct iosm_protocol *ipc_protocol; 339 struct ipc_task *ipc_task; 340 struct iosm_wwan *wwan; 341 struct iosm_mux *mux; 342 struct iosm_cdev *ipc_port[IPC_MEM_MAX_CHANNELS]; 343 struct iosm_pcie *pcie; 344 #ifdef CONFIG_WWAN_DEBUGFS 345 struct iosm_trace *trace; 346 #endif 347 struct device *dev; 348 enum ipc_mem_device_ipc_state ipc_requested_state; 349 struct ipc_mem_channel channels[IPC_MEM_MAX_CHANNELS]; 350 struct iosm_devlink *ipc_devlink; 351 u32 ipc_status; 352 u32 nr_of_channels; 353 struct hrtimer startup_timer; 354 ktime_t hrtimer_period; 355 struct hrtimer tdupdate_timer; 356 struct hrtimer fast_update_timer; 357 struct hrtimer td_alloc_timer; 358 struct hrtimer adb_timer; 359 enum rom_exit_code rom_exit_code; 360 u32 enter_runtime; 361 struct completion ul_pend_sem; 362 u32 app_notify_ul_pend; 363 struct completion dl_pend_sem; 364 u32 app_notify_dl_pend; 365 enum ipc_phase phase; 366 u16 pci_device_id; 367 int cp_version; 368 int device_sleep; 369 struct work_struct run_state_worker; 370 u8 ev_irq_pending[IPC_IRQ_VECTORS]; 371 unsigned long flag; 372 u8 td_update_timer_suspended:1, 373 ev_mux_net_transmit_pending:1, 374 reset_det_n:1, 375 pcie_wake_n:1; 376 #ifdef CONFIG_WWAN_DEBUGFS 377 struct dentry *debugfs_wwan_dir; 378 struct dentry *debugfs_dir; 379 #endif 380 }; 381 382 /** 383 * ipc_imem_init - Initialize the shared memory region 384 * @pcie: Pointer to core driver data-struct 385 * @device_id: PCI device ID 386 * @mmio: Pointer to the mmio area 387 * @dev: Pointer to device structure 388 * 389 * Returns: Initialized imem pointer on success else NULL 390 */ 391 struct iosm_imem *ipc_imem_init(struct iosm_pcie *pcie, unsigned int device_id, 392 void __iomem *mmio, struct device *dev); 393 394 /** 395 * ipc_imem_pm_s2idle_sleep - Set PM variables to sleep/active for 396 * s2idle sleep/active 397 * @ipc_imem: Pointer to imem data-struct 398 * @sleep: Set PM Variable to sleep/active 399 */ 400 void ipc_imem_pm_s2idle_sleep(struct iosm_imem *ipc_imem, bool sleep); 401 402 /** 403 * ipc_imem_pm_suspend - The HAL shall ask the shared memory layer 404 * whether D3 is allowed. 405 * @ipc_imem: Pointer to imem data-struct 406 */ 407 void ipc_imem_pm_suspend(struct iosm_imem *ipc_imem); 408 409 /** 410 * ipc_imem_pm_resume - The HAL shall inform the shared memory layer 411 * that the device is active. 412 * @ipc_imem: Pointer to imem data-struct 413 */ 414 void ipc_imem_pm_resume(struct iosm_imem *ipc_imem); 415 416 /** 417 * ipc_imem_cleanup - Inform CP and free the shared memory resources. 418 * @ipc_imem: Pointer to imem data-struct 419 */ 420 void ipc_imem_cleanup(struct iosm_imem *ipc_imem); 421 422 /** 423 * ipc_imem_irq_process - Shift the IRQ actions to the IPC thread. 424 * @ipc_imem: Pointer to imem data-struct 425 * @irq: Irq number 426 */ 427 void ipc_imem_irq_process(struct iosm_imem *ipc_imem, int irq); 428 429 /** 430 * imem_get_device_sleep_state - Get the device sleep state value. 431 * @ipc_imem: Pointer to imem instance 432 * 433 * Returns: device sleep state 434 */ 435 int imem_get_device_sleep_state(struct iosm_imem *ipc_imem); 436 437 /** 438 * ipc_imem_td_update_timer_suspend - Updates the TD Update Timer suspend flag. 439 * @ipc_imem: Pointer to imem data-struct 440 * @suspend: Flag to update. If TRUE then HP update doorbell is triggered to 441 * device without any wait. If FALSE then HP update doorbell is 442 * delayed until timeout. 443 */ 444 void ipc_imem_td_update_timer_suspend(struct iosm_imem *ipc_imem, bool suspend); 445 446 /** 447 * ipc_imem_channel_close - Release the channel resources. 448 * @ipc_imem: Pointer to imem data-struct 449 * @channel_id: Channel ID to be cleaned up. 450 */ 451 void ipc_imem_channel_close(struct iosm_imem *ipc_imem, int channel_id); 452 453 /** 454 * ipc_imem_channel_alloc - Reserves a channel 455 * @ipc_imem: Pointer to imem data-struct 456 * @index: ID to lookup from the preallocated list. 457 * @ctype: Channel type. 458 * 459 * Returns: Index on success and failure value on error 460 */ 461 int ipc_imem_channel_alloc(struct iosm_imem *ipc_imem, int index, 462 enum ipc_ctype ctype); 463 464 /** 465 * ipc_imem_channel_open - Establish the pipes. 466 * @ipc_imem: Pointer to imem data-struct 467 * @channel_id: Channel ID returned during alloc. 468 * @db_id: Doorbell ID for trigger identifier. 469 * 470 * Returns: Pointer of ipc_mem_channel on success and NULL on failure. 471 */ 472 struct ipc_mem_channel *ipc_imem_channel_open(struct iosm_imem *ipc_imem, 473 int channel_id, u32 db_id); 474 475 /** 476 * ipc_imem_td_update_timer_start - Starts the TD Update Timer if not running. 477 * @ipc_imem: Pointer to imem data-struct 478 */ 479 void ipc_imem_td_update_timer_start(struct iosm_imem *ipc_imem); 480 481 /** 482 * ipc_imem_ul_write_td - Pass the channel UL list to protocol layer for TD 483 * preparation and sending them to the device. 484 * @ipc_imem: Pointer to imem data-struct 485 * 486 * Returns: TRUE of HP Doorbell trigger is pending. FALSE otherwise. 487 */ 488 bool ipc_imem_ul_write_td(struct iosm_imem *ipc_imem); 489 490 /** 491 * ipc_imem_ul_send - Dequeue SKB from channel list and start with 492 * the uplink transfer.If HP Doorbell is pending to be 493 * triggered then starts the TD Update Timer. 494 * @ipc_imem: Pointer to imem data-struct 495 */ 496 void ipc_imem_ul_send(struct iosm_imem *ipc_imem); 497 498 /** 499 * ipc_imem_channel_update - Set or modify pipe config of an existing channel 500 * @ipc_imem: Pointer to imem data-struct 501 * @id: Channel config index 502 * @chnl_cfg: Channel config struct 503 * @irq_moderation: Timer in usec for irq_moderation 504 */ 505 void ipc_imem_channel_update(struct iosm_imem *ipc_imem, int id, 506 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 507 508 /** 509 * ipc_imem_channel_free -Free an IPC channel. 510 * @channel: Channel to be freed 511 */ 512 void ipc_imem_channel_free(struct ipc_mem_channel *channel); 513 514 /** 515 * ipc_imem_hrtimer_stop - Stop the hrtimer 516 * @hr_timer: Pointer to hrtimer instance 517 */ 518 void ipc_imem_hrtimer_stop(struct hrtimer *hr_timer); 519 520 /** 521 * ipc_imem_pipe_cleanup - Reset volatile pipe content for all channels 522 * @ipc_imem: Pointer to imem data-struct 523 * @pipe: Pipe to cleaned up 524 */ 525 void ipc_imem_pipe_cleanup(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 526 527 /** 528 * ipc_imem_pipe_close - Send msg to device to close pipe 529 * @ipc_imem: Pointer to imem data-struct 530 * @pipe: Pipe to be closed 531 */ 532 void ipc_imem_pipe_close(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 533 534 /** 535 * ipc_imem_phase_update - Get the CP execution state 536 * and map it to the AP phase. 537 * @ipc_imem: Pointer to imem data-struct 538 * 539 * Returns: Current ap updated phase 540 */ 541 enum ipc_phase ipc_imem_phase_update(struct iosm_imem *ipc_imem); 542 543 /** 544 * ipc_imem_phase_get_string - Return the current operation 545 * phase as string. 546 * @phase: AP phase 547 * 548 * Returns: AP phase string 549 */ 550 const char *ipc_imem_phase_get_string(enum ipc_phase phase); 551 552 /** 553 * ipc_imem_msg_send_feature_set - Send feature set message to modem 554 * @ipc_imem: Pointer to imem data-struct 555 * @reset_enable: 0 = out-of-band, 1 = in-band-crash notification 556 * @atomic_ctx: if disabled call in tasklet context 557 * 558 */ 559 void ipc_imem_msg_send_feature_set(struct iosm_imem *ipc_imem, 560 unsigned int reset_enable, bool atomic_ctx); 561 562 /** 563 * ipc_imem_ipc_init_check - Send the init event to CP, wait a certain time and 564 * set CP to runtime with the context information 565 * @ipc_imem: Pointer to imem data-struct 566 */ 567 void ipc_imem_ipc_init_check(struct iosm_imem *ipc_imem); 568 569 /** 570 * ipc_imem_channel_init - Initialize the channel list with UL/DL pipe pairs. 571 * @ipc_imem: Pointer to imem data-struct 572 * @ctype: Channel type 573 * @chnl_cfg: Channel configuration struct 574 * @irq_moderation: Timer in usec for irq_moderation 575 */ 576 void ipc_imem_channel_init(struct iosm_imem *ipc_imem, enum ipc_ctype ctype, 577 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 578 579 /** 580 * ipc_imem_devlink_trigger_chip_info - Inform devlink that the chip 581 * information are available if the 582 * flashing to RAM interworking shall be 583 * executed. 584 * @ipc_imem: Pointer to imem structure 585 * 586 * Returns: 0 on success, -1 on failure 587 */ 588 int ipc_imem_devlink_trigger_chip_info(struct iosm_imem *ipc_imem); 589 590 void ipc_imem_adb_timer_start(struct iosm_imem *ipc_imem); 591 592 #endif 593