1 /* ZD1211 USB-WLAN driver for Linux 2 * 3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de> 4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef _ZD_CHIP_H 21 #define _ZD_CHIP_H 22 23 #include <net/mac80211.h> 24 25 #include "zd_rf.h" 26 #include "zd_usb.h" 27 28 /* Header for the Media Access Controller (MAC) and the Baseband Processor 29 * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and 30 * adds a processor for handling the USB protocol. 31 */ 32 33 /* Address space */ 34 enum { 35 /* CONTROL REGISTERS */ 36 CR_START = 0x9000, 37 38 39 /* FIRMWARE */ 40 FW_START = 0xee00, 41 42 43 /* EEPROM */ 44 E2P_START = 0xf800, 45 E2P_LEN = 0x800, 46 47 /* EEPROM layout */ 48 E2P_LOAD_CODE_LEN = 0xe, /* base 0xf800 */ 49 E2P_LOAD_VECT_LEN = 0x9, /* base 0xf80e */ 50 /* E2P_DATA indexes into this */ 51 E2P_DATA_LEN = 0x7e, /* base 0xf817 */ 52 E2P_BOOT_CODE_LEN = 0x760, /* base 0xf895 */ 53 E2P_INTR_VECT_LEN = 0xb, /* base 0xfff5 */ 54 55 /* Some precomputed offsets into the EEPROM */ 56 E2P_DATA_OFFSET = E2P_LOAD_CODE_LEN + E2P_LOAD_VECT_LEN, 57 E2P_BOOT_CODE_OFFSET = E2P_DATA_OFFSET + E2P_DATA_LEN, 58 }; 59 60 #define CTL_REG(offset) ((zd_addr_t)(CR_START + (offset))) 61 #define E2P_DATA(offset) ((zd_addr_t)(E2P_START + E2P_DATA_OFFSET + (offset))) 62 #define FWRAW_DATA(offset) ((zd_addr_t)(FW_START + (offset))) 63 64 /* 8-bit hardware registers */ 65 #define ZD_CR0 CTL_REG(0x0000) 66 #define ZD_CR1 CTL_REG(0x0004) 67 #define ZD_CR2 CTL_REG(0x0008) 68 #define ZD_CR3 CTL_REG(0x000C) 69 70 #define ZD_CR5 CTL_REG(0x0010) 71 /* bit 5: if set short preamble used 72 * bit 6: filter band - Japan channel 14 on, else off 73 */ 74 #define ZD_CR6 CTL_REG(0x0014) 75 #define ZD_CR7 CTL_REG(0x0018) 76 #define ZD_CR8 CTL_REG(0x001C) 77 78 #define ZD_CR4 CTL_REG(0x0020) 79 80 #define ZD_CR9 CTL_REG(0x0024) 81 /* bit 2: antenna switch (together with ZD_CR10) */ 82 #define ZD_CR10 CTL_REG(0x0028) 83 /* bit 1: antenna switch (together with ZD_CR9) 84 * RF2959 controls with ZD_CR11 radion on and off 85 */ 86 #define ZD_CR11 CTL_REG(0x002C) 87 /* bit 6: TX power control for OFDM 88 * RF2959 controls with ZD_CR10 radio on and off 89 */ 90 #define ZD_CR12 CTL_REG(0x0030) 91 #define ZD_CR13 CTL_REG(0x0034) 92 #define ZD_CR14 CTL_REG(0x0038) 93 #define ZD_CR15 CTL_REG(0x003C) 94 #define ZD_CR16 CTL_REG(0x0040) 95 #define ZD_CR17 CTL_REG(0x0044) 96 #define ZD_CR18 CTL_REG(0x0048) 97 #define ZD_CR19 CTL_REG(0x004C) 98 #define ZD_CR20 CTL_REG(0x0050) 99 #define ZD_CR21 CTL_REG(0x0054) 100 #define ZD_CR22 CTL_REG(0x0058) 101 #define ZD_CR23 CTL_REG(0x005C) 102 #define ZD_CR24 CTL_REG(0x0060) /* CCA threshold */ 103 #define ZD_CR25 CTL_REG(0x0064) 104 #define ZD_CR26 CTL_REG(0x0068) 105 #define ZD_CR27 CTL_REG(0x006C) 106 #define ZD_CR28 CTL_REG(0x0070) 107 #define ZD_CR29 CTL_REG(0x0074) 108 #define ZD_CR30 CTL_REG(0x0078) 109 #define ZD_CR31 CTL_REG(0x007C) /* TX power control for RF in 110 * CCK mode 111 */ 112 #define ZD_CR32 CTL_REG(0x0080) 113 #define ZD_CR33 CTL_REG(0x0084) 114 #define ZD_CR34 CTL_REG(0x0088) 115 #define ZD_CR35 CTL_REG(0x008C) 116 #define ZD_CR36 CTL_REG(0x0090) 117 #define ZD_CR37 CTL_REG(0x0094) 118 #define ZD_CR38 CTL_REG(0x0098) 119 #define ZD_CR39 CTL_REG(0x009C) 120 #define ZD_CR40 CTL_REG(0x00A0) 121 #define ZD_CR41 CTL_REG(0x00A4) 122 #define ZD_CR42 CTL_REG(0x00A8) 123 #define ZD_CR43 CTL_REG(0x00AC) 124 #define ZD_CR44 CTL_REG(0x00B0) 125 #define ZD_CR45 CTL_REG(0x00B4) 126 #define ZD_CR46 CTL_REG(0x00B8) 127 #define ZD_CR47 CTL_REG(0x00BC) /* CCK baseband gain 128 * (patch value might be in EEPROM) 129 */ 130 #define ZD_CR48 CTL_REG(0x00C0) 131 #define ZD_CR49 CTL_REG(0x00C4) 132 #define ZD_CR50 CTL_REG(0x00C8) 133 #define ZD_CR51 CTL_REG(0x00CC) /* TX power control for RF in 134 * 6-36M modes 135 */ 136 #define ZD_CR52 CTL_REG(0x00D0) /* TX power control for RF in 137 * 48M mode 138 */ 139 #define ZD_CR53 CTL_REG(0x00D4) /* TX power control for RF in 140 * 54M mode 141 */ 142 #define ZD_CR54 CTL_REG(0x00D8) 143 #define ZD_CR55 CTL_REG(0x00DC) 144 #define ZD_CR56 CTL_REG(0x00E0) 145 #define ZD_CR57 CTL_REG(0x00E4) 146 #define ZD_CR58 CTL_REG(0x00E8) 147 #define ZD_CR59 CTL_REG(0x00EC) 148 #define ZD_CR60 CTL_REG(0x00F0) 149 #define ZD_CR61 CTL_REG(0x00F4) 150 #define ZD_CR62 CTL_REG(0x00F8) 151 #define ZD_CR63 CTL_REG(0x00FC) 152 #define ZD_CR64 CTL_REG(0x0100) 153 #define ZD_CR65 CTL_REG(0x0104) /* OFDM 54M calibration */ 154 #define ZD_CR66 CTL_REG(0x0108) /* OFDM 48M calibration */ 155 #define ZD_CR67 CTL_REG(0x010C) /* OFDM 36M calibration */ 156 #define ZD_CR68 CTL_REG(0x0110) /* CCK calibration */ 157 #define ZD_CR69 CTL_REG(0x0114) 158 #define ZD_CR70 CTL_REG(0x0118) 159 #define ZD_CR71 CTL_REG(0x011C) 160 #define ZD_CR72 CTL_REG(0x0120) 161 #define ZD_CR73 CTL_REG(0x0124) 162 #define ZD_CR74 CTL_REG(0x0128) 163 #define ZD_CR75 CTL_REG(0x012C) 164 #define ZD_CR76 CTL_REG(0x0130) 165 #define ZD_CR77 CTL_REG(0x0134) 166 #define ZD_CR78 CTL_REG(0x0138) 167 #define ZD_CR79 CTL_REG(0x013C) 168 #define ZD_CR80 CTL_REG(0x0140) 169 #define ZD_CR81 CTL_REG(0x0144) 170 #define ZD_CR82 CTL_REG(0x0148) 171 #define ZD_CR83 CTL_REG(0x014C) 172 #define ZD_CR84 CTL_REG(0x0150) 173 #define ZD_CR85 CTL_REG(0x0154) 174 #define ZD_CR86 CTL_REG(0x0158) 175 #define ZD_CR87 CTL_REG(0x015C) 176 #define ZD_CR88 CTL_REG(0x0160) 177 #define ZD_CR89 CTL_REG(0x0164) 178 #define ZD_CR90 CTL_REG(0x0168) 179 #define ZD_CR91 CTL_REG(0x016C) 180 #define ZD_CR92 CTL_REG(0x0170) 181 #define ZD_CR93 CTL_REG(0x0174) 182 #define ZD_CR94 CTL_REG(0x0178) 183 #define ZD_CR95 CTL_REG(0x017C) 184 #define ZD_CR96 CTL_REG(0x0180) 185 #define ZD_CR97 CTL_REG(0x0184) 186 #define ZD_CR98 CTL_REG(0x0188) 187 #define ZD_CR99 CTL_REG(0x018C) 188 #define ZD_CR100 CTL_REG(0x0190) 189 #define ZD_CR101 CTL_REG(0x0194) 190 #define ZD_CR102 CTL_REG(0x0198) 191 #define ZD_CR103 CTL_REG(0x019C) 192 #define ZD_CR104 CTL_REG(0x01A0) 193 #define ZD_CR105 CTL_REG(0x01A4) 194 #define ZD_CR106 CTL_REG(0x01A8) 195 #define ZD_CR107 CTL_REG(0x01AC) 196 #define ZD_CR108 CTL_REG(0x01B0) 197 #define ZD_CR109 CTL_REG(0x01B4) 198 #define ZD_CR110 CTL_REG(0x01B8) 199 #define ZD_CR111 CTL_REG(0x01BC) 200 #define ZD_CR112 CTL_REG(0x01C0) 201 #define ZD_CR113 CTL_REG(0x01C4) 202 #define ZD_CR114 CTL_REG(0x01C8) 203 #define ZD_CR115 CTL_REG(0x01CC) 204 #define ZD_CR116 CTL_REG(0x01D0) 205 #define ZD_CR117 CTL_REG(0x01D4) 206 #define ZD_CR118 CTL_REG(0x01D8) 207 #define ZD_CR119 CTL_REG(0x01DC) 208 #define ZD_CR120 CTL_REG(0x01E0) 209 #define ZD_CR121 CTL_REG(0x01E4) 210 #define ZD_CR122 CTL_REG(0x01E8) 211 #define ZD_CR123 CTL_REG(0x01EC) 212 #define ZD_CR124 CTL_REG(0x01F0) 213 #define ZD_CR125 CTL_REG(0x01F4) 214 #define ZD_CR126 CTL_REG(0x01F8) 215 #define ZD_CR127 CTL_REG(0x01FC) 216 #define ZD_CR128 CTL_REG(0x0200) 217 #define ZD_CR129 CTL_REG(0x0204) 218 #define ZD_CR130 CTL_REG(0x0208) 219 #define ZD_CR131 CTL_REG(0x020C) 220 #define ZD_CR132 CTL_REG(0x0210) 221 #define ZD_CR133 CTL_REG(0x0214) 222 #define ZD_CR134 CTL_REG(0x0218) 223 #define ZD_CR135 CTL_REG(0x021C) 224 #define ZD_CR136 CTL_REG(0x0220) 225 #define ZD_CR137 CTL_REG(0x0224) 226 #define ZD_CR138 CTL_REG(0x0228) 227 #define ZD_CR139 CTL_REG(0x022C) 228 #define ZD_CR140 CTL_REG(0x0230) 229 #define ZD_CR141 CTL_REG(0x0234) 230 #define ZD_CR142 CTL_REG(0x0238) 231 #define ZD_CR143 CTL_REG(0x023C) 232 #define ZD_CR144 CTL_REG(0x0240) 233 #define ZD_CR145 CTL_REG(0x0244) 234 #define ZD_CR146 CTL_REG(0x0248) 235 #define ZD_CR147 CTL_REG(0x024C) 236 #define ZD_CR148 CTL_REG(0x0250) 237 #define ZD_CR149 CTL_REG(0x0254) 238 #define ZD_CR150 CTL_REG(0x0258) 239 #define ZD_CR151 CTL_REG(0x025C) 240 #define ZD_CR152 CTL_REG(0x0260) 241 #define ZD_CR153 CTL_REG(0x0264) 242 #define ZD_CR154 CTL_REG(0x0268) 243 #define ZD_CR155 CTL_REG(0x026C) 244 #define ZD_CR156 CTL_REG(0x0270) 245 #define ZD_CR157 CTL_REG(0x0274) 246 #define ZD_CR158 CTL_REG(0x0278) 247 #define ZD_CR159 CTL_REG(0x027C) 248 #define ZD_CR160 CTL_REG(0x0280) 249 #define ZD_CR161 CTL_REG(0x0284) 250 #define ZD_CR162 CTL_REG(0x0288) 251 #define ZD_CR163 CTL_REG(0x028C) 252 #define ZD_CR164 CTL_REG(0x0290) 253 #define ZD_CR165 CTL_REG(0x0294) 254 #define ZD_CR166 CTL_REG(0x0298) 255 #define ZD_CR167 CTL_REG(0x029C) 256 #define ZD_CR168 CTL_REG(0x02A0) 257 #define ZD_CR169 CTL_REG(0x02A4) 258 #define ZD_CR170 CTL_REG(0x02A8) 259 #define ZD_CR171 CTL_REG(0x02AC) 260 #define ZD_CR172 CTL_REG(0x02B0) 261 #define ZD_CR173 CTL_REG(0x02B4) 262 #define ZD_CR174 CTL_REG(0x02B8) 263 #define ZD_CR175 CTL_REG(0x02BC) 264 #define ZD_CR176 CTL_REG(0x02C0) 265 #define ZD_CR177 CTL_REG(0x02C4) 266 #define ZD_CR178 CTL_REG(0x02C8) 267 #define ZD_CR179 CTL_REG(0x02CC) 268 #define ZD_CR180 CTL_REG(0x02D0) 269 #define ZD_CR181 CTL_REG(0x02D4) 270 #define ZD_CR182 CTL_REG(0x02D8) 271 #define ZD_CR183 CTL_REG(0x02DC) 272 #define ZD_CR184 CTL_REG(0x02E0) 273 #define ZD_CR185 CTL_REG(0x02E4) 274 #define ZD_CR186 CTL_REG(0x02E8) 275 #define ZD_CR187 CTL_REG(0x02EC) 276 #define ZD_CR188 CTL_REG(0x02F0) 277 #define ZD_CR189 CTL_REG(0x02F4) 278 #define ZD_CR190 CTL_REG(0x02F8) 279 #define ZD_CR191 CTL_REG(0x02FC) 280 #define ZD_CR192 CTL_REG(0x0300) 281 #define ZD_CR193 CTL_REG(0x0304) 282 #define ZD_CR194 CTL_REG(0x0308) 283 #define ZD_CR195 CTL_REG(0x030C) 284 #define ZD_CR196 CTL_REG(0x0310) 285 #define ZD_CR197 CTL_REG(0x0314) 286 #define ZD_CR198 CTL_REG(0x0318) 287 #define ZD_CR199 CTL_REG(0x031C) 288 #define ZD_CR200 CTL_REG(0x0320) 289 #define ZD_CR201 CTL_REG(0x0324) 290 #define ZD_CR202 CTL_REG(0x0328) 291 #define ZD_CR203 CTL_REG(0x032C) /* I2C bus template value & flash 292 * control 293 */ 294 #define ZD_CR204 CTL_REG(0x0330) 295 #define ZD_CR205 CTL_REG(0x0334) 296 #define ZD_CR206 CTL_REG(0x0338) 297 #define ZD_CR207 CTL_REG(0x033C) 298 #define ZD_CR208 CTL_REG(0x0340) 299 #define ZD_CR209 CTL_REG(0x0344) 300 #define ZD_CR210 CTL_REG(0x0348) 301 #define ZD_CR211 CTL_REG(0x034C) 302 #define ZD_CR212 CTL_REG(0x0350) 303 #define ZD_CR213 CTL_REG(0x0354) 304 #define ZD_CR214 CTL_REG(0x0358) 305 #define ZD_CR215 CTL_REG(0x035C) 306 #define ZD_CR216 CTL_REG(0x0360) 307 #define ZD_CR217 CTL_REG(0x0364) 308 #define ZD_CR218 CTL_REG(0x0368) 309 #define ZD_CR219 CTL_REG(0x036C) 310 #define ZD_CR220 CTL_REG(0x0370) 311 #define ZD_CR221 CTL_REG(0x0374) 312 #define ZD_CR222 CTL_REG(0x0378) 313 #define ZD_CR223 CTL_REG(0x037C) 314 #define ZD_CR224 CTL_REG(0x0380) 315 #define ZD_CR225 CTL_REG(0x0384) 316 #define ZD_CR226 CTL_REG(0x0388) 317 #define ZD_CR227 CTL_REG(0x038C) 318 #define ZD_CR228 CTL_REG(0x0390) 319 #define ZD_CR229 CTL_REG(0x0394) 320 #define ZD_CR230 CTL_REG(0x0398) 321 #define ZD_CR231 CTL_REG(0x039C) 322 #define ZD_CR232 CTL_REG(0x03A0) 323 #define ZD_CR233 CTL_REG(0x03A4) 324 #define ZD_CR234 CTL_REG(0x03A8) 325 #define ZD_CR235 CTL_REG(0x03AC) 326 #define ZD_CR236 CTL_REG(0x03B0) 327 328 #define ZD_CR240 CTL_REG(0x03C0) 329 /* bit 7: host-controlled RF register writes 330 * ZD_CR241-ZD_CR245: for hardware controlled writing of RF bits, not needed for 331 * USB 332 */ 333 #define ZD_CR241 CTL_REG(0x03C4) 334 #define ZD_CR242 CTL_REG(0x03C8) 335 #define ZD_CR243 CTL_REG(0x03CC) 336 #define ZD_CR244 CTL_REG(0x03D0) 337 #define ZD_CR245 CTL_REG(0x03D4) 338 339 #define ZD_CR251 CTL_REG(0x03EC) /* only used for activation and 340 * deactivation of Airoha RFs AL2230 341 * and AL7230B 342 */ 343 #define ZD_CR252 CTL_REG(0x03F0) 344 #define ZD_CR253 CTL_REG(0x03F4) 345 #define ZD_CR254 CTL_REG(0x03F8) 346 #define ZD_CR255 CTL_REG(0x03FC) 347 348 #define CR_MAX_PHY_REG 255 349 350 /* Taken from the ZYDAS driver, not all of them are relevant for the ZD1211 351 * driver. 352 */ 353 354 #define CR_RF_IF_CLK CTL_REG(0x0400) 355 #define CR_RF_IF_DATA CTL_REG(0x0404) 356 #define CR_PE1_PE2 CTL_REG(0x0408) 357 #define CR_PE2_DLY CTL_REG(0x040C) 358 #define CR_LE1 CTL_REG(0x0410) 359 #define CR_LE2 CTL_REG(0x0414) 360 /* Seems to enable/disable GPI (General Purpose IO?) */ 361 #define CR_GPI_EN CTL_REG(0x0418) 362 #define CR_RADIO_PD CTL_REG(0x042C) 363 #define CR_RF2948_PD CTL_REG(0x042C) 364 #define CR_ENABLE_PS_MANUAL_AGC CTL_REG(0x043C) 365 #define CR_CONFIG_PHILIPS CTL_REG(0x0440) 366 #define CR_SA2400_SER_AP CTL_REG(0x0444) 367 #define CR_I2C_WRITE CTL_REG(0x0444) 368 #define CR_SA2400_SER_RP CTL_REG(0x0448) 369 #define CR_RADIO_PE CTL_REG(0x0458) 370 #define CR_RST_BUS_MASTER CTL_REG(0x045C) 371 #define CR_RFCFG CTL_REG(0x0464) 372 #define CR_HSTSCHG CTL_REG(0x046C) 373 #define CR_PHY_ON CTL_REG(0x0474) 374 #define CR_RX_DELAY CTL_REG(0x0478) 375 #define CR_RX_PE_DELAY CTL_REG(0x047C) 376 #define CR_GPIO_1 CTL_REG(0x0490) 377 #define CR_GPIO_2 CTL_REG(0x0494) 378 #define CR_EncryBufMux CTL_REG(0x04A8) 379 #define CR_PS_CTRL CTL_REG(0x0500) 380 #define CR_ADDA_PWR_DWN CTL_REG(0x0504) 381 #define CR_ADDA_MBIAS_WARMTIME CTL_REG(0x0508) 382 #define CR_MAC_PS_STATE CTL_REG(0x050C) 383 384 #define CR_INTERRUPT CTL_REG(0x0510) 385 #define INT_TX_COMPLETE (1 << 0) 386 #define INT_RX_COMPLETE (1 << 1) 387 #define INT_RETRY_FAIL (1 << 2) 388 #define INT_WAKEUP (1 << 3) 389 #define INT_DTIM_NOTIFY (1 << 5) 390 #define INT_CFG_NEXT_BCN (1 << 6) 391 #define INT_BUS_ABORT (1 << 7) 392 #define INT_TX_FIFO_READY (1 << 8) 393 #define INT_UART (1 << 9) 394 #define INT_TX_COMPLETE_EN (1 << 16) 395 #define INT_RX_COMPLETE_EN (1 << 17) 396 #define INT_RETRY_FAIL_EN (1 << 18) 397 #define INT_WAKEUP_EN (1 << 19) 398 #define INT_DTIM_NOTIFY_EN (1 << 21) 399 #define INT_CFG_NEXT_BCN_EN (1 << 22) 400 #define INT_BUS_ABORT_EN (1 << 23) 401 #define INT_TX_FIFO_READY_EN (1 << 24) 402 #define INT_UART_EN (1 << 25) 403 404 #define CR_TSF_LOW_PART CTL_REG(0x0514) 405 #define CR_TSF_HIGH_PART CTL_REG(0x0518) 406 407 /* Following three values are in time units (1024us) 408 * Following condition must be met: 409 * atim < tbtt < bcn 410 */ 411 #define CR_ATIM_WND_PERIOD CTL_REG(0x051C) 412 #define CR_BCN_INTERVAL CTL_REG(0x0520) 413 #define CR_PRE_TBTT CTL_REG(0x0524) 414 /* in units of TU(1024us) */ 415 416 /* for UART support */ 417 #define CR_UART_RBR_THR_DLL CTL_REG(0x0540) 418 #define CR_UART_DLM_IER CTL_REG(0x0544) 419 #define CR_UART_IIR_FCR CTL_REG(0x0548) 420 #define CR_UART_LCR CTL_REG(0x054c) 421 #define CR_UART_MCR CTL_REG(0x0550) 422 #define CR_UART_LSR CTL_REG(0x0554) 423 #define CR_UART_MSR CTL_REG(0x0558) 424 #define CR_UART_ECR CTL_REG(0x055c) 425 #define CR_UART_STATUS CTL_REG(0x0560) 426 427 #define CR_PCI_TX_ADDR_P1 CTL_REG(0x0600) 428 #define CR_PCI_TX_AddR_P2 CTL_REG(0x0604) 429 #define CR_PCI_RX_AddR_P1 CTL_REG(0x0608) 430 #define CR_PCI_RX_AddR_P2 CTL_REG(0x060C) 431 432 /* must be overwritten if custom MAC address will be used */ 433 #define CR_MAC_ADDR_P1 CTL_REG(0x0610) 434 #define CR_MAC_ADDR_P2 CTL_REG(0x0614) 435 #define CR_BSSID_P1 CTL_REG(0x0618) 436 #define CR_BSSID_P2 CTL_REG(0x061C) 437 #define CR_BCN_PLCP_CFG CTL_REG(0x0620) 438 439 /* Group hash table for filtering incoming packets. 440 * 441 * The group hash table is 64 bit large and split over two parts. The first 442 * part is the lower part. The upper 6 bits of the last byte of the target 443 * address are used as index. Packets are received if the hash table bit is 444 * set. This is used for multicast handling, but for broadcasts (address 445 * ff:ff:ff:ff:ff:ff) the highest bit in the second table must also be set. 446 */ 447 #define CR_GROUP_HASH_P1 CTL_REG(0x0624) 448 #define CR_GROUP_HASH_P2 CTL_REG(0x0628) 449 450 #define CR_RX_TIMEOUT CTL_REG(0x062C) 451 452 /* Basic rates supported by the BSS. When producing ACK or CTS messages, the 453 * device will use a rate in this table that is less than or equal to the rate 454 * of the incoming frame which prompted the response. */ 455 #define CR_BASIC_RATE_TBL CTL_REG(0x0630) 456 #define CR_RATE_1M (1 << 0) /* 802.11b */ 457 #define CR_RATE_2M (1 << 1) /* 802.11b */ 458 #define CR_RATE_5_5M (1 << 2) /* 802.11b */ 459 #define CR_RATE_11M (1 << 3) /* 802.11b */ 460 #define CR_RATE_6M (1 << 8) /* 802.11g */ 461 #define CR_RATE_9M (1 << 9) /* 802.11g */ 462 #define CR_RATE_12M (1 << 10) /* 802.11g */ 463 #define CR_RATE_18M (1 << 11) /* 802.11g */ 464 #define CR_RATE_24M (1 << 12) /* 802.11g */ 465 #define CR_RATE_36M (1 << 13) /* 802.11g */ 466 #define CR_RATE_48M (1 << 14) /* 802.11g */ 467 #define CR_RATE_54M (1 << 15) /* 802.11g */ 468 #define CR_RATES_80211G 0xff00 469 #define CR_RATES_80211B 0x000f 470 471 /* Mandatory rates required in the BSS. When producing ACK or CTS messages, if 472 * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will 473 * look for a rate in this table that is less than or equal to the rate of 474 * the incoming frame. */ 475 #define CR_MANDATORY_RATE_TBL CTL_REG(0x0634) 476 #define CR_RTS_CTS_RATE CTL_REG(0x0638) 477 478 /* These are all bit indexes in CR_RTS_CTS_RATE, so remember to shift. */ 479 #define RTSCTS_SH_RTS_RATE 0 480 #define RTSCTS_SH_EXP_CTS_RATE 4 481 #define RTSCTS_SH_RTS_MOD_TYPE 8 482 #define RTSCTS_SH_RTS_PMB_TYPE 9 483 #define RTSCTS_SH_CTS_RATE 16 484 #define RTSCTS_SH_CTS_MOD_TYPE 24 485 #define RTSCTS_SH_CTS_PMB_TYPE 25 486 487 #define CR_WEP_PROTECT CTL_REG(0x063C) 488 #define CR_RX_THRESHOLD CTL_REG(0x0640) 489 490 /* register for controlling the LEDS */ 491 #define CR_LED CTL_REG(0x0644) 492 /* masks for controlling LEDs */ 493 #define LED1 (1 << 8) 494 #define LED2 (1 << 9) 495 #define LED_SW (1 << 10) 496 497 /* Seems to indicate that the configuration is over. 498 */ 499 #define CR_AFTER_PNP CTL_REG(0x0648) 500 #define CR_ACK_TIME_80211 CTL_REG(0x0658) 501 502 #define CR_RX_OFFSET CTL_REG(0x065c) 503 504 #define CR_BCN_LENGTH CTL_REG(0x0664) 505 #define CR_PHY_DELAY CTL_REG(0x066C) 506 #define CR_BCN_FIFO CTL_REG(0x0670) 507 #define CR_SNIFFER_ON CTL_REG(0x0674) 508 509 #define CR_ENCRYPTION_TYPE CTL_REG(0x0678) 510 #define NO_WEP 0 511 #define WEP64 1 512 #define WEP128 5 513 #define WEP256 6 514 #define ENC_SNIFFER 8 515 516 #define CR_ZD1211_RETRY_MAX CTL_REG(0x067C) 517 518 #define CR_REG1 CTL_REG(0x0680) 519 /* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical 520 * registers, so one could argue it is a LOCK bit. But calling it 521 * LOCK_PHY_REGS makes it confusing. 522 */ 523 #define UNLOCK_PHY_REGS (1 << 7) 524 525 #define CR_DEVICE_STATE CTL_REG(0x0684) 526 #define CR_UNDERRUN_CNT CTL_REG(0x0688) 527 528 #define CR_RX_FILTER CTL_REG(0x068c) 529 #define RX_FILTER_ASSOC_REQUEST (1 << 0) 530 #define RX_FILTER_ASSOC_RESPONSE (1 << 1) 531 #define RX_FILTER_REASSOC_REQUEST (1 << 2) 532 #define RX_FILTER_REASSOC_RESPONSE (1 << 3) 533 #define RX_FILTER_PROBE_REQUEST (1 << 4) 534 #define RX_FILTER_PROBE_RESPONSE (1 << 5) 535 /* bits 6 and 7 reserved */ 536 #define RX_FILTER_BEACON (1 << 8) 537 #define RX_FILTER_ATIM (1 << 9) 538 #define RX_FILTER_DISASSOC (1 << 10) 539 #define RX_FILTER_AUTH (1 << 11) 540 #define RX_FILTER_DEAUTH (1 << 12) 541 #define RX_FILTER_PSPOLL (1 << 26) 542 #define RX_FILTER_RTS (1 << 27) 543 #define RX_FILTER_CTS (1 << 28) 544 #define RX_FILTER_ACK (1 << 29) 545 #define RX_FILTER_CFEND (1 << 30) 546 #define RX_FILTER_CFACK (1 << 31) 547 548 /* Enable bits for all frames you are interested in. */ 549 #define STA_RX_FILTER (RX_FILTER_ASSOC_REQUEST | RX_FILTER_ASSOC_RESPONSE | \ 550 RX_FILTER_REASSOC_REQUEST | RX_FILTER_REASSOC_RESPONSE | \ 551 RX_FILTER_PROBE_REQUEST | RX_FILTER_PROBE_RESPONSE | \ 552 (0x3 << 6) /* vendor driver sets these reserved bits */ | \ 553 RX_FILTER_BEACON | RX_FILTER_ATIM | RX_FILTER_DISASSOC | \ 554 RX_FILTER_AUTH | RX_FILTER_DEAUTH | \ 555 (0x7 << 13) /* vendor driver sets these reserved bits */ | \ 556 RX_FILTER_PSPOLL | RX_FILTER_ACK) /* 0x2400ffff */ 557 558 #define RX_FILTER_CTRL (RX_FILTER_RTS | RX_FILTER_CTS | \ 559 RX_FILTER_CFEND | RX_FILTER_CFACK) 560 561 #define BCN_MODE_AP 0x1000000 562 #define BCN_MODE_IBSS 0x2000000 563 564 /* Monitor mode sets filter to 0xfffff */ 565 566 #define CR_ACK_TIMEOUT_EXT CTL_REG(0x0690) 567 #define CR_BCN_FIFO_SEMAPHORE CTL_REG(0x0694) 568 569 #define CR_IFS_VALUE CTL_REG(0x0698) 570 #define IFS_VALUE_DIFS_SH 0 571 #define IFS_VALUE_EIFS_SH 12 572 #define IFS_VALUE_SIFS_SH 24 573 #define IFS_VALUE_DEFAULT (( 50 << IFS_VALUE_DIFS_SH) | \ 574 (1148 << IFS_VALUE_EIFS_SH) | \ 575 ( 10 << IFS_VALUE_SIFS_SH)) 576 577 #define CR_RX_TIME_OUT CTL_REG(0x069C) 578 #define CR_TOTAL_RX_FRM CTL_REG(0x06A0) 579 #define CR_CRC32_CNT CTL_REG(0x06A4) 580 #define CR_CRC16_CNT CTL_REG(0x06A8) 581 #define CR_DECRYPTION_ERR_UNI CTL_REG(0x06AC) 582 #define CR_RX_FIFO_OVERRUN CTL_REG(0x06B0) 583 584 #define CR_DECRYPTION_ERR_MUL CTL_REG(0x06BC) 585 586 #define CR_NAV_CNT CTL_REG(0x06C4) 587 #define CR_NAV_CCA CTL_REG(0x06C8) 588 #define CR_RETRY_CNT CTL_REG(0x06CC) 589 590 #define CR_READ_TCB_ADDR CTL_REG(0x06E8) 591 #define CR_READ_RFD_ADDR CTL_REG(0x06EC) 592 #define CR_CWMIN_CWMAX CTL_REG(0x06F0) 593 #define CR_TOTAL_TX_FRM CTL_REG(0x06F4) 594 595 /* CAM: Continuous Access Mode (power management) */ 596 #define CR_CAM_MODE CTL_REG(0x0700) 597 #define MODE_IBSS 0x0 598 #define MODE_AP 0x1 599 #define MODE_STA 0x2 600 #define MODE_AP_WDS 0x3 601 602 #define CR_CAM_ROLL_TB_LOW CTL_REG(0x0704) 603 #define CR_CAM_ROLL_TB_HIGH CTL_REG(0x0708) 604 #define CR_CAM_ADDRESS CTL_REG(0x070C) 605 #define CR_CAM_DATA CTL_REG(0x0710) 606 607 #define CR_ROMDIR CTL_REG(0x0714) 608 609 #define CR_DECRY_ERR_FLG_LOW CTL_REG(0x0714) 610 #define CR_DECRY_ERR_FLG_HIGH CTL_REG(0x0718) 611 612 #define CR_WEPKEY0 CTL_REG(0x0720) 613 #define CR_WEPKEY1 CTL_REG(0x0724) 614 #define CR_WEPKEY2 CTL_REG(0x0728) 615 #define CR_WEPKEY3 CTL_REG(0x072C) 616 #define CR_WEPKEY4 CTL_REG(0x0730) 617 #define CR_WEPKEY5 CTL_REG(0x0734) 618 #define CR_WEPKEY6 CTL_REG(0x0738) 619 #define CR_WEPKEY7 CTL_REG(0x073C) 620 #define CR_WEPKEY8 CTL_REG(0x0740) 621 #define CR_WEPKEY9 CTL_REG(0x0744) 622 #define CR_WEPKEY10 CTL_REG(0x0748) 623 #define CR_WEPKEY11 CTL_REG(0x074C) 624 #define CR_WEPKEY12 CTL_REG(0x0750) 625 #define CR_WEPKEY13 CTL_REG(0x0754) 626 #define CR_WEPKEY14 CTL_REG(0x0758) 627 #define CR_WEPKEY15 CTL_REG(0x075c) 628 #define CR_TKIP_MODE CTL_REG(0x0760) 629 630 #define CR_EEPROM_PROTECT0 CTL_REG(0x0758) 631 #define CR_EEPROM_PROTECT1 CTL_REG(0x075C) 632 633 #define CR_DBG_FIFO_RD CTL_REG(0x0800) 634 #define CR_DBG_SELECT CTL_REG(0x0804) 635 #define CR_FIFO_Length CTL_REG(0x0808) 636 637 638 #define CR_RSSI_MGC CTL_REG(0x0810) 639 640 #define CR_PON CTL_REG(0x0818) 641 #define CR_RX_ON CTL_REG(0x081C) 642 #define CR_TX_ON CTL_REG(0x0820) 643 #define CR_CHIP_EN CTL_REG(0x0824) 644 #define CR_LO_SW CTL_REG(0x0828) 645 #define CR_TXRX_SW CTL_REG(0x082C) 646 #define CR_S_MD CTL_REG(0x0830) 647 648 #define CR_USB_DEBUG_PORT CTL_REG(0x0888) 649 #define CR_ZD1211B_CWIN_MAX_MIN_AC0 CTL_REG(0x0b00) 650 #define CR_ZD1211B_CWIN_MAX_MIN_AC1 CTL_REG(0x0b04) 651 #define CR_ZD1211B_CWIN_MAX_MIN_AC2 CTL_REG(0x0b08) 652 #define CR_ZD1211B_CWIN_MAX_MIN_AC3 CTL_REG(0x0b0c) 653 #define CR_ZD1211B_AIFS_CTL1 CTL_REG(0x0b10) 654 #define CR_ZD1211B_AIFS_CTL2 CTL_REG(0x0b14) 655 #define CR_ZD1211B_TXOP CTL_REG(0x0b20) 656 #define CR_ZD1211B_RETRY_MAX CTL_REG(0x0b28) 657 658 /* Value for CR_ZD1211_RETRY_MAX & CR_ZD1211B_RETRY_MAX. Vendor driver uses 2, 659 * we use 0. The first rate is tried (count+2), then all next rates are tried 660 * twice, until 1 Mbits is tried. */ 661 #define ZD1211_RETRY_COUNT 0 662 #define ZD1211B_RETRY_COUNT \ 663 (ZD1211_RETRY_COUNT << 0)| \ 664 (ZD1211_RETRY_COUNT << 8)| \ 665 (ZD1211_RETRY_COUNT << 16)| \ 666 (ZD1211_RETRY_COUNT << 24) 667 668 /* Used to detect PLL lock */ 669 #define UW2453_INTR_REG ((zd_addr_t)0x85c1) 670 671 #define CWIN_SIZE 0x007f043f 672 673 674 #define HWINT_ENABLED \ 675 (INT_TX_COMPLETE_EN| \ 676 INT_RX_COMPLETE_EN| \ 677 INT_RETRY_FAIL_EN| \ 678 INT_WAKEUP_EN| \ 679 INT_CFG_NEXT_BCN_EN) 680 681 #define HWINT_DISABLED 0 682 683 #define E2P_PWR_INT_GUARD 8 684 #define E2P_CHANNEL_COUNT 14 685 686 /* If you compare this addresses with the ZYDAS orignal driver, please notify 687 * that we use word mapping for the EEPROM. 688 */ 689 690 /* 691 * Upper 16 bit contains the regulatory domain. 692 */ 693 #define E2P_SUBID E2P_DATA(0x00) 694 #define E2P_POD E2P_DATA(0x02) 695 #define E2P_MAC_ADDR_P1 E2P_DATA(0x04) 696 #define E2P_MAC_ADDR_P2 E2P_DATA(0x06) 697 #define E2P_PWR_CAL_VALUE1 E2P_DATA(0x08) 698 #define E2P_PWR_CAL_VALUE2 E2P_DATA(0x0a) 699 #define E2P_PWR_CAL_VALUE3 E2P_DATA(0x0c) 700 #define E2P_PWR_CAL_VALUE4 E2P_DATA(0x0e) 701 #define E2P_PWR_INT_VALUE1 E2P_DATA(0x10) 702 #define E2P_PWR_INT_VALUE2 E2P_DATA(0x12) 703 #define E2P_PWR_INT_VALUE3 E2P_DATA(0x14) 704 #define E2P_PWR_INT_VALUE4 E2P_DATA(0x16) 705 706 /* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30) 707 * also only 11 channels. */ 708 #define E2P_ALLOWED_CHANNEL E2P_DATA(0x18) 709 710 #define E2P_DEVICE_VER E2P_DATA(0x20) 711 #define E2P_PHY_REG E2P_DATA(0x25) 712 #define E2P_36M_CAL_VALUE1 E2P_DATA(0x28) 713 #define E2P_36M_CAL_VALUE2 E2P_DATA(0x2a) 714 #define E2P_36M_CAL_VALUE3 E2P_DATA(0x2c) 715 #define E2P_36M_CAL_VALUE4 E2P_DATA(0x2e) 716 #define E2P_11A_INT_VALUE1 E2P_DATA(0x30) 717 #define E2P_11A_INT_VALUE2 E2P_DATA(0x32) 718 #define E2P_11A_INT_VALUE3 E2P_DATA(0x34) 719 #define E2P_11A_INT_VALUE4 E2P_DATA(0x36) 720 #define E2P_48M_CAL_VALUE1 E2P_DATA(0x38) 721 #define E2P_48M_CAL_VALUE2 E2P_DATA(0x3a) 722 #define E2P_48M_CAL_VALUE3 E2P_DATA(0x3c) 723 #define E2P_48M_CAL_VALUE4 E2P_DATA(0x3e) 724 #define E2P_48M_INT_VALUE1 E2P_DATA(0x40) 725 #define E2P_48M_INT_VALUE2 E2P_DATA(0x42) 726 #define E2P_48M_INT_VALUE3 E2P_DATA(0x44) 727 #define E2P_48M_INT_VALUE4 E2P_DATA(0x46) 728 #define E2P_54M_CAL_VALUE1 E2P_DATA(0x48) /* ??? */ 729 #define E2P_54M_CAL_VALUE2 E2P_DATA(0x4a) 730 #define E2P_54M_CAL_VALUE3 E2P_DATA(0x4c) 731 #define E2P_54M_CAL_VALUE4 E2P_DATA(0x4e) 732 #define E2P_54M_INT_VALUE1 E2P_DATA(0x50) 733 #define E2P_54M_INT_VALUE2 E2P_DATA(0x52) 734 #define E2P_54M_INT_VALUE3 E2P_DATA(0x54) 735 #define E2P_54M_INT_VALUE4 E2P_DATA(0x56) 736 737 /* This word contains the base address of the FW_REG_ registers below */ 738 #define FWRAW_REGS_ADDR FWRAW_DATA(0x1d) 739 740 /* All 16 bit values, offset from the address in FWRAW_REGS_ADDR */ 741 enum { 742 FW_REG_FIRMWARE_VER = 0, 743 /* non-zero if USB high speed connection */ 744 FW_REG_USB_SPEED = 1, 745 FW_REG_FIX_TX_RATE = 2, 746 /* Seems to be able to control LEDs over the firmware */ 747 FW_REG_LED_LINK_STATUS = 3, 748 FW_REG_SOFT_RESET = 4, 749 FW_REG_FLASH_CHK = 5, 750 }; 751 752 /* Values for FW_LINK_STATUS */ 753 #define FW_LINK_OFF 0x0 754 #define FW_LINK_TX 0x1 755 /* 0x2 - link led on? */ 756 757 enum { 758 /* indices for ofdm_cal_values */ 759 OFDM_36M_INDEX = 0, 760 OFDM_48M_INDEX = 1, 761 OFDM_54M_INDEX = 2, 762 }; 763 764 struct zd_chip { 765 struct zd_usb usb; 766 struct zd_rf rf; 767 struct mutex mutex; 768 /* Base address of FW_REG_ registers */ 769 zd_addr_t fw_regs_base; 770 /* EepSetPoint in the vendor driver */ 771 u8 pwr_cal_values[E2P_CHANNEL_COUNT]; 772 /* integration values in the vendor driver */ 773 u8 pwr_int_values[E2P_CHANNEL_COUNT]; 774 /* SetPointOFDM in the vendor driver */ 775 u8 ofdm_cal_values[3][E2P_CHANNEL_COUNT]; 776 u16 link_led; 777 unsigned int pa_type:4, 778 patch_cck_gain:1, patch_cr157:1, patch_6m_band_edge:1, 779 new_phy_layout:1, al2230s_bit:1, 780 supports_tx_led:1; 781 }; 782 783 static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb) 784 { 785 return container_of(usb, struct zd_chip, usb); 786 } 787 788 static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf) 789 { 790 return container_of(rf, struct zd_chip, rf); 791 } 792 793 #define zd_chip_dev(chip) (&(chip)->usb.intf->dev) 794 795 void zd_chip_init(struct zd_chip *chip, 796 struct ieee80211_hw *hw, 797 struct usb_interface *intf); 798 void zd_chip_clear(struct zd_chip *chip); 799 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr); 800 int zd_chip_init_hw(struct zd_chip *chip); 801 int zd_chip_reset(struct zd_chip *chip); 802 803 static inline int zd_chip_is_zd1211b(struct zd_chip *chip) 804 { 805 return chip->usb.is_zd1211b; 806 } 807 808 static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values, 809 const zd_addr_t *addresses, 810 unsigned int count) 811 { 812 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 813 return zd_usb_ioread16v(&chip->usb, values, addresses, count); 814 } 815 816 static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value, 817 const zd_addr_t addr) 818 { 819 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 820 return zd_usb_ioread16(&chip->usb, value, addr); 821 } 822 823 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, 824 const zd_addr_t *addresses, unsigned int count); 825 826 static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value, 827 const zd_addr_t addr) 828 { 829 return zd_ioread32v_locked(chip, value, &addr, 1); 830 } 831 832 static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value, 833 zd_addr_t addr) 834 { 835 struct zd_ioreq16 ioreq; 836 837 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 838 ioreq.addr = addr; 839 ioreq.value = value; 840 841 return zd_usb_iowrite16v(&chip->usb, &ioreq, 1); 842 } 843 844 int zd_iowrite16a_locked(struct zd_chip *chip, 845 const struct zd_ioreq16 *ioreqs, unsigned int count); 846 847 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 848 unsigned int count); 849 850 static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value, 851 zd_addr_t addr) 852 { 853 struct zd_ioreq32 ioreq; 854 855 ioreq.addr = addr; 856 ioreq.value = value; 857 858 return _zd_iowrite32v_locked(chip, &ioreq, 1); 859 } 860 861 int zd_iowrite32a_locked(struct zd_chip *chip, 862 const struct zd_ioreq32 *ioreqs, unsigned int count); 863 864 static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits) 865 { 866 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 867 return zd_usb_rfwrite(&chip->usb, value, bits); 868 } 869 870 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value); 871 872 int zd_rfwritev_locked(struct zd_chip *chip, 873 const u32* values, unsigned int count, u8 bits); 874 int zd_rfwritev_cr_locked(struct zd_chip *chip, 875 const u32* values, unsigned int count); 876 877 /* Locking functions for reading and writing registers. 878 * The different parameters are intentional. 879 */ 880 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value); 881 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value); 882 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value); 883 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value); 884 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, 885 u32 *values, unsigned int count); 886 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 887 unsigned int count); 888 889 int zd_chip_set_channel(struct zd_chip *chip, u8 channel); 890 static inline u8 _zd_chip_get_channel(struct zd_chip *chip) 891 { 892 return chip->rf.channel; 893 } 894 u8 zd_chip_get_channel(struct zd_chip *chip); 895 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain); 896 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr); 897 int zd_write_bssid(struct zd_chip *chip, const u8 *bssid); 898 int zd_chip_switch_radio_on(struct zd_chip *chip); 899 int zd_chip_switch_radio_off(struct zd_chip *chip); 900 int zd_chip_enable_int(struct zd_chip *chip); 901 void zd_chip_disable_int(struct zd_chip *chip); 902 int zd_chip_enable_rxtx(struct zd_chip *chip); 903 void zd_chip_disable_rxtx(struct zd_chip *chip); 904 int zd_chip_enable_hwint(struct zd_chip *chip); 905 int zd_chip_disable_hwint(struct zd_chip *chip); 906 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel); 907 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, int preamble); 908 909 static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type) 910 { 911 return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type); 912 } 913 914 static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type) 915 { 916 return zd_iowrite32(chip, CR_ENCRYPTION_TYPE, type); 917 } 918 919 static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates) 920 { 921 return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates); 922 } 923 924 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates); 925 926 int zd_chip_lock_phy_regs(struct zd_chip *chip); 927 int zd_chip_unlock_phy_regs(struct zd_chip *chip); 928 929 enum led_status { 930 ZD_LED_OFF = 0, 931 ZD_LED_SCANNING = 1, 932 ZD_LED_ASSOCIATED = 2, 933 }; 934 935 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status); 936 937 int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period, 938 int type); 939 940 static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval) 941 { 942 return zd_ioread32(chip, CR_BCN_INTERVAL, interval); 943 } 944 945 struct rx_status; 946 947 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status); 948 949 struct zd_mc_hash { 950 u32 low; 951 u32 high; 952 }; 953 954 static inline void zd_mc_clear(struct zd_mc_hash *hash) 955 { 956 hash->low = 0; 957 /* The interfaces must always received broadcasts. 958 * The hash of the broadcast address ff:ff:ff:ff:ff:ff is 63. 959 */ 960 hash->high = 0x80000000; 961 } 962 963 static inline void zd_mc_add_all(struct zd_mc_hash *hash) 964 { 965 hash->low = hash->high = 0xffffffff; 966 } 967 968 static inline void zd_mc_add_addr(struct zd_mc_hash *hash, u8 *addr) 969 { 970 unsigned int i = addr[5] >> 2; 971 if (i < 32) { 972 hash->low |= 1 << i; 973 } else { 974 hash->high |= 1 << (i-32); 975 } 976 } 977 978 int zd_chip_set_multicast_hash(struct zd_chip *chip, 979 struct zd_mc_hash *hash); 980 981 u64 zd_chip_get_tsf(struct zd_chip *chip); 982 983 #endif /* _ZD_CHIP_H */ 984