1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* ZD1211 USB-WLAN driver for Linux 3 * 4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de> 5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org> 6 */ 7 8 /* This file implements all the hardware specific functions for the ZD1211 9 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy 10 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/errno.h> 15 #include <linux/slab.h> 16 17 #include "zd_def.h" 18 #include "zd_chip.h" 19 #include "zd_mac.h" 20 #include "zd_rf.h" 21 22 void zd_chip_init(struct zd_chip *chip, 23 struct ieee80211_hw *hw, 24 struct usb_interface *intf) 25 { 26 memset(chip, 0, sizeof(*chip)); 27 mutex_init(&chip->mutex); 28 zd_usb_init(&chip->usb, hw, intf); 29 zd_rf_init(&chip->rf); 30 } 31 32 void zd_chip_clear(struct zd_chip *chip) 33 { 34 ZD_ASSERT(!mutex_is_locked(&chip->mutex)); 35 zd_usb_clear(&chip->usb); 36 zd_rf_clear(&chip->rf); 37 mutex_destroy(&chip->mutex); 38 ZD_MEMCLEAR(chip, sizeof(*chip)); 39 } 40 41 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size) 42 { 43 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip)); 44 return scnprintf(buffer, size, "%02x-%02x-%02x", 45 addr[0], addr[1], addr[2]); 46 } 47 48 /* Prints an identifier line, which will support debugging. */ 49 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size) 50 { 51 int i = 0; 52 53 i = scnprintf(buffer, size, "zd1211%s chip ", 54 zd_chip_is_zd1211b(chip) ? "b" : ""); 55 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i); 56 i += scnprintf(buffer+i, size-i, " "); 57 i += scnprint_mac_oui(chip, buffer+i, size-i); 58 i += scnprintf(buffer+i, size-i, " "); 59 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i); 60 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type, 61 chip->patch_cck_gain ? 'g' : '-', 62 chip->patch_cr157 ? '7' : '-', 63 chip->patch_6m_band_edge ? '6' : '-', 64 chip->new_phy_layout ? 'N' : '-', 65 chip->al2230s_bit ? 'S' : '-'); 66 return i; 67 } 68 69 static void print_id(struct zd_chip *chip) 70 { 71 char buffer[80]; 72 73 scnprint_id(chip, buffer, sizeof(buffer)); 74 buffer[sizeof(buffer)-1] = 0; 75 dev_info(zd_chip_dev(chip), "%s\n", buffer); 76 } 77 78 static zd_addr_t inc_addr(zd_addr_t addr) 79 { 80 u16 a = (u16)addr; 81 /* Control registers use byte addressing, but everything else uses word 82 * addressing. */ 83 if ((a & 0xf000) == CR_START) 84 a += 2; 85 else 86 a += 1; 87 return (zd_addr_t)a; 88 } 89 90 /* Read a variable number of 32-bit values. Parameter count is not allowed to 91 * exceed USB_MAX_IOREAD32_COUNT. 92 */ 93 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr, 94 unsigned int count) 95 { 96 int r; 97 int i; 98 zd_addr_t a16[USB_MAX_IOREAD32_COUNT * 2]; 99 u16 v16[USB_MAX_IOREAD32_COUNT * 2]; 100 unsigned int count16; 101 102 if (count > USB_MAX_IOREAD32_COUNT) 103 return -EINVAL; 104 105 /* Use stack for values and addresses. */ 106 count16 = 2 * count; 107 BUG_ON(count16 * sizeof(zd_addr_t) > sizeof(a16)); 108 BUG_ON(count16 * sizeof(u16) > sizeof(v16)); 109 110 for (i = 0; i < count; i++) { 111 int j = 2*i; 112 /* We read the high word always first. */ 113 a16[j] = inc_addr(addr[i]); 114 a16[j+1] = addr[i]; 115 } 116 117 r = zd_ioread16v_locked(chip, v16, a16, count16); 118 if (r) { 119 dev_dbg_f(zd_chip_dev(chip), 120 "error: %s. Error number %d\n", __func__, r); 121 return r; 122 } 123 124 for (i = 0; i < count; i++) { 125 int j = 2*i; 126 values[i] = (v16[j] << 16) | v16[j+1]; 127 } 128 129 return 0; 130 } 131 132 static int _zd_iowrite32v_async_locked(struct zd_chip *chip, 133 const struct zd_ioreq32 *ioreqs, 134 unsigned int count) 135 { 136 int i, j, r; 137 struct zd_ioreq16 ioreqs16[USB_MAX_IOWRITE32_COUNT * 2]; 138 unsigned int count16; 139 140 /* Use stack for values and addresses. */ 141 142 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 143 144 if (count == 0) 145 return 0; 146 if (count > USB_MAX_IOWRITE32_COUNT) 147 return -EINVAL; 148 149 count16 = 2 * count; 150 BUG_ON(count16 * sizeof(struct zd_ioreq16) > sizeof(ioreqs16)); 151 152 for (i = 0; i < count; i++) { 153 j = 2*i; 154 /* We write the high word always first. */ 155 ioreqs16[j].value = ioreqs[i].value >> 16; 156 ioreqs16[j].addr = inc_addr(ioreqs[i].addr); 157 ioreqs16[j+1].value = ioreqs[i].value; 158 ioreqs16[j+1].addr = ioreqs[i].addr; 159 } 160 161 r = zd_usb_iowrite16v_async(&chip->usb, ioreqs16, count16); 162 #ifdef DEBUG 163 if (r) { 164 dev_dbg_f(zd_chip_dev(chip), 165 "error %d in zd_usb_write16v\n", r); 166 } 167 #endif /* DEBUG */ 168 return r; 169 } 170 171 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 172 unsigned int count) 173 { 174 int r; 175 176 zd_usb_iowrite16v_async_start(&chip->usb); 177 r = _zd_iowrite32v_async_locked(chip, ioreqs, count); 178 if (r) { 179 zd_usb_iowrite16v_async_end(&chip->usb, 0); 180 return r; 181 } 182 return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */); 183 } 184 185 int zd_iowrite16a_locked(struct zd_chip *chip, 186 const struct zd_ioreq16 *ioreqs, unsigned int count) 187 { 188 int r; 189 unsigned int i, j, t, max; 190 191 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 192 zd_usb_iowrite16v_async_start(&chip->usb); 193 194 for (i = 0; i < count; i += j + t) { 195 t = 0; 196 max = count-i; 197 if (max > USB_MAX_IOWRITE16_COUNT) 198 max = USB_MAX_IOWRITE16_COUNT; 199 for (j = 0; j < max; j++) { 200 if (!ioreqs[i+j].addr) { 201 t = 1; 202 break; 203 } 204 } 205 206 r = zd_usb_iowrite16v_async(&chip->usb, &ioreqs[i], j); 207 if (r) { 208 zd_usb_iowrite16v_async_end(&chip->usb, 0); 209 dev_dbg_f(zd_chip_dev(chip), 210 "error zd_usb_iowrite16v. Error number %d\n", 211 r); 212 return r; 213 } 214 } 215 216 return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */); 217 } 218 219 /* Writes a variable number of 32 bit registers. The functions will split 220 * that in several USB requests. A split can be forced by inserting an IO 221 * request with an zero address field. 222 */ 223 int zd_iowrite32a_locked(struct zd_chip *chip, 224 const struct zd_ioreq32 *ioreqs, unsigned int count) 225 { 226 int r; 227 unsigned int i, j, t, max; 228 229 zd_usb_iowrite16v_async_start(&chip->usb); 230 231 for (i = 0; i < count; i += j + t) { 232 t = 0; 233 max = count-i; 234 if (max > USB_MAX_IOWRITE32_COUNT) 235 max = USB_MAX_IOWRITE32_COUNT; 236 for (j = 0; j < max; j++) { 237 if (!ioreqs[i+j].addr) { 238 t = 1; 239 break; 240 } 241 } 242 243 r = _zd_iowrite32v_async_locked(chip, &ioreqs[i], j); 244 if (r) { 245 zd_usb_iowrite16v_async_end(&chip->usb, 0); 246 dev_dbg_f(zd_chip_dev(chip), 247 "error _%s. Error number %d\n", __func__, 248 r); 249 return r; 250 } 251 } 252 253 return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */); 254 } 255 256 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value) 257 { 258 int r; 259 260 mutex_lock(&chip->mutex); 261 r = zd_ioread16_locked(chip, value, addr); 262 mutex_unlock(&chip->mutex); 263 return r; 264 } 265 266 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value) 267 { 268 int r; 269 270 mutex_lock(&chip->mutex); 271 r = zd_ioread32_locked(chip, value, addr); 272 mutex_unlock(&chip->mutex); 273 return r; 274 } 275 276 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) 277 { 278 int r; 279 280 mutex_lock(&chip->mutex); 281 r = zd_iowrite16_locked(chip, value, addr); 282 mutex_unlock(&chip->mutex); 283 return r; 284 } 285 286 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value) 287 { 288 int r; 289 290 mutex_lock(&chip->mutex); 291 r = zd_iowrite32_locked(chip, value, addr); 292 mutex_unlock(&chip->mutex); 293 return r; 294 } 295 296 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, 297 u32 *values, unsigned int count) 298 { 299 int r; 300 301 mutex_lock(&chip->mutex); 302 r = zd_ioread32v_locked(chip, values, addresses, count); 303 mutex_unlock(&chip->mutex); 304 return r; 305 } 306 307 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 308 unsigned int count) 309 { 310 int r; 311 312 mutex_lock(&chip->mutex); 313 r = zd_iowrite32a_locked(chip, ioreqs, count); 314 mutex_unlock(&chip->mutex); 315 return r; 316 } 317 318 static int read_pod(struct zd_chip *chip, u8 *rf_type) 319 { 320 int r; 321 u32 value; 322 323 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 324 r = zd_ioread32_locked(chip, &value, E2P_POD); 325 if (r) 326 goto error; 327 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value); 328 329 /* FIXME: AL2230 handling (Bit 7 in POD) */ 330 *rf_type = value & 0x0f; 331 chip->pa_type = (value >> 16) & 0x0f; 332 chip->patch_cck_gain = (value >> 8) & 0x1; 333 chip->patch_cr157 = (value >> 13) & 0x1; 334 chip->patch_6m_band_edge = (value >> 21) & 0x1; 335 chip->new_phy_layout = (value >> 31) & 0x1; 336 chip->al2230s_bit = (value >> 7) & 0x1; 337 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2; 338 chip->supports_tx_led = 1; 339 if (value & (1 << 24)) { /* LED scenario */ 340 if (value & (1 << 29)) 341 chip->supports_tx_led = 0; 342 } 343 344 dev_dbg_f(zd_chip_dev(chip), 345 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d " 346 "patch 6M %d new PHY %d link LED%d tx led %d\n", 347 zd_rf_name(*rf_type), *rf_type, 348 chip->pa_type, chip->patch_cck_gain, 349 chip->patch_cr157, chip->patch_6m_band_edge, 350 chip->new_phy_layout, 351 chip->link_led == LED1 ? 1 : 2, 352 chip->supports_tx_led); 353 return 0; 354 error: 355 *rf_type = 0; 356 chip->pa_type = 0; 357 chip->patch_cck_gain = 0; 358 chip->patch_cr157 = 0; 359 chip->patch_6m_band_edge = 0; 360 chip->new_phy_layout = 0; 361 return r; 362 } 363 364 static int zd_write_mac_addr_common(struct zd_chip *chip, const u8 *mac_addr, 365 const struct zd_ioreq32 *in_reqs, 366 const char *type) 367 { 368 int r; 369 struct zd_ioreq32 reqs[2] = {in_reqs[0], in_reqs[1]}; 370 371 if (mac_addr) { 372 reqs[0].value = (mac_addr[3] << 24) 373 | (mac_addr[2] << 16) 374 | (mac_addr[1] << 8) 375 | mac_addr[0]; 376 reqs[1].value = (mac_addr[5] << 8) 377 | mac_addr[4]; 378 dev_dbg_f(zd_chip_dev(chip), "%s addr %pM\n", type, mac_addr); 379 } else { 380 dev_dbg_f(zd_chip_dev(chip), "set NULL %s\n", type); 381 } 382 383 mutex_lock(&chip->mutex); 384 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); 385 mutex_unlock(&chip->mutex); 386 return r; 387 } 388 389 /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and 390 * CR_MAC_ADDR_P2 must be overwritten 391 */ 392 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr) 393 { 394 static const struct zd_ioreq32 reqs[2] = { 395 [0] = { .addr = CR_MAC_ADDR_P1 }, 396 [1] = { .addr = CR_MAC_ADDR_P2 }, 397 }; 398 399 return zd_write_mac_addr_common(chip, mac_addr, reqs, "mac"); 400 } 401 402 int zd_write_bssid(struct zd_chip *chip, const u8 *bssid) 403 { 404 static const struct zd_ioreq32 reqs[2] = { 405 [0] = { .addr = CR_BSSID_P1 }, 406 [1] = { .addr = CR_BSSID_P2 }, 407 }; 408 409 return zd_write_mac_addr_common(chip, bssid, reqs, "bssid"); 410 } 411 412 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain) 413 { 414 int r; 415 u32 value; 416 417 mutex_lock(&chip->mutex); 418 r = zd_ioread32_locked(chip, &value, E2P_SUBID); 419 mutex_unlock(&chip->mutex); 420 if (r) 421 return r; 422 423 *regdomain = value >> 16; 424 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain); 425 426 return 0; 427 } 428 429 static int read_values(struct zd_chip *chip, u8 *values, size_t count, 430 zd_addr_t e2p_addr, u32 guard) 431 { 432 int r; 433 int i; 434 u32 v; 435 436 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 437 for (i = 0;;) { 438 r = zd_ioread32_locked(chip, &v, 439 (zd_addr_t)((u16)e2p_addr+i/2)); 440 if (r) 441 return r; 442 v -= guard; 443 if (i+4 < count) { 444 values[i++] = v; 445 values[i++] = v >> 8; 446 values[i++] = v >> 16; 447 values[i++] = v >> 24; 448 continue; 449 } 450 for (;i < count; i++) 451 values[i] = v >> (8*(i%3)); 452 return 0; 453 } 454 } 455 456 static int read_pwr_cal_values(struct zd_chip *chip) 457 { 458 return read_values(chip, chip->pwr_cal_values, 459 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1, 460 0); 461 } 462 463 static int read_pwr_int_values(struct zd_chip *chip) 464 { 465 return read_values(chip, chip->pwr_int_values, 466 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1, 467 E2P_PWR_INT_GUARD); 468 } 469 470 static int read_ofdm_cal_values(struct zd_chip *chip) 471 { 472 int r; 473 int i; 474 static const zd_addr_t addresses[] = { 475 E2P_36M_CAL_VALUE1, 476 E2P_48M_CAL_VALUE1, 477 E2P_54M_CAL_VALUE1, 478 }; 479 480 for (i = 0; i < 3; i++) { 481 r = read_values(chip, chip->ofdm_cal_values[i], 482 E2P_CHANNEL_COUNT, addresses[i], 0); 483 if (r) 484 return r; 485 } 486 return 0; 487 } 488 489 static int read_cal_int_tables(struct zd_chip *chip) 490 { 491 int r; 492 493 r = read_pwr_cal_values(chip); 494 if (r) 495 return r; 496 r = read_pwr_int_values(chip); 497 if (r) 498 return r; 499 r = read_ofdm_cal_values(chip); 500 if (r) 501 return r; 502 return 0; 503 } 504 505 /* phy means physical registers */ 506 int zd_chip_lock_phy_regs(struct zd_chip *chip) 507 { 508 int r; 509 u32 tmp; 510 511 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 512 r = zd_ioread32_locked(chip, &tmp, CR_REG1); 513 if (r) { 514 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r); 515 return r; 516 } 517 518 tmp &= ~UNLOCK_PHY_REGS; 519 520 r = zd_iowrite32_locked(chip, tmp, CR_REG1); 521 if (r) 522 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); 523 return r; 524 } 525 526 int zd_chip_unlock_phy_regs(struct zd_chip *chip) 527 { 528 int r; 529 u32 tmp; 530 531 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 532 r = zd_ioread32_locked(chip, &tmp, CR_REG1); 533 if (r) { 534 dev_err(zd_chip_dev(chip), 535 "error ioread32(CR_REG1): %d\n", r); 536 return r; 537 } 538 539 tmp |= UNLOCK_PHY_REGS; 540 541 r = zd_iowrite32_locked(chip, tmp, CR_REG1); 542 if (r) 543 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); 544 return r; 545 } 546 547 /* ZD_CR157 can be optionally patched by the EEPROM for original ZD1211 */ 548 static int patch_cr157(struct zd_chip *chip) 549 { 550 int r; 551 u16 value; 552 553 if (!chip->patch_cr157) 554 return 0; 555 556 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG); 557 if (r) 558 return r; 559 560 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8); 561 return zd_iowrite32_locked(chip, value >> 8, ZD_CR157); 562 } 563 564 /* 565 * 6M band edge can be optionally overwritten for certain RF's 566 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge 567 * bit (for AL2230, AL2230S) 568 */ 569 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel) 570 { 571 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 572 if (!chip->patch_6m_band_edge) 573 return 0; 574 575 return zd_rf_patch_6m_band_edge(&chip->rf, channel); 576 } 577 578 /* Generic implementation of 6M band edge patching, used by most RFs via 579 * zd_rf_generic_patch_6m() */ 580 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel) 581 { 582 struct zd_ioreq16 ioreqs[] = { 583 { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, 584 { ZD_CR47, 0x1e }, 585 }; 586 587 /* FIXME: Channel 11 is not the edge for all regulatory domains. */ 588 if (channel == 1 || channel == 11) 589 ioreqs[0].value = 0x12; 590 591 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel); 592 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 593 } 594 595 static int zd1211_hw_reset_phy(struct zd_chip *chip) 596 { 597 static const struct zd_ioreq16 ioreqs[] = { 598 { ZD_CR0, 0x0a }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 }, 599 { ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xa0 }, 600 { ZD_CR10, 0x81 }, { ZD_CR11, 0x00 }, { ZD_CR12, 0x7f }, 601 { ZD_CR13, 0x8c }, { ZD_CR14, 0x80 }, { ZD_CR15, 0x3d }, 602 { ZD_CR16, 0x20 }, { ZD_CR17, 0x1e }, { ZD_CR18, 0x0a }, 603 { ZD_CR19, 0x48 }, { ZD_CR20, 0x0c }, { ZD_CR21, 0x0c }, 604 { ZD_CR22, 0x23 }, { ZD_CR23, 0x90 }, { ZD_CR24, 0x14 }, 605 { ZD_CR25, 0x40 }, { ZD_CR26, 0x10 }, { ZD_CR27, 0x19 }, 606 { ZD_CR28, 0x7f }, { ZD_CR29, 0x80 }, { ZD_CR30, 0x4b }, 607 { ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 }, 608 { ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 }, 609 { ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c }, 610 { ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 }, 611 { ZD_CR43, 0x10 }, { ZD_CR44, 0x12 }, { ZD_CR46, 0xff }, 612 { ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b }, 613 { ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 }, 614 { ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 }, 615 { ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff }, 616 { ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 }, 617 { ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 }, 618 { ZD_CR79, 0x68 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 }, 619 { ZD_CR82, 0x00 }, { ZD_CR83, 0x00 }, { ZD_CR84, 0x00 }, 620 { ZD_CR85, 0x02 }, { ZD_CR86, 0x00 }, { ZD_CR87, 0x00 }, 621 { ZD_CR88, 0xff }, { ZD_CR89, 0xfc }, { ZD_CR90, 0x00 }, 622 { ZD_CR91, 0x00 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x08 }, 623 { ZD_CR94, 0x00 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0xff }, 624 { ZD_CR97, 0xe7 }, { ZD_CR98, 0x00 }, { ZD_CR99, 0x00 }, 625 { ZD_CR100, 0x00 }, { ZD_CR101, 0xae }, { ZD_CR102, 0x02 }, 626 { ZD_CR103, 0x00 }, { ZD_CR104, 0x03 }, { ZD_CR105, 0x65 }, 627 { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, { ZD_CR108, 0x0a }, 628 { ZD_CR109, 0xaa }, { ZD_CR110, 0xaa }, { ZD_CR111, 0x25 }, 629 { ZD_CR112, 0x25 }, { ZD_CR113, 0x00 }, { ZD_CR119, 0x1e }, 630 { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 }, 631 { }, 632 { ZD_CR5, 0x00 }, { ZD_CR6, 0x00 }, { ZD_CR7, 0x00 }, 633 { ZD_CR8, 0x00 }, { ZD_CR9, 0x20 }, { ZD_CR12, 0xf0 }, 634 { ZD_CR20, 0x0e }, { ZD_CR21, 0x0e }, { ZD_CR27, 0x10 }, 635 { ZD_CR44, 0x33 }, { ZD_CR47, 0x1E }, { ZD_CR83, 0x24 }, 636 { ZD_CR84, 0x04 }, { ZD_CR85, 0x00 }, { ZD_CR86, 0x0C }, 637 { ZD_CR87, 0x12 }, { ZD_CR88, 0x0C }, { ZD_CR89, 0x00 }, 638 { ZD_CR90, 0x10 }, { ZD_CR91, 0x08 }, { ZD_CR93, 0x00 }, 639 { ZD_CR94, 0x01 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0x50 }, 640 { ZD_CR97, 0x37 }, { ZD_CR98, 0x35 }, { ZD_CR101, 0x13 }, 641 { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 }, 642 { ZD_CR105, 0x12 }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 }, 643 { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 }, 644 { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 }, 645 { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR120, 0x4f }, 646 { ZD_CR125, 0xaa }, { ZD_CR127, 0x03 }, { ZD_CR128, 0x14 }, 647 { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, { ZD_CR131, 0x0C }, 648 { ZD_CR136, 0xdf }, { ZD_CR137, 0x40 }, { ZD_CR138, 0xa0 }, 649 { ZD_CR139, 0xb0 }, { ZD_CR140, 0x99 }, { ZD_CR141, 0x82 }, 650 { ZD_CR142, 0x54 }, { ZD_CR143, 0x1c }, { ZD_CR144, 0x6c }, 651 { ZD_CR147, 0x07 }, { ZD_CR148, 0x4c }, { ZD_CR149, 0x50 }, 652 { ZD_CR150, 0x0e }, { ZD_CR151, 0x18 }, { ZD_CR160, 0xfe }, 653 { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa }, 654 { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe }, 655 { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba }, 656 { ZD_CR170, 0xba }, { ZD_CR171, 0xba }, 657 /* Note: ZD_CR204 must lead the ZD_CR203 */ 658 { ZD_CR204, 0x7d }, 659 { }, 660 { ZD_CR203, 0x30 }, 661 }; 662 663 int r, t; 664 665 dev_dbg_f(zd_chip_dev(chip), "\n"); 666 667 r = zd_chip_lock_phy_regs(chip); 668 if (r) 669 goto out; 670 671 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 672 if (r) 673 goto unlock; 674 675 r = patch_cr157(chip); 676 unlock: 677 t = zd_chip_unlock_phy_regs(chip); 678 if (t && !r) 679 r = t; 680 out: 681 return r; 682 } 683 684 static int zd1211b_hw_reset_phy(struct zd_chip *chip) 685 { 686 static const struct zd_ioreq16 ioreqs[] = { 687 { ZD_CR0, 0x14 }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 }, 688 { ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xe0 }, 689 { ZD_CR10, 0x81 }, 690 /* power control { { ZD_CR11, 1 << 6 }, */ 691 { ZD_CR11, 0x00 }, 692 { ZD_CR12, 0xf0 }, { ZD_CR13, 0x8c }, { ZD_CR14, 0x80 }, 693 { ZD_CR15, 0x3d }, { ZD_CR16, 0x20 }, { ZD_CR17, 0x1e }, 694 { ZD_CR18, 0x0a }, { ZD_CR19, 0x48 }, 695 { ZD_CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ 696 { ZD_CR21, 0x0e }, { ZD_CR22, 0x23 }, { ZD_CR23, 0x90 }, 697 { ZD_CR24, 0x14 }, { ZD_CR25, 0x40 }, { ZD_CR26, 0x10 }, 698 { ZD_CR27, 0x10 }, { ZD_CR28, 0x7f }, { ZD_CR29, 0x80 }, 699 { ZD_CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */ 700 { ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 }, 701 { ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 }, 702 { ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c }, 703 { ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 }, 704 { ZD_CR43, 0x10 }, { ZD_CR44, 0x33 }, { ZD_CR46, 0xff }, 705 { ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b }, 706 { ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 }, 707 { ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 }, 708 { ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff }, 709 { ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 }, 710 { ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 }, 711 { ZD_CR79, 0xf0 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 }, 712 { ZD_CR82, 0x00 }, { ZD_CR83, 0x24 }, { ZD_CR84, 0x04 }, 713 { ZD_CR85, 0x00 }, { ZD_CR86, 0x0c }, { ZD_CR87, 0x12 }, 714 { ZD_CR88, 0x0c }, { ZD_CR89, 0x00 }, { ZD_CR90, 0x58 }, 715 { ZD_CR91, 0x04 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x00 }, 716 { ZD_CR94, 0x01 }, 717 { ZD_CR95, 0x20 }, /* ZD1211B */ 718 { ZD_CR96, 0x50 }, { ZD_CR97, 0x37 }, { ZD_CR98, 0x35 }, 719 { ZD_CR99, 0x00 }, { ZD_CR100, 0x01 }, { ZD_CR101, 0x13 }, 720 { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 }, 721 { ZD_CR105, 0x12 }, { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, 722 { ZD_CR108, 0x0a }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 }, 723 { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 }, 724 { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 }, 725 { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR119, 0x1e }, 726 { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 }, 727 { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, 728 { ZD_CR131, 0x0c }, { ZD_CR136, 0xdf }, { ZD_CR137, 0xa0 }, 729 { ZD_CR138, 0xa8 }, { ZD_CR139, 0xb4 }, { ZD_CR140, 0x98 }, 730 { ZD_CR141, 0x82 }, { ZD_CR142, 0x53 }, { ZD_CR143, 0x1c }, 731 { ZD_CR144, 0x6c }, { ZD_CR147, 0x07 }, { ZD_CR148, 0x40 }, 732 { ZD_CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ 733 { ZD_CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ 734 { ZD_CR151, 0x18 }, { ZD_CR159, 0x70 }, { ZD_CR160, 0xfe }, 735 { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa }, 736 { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe }, 737 { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba }, 738 { ZD_CR170, 0xba }, { ZD_CR171, 0xba }, 739 /* Note: ZD_CR204 must lead the ZD_CR203 */ 740 { ZD_CR204, 0x7d }, 741 {}, 742 { ZD_CR203, 0x30 }, 743 }; 744 745 int r, t; 746 747 dev_dbg_f(zd_chip_dev(chip), "\n"); 748 749 r = zd_chip_lock_phy_regs(chip); 750 if (r) 751 goto out; 752 753 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 754 t = zd_chip_unlock_phy_regs(chip); 755 if (t && !r) 756 r = t; 757 out: 758 return r; 759 } 760 761 static int hw_reset_phy(struct zd_chip *chip) 762 { 763 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) : 764 zd1211_hw_reset_phy(chip); 765 } 766 767 static int zd1211_hw_init_hmac(struct zd_chip *chip) 768 { 769 static const struct zd_ioreq32 ioreqs[] = { 770 { CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT }, 771 { CR_RX_THRESHOLD, 0x000c0640 }, 772 }; 773 774 dev_dbg_f(zd_chip_dev(chip), "\n"); 775 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 776 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 777 } 778 779 static int zd1211b_hw_init_hmac(struct zd_chip *chip) 780 { 781 static const struct zd_ioreq32 ioreqs[] = { 782 { CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT }, 783 { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f }, 784 { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f }, 785 { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f }, 786 { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f }, 787 { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, 788 { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, 789 { CR_ZD1211B_TXOP, 0x01800824 }, 790 { CR_RX_THRESHOLD, 0x000c0eff, }, 791 }; 792 793 dev_dbg_f(zd_chip_dev(chip), "\n"); 794 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 795 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 796 } 797 798 static int hw_init_hmac(struct zd_chip *chip) 799 { 800 int r; 801 static const struct zd_ioreq32 ioreqs[] = { 802 { CR_ACK_TIMEOUT_EXT, 0x20 }, 803 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, 804 { CR_SNIFFER_ON, 0 }, 805 { CR_RX_FILTER, STA_RX_FILTER }, 806 { CR_GROUP_HASH_P1, 0x00 }, 807 { CR_GROUP_HASH_P2, 0x80000000 }, 808 { CR_REG1, 0xa4 }, 809 { CR_ADDA_PWR_DWN, 0x7f }, 810 { CR_BCN_PLCP_CFG, 0x00f00401 }, 811 { CR_PHY_DELAY, 0x00 }, 812 { CR_ACK_TIMEOUT_EXT, 0x80 }, 813 { CR_ADDA_PWR_DWN, 0x00 }, 814 { CR_ACK_TIME_80211, 0x100 }, 815 { CR_RX_PE_DELAY, 0x70 }, 816 { CR_PS_CTRL, 0x10000000 }, 817 { CR_RTS_CTS_RATE, 0x02030203 }, 818 { CR_AFTER_PNP, 0x1 }, 819 { CR_WEP_PROTECT, 0x114 }, 820 { CR_IFS_VALUE, IFS_VALUE_DEFAULT }, 821 { CR_CAM_MODE, MODE_AP_WDS}, 822 }; 823 824 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 825 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 826 if (r) 827 return r; 828 829 return zd_chip_is_zd1211b(chip) ? 830 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); 831 } 832 833 struct aw_pt_bi { 834 u32 atim_wnd_period; 835 u32 pre_tbtt; 836 u32 beacon_interval; 837 }; 838 839 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) 840 { 841 int r; 842 static const zd_addr_t aw_pt_bi_addr[] = 843 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL }; 844 u32 values[3]; 845 846 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, 847 ARRAY_SIZE(aw_pt_bi_addr)); 848 if (r) { 849 memset(s, 0, sizeof(*s)); 850 return r; 851 } 852 853 s->atim_wnd_period = values[0]; 854 s->pre_tbtt = values[1]; 855 s->beacon_interval = values[2]; 856 return 0; 857 } 858 859 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) 860 { 861 struct zd_ioreq32 reqs[3]; 862 u16 b_interval = s->beacon_interval & 0xffff; 863 864 if (b_interval <= 5) 865 b_interval = 5; 866 if (s->pre_tbtt < 4 || s->pre_tbtt >= b_interval) 867 s->pre_tbtt = b_interval - 1; 868 if (s->atim_wnd_period >= s->pre_tbtt) 869 s->atim_wnd_period = s->pre_tbtt - 1; 870 871 reqs[0].addr = CR_ATIM_WND_PERIOD; 872 reqs[0].value = s->atim_wnd_period; 873 reqs[1].addr = CR_PRE_TBTT; 874 reqs[1].value = s->pre_tbtt; 875 reqs[2].addr = CR_BCN_INTERVAL; 876 reqs[2].value = (s->beacon_interval & ~0xffff) | b_interval; 877 878 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); 879 } 880 881 882 static int set_beacon_interval(struct zd_chip *chip, u16 interval, 883 u8 dtim_period, int type) 884 { 885 int r; 886 struct aw_pt_bi s; 887 u32 b_interval, mode_flag; 888 889 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 890 891 if (interval > 0) { 892 switch (type) { 893 case NL80211_IFTYPE_ADHOC: 894 case NL80211_IFTYPE_MESH_POINT: 895 mode_flag = BCN_MODE_IBSS; 896 break; 897 case NL80211_IFTYPE_AP: 898 mode_flag = BCN_MODE_AP; 899 break; 900 default: 901 mode_flag = 0; 902 break; 903 } 904 } else { 905 dtim_period = 0; 906 mode_flag = 0; 907 } 908 909 b_interval = mode_flag | (dtim_period << 16) | interval; 910 911 r = zd_iowrite32_locked(chip, b_interval, CR_BCN_INTERVAL); 912 if (r) 913 return r; 914 r = get_aw_pt_bi(chip, &s); 915 if (r) 916 return r; 917 return set_aw_pt_bi(chip, &s); 918 } 919 920 int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period, 921 int type) 922 { 923 int r; 924 925 mutex_lock(&chip->mutex); 926 r = set_beacon_interval(chip, interval, dtim_period, type); 927 mutex_unlock(&chip->mutex); 928 return r; 929 } 930 931 static int hw_init(struct zd_chip *chip) 932 { 933 int r; 934 935 dev_dbg_f(zd_chip_dev(chip), "\n"); 936 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 937 r = hw_reset_phy(chip); 938 if (r) 939 return r; 940 941 r = hw_init_hmac(chip); 942 if (r) 943 return r; 944 945 return set_beacon_interval(chip, 100, 0, NL80211_IFTYPE_UNSPECIFIED); 946 } 947 948 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset) 949 { 950 return (zd_addr_t)((u16)chip->fw_regs_base + offset); 951 } 952 953 #ifdef DEBUG 954 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, 955 const char *addr_string) 956 { 957 int r; 958 u32 value; 959 960 r = zd_ioread32_locked(chip, &value, addr); 961 if (r) { 962 dev_dbg_f(zd_chip_dev(chip), 963 "error reading %s. Error number %d\n", addr_string, r); 964 return r; 965 } 966 967 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n", 968 addr_string, (unsigned int)value); 969 return 0; 970 } 971 972 static int test_init(struct zd_chip *chip) 973 { 974 int r; 975 976 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP"); 977 if (r) 978 return r; 979 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN"); 980 if (r) 981 return r; 982 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT"); 983 } 984 985 static void dump_fw_registers(struct zd_chip *chip) 986 { 987 const zd_addr_t addr[4] = { 988 fw_reg_addr(chip, FW_REG_FIRMWARE_VER), 989 fw_reg_addr(chip, FW_REG_USB_SPEED), 990 fw_reg_addr(chip, FW_REG_FIX_TX_RATE), 991 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), 992 }; 993 994 int r; 995 u16 values[4]; 996 997 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr, 998 ARRAY_SIZE(addr)); 999 if (r) { 1000 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n", 1001 r); 1002 return; 1003 } 1004 1005 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); 1006 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]); 1007 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]); 1008 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]); 1009 } 1010 #endif /* DEBUG */ 1011 1012 static int print_fw_version(struct zd_chip *chip) 1013 { 1014 struct wiphy *wiphy = zd_chip_to_mac(chip)->hw->wiphy; 1015 int r; 1016 u16 version; 1017 1018 r = zd_ioread16_locked(chip, &version, 1019 fw_reg_addr(chip, FW_REG_FIRMWARE_VER)); 1020 if (r) 1021 return r; 1022 1023 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version); 1024 1025 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), 1026 "%04hx", version); 1027 1028 return 0; 1029 } 1030 1031 static int set_mandatory_rates(struct zd_chip *chip, int gmode) 1032 { 1033 u32 rates; 1034 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 1035 /* This sets the mandatory rates, which only depend from the standard 1036 * that the device is supporting. Until further notice we should try 1037 * to support 802.11g also for full speed USB. 1038 */ 1039 if (!gmode) 1040 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M; 1041 else 1042 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M| 1043 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M; 1044 1045 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); 1046 } 1047 1048 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, 1049 int preamble) 1050 { 1051 u32 value = 0; 1052 1053 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble); 1054 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE; 1055 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE; 1056 1057 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */ 1058 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE; 1059 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE; 1060 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE; 1061 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE; 1062 1063 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE); 1064 } 1065 1066 int zd_chip_enable_hwint(struct zd_chip *chip) 1067 { 1068 int r; 1069 1070 mutex_lock(&chip->mutex); 1071 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT); 1072 mutex_unlock(&chip->mutex); 1073 return r; 1074 } 1075 1076 static int disable_hwint(struct zd_chip *chip) 1077 { 1078 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT); 1079 } 1080 1081 int zd_chip_disable_hwint(struct zd_chip *chip) 1082 { 1083 int r; 1084 1085 mutex_lock(&chip->mutex); 1086 r = disable_hwint(chip); 1087 mutex_unlock(&chip->mutex); 1088 return r; 1089 } 1090 1091 static int read_fw_regs_offset(struct zd_chip *chip) 1092 { 1093 int r; 1094 1095 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 1096 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base, 1097 FWRAW_REGS_ADDR); 1098 if (r) 1099 return r; 1100 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n", 1101 (u16)chip->fw_regs_base); 1102 1103 return 0; 1104 } 1105 1106 /* Read mac address using pre-firmware interface */ 1107 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr) 1108 { 1109 dev_dbg_f(zd_chip_dev(chip), "\n"); 1110 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr, 1111 ETH_ALEN); 1112 } 1113 1114 int zd_chip_init_hw(struct zd_chip *chip) 1115 { 1116 int r; 1117 u8 rf_type; 1118 1119 dev_dbg_f(zd_chip_dev(chip), "\n"); 1120 1121 mutex_lock(&chip->mutex); 1122 1123 #ifdef DEBUG 1124 r = test_init(chip); 1125 if (r) 1126 goto out; 1127 #endif 1128 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP); 1129 if (r) 1130 goto out; 1131 1132 r = read_fw_regs_offset(chip); 1133 if (r) 1134 goto out; 1135 1136 /* GPI is always disabled, also in the other driver. 1137 */ 1138 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); 1139 if (r) 1140 goto out; 1141 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX); 1142 if (r) 1143 goto out; 1144 /* Currently we support IEEE 802.11g for full and high speed USB. 1145 * It might be discussed, whether we should support pure b mode for 1146 * full speed USB. 1147 */ 1148 r = set_mandatory_rates(chip, 1); 1149 if (r) 1150 goto out; 1151 /* Disabling interrupts is certainly a smart thing here. 1152 */ 1153 r = disable_hwint(chip); 1154 if (r) 1155 goto out; 1156 r = read_pod(chip, &rf_type); 1157 if (r) 1158 goto out; 1159 r = hw_init(chip); 1160 if (r) 1161 goto out; 1162 r = zd_rf_init_hw(&chip->rf, rf_type); 1163 if (r) 1164 goto out; 1165 1166 r = print_fw_version(chip); 1167 if (r) 1168 goto out; 1169 1170 #ifdef DEBUG 1171 dump_fw_registers(chip); 1172 r = test_init(chip); 1173 if (r) 1174 goto out; 1175 #endif /* DEBUG */ 1176 1177 r = read_cal_int_tables(chip); 1178 if (r) 1179 goto out; 1180 1181 print_id(chip); 1182 out: 1183 mutex_unlock(&chip->mutex); 1184 return r; 1185 } 1186 1187 static int update_pwr_int(struct zd_chip *chip, u8 channel) 1188 { 1189 u8 value = chip->pwr_int_values[channel - 1]; 1190 return zd_iowrite16_locked(chip, value, ZD_CR31); 1191 } 1192 1193 static int update_pwr_cal(struct zd_chip *chip, u8 channel) 1194 { 1195 u8 value = chip->pwr_cal_values[channel-1]; 1196 return zd_iowrite16_locked(chip, value, ZD_CR68); 1197 } 1198 1199 static int update_ofdm_cal(struct zd_chip *chip, u8 channel) 1200 { 1201 struct zd_ioreq16 ioreqs[3]; 1202 1203 ioreqs[0].addr = ZD_CR67; 1204 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; 1205 ioreqs[1].addr = ZD_CR66; 1206 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1]; 1207 ioreqs[2].addr = ZD_CR65; 1208 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1]; 1209 1210 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1211 } 1212 1213 static int update_channel_integration_and_calibration(struct zd_chip *chip, 1214 u8 channel) 1215 { 1216 int r; 1217 1218 if (!zd_rf_should_update_pwr_int(&chip->rf)) 1219 return 0; 1220 1221 r = update_pwr_int(chip, channel); 1222 if (r) 1223 return r; 1224 if (zd_chip_is_zd1211b(chip)) { 1225 static const struct zd_ioreq16 ioreqs[] = { 1226 { ZD_CR69, 0x28 }, 1227 {}, 1228 { ZD_CR69, 0x2a }, 1229 }; 1230 1231 r = update_ofdm_cal(chip, channel); 1232 if (r) 1233 return r; 1234 r = update_pwr_cal(chip, channel); 1235 if (r) 1236 return r; 1237 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1238 if (r) 1239 return r; 1240 } 1241 1242 return 0; 1243 } 1244 1245 /* The CCK baseband gain can be optionally patched by the EEPROM */ 1246 static int patch_cck_gain(struct zd_chip *chip) 1247 { 1248 int r; 1249 u32 value; 1250 1251 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf)) 1252 return 0; 1253 1254 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 1255 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); 1256 if (r) 1257 return r; 1258 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); 1259 return zd_iowrite16_locked(chip, value & 0xff, ZD_CR47); 1260 } 1261 1262 int zd_chip_set_channel(struct zd_chip *chip, u8 channel) 1263 { 1264 int r, t; 1265 1266 mutex_lock(&chip->mutex); 1267 r = zd_chip_lock_phy_regs(chip); 1268 if (r) 1269 goto out; 1270 r = zd_rf_set_channel(&chip->rf, channel); 1271 if (r) 1272 goto unlock; 1273 r = update_channel_integration_and_calibration(chip, channel); 1274 if (r) 1275 goto unlock; 1276 r = patch_cck_gain(chip); 1277 if (r) 1278 goto unlock; 1279 r = patch_6m_band_edge(chip, channel); 1280 if (r) 1281 goto unlock; 1282 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); 1283 unlock: 1284 t = zd_chip_unlock_phy_regs(chip); 1285 if (t && !r) 1286 r = t; 1287 out: 1288 mutex_unlock(&chip->mutex); 1289 return r; 1290 } 1291 1292 u8 zd_chip_get_channel(struct zd_chip *chip) 1293 { 1294 u8 channel; 1295 1296 mutex_lock(&chip->mutex); 1297 channel = chip->rf.channel; 1298 mutex_unlock(&chip->mutex); 1299 return channel; 1300 } 1301 1302 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) 1303 { 1304 const zd_addr_t a[] = { 1305 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), 1306 CR_LED, 1307 }; 1308 1309 int r; 1310 u16 v[ARRAY_SIZE(a)]; 1311 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { 1312 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, 1313 [1] = { CR_LED }, 1314 }; 1315 u16 other_led; 1316 1317 mutex_lock(&chip->mutex); 1318 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a)); 1319 if (r) 1320 goto out; 1321 1322 other_led = chip->link_led == LED1 ? LED2 : LED1; 1323 1324 switch (status) { 1325 case ZD_LED_OFF: 1326 ioreqs[0].value = FW_LINK_OFF; 1327 ioreqs[1].value = v[1] & ~(LED1|LED2); 1328 break; 1329 case ZD_LED_SCANNING: 1330 ioreqs[0].value = FW_LINK_OFF; 1331 ioreqs[1].value = v[1] & ~other_led; 1332 if ((u32)ktime_get_seconds() % 3 == 0) { 1333 ioreqs[1].value &= ~chip->link_led; 1334 } else { 1335 ioreqs[1].value |= chip->link_led; 1336 } 1337 break; 1338 case ZD_LED_ASSOCIATED: 1339 ioreqs[0].value = FW_LINK_TX; 1340 ioreqs[1].value = v[1] & ~other_led; 1341 ioreqs[1].value |= chip->link_led; 1342 break; 1343 default: 1344 r = -EINVAL; 1345 goto out; 1346 } 1347 1348 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) { 1349 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1350 if (r) 1351 goto out; 1352 } 1353 r = 0; 1354 out: 1355 mutex_unlock(&chip->mutex); 1356 return r; 1357 } 1358 1359 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates) 1360 { 1361 int r; 1362 1363 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G)) 1364 return -EINVAL; 1365 1366 mutex_lock(&chip->mutex); 1367 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL); 1368 mutex_unlock(&chip->mutex); 1369 return r; 1370 } 1371 1372 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame) 1373 { 1374 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame); 1375 } 1376 1377 /** 1378 * zd_rx_rate - report zd-rate 1379 * @rx_frame - received frame 1380 * @rx_status - rx_status as given by the device 1381 * 1382 * This function converts the rate as encoded in the received packet to the 1383 * zd-rate, we are using on other places in the driver. 1384 */ 1385 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status) 1386 { 1387 u8 zd_rate; 1388 if (status->frame_status & ZD_RX_OFDM) { 1389 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame); 1390 } else { 1391 switch (zd_cck_plcp_header_signal(rx_frame)) { 1392 case ZD_CCK_PLCP_SIGNAL_1M: 1393 zd_rate = ZD_CCK_RATE_1M; 1394 break; 1395 case ZD_CCK_PLCP_SIGNAL_2M: 1396 zd_rate = ZD_CCK_RATE_2M; 1397 break; 1398 case ZD_CCK_PLCP_SIGNAL_5M5: 1399 zd_rate = ZD_CCK_RATE_5_5M; 1400 break; 1401 case ZD_CCK_PLCP_SIGNAL_11M: 1402 zd_rate = ZD_CCK_RATE_11M; 1403 break; 1404 default: 1405 zd_rate = 0; 1406 } 1407 } 1408 1409 return zd_rate; 1410 } 1411 1412 int zd_chip_switch_radio_on(struct zd_chip *chip) 1413 { 1414 int r; 1415 1416 mutex_lock(&chip->mutex); 1417 r = zd_switch_radio_on(&chip->rf); 1418 mutex_unlock(&chip->mutex); 1419 return r; 1420 } 1421 1422 int zd_chip_switch_radio_off(struct zd_chip *chip) 1423 { 1424 int r; 1425 1426 mutex_lock(&chip->mutex); 1427 r = zd_switch_radio_off(&chip->rf); 1428 mutex_unlock(&chip->mutex); 1429 return r; 1430 } 1431 1432 int zd_chip_enable_int(struct zd_chip *chip) 1433 { 1434 int r; 1435 1436 mutex_lock(&chip->mutex); 1437 r = zd_usb_enable_int(&chip->usb); 1438 mutex_unlock(&chip->mutex); 1439 return r; 1440 } 1441 1442 void zd_chip_disable_int(struct zd_chip *chip) 1443 { 1444 mutex_lock(&chip->mutex); 1445 zd_usb_disable_int(&chip->usb); 1446 mutex_unlock(&chip->mutex); 1447 1448 /* cancel pending interrupt work */ 1449 cancel_work_sync(&zd_chip_to_mac(chip)->process_intr); 1450 } 1451 1452 int zd_chip_enable_rxtx(struct zd_chip *chip) 1453 { 1454 int r; 1455 1456 mutex_lock(&chip->mutex); 1457 zd_usb_enable_tx(&chip->usb); 1458 r = zd_usb_enable_rx(&chip->usb); 1459 zd_tx_watchdog_enable(&chip->usb); 1460 mutex_unlock(&chip->mutex); 1461 return r; 1462 } 1463 1464 void zd_chip_disable_rxtx(struct zd_chip *chip) 1465 { 1466 mutex_lock(&chip->mutex); 1467 zd_tx_watchdog_disable(&chip->usb); 1468 zd_usb_disable_rx(&chip->usb); 1469 zd_usb_disable_tx(&chip->usb); 1470 mutex_unlock(&chip->mutex); 1471 } 1472 1473 int zd_rfwritev_locked(struct zd_chip *chip, 1474 const u32* values, unsigned int count, u8 bits) 1475 { 1476 int r; 1477 unsigned int i; 1478 1479 for (i = 0; i < count; i++) { 1480 r = zd_rfwrite_locked(chip, values[i], bits); 1481 if (r) 1482 return r; 1483 } 1484 1485 return 0; 1486 } 1487 1488 /* 1489 * We can optionally program the RF directly through CR regs, if supported by 1490 * the hardware. This is much faster than the older method. 1491 */ 1492 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value) 1493 { 1494 const struct zd_ioreq16 ioreqs[] = { 1495 { ZD_CR244, (value >> 16) & 0xff }, 1496 { ZD_CR243, (value >> 8) & 0xff }, 1497 { ZD_CR242, value & 0xff }, 1498 }; 1499 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 1500 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1501 } 1502 1503 int zd_rfwritev_cr_locked(struct zd_chip *chip, 1504 const u32 *values, unsigned int count) 1505 { 1506 int r; 1507 unsigned int i; 1508 1509 for (i = 0; i < count; i++) { 1510 r = zd_rfwrite_cr_locked(chip, values[i]); 1511 if (r) 1512 return r; 1513 } 1514 1515 return 0; 1516 } 1517 1518 int zd_chip_set_multicast_hash(struct zd_chip *chip, 1519 struct zd_mc_hash *hash) 1520 { 1521 const struct zd_ioreq32 ioreqs[] = { 1522 { CR_GROUP_HASH_P1, hash->low }, 1523 { CR_GROUP_HASH_P2, hash->high }, 1524 }; 1525 1526 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1527 } 1528 1529 u64 zd_chip_get_tsf(struct zd_chip *chip) 1530 { 1531 int r; 1532 static const zd_addr_t aw_pt_bi_addr[] = 1533 { CR_TSF_LOW_PART, CR_TSF_HIGH_PART }; 1534 u32 values[2]; 1535 u64 tsf; 1536 1537 mutex_lock(&chip->mutex); 1538 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, 1539 ARRAY_SIZE(aw_pt_bi_addr)); 1540 mutex_unlock(&chip->mutex); 1541 if (r) 1542 return 0; 1543 1544 tsf = values[1]; 1545 tsf = (tsf << 32) | values[0]; 1546 1547 return tsf; 1548 } 1549