1 /* 2 * This file is part of wlcore 3 * 4 * Copyright (C) 2011 Texas Instruments Inc. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22 #ifndef __REG_H__ 23 #define __REG_H__ 24 25 #define WL18XX_REGISTERS_BASE 0x00800000 26 #define WL18XX_CODE_BASE 0x00000000 27 #define WL18XX_DATA_BASE 0x00400000 28 #define WL18XX_DOUBLE_BUFFER_BASE 0x00600000 29 #define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000 30 #define WL18XX_PHY_BASE 0x00900000 31 #define WL18XX_TOP_OCP_BASE 0x00A00000 32 #define WL18XX_PACKET_RAM_BASE 0x00B00000 33 #define WL18XX_HOST_BASE 0x00C00000 34 35 #define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000 36 37 #define WL18XX_REG_BOOT_PART_START 0x00802000 38 #define WL18XX_REG_BOOT_PART_SIZE 0x00014578 39 40 #define WL18XX_PHY_INIT_MEM_ADDR 0x80926000 41 #define WL18XX_PHY_END_MEM_ADDR 0x8093CA44 42 #define WL18XX_PHY_INIT_MEM_SIZE \ 43 (WL18XX_PHY_END_MEM_ADDR - WL18XX_PHY_INIT_MEM_ADDR) 44 45 #define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE) 46 #define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000) 47 #define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000) 48 #define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000) 49 #define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000) 50 #define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000) 51 #define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000) 52 #define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000) 53 #define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000) 54 #define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000) 55 #define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800) 56 #define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00) 57 #define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000) 58 #define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400) 59 60 #define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004) 61 #define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8) 62 #define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0) 63 #define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074) 64 #define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078) 65 #define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC) 66 67 #define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C) 68 69 #define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018) 70 #define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008) 71 72 /* Scratch Pad registers*/ 73 #define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC) 74 #define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0) 75 #define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4) 76 #define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8) 77 #define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC) 78 #define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504) 79 #define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500) 80 #define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508) 81 #define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510) 82 #define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C) 83 #define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514) 84 #define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518) 85 #define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C) 86 #define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520) 87 88 /* Spare registers*/ 89 #define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194) 90 #define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198) 91 #define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C) 92 #define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0) 93 #define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4) 94 #define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8) 95 #define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC) 96 #define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0) 97 #define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524) 98 #define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528) 99 #define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C) 100 #define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530) 101 #define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534) 102 #define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538) 103 #define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C) 104 #define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540) 105 106 #define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0) 107 #define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1) 108 #define WL18XX_EEPROMLESS_IND (WL18XX_SCR_PAD4) 109 110 #define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100) 111 #define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C) 112 113 /* PRCM registers */ 114 #define PLATFORM_DETECTION 0xA0E3E0 115 #define OCS_EN 0xA02080 116 #define PRIMARY_CLK_DETECT 0xA020A6 117 #define PLLSH_COEX_PLL_N 0xA02384 118 #define PLLSH_COEX_PLL_M 0xA02382 119 #define PLLSH_COEX_PLL_SWALLOW_EN 0xA0238E 120 #define PLLSH_WL_PLL_SEL 0xA02398 121 122 #define PLLSH_WCS_PLL_N 0xA02362 123 #define PLLSH_WCS_PLL_M 0xA02360 124 #define PLLSH_WCS_PLL_Q_FACTOR_CFG_1 0xA02364 125 #define PLLSH_WCS_PLL_Q_FACTOR_CFG_2 0xA02366 126 #define PLLSH_WCS_PLL_P_FACTOR_CFG_1 0xA02368 127 #define PLLSH_WCS_PLL_P_FACTOR_CFG_2 0xA0236A 128 #define PLLSH_WCS_PLL_SWALLOW_EN 0xA0236C 129 #define PLLSH_WL_PLL_EN 0xA02392 130 131 #define PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK 0xFFFF 132 #define PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK 0x007F 133 #define PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK 0xFFFF 134 #define PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK 0x000F 135 136 #define PLLSH_WL_PLL_EN_VAL1 0x7 137 #define PLLSH_WL_PLL_EN_VAL2 0x2 138 #define PLLSH_COEX_PLL_SWALLOW_EN_VAL1 0x2 139 #define PLLSH_COEX_PLL_SWALLOW_EN_VAL2 0x11 140 141 #define PLLSH_WCS_PLL_SWALLOW_EN_VAL1 0x1 142 #define PLLSH_WCS_PLL_SWALLOW_EN_VAL2 0x12 143 144 #define PLLSH_WL_PLL_SEL_WCS_PLL 0x0 145 #define PLLSH_WL_PLL_SEL_COEX_PLL 0x1 146 147 #define WL18XX_REG_FUSE_DATA_1_3 0xA0260C 148 #define WL18XX_PG_VER_MASK 0x70 149 #define WL18XX_PG_VER_OFFSET 4 150 #define WL18XX_ROM_VER_MASK 0x3e00 151 #define WL18XX_ROM_VER_OFFSET 9 152 #define WL18XX_METAL_VER_MASK 0xC 153 #define WL18XX_METAL_VER_OFFSET 2 154 #define WL18XX_NEW_METAL_VER_MASK 0x180 155 #define WL18XX_NEW_METAL_VER_OFFSET 7 156 157 #define WL18XX_PACKAGE_TYPE_OFFSET 13 158 #define WL18XX_PACKAGE_TYPE_WSP 0 159 160 #define WL18XX_REG_FUSE_DATA_2_3 0xA02614 161 #define WL18XX_RDL_VER_MASK 0x1f00 162 #define WL18XX_RDL_VER_OFFSET 8 163 164 #define WL18XX_REG_FUSE_BD_ADDR_1 0xA02602 165 #define WL18XX_REG_FUSE_BD_ADDR_2 0xA02606 166 167 #define WL18XX_CMD_MBOX_ADDRESS 0xB007B4 168 169 #define WL18XX_FW_STATUS_ADDR 0x50F8 170 171 #define CHIP_ID_185x_PG10 (0x06030101) 172 #define CHIP_ID_185x_PG20 (0x06030111) 173 174 /* 175 * Host Command Interrupt. Setting this bit masks 176 * the interrupt that the host issues to inform 177 * the FW that it has sent a command 178 * to the Wlan hardware Command Mailbox. 179 */ 180 #define WL18XX_INTR_TRIG_CMD BIT(28) 181 182 /* 183 * Host Event Acknowlegde Interrupt. The host 184 * sets this bit to acknowledge that it received 185 * the unsolicited information from the event 186 * mailbox. 187 */ 188 #define WL18XX_INTR_TRIG_EVENT_ACK BIT(29) 189 190 /* 191 * To boot the firmware in PLT mode we need to write this value in 192 * SCR_PAD8 before starting. 193 */ 194 #define WL18XX_SCR_PAD8_PLT 0xBABABEBE 195 196 enum { 197 COMPONENT_NO_SWITCH = 0x0, 198 COMPONENT_2_WAY_SWITCH = 0x1, 199 COMPONENT_3_WAY_SWITCH = 0x2, 200 COMPONENT_MATCHING = 0x3, 201 }; 202 203 enum { 204 FEM_NONE = 0x0, 205 FEM_VENDOR_1 = 0x1, 206 FEM_VENDOR_2 = 0x2, 207 FEM_VENDOR_3 = 0x3, 208 }; 209 210 enum { 211 BOARD_TYPE_EVB_18XX = 0, 212 BOARD_TYPE_DVP_18XX = 1, 213 BOARD_TYPE_HDK_18XX = 2, 214 BOARD_TYPE_FPGA_18XX = 3, 215 BOARD_TYPE_COM8_18XX = 4, 216 217 NUM_BOARD_TYPES, 218 }; 219 220 enum wl18xx_rdl_num { 221 RDL_NONE = 0, 222 RDL_1_HP = 1, 223 RDL_2_SP = 2, 224 RDL_3_HP = 3, 225 RDL_4_SP = 4, 226 RDL_5_SP = 0x11, 227 RDL_6_SP = 0x12, 228 RDL_7_SP = 0x13, 229 RDL_8_SP = 0x14, 230 231 _RDL_LAST, 232 RDL_MAX = _RDL_LAST - 1, 233 }; 234 235 236 /* FPGA_SPARE_1 register - used to change the PHY ATPG clock at boot time */ 237 #define WL18XX_PHY_FPGA_SPARE_1 0x8093CA40 238 239 /* command to disable FDSP clock */ 240 #define MEM_FDSP_CLK_120_DISABLE 0x80000000 241 242 /* command to set ATPG clock toward FDSP Code RAM rather than its own clock */ 243 #define MEM_FDSP_CODERAM_FUNC_CLK_SEL 0xC0000000 244 245 /* command to re-enable FDSP clock */ 246 #define MEM_FDSP_CLK_120_ENABLE 0x40000000 247 248 #endif /* __REG_H__ */ 249