1 /* 2 * This file is part of wl18xx 3 * 4 * Copyright (C) 2011 Texas Instruments. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22 #ifndef __WL18XX_ACX_H__ 23 #define __WL18XX_ACX_H__ 24 25 #include "../wlcore/wlcore.h" 26 #include "../wlcore/acx.h" 27 28 enum { 29 ACX_NS_IPV6_FILTER = 0x0050, 30 ACX_PEER_HT_OPERATION_MODE_CFG = 0x0051, 31 ACX_CSUM_CONFIG = 0x0052, 32 ACX_SIM_CONFIG = 0x0053, 33 ACX_CLEAR_STATISTICS = 0x0054, 34 ACX_AUTO_RX_STREAMING = 0x0055, 35 ACX_PEER_CAP = 0x0056 36 }; 37 38 /* numbers of bits the length field takes (add 1 for the actual number) */ 39 #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15 40 41 #define WL18XX_ACX_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \ 42 WL1271_ACX_INTR_INIT_COMPLETE | \ 43 WL1271_ACX_INTR_EVENT_A | \ 44 WL1271_ACX_INTR_EVENT_B | \ 45 WL1271_ACX_INTR_CMD_COMPLETE | \ 46 WL1271_ACX_INTR_HW_AVAILABLE | \ 47 WL1271_ACX_INTR_DATA | \ 48 WL1271_ACX_SW_INTR_WATCHDOG) 49 50 #define WL18XX_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ 51 WL1271_ACX_INTR_EVENT_A | \ 52 WL1271_ACX_INTR_EVENT_B | \ 53 WL1271_ACX_INTR_HW_AVAILABLE | \ 54 WL1271_ACX_INTR_DATA | \ 55 WL1271_ACX_SW_INTR_WATCHDOG) 56 57 struct wl18xx_acx_host_config_bitmap { 58 struct acx_header header; 59 60 __le32 host_cfg_bitmap; 61 62 __le32 host_sdio_block_size; 63 64 /* extra mem blocks per frame in TX. */ 65 __le32 extra_mem_blocks; 66 67 /* 68 * number of bits of the length field in the first TX word 69 * (up to 15 - for using the entire 16 bits). 70 */ 71 __le32 length_field_size; 72 73 } __packed; 74 75 enum { 76 CHECKSUM_OFFLOAD_DISABLED = 0, 77 CHECKSUM_OFFLOAD_ENABLED = 1, 78 CHECKSUM_OFFLOAD_FAKE_RX = 2, 79 CHECKSUM_OFFLOAD_INVALID = 0xFF 80 }; 81 82 struct wl18xx_acx_checksum_state { 83 struct acx_header header; 84 85 /* enum acx_checksum_state */ 86 u8 checksum_state; 87 u8 pad[3]; 88 } __packed; 89 90 91 struct wl18xx_acx_error_stats { 92 u32 error_frame; 93 u32 error_null_Frame_tx_start; 94 u32 error_numll_frame_cts_start; 95 u32 error_bar_retry; 96 u32 error_frame_cts_nul_flid; 97 } __packed; 98 99 struct wl18xx_acx_debug_stats { 100 u32 debug1; 101 u32 debug2; 102 u32 debug3; 103 u32 debug4; 104 u32 debug5; 105 u32 debug6; 106 } __packed; 107 108 struct wl18xx_acx_ring_stats { 109 u32 prepared_descs; 110 u32 tx_cmplt; 111 } __packed; 112 113 struct wl18xx_acx_tx_stats { 114 u32 tx_prepared_descs; 115 u32 tx_cmplt; 116 u32 tx_template_prepared; 117 u32 tx_data_prepared; 118 u32 tx_template_programmed; 119 u32 tx_data_programmed; 120 u32 tx_burst_programmed; 121 u32 tx_starts; 122 u32 tx_imm_resp; 123 u32 tx_start_templates; 124 u32 tx_start_int_templates; 125 u32 tx_start_fw_gen; 126 u32 tx_start_data; 127 u32 tx_start_null_frame; 128 u32 tx_exch; 129 u32 tx_retry_template; 130 u32 tx_retry_data; 131 u32 tx_exch_pending; 132 u32 tx_exch_expiry; 133 u32 tx_done_template; 134 u32 tx_done_data; 135 u32 tx_done_int_template; 136 u32 tx_frame_checksum; 137 u32 tx_checksum_result; 138 u32 frag_called; 139 u32 frag_mpdu_alloc_failed; 140 u32 frag_init_called; 141 u32 frag_in_process_called; 142 u32 frag_tkip_called; 143 u32 frag_key_not_found; 144 u32 frag_need_fragmentation; 145 u32 frag_bad_mblk_num; 146 u32 frag_failed; 147 u32 frag_cache_hit; 148 u32 frag_cache_miss; 149 } __packed; 150 151 struct wl18xx_acx_rx_stats { 152 u32 rx_beacon_early_term; 153 u32 rx_out_of_mpdu_nodes; 154 u32 rx_hdr_overflow; 155 u32 rx_dropped_frame; 156 u32 rx_done_stage; 157 u32 rx_done; 158 u32 rx_defrag; 159 u32 rx_defrag_end; 160 u32 rx_cmplt; 161 u32 rx_pre_complt; 162 u32 rx_cmplt_task; 163 u32 rx_phy_hdr; 164 u32 rx_timeout; 165 u32 rx_timeout_wa; 166 u32 rx_wa_density_dropped_frame; 167 u32 rx_wa_ba_not_expected; 168 u32 rx_frame_checksum; 169 u32 rx_checksum_result; 170 u32 defrag_called; 171 u32 defrag_init_called; 172 u32 defrag_in_process_called; 173 u32 defrag_tkip_called; 174 u32 defrag_need_defrag; 175 u32 defrag_decrypt_failed; 176 u32 decrypt_key_not_found; 177 u32 defrag_need_decrypt; 178 u32 rx_tkip_replays; 179 } __packed; 180 181 struct wl18xx_acx_isr_stats { 182 u32 irqs; 183 } __packed; 184 185 #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10 186 187 struct wl18xx_acx_pwr_stats { 188 u32 missing_bcns_cnt; 189 u32 rcvd_bcns_cnt; 190 u32 connection_out_of_sync; 191 u32 cont_miss_bcns_spread[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD]; 192 u32 rcvd_awake_bcns_cnt; 193 } __packed; 194 195 struct wl18xx_acx_event_stats { 196 u32 calibration; 197 u32 rx_mismatch; 198 u32 rx_mem_empty; 199 } __packed; 200 201 struct wl18xx_acx_ps_poll_stats { 202 u32 ps_poll_timeouts; 203 u32 upsd_timeouts; 204 u32 upsd_max_ap_turn; 205 u32 ps_poll_max_ap_turn; 206 u32 ps_poll_utilization; 207 u32 upsd_utilization; 208 } __packed; 209 210 struct wl18xx_acx_rx_filter_stats { 211 u32 beacon_filter; 212 u32 arp_filter; 213 u32 mc_filter; 214 u32 dup_filter; 215 u32 data_filter; 216 u32 ibss_filter; 217 u32 protection_filter; 218 u32 accum_arp_pend_requests; 219 u32 max_arp_queue_dep; 220 } __packed; 221 222 struct wl18xx_acx_rx_rate_stats { 223 u32 rx_frames_per_rates[50]; 224 } __packed; 225 226 #define AGGR_STATS_TX_AGG 16 227 #define AGGR_STATS_TX_RATE 16 228 #define AGGR_STATS_RX_SIZE_LEN 16 229 230 struct wl18xx_acx_aggr_stats { 231 u32 tx_agg_vs_rate[AGGR_STATS_TX_AGG * AGGR_STATS_TX_RATE]; 232 u32 rx_size[AGGR_STATS_RX_SIZE_LEN]; 233 } __packed; 234 235 #define PIPE_STATS_HW_FIFO 11 236 237 struct wl18xx_acx_pipeline_stats { 238 u32 hs_tx_stat_fifo_int; 239 u32 hs_rx_stat_fifo_int; 240 u32 tcp_tx_stat_fifo_int; 241 u32 tcp_rx_stat_fifo_int; 242 u32 enc_tx_stat_fifo_int; 243 u32 enc_rx_stat_fifo_int; 244 u32 rx_complete_stat_fifo_int; 245 u32 pre_proc_swi; 246 u32 post_proc_swi; 247 u32 sec_frag_swi; 248 u32 pre_to_defrag_swi; 249 u32 defrag_to_csum_swi; 250 u32 csum_to_rx_xfer_swi; 251 u32 dec_packet_in; 252 u32 dec_packet_in_fifo_full; 253 u32 dec_packet_out; 254 u32 cs_rx_packet_in; 255 u32 cs_rx_packet_out; 256 u16 pipeline_fifo_full[PIPE_STATS_HW_FIFO]; 257 } __packed; 258 259 struct wl18xx_acx_mem_stats { 260 u32 rx_free_mem_blks; 261 u32 tx_free_mem_blks; 262 u32 fwlog_free_mem_blks; 263 u32 fw_gen_free_mem_blks; 264 } __packed; 265 266 struct wl18xx_acx_statistics { 267 struct acx_header header; 268 269 struct wl18xx_acx_error_stats error; 270 struct wl18xx_acx_debug_stats debug; 271 struct wl18xx_acx_tx_stats tx; 272 struct wl18xx_acx_rx_stats rx; 273 struct wl18xx_acx_isr_stats isr; 274 struct wl18xx_acx_pwr_stats pwr; 275 struct wl18xx_acx_ps_poll_stats ps_poll; 276 struct wl18xx_acx_rx_filter_stats rx_filter; 277 struct wl18xx_acx_rx_rate_stats rx_rate; 278 struct wl18xx_acx_aggr_stats aggr_size; 279 struct wl18xx_acx_pipeline_stats pipeline; 280 struct wl18xx_acx_mem_stats mem; 281 } __packed; 282 283 struct wl18xx_acx_clear_statistics { 284 struct acx_header header; 285 }; 286 287 enum wlcore_bandwidth { 288 WLCORE_BANDWIDTH_20MHZ, 289 WLCORE_BANDWIDTH_40MHZ, 290 }; 291 292 struct wlcore_peer_ht_operation_mode { 293 struct acx_header header; 294 295 u8 hlid; 296 u8 bandwidth; /* enum wlcore_bandwidth */ 297 u8 padding[2]; 298 }; 299 300 /* 301 * ACX_PEER_CAP 302 * this struct is very similar to wl1271_acx_ht_capabilities, with the 303 * addition of supported rates 304 */ 305 struct wlcore_acx_peer_cap { 306 struct acx_header header; 307 308 /* bitmask of capability bits supported by the peer */ 309 __le32 ht_capabilites; 310 311 /* rates supported by the remote peer */ 312 __le32 supported_rates; 313 314 /* Indicates to which link these capabilities apply. */ 315 u8 hlid; 316 317 /* 318 * This the maximum A-MPDU length supported by the AP. The FW may not 319 * exceed this length when sending A-MPDUs 320 */ 321 u8 ampdu_max_length; 322 323 /* This is the minimal spacing required when sending A-MPDUs to the AP*/ 324 u8 ampdu_min_spacing; 325 326 u8 padding; 327 } __packed; 328 329 int wl18xx_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap, 330 u32 sdio_blk_size, u32 extra_mem_blks, 331 u32 len_field_size); 332 int wl18xx_acx_set_checksum_state(struct wl1271 *wl); 333 int wl18xx_acx_clear_statistics(struct wl1271 *wl); 334 int wl18xx_acx_peer_ht_operation_mode(struct wl1271 *wl, u8 hlid, bool wide); 335 int wl18xx_acx_set_peer_cap(struct wl1271 *wl, 336 struct ieee80211_sta_ht_cap *ht_cap, 337 bool allow_ht_operation, 338 u32 rate_set, u8 hlid); 339 340 #endif /* __WL18XX_ACX_H__ */ 341