1 /* 2 * This file is part of wl1251 3 * 4 * Copyright (c) 1998-2007 Texas Instruments Incorporated 5 * Copyright (C) 2008 Nokia Corporation 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 19 * 02110-1301 USA 20 * 21 */ 22 23 #ifndef __WL1251_ACX_H__ 24 #define __WL1251_ACX_H__ 25 26 #include "wl1251.h" 27 #include "cmd.h" 28 29 /* Target's information element */ 30 struct acx_header { 31 struct wl1251_cmd_header cmd; 32 33 /* acx (or information element) header */ 34 u16 id; 35 36 /* payload length (not including headers */ 37 u16 len; 38 } __packed; 39 40 struct acx_error_counter { 41 struct acx_header header; 42 43 /* The number of PLCP errors since the last time this */ 44 /* information element was interrogated. This field is */ 45 /* automatically cleared when it is interrogated.*/ 46 u32 PLCP_error; 47 48 /* The number of FCS errors since the last time this */ 49 /* information element was interrogated. This field is */ 50 /* automatically cleared when it is interrogated.*/ 51 u32 FCS_error; 52 53 /* The number of MPDUs without PLCP header errors received*/ 54 /* since the last time this information element was interrogated. */ 55 /* This field is automatically cleared when it is interrogated.*/ 56 u32 valid_frame; 57 58 /* the number of missed sequence numbers in the squentially */ 59 /* values of frames seq numbers */ 60 u32 seq_num_miss; 61 } __packed; 62 63 struct acx_revision { 64 struct acx_header header; 65 66 /* 67 * The WiLink firmware version, an ASCII string x.x.x.x, 68 * that uniquely identifies the current firmware. 69 * The left most digit is incremented each time a 70 * significant change is made to the firmware, such as 71 * code redesign or new platform support. 72 * The second digit is incremented when major enhancements 73 * are added or major fixes are made. 74 * The third digit is incremented for each GA release. 75 * The fourth digit is incremented for each build. 76 * The first two digits identify a firmware release version, 77 * in other words, a unique set of features. 78 * The first three digits identify a GA release. 79 */ 80 char fw_version[20]; 81 82 /* 83 * This 4 byte field specifies the WiLink hardware version. 84 * bits 0 - 15: Reserved. 85 * bits 16 - 23: Version ID - The WiLink version ID 86 * (1 = first spin, 2 = second spin, and so on). 87 * bits 24 - 31: Chip ID - The WiLink chip ID. 88 */ 89 u32 hw_version; 90 } __packed; 91 92 enum wl1251_psm_mode { 93 /* Active mode */ 94 WL1251_PSM_CAM = 0, 95 96 /* Power save mode */ 97 WL1251_PSM_PS = 1, 98 99 /* Extreme low power */ 100 WL1251_PSM_ELP = 2, 101 }; 102 103 struct acx_sleep_auth { 104 struct acx_header header; 105 106 /* The sleep level authorization of the device. */ 107 /* 0 - Always active*/ 108 /* 1 - Power down mode: light / fast sleep*/ 109 /* 2 - ELP mode: Deep / Max sleep*/ 110 u8 sleep_auth; 111 u8 padding[3]; 112 } __packed; 113 114 enum { 115 HOSTIF_PCI_MASTER_HOST_INDIRECT, 116 HOSTIF_PCI_MASTER_HOST_DIRECT, 117 HOSTIF_SLAVE, 118 HOSTIF_PKT_RING, 119 HOSTIF_DONTCARE = 0xFF 120 }; 121 122 #define DEFAULT_UCAST_PRIORITY 0 123 #define DEFAULT_RX_Q_PRIORITY 0 124 #define DEFAULT_NUM_STATIONS 1 125 #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */ 126 #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */ 127 #define TRACE_BUFFER_MAX_SIZE 256 128 129 #define DP_RX_PACKET_RING_CHUNK_SIZE 1600 130 #define DP_TX_PACKET_RING_CHUNK_SIZE 1600 131 #define DP_RX_PACKET_RING_CHUNK_NUM 2 132 #define DP_TX_PACKET_RING_CHUNK_NUM 2 133 #define DP_TX_COMPLETE_TIME_OUT 20 134 #define FW_TX_CMPLT_BLOCK_SIZE 16 135 136 struct acx_data_path_params { 137 struct acx_header header; 138 139 u16 rx_packet_ring_chunk_size; 140 u16 tx_packet_ring_chunk_size; 141 142 u8 rx_packet_ring_chunk_num; 143 u8 tx_packet_ring_chunk_num; 144 145 /* 146 * Maximum number of packets that can be gathered 147 * in the TX complete ring before an interrupt 148 * is generated. 149 */ 150 u8 tx_complete_threshold; 151 152 /* Number of pending TX complete entries in cyclic ring.*/ 153 u8 tx_complete_ring_depth; 154 155 /* 156 * Max num microseconds since a packet enters the TX 157 * complete ring until an interrupt is generated. 158 */ 159 u32 tx_complete_timeout; 160 } __packed; 161 162 163 struct acx_data_path_params_resp { 164 struct acx_header header; 165 166 u16 rx_packet_ring_chunk_size; 167 u16 tx_packet_ring_chunk_size; 168 169 u8 rx_packet_ring_chunk_num; 170 u8 tx_packet_ring_chunk_num; 171 172 u8 pad[2]; 173 174 u32 rx_packet_ring_addr; 175 u32 tx_packet_ring_addr; 176 177 u32 rx_control_addr; 178 u32 tx_control_addr; 179 180 u32 tx_complete_addr; 181 } __packed; 182 183 #define TX_MSDU_LIFETIME_MIN 0 184 #define TX_MSDU_LIFETIME_MAX 3000 185 #define TX_MSDU_LIFETIME_DEF 512 186 #define RX_MSDU_LIFETIME_MIN 0 187 #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF 188 #define RX_MSDU_LIFETIME_DEF 512000 189 190 struct acx_rx_msdu_lifetime { 191 struct acx_header header; 192 193 /* 194 * The maximum amount of time, in TU, before the 195 * firmware discards the MSDU. 196 */ 197 u32 lifetime; 198 } __packed; 199 200 /* 201 * RX Config Options Table 202 * Bit Definition 203 * === ========== 204 * 31:14 Reserved 205 * 13 Copy RX Status - when set, write three receive status words 206 * to top of rx'd MPDUs. 207 * When cleared, do not write three status words (added rev 1.5) 208 * 12 Reserved 209 * 11 RX Complete upon FCS error - when set, give rx complete 210 * interrupt for FCS errors, after the rx filtering, e.g. unicast 211 * frames not to us with FCS error will not generate an interrupt. 212 * 10 SSID Filter Enable - When set, the WiLink discards all beacon, 213 * probe request, and probe response frames with an SSID that does 214 * not match the SSID specified by the host in the START/JOIN 215 * command. 216 * When clear, the WiLink receives frames with any SSID. 217 * 9 Broadcast Filter Enable - When set, the WiLink discards all 218 * broadcast frames. When clear, the WiLink receives all received 219 * broadcast frames. 220 * 8:6 Reserved 221 * 5 BSSID Filter Enable - When set, the WiLink discards any frames 222 * with a BSSID that does not match the BSSID specified by the 223 * host. 224 * When clear, the WiLink receives frames from any BSSID. 225 * 4 MAC Addr Filter - When set, the WiLink discards any frames 226 * with a destination address that does not match the MAC address 227 * of the adaptor. 228 * When clear, the WiLink receives frames destined to any MAC 229 * address. 230 * 3 Promiscuous - When set, the WiLink receives all valid frames 231 * (i.e., all frames that pass the FCS check). 232 * When clear, only frames that pass the other filters specified 233 * are received. 234 * 2 FCS - When set, the WiLink includes the FCS with the received 235 * frame. 236 * When cleared, the FCS is discarded. 237 * 1 PLCP header - When set, write all data from baseband to frame 238 * buffer including PHY header. 239 * 0 Reserved - Always equal to 0. 240 * 241 * RX Filter Options Table 242 * Bit Definition 243 * === ========== 244 * 31:12 Reserved - Always equal to 0. 245 * 11 Association - When set, the WiLink receives all association 246 * related frames (association request/response, reassocation 247 * request/response, and disassociation). When clear, these frames 248 * are discarded. 249 * 10 Auth/De auth - When set, the WiLink receives all authentication 250 * and de-authentication frames. When clear, these frames are 251 * discarded. 252 * 9 Beacon - When set, the WiLink receives all beacon frames. 253 * When clear, these frames are discarded. 254 * 8 Contention Free - When set, the WiLink receives all contention 255 * free frames. 256 * When clear, these frames are discarded. 257 * 7 Control - When set, the WiLink receives all control frames. 258 * When clear, these frames are discarded. 259 * 6 Data - When set, the WiLink receives all data frames. 260 * When clear, these frames are discarded. 261 * 5 FCS Error - When set, the WiLink receives frames that have FCS 262 * errors. 263 * When clear, these frames are discarded. 264 * 4 Management - When set, the WiLink receives all management 265 * frames. 266 * When clear, these frames are discarded. 267 * 3 Probe Request - When set, the WiLink receives all probe request 268 * frames. 269 * When clear, these frames are discarded. 270 * 2 Probe Response - When set, the WiLink receives all probe 271 * response frames. 272 * When clear, these frames are discarded. 273 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK 274 * frames. 275 * When clear, these frames are discarded. 276 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames 277 * that have reserved frame types and sub types as defined by the 278 * 802.11 specification. 279 * When clear, these frames are discarded. 280 */ 281 struct acx_rx_config { 282 struct acx_header header; 283 284 u32 config_options; 285 u32 filter_options; 286 } __packed; 287 288 enum { 289 QOS_AC_BE = 0, 290 QOS_AC_BK, 291 QOS_AC_VI, 292 QOS_AC_VO, 293 QOS_HIGHEST_AC_INDEX = QOS_AC_VO, 294 }; 295 296 #define MAX_NUM_OF_AC (QOS_HIGHEST_AC_INDEX+1) 297 #define FIRST_AC_INDEX QOS_AC_BE 298 #define MAX_NUM_OF_802_1d_TAGS 8 299 #define AC_PARAMS_MAX_TSID 15 300 #define MAX_APSD_CONF 0xffff 301 302 #define QOS_TX_HIGH_MIN (0) 303 #define QOS_TX_HIGH_MAX (100) 304 305 #define QOS_TX_HIGH_BK_DEF (25) 306 #define QOS_TX_HIGH_BE_DEF (35) 307 #define QOS_TX_HIGH_VI_DEF (35) 308 #define QOS_TX_HIGH_VO_DEF (35) 309 310 #define QOS_TX_LOW_BK_DEF (15) 311 #define QOS_TX_LOW_BE_DEF (25) 312 #define QOS_TX_LOW_VI_DEF (25) 313 #define QOS_TX_LOW_VO_DEF (25) 314 315 struct acx_tx_queue_qos_config { 316 struct acx_header header; 317 318 u8 qid; 319 u8 pad[3]; 320 321 /* Max number of blocks allowd in the queue */ 322 u16 high_threshold; 323 324 /* Lowest memory blocks guaranteed for this queue */ 325 u16 low_threshold; 326 } __packed; 327 328 struct acx_packet_detection { 329 struct acx_header header; 330 331 u32 threshold; 332 } __packed; 333 334 335 enum acx_slot_type { 336 SLOT_TIME_LONG = 0, 337 SLOT_TIME_SHORT = 1, 338 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT, 339 MAX_SLOT_TIMES = 0xFF 340 }; 341 342 #define STATION_WONE_INDEX 0 343 344 struct acx_slot { 345 struct acx_header header; 346 347 u8 wone_index; /* Reserved */ 348 u8 slot_time; 349 u8 reserved[6]; 350 } __packed; 351 352 353 #define ADDRESS_GROUP_MAX (8) 354 #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ADDRESS_GROUP_MAX) 355 356 struct acx_dot11_grp_addr_tbl { 357 struct acx_header header; 358 359 u8 enabled; 360 u8 num_groups; 361 u8 pad[2]; 362 u8 mac_table[ADDRESS_GROUP_MAX_LEN]; 363 } __packed; 364 365 366 #define RX_TIMEOUT_PS_POLL_MIN 0 367 #define RX_TIMEOUT_PS_POLL_MAX (200000) 368 #define RX_TIMEOUT_PS_POLL_DEF (15) 369 #define RX_TIMEOUT_UPSD_MIN 0 370 #define RX_TIMEOUT_UPSD_MAX (200000) 371 #define RX_TIMEOUT_UPSD_DEF (15) 372 373 struct acx_rx_timeout { 374 struct acx_header header; 375 376 /* 377 * The longest time the STA will wait to receive 378 * traffic from the AP after a PS-poll has been 379 * transmitted. 380 */ 381 u16 ps_poll_timeout; 382 383 /* 384 * The longest time the STA will wait to receive 385 * traffic from the AP after a frame has been sent 386 * from an UPSD enabled queue. 387 */ 388 u16 upsd_timeout; 389 } __packed; 390 391 #define RTS_THRESHOLD_MIN 0 392 #define RTS_THRESHOLD_MAX 4096 393 #define RTS_THRESHOLD_DEF 2347 394 395 struct acx_rts_threshold { 396 struct acx_header header; 397 398 u16 threshold; 399 u8 pad[2]; 400 } __packed; 401 402 enum wl1251_acx_low_rssi_type { 403 /* 404 * The event is a "Level" indication which keeps triggering 405 * as long as the average RSSI is below the threshold. 406 */ 407 WL1251_ACX_LOW_RSSI_TYPE_LEVEL = 0, 408 409 /* 410 * The event is an "Edge" indication which triggers 411 * only when the RSSI threshold is crossed from above. 412 */ 413 WL1251_ACX_LOW_RSSI_TYPE_EDGE = 1, 414 }; 415 416 struct acx_low_rssi { 417 struct acx_header header; 418 419 /* 420 * The threshold (in dBm) below (or above after low rssi 421 * indication) which the firmware generates an interrupt to the 422 * host. This parameter is signed. 423 */ 424 s8 threshold; 425 426 /* 427 * The weight of the current RSSI sample, before adding the new 428 * sample, that is used to calculate the average RSSI. 429 */ 430 u8 weight; 431 432 /* 433 * The number of Beacons/Probe response frames that will be 434 * received before issuing the Low or Regained RSSI event. 435 */ 436 u8 depth; 437 438 /* 439 * Configures how the Low RSSI Event is triggered. Refer to 440 * enum wl1251_acx_low_rssi_type for more. 441 */ 442 u8 type; 443 } __packed; 444 445 struct acx_beacon_filter_option { 446 struct acx_header header; 447 448 u8 enable; 449 450 /* 451 * The number of beacons without the unicast TIM 452 * bit set that the firmware buffers before 453 * signaling the host about ready frames. 454 * When set to 0 and the filter is enabled, beacons 455 * without the unicast TIM bit set are dropped. 456 */ 457 u8 max_num_beacons; 458 u8 pad[2]; 459 } __packed; 460 461 /* 462 * ACXBeaconFilterEntry (not 221) 463 * Byte Offset Size (Bytes) Definition 464 * =========== ============ ========== 465 * 0 1 IE identifier 466 * 1 1 Treatment bit mask 467 * 468 * ACXBeaconFilterEntry (221) 469 * Byte Offset Size (Bytes) Definition 470 * =========== ============ ========== 471 * 0 1 IE identifier 472 * 1 1 Treatment bit mask 473 * 2 3 OUI 474 * 5 1 Type 475 * 6 2 Version 476 * 477 * 478 * Treatment bit mask - The information element handling: 479 * bit 0 - The information element is compared and transferred 480 * in case of change. 481 * bit 1 - The information element is transferred to the host 482 * with each appearance or disappearance. 483 * Note that both bits can be set at the same time. 484 */ 485 #define BEACON_FILTER_TABLE_MAX_IE_NUM (32) 486 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6) 487 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2) 488 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6) 489 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \ 490 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \ 491 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \ 492 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE)) 493 494 #define BEACON_RULE_PASS_ON_CHANGE BIT(0) 495 #define BEACON_RULE_PASS_ON_APPEARANCE BIT(1) 496 497 #define BEACON_FILTER_IE_ID_CHANNEL_SWITCH_ANN (37) 498 499 struct acx_beacon_filter_ie_table { 500 struct acx_header header; 501 502 u8 num_ie; 503 u8 pad[3]; 504 u8 table[BEACON_FILTER_TABLE_MAX_SIZE]; 505 } __packed; 506 507 #define SYNCH_FAIL_DEFAULT_THRESHOLD 10 /* number of beacons */ 508 #define NO_BEACON_DEFAULT_TIMEOUT (500) /* in microseconds */ 509 510 struct acx_conn_monit_params { 511 struct acx_header header; 512 513 u32 synch_fail_thold; /* number of beacons missed */ 514 u32 bss_lose_timeout; /* number of TU's from synch fail */ 515 } __packed; 516 517 enum { 518 SG_ENABLE = 0, 519 SG_DISABLE, 520 SG_SENSE_NO_ACTIVITY, 521 SG_SENSE_ACTIVE 522 }; 523 524 struct acx_bt_wlan_coex { 525 struct acx_header header; 526 527 /* 528 * 0 -> PTA enabled 529 * 1 -> PTA disabled 530 * 2 -> sense no active mode, i.e. 531 * an interrupt is sent upon 532 * BT activity. 533 * 3 -> PTA is switched on in response 534 * to the interrupt sending. 535 */ 536 u8 enable; 537 u8 pad[3]; 538 } __packed; 539 540 #define PTA_ANTENNA_TYPE_DEF (0) 541 #define PTA_BT_HP_MAXTIME_DEF (2000) 542 #define PTA_WLAN_HP_MAX_TIME_DEF (5000) 543 #define PTA_SENSE_DISABLE_TIMER_DEF (1350) 544 #define PTA_PROTECTIVE_RX_TIME_DEF (1500) 545 #define PTA_PROTECTIVE_TX_TIME_DEF (1500) 546 #define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000) 547 #define PTA_SIGNALING_TYPE_DEF (1) 548 #define PTA_AFH_LEVERAGE_ON_DEF (0) 549 #define PTA_NUMBER_QUIET_CYCLE_DEF (0) 550 #define PTA_MAX_NUM_CTS_DEF (3) 551 #define PTA_NUMBER_OF_WLAN_PACKETS_DEF (2) 552 #define PTA_NUMBER_OF_BT_PACKETS_DEF (2) 553 #define PTA_PROTECTIVE_RX_TIME_FAST_DEF (1500) 554 #define PTA_PROTECTIVE_TX_TIME_FAST_DEF (3000) 555 #define PTA_CYCLE_TIME_FAST_DEF (8700) 556 #define PTA_RX_FOR_AVALANCHE_DEF (5) 557 #define PTA_ELP_HP_DEF (0) 558 #define PTA_ANTI_STARVE_PERIOD_DEF (500) 559 #define PTA_ANTI_STARVE_NUM_CYCLE_DEF (4) 560 #define PTA_ALLOW_PA_SD_DEF (1) 561 #define PTA_TIME_BEFORE_BEACON_DEF (6300) 562 #define PTA_HPDM_MAX_TIME_DEF (1600) 563 #define PTA_TIME_OUT_NEXT_WLAN_DEF (2550) 564 #define PTA_AUTO_MODE_NO_CTS_DEF (0) 565 #define PTA_BT_HP_RESPECTED_DEF (3) 566 #define PTA_WLAN_RX_MIN_RATE_DEF (24) 567 #define PTA_ACK_MODE_DEF (1) 568 569 struct acx_bt_wlan_coex_param { 570 struct acx_header header; 571 572 /* 573 * The minimum rate of a received WLAN packet in the STA, 574 * during protective mode, of which a new BT-HP request 575 * during this Rx will always be respected and gain the antenna. 576 */ 577 u32 min_rate; 578 579 /* Max time the BT HP will be respected. */ 580 u16 bt_hp_max_time; 581 582 /* Max time the WLAN HP will be respected. */ 583 u16 wlan_hp_max_time; 584 585 /* 586 * The time between the last BT activity 587 * and the moment when the sense mode returns 588 * to SENSE_INACTIVE. 589 */ 590 u16 sense_disable_timer; 591 592 /* Time before the next BT HP instance */ 593 u16 rx_time_bt_hp; 594 u16 tx_time_bt_hp; 595 596 /* range: 10-20000 default: 1500 */ 597 u16 rx_time_bt_hp_fast; 598 u16 tx_time_bt_hp_fast; 599 600 /* range: 2000-65535 default: 8700 */ 601 u16 wlan_cycle_fast; 602 603 /* range: 0 - 15000 (Msec) default: 1000 */ 604 u16 bt_anti_starvation_period; 605 606 /* range 400-10000(Usec) default: 3000 */ 607 u16 next_bt_lp_packet; 608 609 /* Deafult: worst case for BT DH5 traffic */ 610 u16 wake_up_beacon; 611 612 /* range: 0-50000(Usec) default: 1050 */ 613 u16 hp_dm_max_guard_time; 614 615 /* 616 * This is to prevent both BT & WLAN antenna 617 * starvation. 618 * Range: 100-50000(Usec) default:2550 619 */ 620 u16 next_wlan_packet; 621 622 /* 0 -> shared antenna */ 623 u8 antenna_type; 624 625 /* 626 * 0 -> TI legacy 627 * 1 -> Palau 628 */ 629 u8 signal_type; 630 631 /* 632 * BT AFH status 633 * 0 -> no AFH 634 * 1 -> from dedicated GPIO 635 * 2 -> AFH on (from host) 636 */ 637 u8 afh_leverage_on; 638 639 /* 640 * The number of cycles during which no 641 * TX will be sent after 1 cycle of RX 642 * transaction in protective mode 643 */ 644 u8 quiet_cycle_num; 645 646 /* 647 * The maximum number of CTSs that will 648 * be sent for receiving RX packet in 649 * protective mode 650 */ 651 u8 max_cts; 652 653 /* 654 * The number of WLAN packets 655 * transferred in common mode before 656 * switching to BT. 657 */ 658 u8 wlan_packets_num; 659 660 /* 661 * The number of BT packets 662 * transferred in common mode before 663 * switching to WLAN. 664 */ 665 u8 bt_packets_num; 666 667 /* range: 1-255 default: 5 */ 668 u8 missed_rx_avalanche; 669 670 /* range: 0-1 default: 1 */ 671 u8 wlan_elp_hp; 672 673 /* range: 0 - 15 default: 4 */ 674 u8 bt_anti_starvation_cycles; 675 676 u8 ack_mode_dual_ant; 677 678 /* 679 * Allow PA_SD assertion/de-assertion 680 * during enabled BT activity. 681 */ 682 u8 pa_sd_enable; 683 684 /* 685 * Enable/Disable PTA in auto mode: 686 * Support Both Active & P.S modes 687 */ 688 u8 pta_auto_mode_enable; 689 690 /* range: 0 - 20 default: 1 */ 691 u8 bt_hp_respected_num; 692 } __packed; 693 694 #define CCA_THRSH_ENABLE_ENERGY_D 0x140A 695 #define CCA_THRSH_DISABLE_ENERGY_D 0xFFEF 696 697 struct acx_energy_detection { 698 struct acx_header header; 699 700 /* The RX Clear Channel Assessment threshold in the PHY */ 701 u16 rx_cca_threshold; 702 u8 tx_energy_detection; 703 u8 pad; 704 } __packed; 705 706 #define BCN_RX_TIMEOUT_DEF_VALUE 10000 707 #define BROADCAST_RX_TIMEOUT_DEF_VALUE 20000 708 #define RX_BROADCAST_IN_PS_DEF_VALUE 1 709 #define CONSECUTIVE_PS_POLL_FAILURE_DEF 4 710 711 struct acx_beacon_broadcast { 712 struct acx_header header; 713 714 u16 beacon_rx_timeout; 715 u16 broadcast_timeout; 716 717 /* Enables receiving of broadcast packets in PS mode */ 718 u8 rx_broadcast_in_ps; 719 720 /* Consecutive PS Poll failures before updating the host */ 721 u8 ps_poll_threshold; 722 u8 pad[2]; 723 } __packed; 724 725 struct acx_event_mask { 726 struct acx_header header; 727 728 u32 event_mask; 729 u32 high_event_mask; /* Unused */ 730 } __packed; 731 732 #define CFG_RX_FCS BIT(2) 733 #define CFG_RX_ALL_GOOD BIT(3) 734 #define CFG_UNI_FILTER_EN BIT(4) 735 #define CFG_BSSID_FILTER_EN BIT(5) 736 #define CFG_MC_FILTER_EN BIT(6) 737 #define CFG_MC_ADDR0_EN BIT(7) 738 #define CFG_MC_ADDR1_EN BIT(8) 739 #define CFG_BC_REJECT_EN BIT(9) 740 #define CFG_SSID_FILTER_EN BIT(10) 741 #define CFG_RX_INT_FCS_ERROR BIT(11) 742 #define CFG_RX_INT_ENCRYPTED BIT(12) 743 #define CFG_RX_WR_RX_STATUS BIT(13) 744 #define CFG_RX_FILTER_NULTI BIT(14) 745 #define CFG_RX_RESERVE BIT(15) 746 #define CFG_RX_TIMESTAMP_TSF BIT(16) 747 748 #define CFG_RX_RSV_EN BIT(0) 749 #define CFG_RX_RCTS_ACK BIT(1) 750 #define CFG_RX_PRSP_EN BIT(2) 751 #define CFG_RX_PREQ_EN BIT(3) 752 #define CFG_RX_MGMT_EN BIT(4) 753 #define CFG_RX_FCS_ERROR BIT(5) 754 #define CFG_RX_DATA_EN BIT(6) 755 #define CFG_RX_CTL_EN BIT(7) 756 #define CFG_RX_CF_EN BIT(8) 757 #define CFG_RX_BCN_EN BIT(9) 758 #define CFG_RX_AUTH_EN BIT(10) 759 #define CFG_RX_ASSOC_EN BIT(11) 760 761 #define SCAN_PASSIVE BIT(0) 762 #define SCAN_5GHZ_BAND BIT(1) 763 #define SCAN_TRIGGERED BIT(2) 764 #define SCAN_PRIORITY_HIGH BIT(3) 765 766 struct acx_fw_gen_frame_rates { 767 struct acx_header header; 768 769 u8 tx_ctrl_frame_rate; /* RATE_* */ 770 u8 tx_ctrl_frame_mod; /* CCK_* or PBCC_* */ 771 u8 tx_mgt_frame_rate; 772 u8 tx_mgt_frame_mod; 773 } __packed; 774 775 /* STA MAC */ 776 struct acx_dot11_station_id { 777 struct acx_header header; 778 779 u8 mac[ETH_ALEN]; 780 u8 pad[2]; 781 } __packed; 782 783 struct acx_feature_config { 784 struct acx_header header; 785 786 u32 options; 787 u32 data_flow_options; 788 } __packed; 789 790 struct acx_current_tx_power { 791 struct acx_header header; 792 793 u8 current_tx_power; 794 u8 padding[3]; 795 } __packed; 796 797 struct acx_dot11_default_key { 798 struct acx_header header; 799 800 u8 id; 801 u8 pad[3]; 802 } __packed; 803 804 struct acx_tsf_info { 805 struct acx_header header; 806 807 u32 current_tsf_msb; 808 u32 current_tsf_lsb; 809 u32 last_TBTT_msb; 810 u32 last_TBTT_lsb; 811 u8 last_dtim_count; 812 u8 pad[3]; 813 } __packed; 814 815 enum acx_wake_up_event { 816 WAKE_UP_EVENT_BEACON_BITMAP = 0x01, /* Wake on every Beacon*/ 817 WAKE_UP_EVENT_DTIM_BITMAP = 0x02, /* Wake on every DTIM*/ 818 WAKE_UP_EVENT_N_DTIM_BITMAP = 0x04, /* Wake on every Nth DTIM */ 819 WAKE_UP_EVENT_N_BEACONS_BITMAP = 0x08, /* Wake on every Nth Beacon */ 820 WAKE_UP_EVENT_BITS_MASK = 0x0F 821 }; 822 823 struct acx_wake_up_condition { 824 struct acx_header header; 825 826 u8 wake_up_event; /* Only one bit can be set */ 827 u8 listen_interval; 828 u8 pad[2]; 829 } __packed; 830 831 struct acx_aid { 832 struct acx_header header; 833 834 /* 835 * To be set when associated with an AP. 836 */ 837 u16 aid; 838 u8 pad[2]; 839 } __packed; 840 841 enum acx_preamble_type { 842 ACX_PREAMBLE_LONG = 0, 843 ACX_PREAMBLE_SHORT = 1 844 }; 845 846 struct acx_preamble { 847 struct acx_header header; 848 849 /* 850 * When set, the WiLink transmits the frames with a short preamble and 851 * when cleared, the WiLink transmits the frames with a long preamble. 852 */ 853 u8 preamble; 854 u8 padding[3]; 855 } __packed; 856 857 enum acx_ctsprotect_type { 858 CTSPROTECT_DISABLE = 0, 859 CTSPROTECT_ENABLE = 1 860 }; 861 862 struct acx_ctsprotect { 863 struct acx_header header; 864 u8 ctsprotect; 865 u8 padding[3]; 866 } __packed; 867 868 struct acx_tx_statistics { 869 u32 internal_desc_overflow; 870 } __packed; 871 872 struct acx_rx_statistics { 873 u32 out_of_mem; 874 u32 hdr_overflow; 875 u32 hw_stuck; 876 u32 dropped; 877 u32 fcs_err; 878 u32 xfr_hint_trig; 879 u32 path_reset; 880 u32 reset_counter; 881 } __packed; 882 883 struct acx_dma_statistics { 884 u32 rx_requested; 885 u32 rx_errors; 886 u32 tx_requested; 887 u32 tx_errors; 888 } __packed; 889 890 struct acx_isr_statistics { 891 /* host command complete */ 892 u32 cmd_cmplt; 893 894 /* fiqisr() */ 895 u32 fiqs; 896 897 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */ 898 u32 rx_headers; 899 900 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */ 901 u32 rx_completes; 902 903 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */ 904 u32 rx_mem_overflow; 905 906 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */ 907 u32 rx_rdys; 908 909 /* irqisr() */ 910 u32 irqs; 911 912 /* (INT_STS_ND & INT_TRIG_TX_PROC) */ 913 u32 tx_procs; 914 915 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */ 916 u32 decrypt_done; 917 918 /* (INT_STS_ND & INT_TRIG_DMA0) */ 919 u32 dma0_done; 920 921 /* (INT_STS_ND & INT_TRIG_DMA1) */ 922 u32 dma1_done; 923 924 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */ 925 u32 tx_exch_complete; 926 927 /* (INT_STS_ND & INT_TRIG_COMMAND) */ 928 u32 commands; 929 930 /* (INT_STS_ND & INT_TRIG_RX_PROC) */ 931 u32 rx_procs; 932 933 /* (INT_STS_ND & INT_TRIG_PM_802) */ 934 u32 hw_pm_mode_changes; 935 936 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */ 937 u32 host_acknowledges; 938 939 /* (INT_STS_ND & INT_TRIG_PM_PCI) */ 940 u32 pci_pm; 941 942 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */ 943 u32 wakeups; 944 945 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */ 946 u32 low_rssi; 947 } __packed; 948 949 struct acx_wep_statistics { 950 /* WEP address keys configured */ 951 u32 addr_key_count; 952 953 /* default keys configured */ 954 u32 default_key_count; 955 956 u32 reserved; 957 958 /* number of times that WEP key not found on lookup */ 959 u32 key_not_found; 960 961 /* number of times that WEP key decryption failed */ 962 u32 decrypt_fail; 963 964 /* WEP packets decrypted */ 965 u32 packets; 966 967 /* WEP decrypt interrupts */ 968 u32 interrupt; 969 } __packed; 970 971 #define ACX_MISSED_BEACONS_SPREAD 10 972 973 struct acx_pwr_statistics { 974 /* the amount of enters into power save mode (both PD & ELP) */ 975 u32 ps_enter; 976 977 /* the amount of enters into ELP mode */ 978 u32 elp_enter; 979 980 /* the amount of missing beacon interrupts to the host */ 981 u32 missing_bcns; 982 983 /* the amount of wake on host-access times */ 984 u32 wake_on_host; 985 986 /* the amount of wake on timer-expire */ 987 u32 wake_on_timer_exp; 988 989 /* the number of packets that were transmitted with PS bit set */ 990 u32 tx_with_ps; 991 992 /* the number of packets that were transmitted with PS bit clear */ 993 u32 tx_without_ps; 994 995 /* the number of received beacons */ 996 u32 rcvd_beacons; 997 998 /* the number of entering into PowerOn (power save off) */ 999 u32 power_save_off; 1000 1001 /* the number of entries into power save mode */ 1002 u16 enable_ps; 1003 1004 /* 1005 * the number of exits from power save, not including failed PS 1006 * transitions 1007 */ 1008 u16 disable_ps; 1009 1010 /* 1011 * the number of times the TSF counter was adjusted because 1012 * of drift 1013 */ 1014 u32 fix_tsf_ps; 1015 1016 /* Gives statistics about the spread continuous missed beacons. 1017 * The 16 LSB are dedicated for the PS mode. 1018 * The 16 MSB are dedicated for the PS mode. 1019 * cont_miss_bcns_spread[0] - single missed beacon. 1020 * cont_miss_bcns_spread[1] - two continuous missed beacons. 1021 * cont_miss_bcns_spread[2] - three continuous missed beacons. 1022 * ... 1023 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons. 1024 */ 1025 u32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD]; 1026 1027 /* the number of beacons in awake mode */ 1028 u32 rcvd_awake_beacons; 1029 } __packed; 1030 1031 struct acx_mic_statistics { 1032 u32 rx_pkts; 1033 u32 calc_failure; 1034 } __packed; 1035 1036 struct acx_aes_statistics { 1037 u32 encrypt_fail; 1038 u32 decrypt_fail; 1039 u32 encrypt_packets; 1040 u32 decrypt_packets; 1041 u32 encrypt_interrupt; 1042 u32 decrypt_interrupt; 1043 } __packed; 1044 1045 struct acx_event_statistics { 1046 u32 heart_beat; 1047 u32 calibration; 1048 u32 rx_mismatch; 1049 u32 rx_mem_empty; 1050 u32 rx_pool; 1051 u32 oom_late; 1052 u32 phy_transmit_error; 1053 u32 tx_stuck; 1054 } __packed; 1055 1056 struct acx_ps_statistics { 1057 u32 pspoll_timeouts; 1058 u32 upsd_timeouts; 1059 u32 upsd_max_sptime; 1060 u32 upsd_max_apturn; 1061 u32 pspoll_max_apturn; 1062 u32 pspoll_utilization; 1063 u32 upsd_utilization; 1064 } __packed; 1065 1066 struct acx_rxpipe_statistics { 1067 u32 rx_prep_beacon_drop; 1068 u32 descr_host_int_trig_rx_data; 1069 u32 beacon_buffer_thres_host_int_trig_rx_data; 1070 u32 missed_beacon_host_int_trig_rx_data; 1071 u32 tx_xfr_host_int_trig_rx_data; 1072 } __packed; 1073 1074 struct acx_statistics { 1075 struct acx_header header; 1076 1077 struct acx_tx_statistics tx; 1078 struct acx_rx_statistics rx; 1079 struct acx_dma_statistics dma; 1080 struct acx_isr_statistics isr; 1081 struct acx_wep_statistics wep; 1082 struct acx_pwr_statistics pwr; 1083 struct acx_aes_statistics aes; 1084 struct acx_mic_statistics mic; 1085 struct acx_event_statistics event; 1086 struct acx_ps_statistics ps; 1087 struct acx_rxpipe_statistics rxpipe; 1088 } __packed; 1089 1090 #define ACX_MAX_RATE_CLASSES 8 1091 #define ACX_RATE_MASK_UNSPECIFIED 0 1092 #define ACX_RATE_RETRY_LIMIT 10 1093 1094 struct acx_rate_class { 1095 u32 enabled_rates; 1096 u8 short_retry_limit; 1097 u8 long_retry_limit; 1098 u8 aflags; 1099 u8 reserved; 1100 } __packed; 1101 1102 struct acx_rate_policy { 1103 struct acx_header header; 1104 1105 u32 rate_class_cnt; 1106 struct acx_rate_class rate_class[ACX_MAX_RATE_CLASSES]; 1107 } __packed; 1108 1109 struct wl1251_acx_memory { 1110 __le16 num_stations; /* number of STAs to be supported. */ 1111 u16 reserved_1; 1112 1113 /* 1114 * Nmber of memory buffers for the RX mem pool. 1115 * The actual number may be less if there are 1116 * not enough blocks left for the minimum num 1117 * of TX ones. 1118 */ 1119 u8 rx_mem_block_num; 1120 u8 reserved_2; 1121 u8 num_tx_queues; /* From 1 to 16 */ 1122 u8 host_if_options; /* HOST_IF* */ 1123 u8 tx_min_mem_block_num; 1124 u8 num_ssid_profiles; 1125 __le16 debug_buffer_size; 1126 } __packed; 1127 1128 1129 #define ACX_RX_DESC_MIN 1 1130 #define ACX_RX_DESC_MAX 127 1131 #define ACX_RX_DESC_DEF 32 1132 struct wl1251_acx_rx_queue_config { 1133 u8 num_descs; 1134 u8 pad; 1135 u8 type; 1136 u8 priority; 1137 __le32 dma_address; 1138 } __packed; 1139 1140 #define ACX_TX_DESC_MIN 1 1141 #define ACX_TX_DESC_MAX 127 1142 #define ACX_TX_DESC_DEF 16 1143 struct wl1251_acx_tx_queue_config { 1144 u8 num_descs; 1145 u8 pad[2]; 1146 u8 attributes; 1147 } __packed; 1148 1149 #define MAX_TX_QUEUE_CONFIGS 5 1150 #define MAX_TX_QUEUES 4 1151 struct wl1251_acx_config_memory { 1152 struct acx_header header; 1153 1154 struct wl1251_acx_memory mem_config; 1155 struct wl1251_acx_rx_queue_config rx_queue_config; 1156 struct wl1251_acx_tx_queue_config tx_queue_config[MAX_TX_QUEUE_CONFIGS]; 1157 } __packed; 1158 1159 struct wl1251_acx_mem_map { 1160 struct acx_header header; 1161 1162 void *code_start; 1163 void *code_end; 1164 1165 void *wep_defkey_start; 1166 void *wep_defkey_end; 1167 1168 void *sta_table_start; 1169 void *sta_table_end; 1170 1171 void *packet_template_start; 1172 void *packet_template_end; 1173 1174 void *queue_memory_start; 1175 void *queue_memory_end; 1176 1177 void *packet_memory_pool_start; 1178 void *packet_memory_pool_end; 1179 1180 void *debug_buffer1_start; 1181 void *debug_buffer1_end; 1182 1183 void *debug_buffer2_start; 1184 void *debug_buffer2_end; 1185 1186 /* Number of blocks FW allocated for TX packets */ 1187 u32 num_tx_mem_blocks; 1188 1189 /* Number of blocks FW allocated for RX packets */ 1190 u32 num_rx_mem_blocks; 1191 } __packed; 1192 1193 1194 struct wl1251_acx_wr_tbtt_and_dtim { 1195 1196 struct acx_header header; 1197 1198 /* Time in TUs between two consecutive beacons */ 1199 u16 tbtt; 1200 1201 /* 1202 * DTIM period 1203 * For BSS: Number of TBTTs in a DTIM period (range: 1-10) 1204 * For IBSS: value shall be set to 1 1205 */ 1206 u8 dtim; 1207 u8 padding; 1208 } __packed; 1209 1210 enum wl1251_acx_bet_mode { 1211 WL1251_ACX_BET_DISABLE = 0, 1212 WL1251_ACX_BET_ENABLE = 1, 1213 }; 1214 1215 struct wl1251_acx_bet_enable { 1216 struct acx_header header; 1217 1218 /* 1219 * Specifies if beacon early termination procedure is enabled or 1220 * disabled, see enum wl1251_acx_bet_mode. 1221 */ 1222 u8 enable; 1223 1224 /* 1225 * Specifies the maximum number of consecutive beacons that may be 1226 * early terminated. After this number is reached at least one full 1227 * beacon must be correctly received in FW before beacon ET 1228 * resumes. Range 0 - 255. 1229 */ 1230 u8 max_consecutive; 1231 1232 u8 padding[2]; 1233 } __packed; 1234 1235 struct wl1251_acx_ac_cfg { 1236 struct acx_header header; 1237 1238 /* 1239 * Access Category - The TX queue's access category 1240 * (refer to AccessCategory_enum) 1241 */ 1242 u8 ac; 1243 1244 /* 1245 * The contention window minimum size (in slots) for 1246 * the access class. 1247 */ 1248 u8 cw_min; 1249 1250 /* 1251 * The contention window maximum size (in slots) for 1252 * the access class. 1253 */ 1254 u16 cw_max; 1255 1256 /* The AIF value (in slots) for the access class. */ 1257 u8 aifsn; 1258 1259 u8 reserved; 1260 1261 /* The TX Op Limit (in microseconds) for the access class. */ 1262 u16 txop_limit; 1263 } __packed; 1264 1265 1266 enum wl1251_acx_channel_type { 1267 CHANNEL_TYPE_DCF = 0, 1268 CHANNEL_TYPE_EDCF = 1, 1269 CHANNEL_TYPE_HCCA = 2, 1270 }; 1271 1272 enum wl1251_acx_ps_scheme { 1273 /* regular ps: simple sending of packets */ 1274 WL1251_ACX_PS_SCHEME_LEGACY = 0, 1275 1276 /* sending a packet triggers a unscheduled apsd downstream */ 1277 WL1251_ACX_PS_SCHEME_UPSD_TRIGGER = 1, 1278 1279 /* a pspoll packet will be sent before every data packet */ 1280 WL1251_ACX_PS_SCHEME_LEGACY_PSPOLL = 2, 1281 1282 /* scheduled apsd mode */ 1283 WL1251_ACX_PS_SCHEME_SAPSD = 3, 1284 }; 1285 1286 enum wl1251_acx_ack_policy { 1287 WL1251_ACX_ACK_POLICY_LEGACY = 0, 1288 WL1251_ACX_ACK_POLICY_NO_ACK = 1, 1289 WL1251_ACX_ACK_POLICY_BLOCK = 2, 1290 }; 1291 1292 struct wl1251_acx_tid_cfg { 1293 struct acx_header header; 1294 1295 /* tx queue id number (0-7) */ 1296 u8 queue; 1297 1298 /* channel access type for the queue, enum wl1251_acx_channel_type */ 1299 u8 type; 1300 1301 /* EDCA: ac index (0-3), HCCA: traffic stream id (8-15) */ 1302 u8 tsid; 1303 1304 /* ps scheme of the specified queue, enum wl1251_acx_ps_scheme */ 1305 u8 ps_scheme; 1306 1307 /* the tx queue ack policy, enum wl1251_acx_ack_policy */ 1308 u8 ack_policy; 1309 1310 u8 padding[3]; 1311 1312 /* not supported */ 1313 u32 apsdconf[2]; 1314 } __packed; 1315 1316 /************************************************************************* 1317 1318 Host Interrupt Register (WiLink -> Host) 1319 1320 **************************************************************************/ 1321 1322 /* RX packet is ready in Xfer buffer #0 */ 1323 #define WL1251_ACX_INTR_RX0_DATA BIT(0) 1324 1325 /* TX result(s) are in the TX complete buffer */ 1326 #define WL1251_ACX_INTR_TX_RESULT BIT(1) 1327 1328 /* OBSOLETE */ 1329 #define WL1251_ACX_INTR_TX_XFR BIT(2) 1330 1331 /* RX packet is ready in Xfer buffer #1 */ 1332 #define WL1251_ACX_INTR_RX1_DATA BIT(3) 1333 1334 /* Event was entered to Event MBOX #A */ 1335 #define WL1251_ACX_INTR_EVENT_A BIT(4) 1336 1337 /* Event was entered to Event MBOX #B */ 1338 #define WL1251_ACX_INTR_EVENT_B BIT(5) 1339 1340 /* OBSOLETE */ 1341 #define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6) 1342 1343 /* Trace message on MBOX #A */ 1344 #define WL1251_ACX_INTR_TRACE_A BIT(7) 1345 1346 /* Trace message on MBOX #B */ 1347 #define WL1251_ACX_INTR_TRACE_B BIT(8) 1348 1349 /* Command processing completion */ 1350 #define WL1251_ACX_INTR_CMD_COMPLETE BIT(9) 1351 1352 /* Init sequence is done */ 1353 #define WL1251_ACX_INTR_INIT_COMPLETE BIT(14) 1354 1355 #define WL1251_ACX_INTR_ALL 0xFFFFFFFF 1356 1357 enum { 1358 ACX_WAKE_UP_CONDITIONS = 0x0002, 1359 ACX_MEM_CFG = 0x0003, 1360 ACX_SLOT = 0x0004, 1361 ACX_QUEUE_HEAD = 0x0005, /* for MASTER mode only */ 1362 ACX_AC_CFG = 0x0007, 1363 ACX_MEM_MAP = 0x0008, 1364 ACX_AID = 0x000A, 1365 ACX_RADIO_PARAM = 0x000B, /* Not used */ 1366 ACX_CFG = 0x000C, /* Not used */ 1367 ACX_FW_REV = 0x000D, 1368 ACX_MEDIUM_USAGE = 0x000F, 1369 ACX_RX_CFG = 0x0010, 1370 ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */ 1371 ACX_BSS_IN_PS = 0x0012, /* for AP only */ 1372 ACX_STATISTICS = 0x0013, /* Debug API */ 1373 ACX_FEATURE_CFG = 0x0015, 1374 ACX_MISC_CFG = 0x0017, /* Not used */ 1375 ACX_TID_CFG = 0x001A, 1376 ACX_BEACON_FILTER_OPT = 0x001F, 1377 ACX_LOW_RSSI = 0x0020, 1378 ACX_NOISE_HIST = 0x0021, 1379 ACX_HDK_VERSION = 0x0022, /* ??? */ 1380 ACX_PD_THRESHOLD = 0x0023, 1381 ACX_DATA_PATH_PARAMS = 0x0024, /* WO */ 1382 ACX_DATA_PATH_RESP_PARAMS = 0x0024, /* RO */ 1383 ACX_CCA_THRESHOLD = 0x0025, 1384 ACX_EVENT_MBOX_MASK = 0x0026, 1385 #ifdef FW_RUNNING_AS_AP 1386 ACX_DTIM_PERIOD = 0x0027, /* for AP only */ 1387 #else 1388 ACX_WR_TBTT_AND_DTIM = 0x0027, /* STA only */ 1389 #endif 1390 ACX_ACI_OPTION_CFG = 0x0029, /* OBSOLETE (for 1251)*/ 1391 ACX_GPIO_CFG = 0x002A, /* Not used */ 1392 ACX_GPIO_SET = 0x002B, /* Not used */ 1393 ACX_PM_CFG = 0x002C, /* To Be Documented */ 1394 ACX_CONN_MONIT_PARAMS = 0x002D, 1395 ACX_AVERAGE_RSSI = 0x002E, /* Not used */ 1396 ACX_CONS_TX_FAILURE = 0x002F, 1397 ACX_BCN_DTIM_OPTIONS = 0x0031, 1398 ACX_SG_ENABLE = 0x0032, 1399 ACX_SG_CFG = 0x0033, 1400 ACX_ANTENNA_DIVERSITY_CFG = 0x0035, /* To Be Documented */ 1401 ACX_LOW_SNR = 0x0037, /* To Be Documented */ 1402 ACX_BEACON_FILTER_TABLE = 0x0038, 1403 ACX_ARP_IP_FILTER = 0x0039, 1404 ACX_ROAMING_STATISTICS_TBL = 0x003B, 1405 ACX_RATE_POLICY = 0x003D, 1406 ACX_CTS_PROTECTION = 0x003E, 1407 ACX_SLEEP_AUTH = 0x003F, 1408 ACX_PREAMBLE_TYPE = 0x0040, 1409 ACX_ERROR_CNT = 0x0041, 1410 ACX_FW_GEN_FRAME_RATES = 0x0042, 1411 ACX_IBSS_FILTER = 0x0044, 1412 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045, 1413 ACX_TSF_INFO = 0x0046, 1414 ACX_CONFIG_PS_WMM = 0x0049, 1415 ACX_ENABLE_RX_DATA_FILTER = 0x004A, 1416 ACX_SET_RX_DATA_FILTER = 0x004B, 1417 ACX_GET_DATA_FILTER_STATISTICS = 0x004C, 1418 ACX_POWER_LEVEL_TABLE = 0x004D, 1419 ACX_BET_ENABLE = 0x0050, 1420 DOT11_STATION_ID = 0x1001, 1421 DOT11_RX_MSDU_LIFE_TIME = 0x1004, 1422 DOT11_CUR_TX_PWR = 0x100D, 1423 DOT11_DEFAULT_KEY = 0x1010, 1424 DOT11_RX_DOT11_MODE = 0x1012, 1425 DOT11_RTS_THRESHOLD = 0x1013, 1426 DOT11_GROUP_ADDRESS_TBL = 0x1014, 1427 1428 MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL, 1429 1430 MAX_IE = 0xFFFF 1431 }; 1432 1433 1434 int wl1251_acx_frame_rates(struct wl1251 *wl, u8 ctrl_rate, u8 ctrl_mod, 1435 u8 mgt_rate, u8 mgt_mod); 1436 int wl1251_acx_station_id(struct wl1251 *wl); 1437 int wl1251_acx_default_key(struct wl1251 *wl, u8 key_id); 1438 int wl1251_acx_wake_up_conditions(struct wl1251 *wl, u8 wake_up_event, 1439 u8 listen_interval); 1440 int wl1251_acx_sleep_auth(struct wl1251 *wl, u8 sleep_auth); 1441 int wl1251_acx_fw_version(struct wl1251 *wl, char *buf, size_t len); 1442 int wl1251_acx_tx_power(struct wl1251 *wl, int power); 1443 int wl1251_acx_feature_cfg(struct wl1251 *wl); 1444 int wl1251_acx_mem_map(struct wl1251 *wl, 1445 struct acx_header *mem_map, size_t len); 1446 int wl1251_acx_data_path_params(struct wl1251 *wl, 1447 struct acx_data_path_params_resp *data_path); 1448 int wl1251_acx_rx_msdu_life_time(struct wl1251 *wl, u32 life_time); 1449 int wl1251_acx_rx_config(struct wl1251 *wl, u32 config, u32 filter); 1450 int wl1251_acx_pd_threshold(struct wl1251 *wl); 1451 int wl1251_acx_slot(struct wl1251 *wl, enum acx_slot_type slot_time); 1452 int wl1251_acx_group_address_tbl(struct wl1251 *wl); 1453 int wl1251_acx_service_period_timeout(struct wl1251 *wl); 1454 int wl1251_acx_rts_threshold(struct wl1251 *wl, u16 rts_threshold); 1455 int wl1251_acx_beacon_filter_opt(struct wl1251 *wl, bool enable_filter); 1456 int wl1251_acx_beacon_filter_table(struct wl1251 *wl); 1457 int wl1251_acx_conn_monit_params(struct wl1251 *wl); 1458 int wl1251_acx_sg_enable(struct wl1251 *wl); 1459 int wl1251_acx_sg_cfg(struct wl1251 *wl); 1460 int wl1251_acx_cca_threshold(struct wl1251 *wl); 1461 int wl1251_acx_bcn_dtim_options(struct wl1251 *wl); 1462 int wl1251_acx_aid(struct wl1251 *wl, u16 aid); 1463 int wl1251_acx_event_mbox_mask(struct wl1251 *wl, u32 event_mask); 1464 int wl1251_acx_low_rssi(struct wl1251 *wl, s8 threshold, u8 weight, 1465 u8 depth, enum wl1251_acx_low_rssi_type type); 1466 int wl1251_acx_set_preamble(struct wl1251 *wl, enum acx_preamble_type preamble); 1467 int wl1251_acx_cts_protect(struct wl1251 *wl, 1468 enum acx_ctsprotect_type ctsprotect); 1469 int wl1251_acx_statistics(struct wl1251 *wl, struct acx_statistics *stats); 1470 int wl1251_acx_tsf_info(struct wl1251 *wl, u64 *mactime); 1471 int wl1251_acx_rate_policies(struct wl1251 *wl); 1472 int wl1251_acx_mem_cfg(struct wl1251 *wl); 1473 int wl1251_acx_wr_tbtt_and_dtim(struct wl1251 *wl, u16 tbtt, u8 dtim); 1474 int wl1251_acx_bet_enable(struct wl1251 *wl, enum wl1251_acx_bet_mode mode, 1475 u8 max_consecutive); 1476 int wl1251_acx_ac_cfg(struct wl1251 *wl, u8 ac, u8 cw_min, u16 cw_max, 1477 u8 aifs, u16 txop); 1478 int wl1251_acx_tid_cfg(struct wl1251 *wl, u8 queue, 1479 enum wl1251_acx_channel_type type, 1480 u8 tsid, enum wl1251_acx_ps_scheme ps_scheme, 1481 enum wl1251_acx_ack_policy ack_policy); 1482 1483 #endif /* __WL1251_ACX_H__ */ 1484