xref: /openbmc/linux/drivers/net/wireless/st/cw1200/hwio.c (revision 0d3b051a)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Low-level device IO routines for ST-Ericsson CW1200 drivers
4  *
5  * Copyright (c) 2010, ST-Ericsson
6  * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
7  *
8  * Based on:
9  * ST-Ericsson UMAC CW1200 driver, which is
10  * Copyright (c) 2010, ST-Ericsson
11  * Author: Ajitpal Singh <ajitpal.singh@lockless.no>
12  */
13 
14 #include <linux/types.h>
15 
16 #include "cw1200.h"
17 #include "hwio.h"
18 #include "hwbus.h"
19 
20  /* Sdio addr is 4*spi_addr */
21 #define SPI_REG_ADDR_TO_SDIO(spi_reg_addr) ((spi_reg_addr) << 2)
22 #define SDIO_ADDR17BIT(buf_id, mpf, rfu, reg_id_ofs) \
23 				((((buf_id)    & 0x1F) << 7) \
24 				| (((mpf)        & 1) << 6) \
25 				| (((rfu)        & 1) << 5) \
26 				| (((reg_id_ofs) & 0x1F) << 0))
27 #define MAX_RETRY		3
28 
29 
30 static int __cw1200_reg_read(struct cw1200_common *priv, u16 addr,
31 			     void *buf, size_t buf_len, int buf_id)
32 {
33 	u16 addr_sdio;
34 	u32 sdio_reg_addr_17bit;
35 
36 	/* Check if buffer is aligned to 4 byte boundary */
37 	if (WARN_ON(((unsigned long)buf & 3) && (buf_len > 4))) {
38 		pr_err("buffer is not aligned.\n");
39 		return -EINVAL;
40 	}
41 
42 	/* Convert to SDIO Register Address */
43 	addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
44 	sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
45 
46 	return priv->hwbus_ops->hwbus_memcpy_fromio(priv->hwbus_priv,
47 						  sdio_reg_addr_17bit,
48 						  buf, buf_len);
49 }
50 
51 static int __cw1200_reg_write(struct cw1200_common *priv, u16 addr,
52 				const void *buf, size_t buf_len, int buf_id)
53 {
54 	u16 addr_sdio;
55 	u32 sdio_reg_addr_17bit;
56 
57 	/* Convert to SDIO Register Address */
58 	addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
59 	sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
60 
61 	return priv->hwbus_ops->hwbus_memcpy_toio(priv->hwbus_priv,
62 						sdio_reg_addr_17bit,
63 						buf, buf_len);
64 }
65 
66 static inline int __cw1200_reg_read_32(struct cw1200_common *priv,
67 					u16 addr, u32 *val)
68 {
69 	__le32 tmp;
70 	int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0);
71 	*val = le32_to_cpu(tmp);
72 	return i;
73 }
74 
75 static inline int __cw1200_reg_write_32(struct cw1200_common *priv,
76 					u16 addr, u32 val)
77 {
78 	__le32 tmp = cpu_to_le32(val);
79 	return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0);
80 }
81 
82 static inline int __cw1200_reg_read_16(struct cw1200_common *priv,
83 					u16 addr, u16 *val)
84 {
85 	__le16 tmp;
86 	int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0);
87 	*val = le16_to_cpu(tmp);
88 	return i;
89 }
90 
91 static inline int __cw1200_reg_write_16(struct cw1200_common *priv,
92 					u16 addr, u16 val)
93 {
94 	__le16 tmp = cpu_to_le16(val);
95 	return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0);
96 }
97 
98 int cw1200_reg_read(struct cw1200_common *priv, u16 addr, void *buf,
99 			size_t buf_len)
100 {
101 	int ret;
102 	priv->hwbus_ops->lock(priv->hwbus_priv);
103 	ret = __cw1200_reg_read(priv, addr, buf, buf_len, 0);
104 	priv->hwbus_ops->unlock(priv->hwbus_priv);
105 	return ret;
106 }
107 
108 int cw1200_reg_write(struct cw1200_common *priv, u16 addr, const void *buf,
109 			size_t buf_len)
110 {
111 	int ret;
112 	priv->hwbus_ops->lock(priv->hwbus_priv);
113 	ret = __cw1200_reg_write(priv, addr, buf, buf_len, 0);
114 	priv->hwbus_ops->unlock(priv->hwbus_priv);
115 	return ret;
116 }
117 
118 int cw1200_data_read(struct cw1200_common *priv, void *buf, size_t buf_len)
119 {
120 	int ret, retry = 1;
121 	int buf_id_rx = priv->buf_id_rx;
122 
123 	priv->hwbus_ops->lock(priv->hwbus_priv);
124 
125 	while (retry <= MAX_RETRY) {
126 		ret = __cw1200_reg_read(priv,
127 					ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
128 					buf_len, buf_id_rx + 1);
129 		if (!ret) {
130 			buf_id_rx = (buf_id_rx + 1) & 3;
131 			priv->buf_id_rx = buf_id_rx;
132 			break;
133 		} else {
134 			retry++;
135 			mdelay(1);
136 			pr_err("error :[%d]\n", ret);
137 		}
138 	}
139 
140 	priv->hwbus_ops->unlock(priv->hwbus_priv);
141 	return ret;
142 }
143 
144 int cw1200_data_write(struct cw1200_common *priv, const void *buf,
145 			size_t buf_len)
146 {
147 	int ret, retry = 1;
148 	int buf_id_tx = priv->buf_id_tx;
149 
150 	priv->hwbus_ops->lock(priv->hwbus_priv);
151 
152 	while (retry <= MAX_RETRY) {
153 		ret = __cw1200_reg_write(priv,
154 					 ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
155 					 buf_len, buf_id_tx);
156 		if (!ret) {
157 			buf_id_tx = (buf_id_tx + 1) & 31;
158 			priv->buf_id_tx = buf_id_tx;
159 			break;
160 		} else {
161 			retry++;
162 			mdelay(1);
163 			pr_err("error :[%d]\n", ret);
164 		}
165 	}
166 
167 	priv->hwbus_ops->unlock(priv->hwbus_priv);
168 	return ret;
169 }
170 
171 int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf,
172 			 size_t buf_len, u32 prefetch, u16 port_addr)
173 {
174 	u32 val32 = 0;
175 	int i, ret;
176 
177 	if ((buf_len / 2) >= 0x1000) {
178 		pr_err("Can't read more than 0xfff words.\n");
179 		return -EINVAL;
180 	}
181 
182 	priv->hwbus_ops->lock(priv->hwbus_priv);
183 	/* Write address */
184 	ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
185 	if (ret < 0) {
186 		pr_err("Can't write address register.\n");
187 		goto out;
188 	}
189 
190 	/* Read CONFIG Register Value - We will read 32 bits */
191 	ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
192 	if (ret < 0) {
193 		pr_err("Can't read config register.\n");
194 		goto out;
195 	}
196 
197 	/* Set PREFETCH bit */
198 	ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID,
199 					val32 | prefetch);
200 	if (ret < 0) {
201 		pr_err("Can't write prefetch bit.\n");
202 		goto out;
203 	}
204 
205 	/* Check for PRE-FETCH bit to be cleared */
206 	for (i = 0; i < 20; i++) {
207 		ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
208 		if (ret < 0) {
209 			pr_err("Can't check prefetch bit.\n");
210 			goto out;
211 		}
212 		if (!(val32 & prefetch))
213 			break;
214 
215 		mdelay(i);
216 	}
217 
218 	if (val32 & prefetch) {
219 		pr_err("Prefetch bit is not cleared.\n");
220 		goto out;
221 	}
222 
223 	/* Read data port */
224 	ret = __cw1200_reg_read(priv, port_addr, buf, buf_len, 0);
225 	if (ret < 0) {
226 		pr_err("Can't read data port.\n");
227 		goto out;
228 	}
229 
230 out:
231 	priv->hwbus_ops->unlock(priv->hwbus_priv);
232 	return ret;
233 }
234 
235 int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf,
236 			size_t buf_len)
237 {
238 	int ret;
239 
240 	if ((buf_len / 2) >= 0x1000) {
241 		pr_err("Can't write more than 0xfff words.\n");
242 		return -EINVAL;
243 	}
244 
245 	priv->hwbus_ops->lock(priv->hwbus_priv);
246 
247 	/* Write address */
248 	ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
249 	if (ret < 0) {
250 		pr_err("Can't write address register.\n");
251 		goto out;
252 	}
253 
254 	/* Write data port */
255 	ret = __cw1200_reg_write(priv, ST90TDS_SRAM_DPORT_REG_ID,
256 					buf, buf_len, 0);
257 	if (ret < 0) {
258 		pr_err("Can't write data port.\n");
259 		goto out;
260 	}
261 
262 out:
263 	priv->hwbus_ops->unlock(priv->hwbus_priv);
264 	return ret;
265 }
266 
267 int __cw1200_irq_enable(struct cw1200_common *priv, int enable)
268 {
269 	u32 val32;
270 	u16 val16;
271 	int ret;
272 
273 	if (HIF_8601_SILICON == priv->hw_type) {
274 		ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
275 		if (ret < 0) {
276 			pr_err("Can't read config register.\n");
277 			return ret;
278 		}
279 
280 		if (enable)
281 			val32 |= ST90TDS_CONF_IRQ_RDY_ENABLE;
282 		else
283 			val32 &= ~ST90TDS_CONF_IRQ_RDY_ENABLE;
284 
285 		ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val32);
286 		if (ret < 0) {
287 			pr_err("Can't write config register.\n");
288 			return ret;
289 		}
290 	} else {
291 		ret = __cw1200_reg_read_16(priv, ST90TDS_CONFIG_REG_ID, &val16);
292 		if (ret < 0) {
293 			pr_err("Can't read control register.\n");
294 			return ret;
295 		}
296 
297 		if (enable)
298 			val16 |= ST90TDS_CONT_IRQ_RDY_ENABLE;
299 		else
300 			val16 &= ~ST90TDS_CONT_IRQ_RDY_ENABLE;
301 
302 		ret = __cw1200_reg_write_16(priv, ST90TDS_CONFIG_REG_ID, val16);
303 		if (ret < 0) {
304 			pr_err("Can't write control register.\n");
305 			return ret;
306 		}
307 	}
308 	return 0;
309 }
310