1 /** 2 * @section LICENSE 3 * Copyright (c) 2014 Redpine Signals Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 19 #ifndef __RSI_SDIO_INTF__ 20 #define __RSI_SDIO_INTF__ 21 22 #include <linux/mmc/card.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/sdio_func.h> 26 #include <linux/mmc/sdio.h> 27 #include <linux/mmc/sd.h> 28 #include <linux/mmc/sdio_ids.h> 29 #include "rsi_main.h" 30 31 #define RSI_SDIO_VENDOR_ID 0x041B 32 #define RSI_SDIO_PID_9113 0x9330 33 #define RSI_SDIO_PID_9116 0x9116 34 35 enum sdio_interrupt_type { 36 BUFFER_FULL = 0x0, 37 BUFFER_AVAILABLE = 0x2, 38 FIRMWARE_ASSERT_IND = 0x3, 39 MSDU_PACKET_PENDING = 0x4, 40 UNKNOWN_INT = 0XE 41 }; 42 43 /* Buffer status register related info */ 44 #define PKT_BUFF_SEMI_FULL 0 45 #define PKT_BUFF_FULL 1 46 #define PKT_MGMT_BUFF_FULL 2 47 #define MSDU_PKT_PENDING 3 48 #define RECV_NUM_BLOCKS 4 49 /* Interrupt Bit Related Macros */ 50 #define PKT_BUFF_AVAILABLE 1 51 #define FW_ASSERT_IND 2 52 53 #define RSI_MASTER_REG_BUF_SIZE 12 54 55 #define RSI_DEVICE_BUFFER_STATUS_REGISTER 0xf3 56 #define RSI_FN1_INT_REGISTER 0xf9 57 #define RSI_INT_ENABLE_REGISTER 0x04 58 #define RSI_INT_ENABLE_MASK 0xfc 59 #define RSI_SD_REQUEST_MASTER 0x10000 60 61 /* FOR SD CARD ONLY */ 62 #define SDIO_RX_NUM_BLOCKS_REG 0x000F1 63 #define SDIO_FW_STATUS_REG 0x000F2 64 #define SDIO_NXT_RD_DELAY2 0x000F5 65 #define SDIO_MASTER_ACCESS_MSBYTE 0x000FA 66 #define SDIO_MASTER_ACCESS_LSBYTE 0x000FB 67 #define SDIO_READ_START_LVL 0x000FC 68 #define SDIO_READ_FIFO_CTL 0x000FD 69 #define SDIO_WRITE_FIFO_CTL 0x000FE 70 #define SDIO_WAKEUP_REG 0x000FF 71 #define SDIO_FUN1_INTR_CLR_REG 0x0008 72 #define SDIO_REG_HIGH_SPEED 0x0013 73 74 #define RSI_GET_SDIO_INTERRUPT_TYPE(_I, TYPE) \ 75 { \ 76 TYPE = \ 77 (_I & (1 << PKT_BUFF_AVAILABLE)) ? \ 78 BUFFER_AVAILABLE : \ 79 (_I & (1 << MSDU_PKT_PENDING)) ? \ 80 MSDU_PACKET_PENDING : \ 81 (_I & (1 << FW_ASSERT_IND)) ? \ 82 FIRMWARE_ASSERT_IND : UNKNOWN_INT; \ 83 } 84 85 /* common registers in SDIO function1 */ 86 #define TA_SOFT_RESET_REG 0x0004 87 #define TA_TH0_PC_REG 0x0400 88 #define TA_HOLD_THREAD_REG 0x0844 89 #define TA_RELEASE_THREAD_REG 0x0848 90 91 #define TA_SOFT_RST_CLR 0 92 #define TA_SOFT_RST_SET BIT(0) 93 #define TA_PC_ZERO 0 94 #define TA_HOLD_THREAD_VALUE 0xF 95 #define TA_RELEASE_THREAD_VALUE 0xF 96 #define TA_BASE_ADDR 0x2200 97 #define MISC_CFG_BASE_ADDR 0x4105 98 99 struct receive_info { 100 bool buffer_full; 101 bool semi_buffer_full; 102 bool mgmt_buffer_full; 103 u32 mgmt_buf_full_counter; 104 u32 buf_semi_full_counter; 105 u8 watch_bufferfull_count; 106 u32 sdio_intr_status_zero; 107 u32 sdio_int_counter; 108 u32 total_sdio_msdu_pending_intr; 109 u32 total_sdio_unknown_intr; 110 u32 buf_full_counter; 111 u32 buf_available_counter; 112 }; 113 114 struct rsi_sdio_rx_q { 115 u8 num_rx_pkts; 116 struct sk_buff_head head; 117 }; 118 119 struct rsi_91x_sdiodev { 120 struct sdio_func *pfunction; 121 struct task_struct *sdio_irq_task; 122 struct receive_info rx_info; 123 u32 next_read_delay; 124 u32 sdio_high_speed_enable; 125 u8 sdio_clock_speed; 126 u32 cardcapability; 127 u8 prev_desc[16]; 128 u16 tx_blk_size; 129 u8 write_fail; 130 bool buff_status_updated; 131 struct rsi_sdio_rx_q rx_q; 132 struct rsi_thread rx_thread; 133 }; 134 135 void rsi_interrupt_handler(struct rsi_hw *adapter); 136 int rsi_init_sdio_slave_regs(struct rsi_hw *adapter); 137 int rsi_sdio_read_register(struct rsi_hw *adapter, u32 addr, u8 *data); 138 int rsi_sdio_host_intf_read_pkt(struct rsi_hw *adapter, u8 *pkt, u32 length); 139 int rsi_sdio_write_register(struct rsi_hw *adapter, u8 function, 140 u32 addr, u8 *data); 141 int rsi_sdio_write_register_multiple(struct rsi_hw *adapter, u32 addr, 142 u8 *data, u16 count); 143 int rsi_sdio_master_access_msword(struct rsi_hw *adapter, u16 ms_word); 144 void rsi_sdio_ack_intr(struct rsi_hw *adapter, u8 int_bit); 145 int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter); 146 int rsi_sdio_check_buffer_status(struct rsi_hw *adapter, u8 q_num); 147 void rsi_sdio_rx_thread(struct rsi_common *common); 148 #endif 149