1 /**
2  * @section LICENSE
3  * Copyright (c) 2014 Redpine Signals Inc.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  *
17  */
18 
19 #ifndef __RSI_SDIO_INTF__
20 #define __RSI_SDIO_INTF__
21 
22 #include <linux/mmc/card.h>
23 #include <linux/mmc/mmc.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/sdio_func.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sd.h>
28 #include <linux/mmc/sdio_ids.h>
29 #include "rsi_main.h"
30 
31 enum sdio_interrupt_type {
32 	BUFFER_FULL         = 0x0,
33 	BUFFER_AVAILABLE    = 0x2,
34 	FIRMWARE_ASSERT_IND = 0x3,
35 	MSDU_PACKET_PENDING = 0x4,
36 	UNKNOWN_INT         = 0XE
37 };
38 
39 /* Buffer status register related info */
40 #define PKT_BUFF_SEMI_FULL                      0
41 #define PKT_BUFF_FULL                           1
42 #define PKT_MGMT_BUFF_FULL                      2
43 #define MSDU_PKT_PENDING                        3
44 /* Interrupt Bit Related Macros */
45 #define PKT_BUFF_AVAILABLE                      1
46 #define FW_ASSERT_IND                           2
47 
48 #define RSI_DEVICE_BUFFER_STATUS_REGISTER       0xf3
49 #define RSI_FN1_INT_REGISTER                    0xf9
50 #define RSI_SD_REQUEST_MASTER                   0x10000
51 
52 /* FOR SD CARD ONLY */
53 #define SDIO_RX_NUM_BLOCKS_REG                  0x000F1
54 #define SDIO_FW_STATUS_REG                      0x000F2
55 #define SDIO_NXT_RD_DELAY2                      0x000F5
56 #define SDIO_MASTER_ACCESS_MSBYTE               0x000FA
57 #define SDIO_MASTER_ACCESS_LSBYTE               0x000FB
58 #define SDIO_READ_START_LVL                     0x000FC
59 #define SDIO_READ_FIFO_CTL                      0x000FD
60 #define SDIO_WRITE_FIFO_CTL                     0x000FE
61 #define SDIO_FUN1_INTR_CLR_REG                  0x0008
62 #define SDIO_REG_HIGH_SPEED                     0x0013
63 
64 #define RSI_GET_SDIO_INTERRUPT_TYPE(_I, TYPE)      \
65 	{					   \
66 		TYPE =                             \
67 		(_I & (1 << PKT_BUFF_AVAILABLE)) ? \
68 		BUFFER_AVAILABLE :		   \
69 		(_I & (1 << MSDU_PKT_PENDING)) ?   \
70 		MSDU_PACKET_PENDING :              \
71 		(_I & (1 << FW_ASSERT_IND)) ?      \
72 		FIRMWARE_ASSERT_IND : UNKNOWN_INT; \
73 	}
74 
75 /* common registers in SDIO function1 */
76 #define TA_SOFT_RESET_REG            0x0004
77 #define TA_TH0_PC_REG                0x0400
78 #define TA_HOLD_THREAD_REG           0x0844
79 #define TA_RELEASE_THREAD_REG        0x0848
80 
81 #define TA_SOFT_RST_CLR              0
82 #define TA_SOFT_RST_SET              BIT(0)
83 #define TA_PC_ZERO                   0
84 #define TA_HOLD_THREAD_VALUE         cpu_to_le32(0xF)
85 #define TA_RELEASE_THREAD_VALUE      cpu_to_le32(0xF)
86 #define TA_BASE_ADDR                 0x2200
87 #define MISC_CFG_BASE_ADDR           0x4105
88 
89 struct receive_info {
90 	bool buffer_full;
91 	bool semi_buffer_full;
92 	bool mgmt_buffer_full;
93 	u32 mgmt_buf_full_counter;
94 	u32 buf_semi_full_counter;
95 	u8 watch_bufferfull_count;
96 	u32 sdio_intr_status_zero;
97 	u32 sdio_int_counter;
98 	u32 total_sdio_msdu_pending_intr;
99 	u32 total_sdio_unknown_intr;
100 	u32 buf_full_counter;
101 	u32 buf_available_counter;
102 };
103 
104 struct rsi_91x_sdiodev {
105 	struct sdio_func *pfunction;
106 	struct task_struct *in_sdio_litefi_irq;
107 	struct receive_info rx_info;
108 	u32 next_read_delay;
109 	u32 sdio_high_speed_enable;
110 	u8 sdio_clock_speed;
111 	u32 cardcapability;
112 	u8 prev_desc[16];
113 	u32 tx_blk_size;
114 	u8 write_fail;
115 };
116 
117 void rsi_interrupt_handler(struct rsi_hw *adapter);
118 int rsi_init_sdio_slave_regs(struct rsi_hw *adapter);
119 int rsi_sdio_device_init(struct rsi_common *common);
120 int rsi_sdio_read_register(struct rsi_hw *adapter, u32 addr, u8 *data);
121 int rsi_sdio_host_intf_read_pkt(struct rsi_hw *adapter, u8 *pkt, u32 length);
122 int rsi_sdio_write_register(struct rsi_hw *adapter, u8 function,
123 			    u32 addr, u8 *data);
124 int rsi_sdio_write_register_multiple(struct rsi_hw *adapter, u32 addr,
125 				     u8 *data, u32 count);
126 void rsi_sdio_ack_intr(struct rsi_hw *adapter, u8 int_bit);
127 int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter);
128 int rsi_sdio_read_buffer_status_register(struct rsi_hw *adapter, u8 q_num);
129 #endif
130