1 /** 2 * @section LICENSE 3 * Copyright (c) 2014 Redpine Signals Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 19 #ifndef __RSI_SDIO_INTF__ 20 #define __RSI_SDIO_INTF__ 21 22 #include <linux/mmc/card.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/sdio_func.h> 26 #include <linux/mmc/sdio.h> 27 #include <linux/mmc/sd.h> 28 #include <linux/mmc/sdio_ids.h> 29 #include "rsi_main.h" 30 31 #define RSI_SDIO_VID_9113 0x041B 32 #define RSI_SDIO_PID_9113 0x9330 33 34 enum sdio_interrupt_type { 35 BUFFER_FULL = 0x0, 36 BUFFER_AVAILABLE = 0x2, 37 FIRMWARE_ASSERT_IND = 0x3, 38 MSDU_PACKET_PENDING = 0x4, 39 UNKNOWN_INT = 0XE 40 }; 41 42 /* Buffer status register related info */ 43 #define PKT_BUFF_SEMI_FULL 0 44 #define PKT_BUFF_FULL 1 45 #define PKT_MGMT_BUFF_FULL 2 46 #define MSDU_PKT_PENDING 3 47 #define RECV_NUM_BLOCKS 4 48 /* Interrupt Bit Related Macros */ 49 #define PKT_BUFF_AVAILABLE 1 50 #define FW_ASSERT_IND 2 51 52 #define RSI_MASTER_REG_BUF_SIZE 12 53 54 #define RSI_DEVICE_BUFFER_STATUS_REGISTER 0xf3 55 #define RSI_FN1_INT_REGISTER 0xf9 56 #define RSI_INT_ENABLE_REGISTER 0x04 57 #define RSI_INT_ENABLE_MASK 0xfc 58 #define RSI_SD_REQUEST_MASTER 0x10000 59 60 /* FOR SD CARD ONLY */ 61 #define SDIO_RX_NUM_BLOCKS_REG 0x000F1 62 #define SDIO_FW_STATUS_REG 0x000F2 63 #define SDIO_NXT_RD_DELAY2 0x000F5 64 #define SDIO_MASTER_ACCESS_MSBYTE 0x000FA 65 #define SDIO_MASTER_ACCESS_LSBYTE 0x000FB 66 #define SDIO_READ_START_LVL 0x000FC 67 #define SDIO_READ_FIFO_CTL 0x000FD 68 #define SDIO_WRITE_FIFO_CTL 0x000FE 69 #define SDIO_WAKEUP_REG 0x000FF 70 #define SDIO_FUN1_INTR_CLR_REG 0x0008 71 #define SDIO_REG_HIGH_SPEED 0x0013 72 73 #define RSI_GET_SDIO_INTERRUPT_TYPE(_I, TYPE) \ 74 { \ 75 TYPE = \ 76 (_I & (1 << PKT_BUFF_AVAILABLE)) ? \ 77 BUFFER_AVAILABLE : \ 78 (_I & (1 << MSDU_PKT_PENDING)) ? \ 79 MSDU_PACKET_PENDING : \ 80 (_I & (1 << FW_ASSERT_IND)) ? \ 81 FIRMWARE_ASSERT_IND : UNKNOWN_INT; \ 82 } 83 84 /* common registers in SDIO function1 */ 85 #define TA_SOFT_RESET_REG 0x0004 86 #define TA_TH0_PC_REG 0x0400 87 #define TA_HOLD_THREAD_REG 0x0844 88 #define TA_RELEASE_THREAD_REG 0x0848 89 90 #define TA_SOFT_RST_CLR 0 91 #define TA_SOFT_RST_SET BIT(0) 92 #define TA_PC_ZERO 0 93 #define TA_HOLD_THREAD_VALUE 0xF 94 #define TA_RELEASE_THREAD_VALUE cpu_to_le32(0xF) 95 #define TA_BASE_ADDR 0x2200 96 #define MISC_CFG_BASE_ADDR 0x4105 97 98 struct receive_info { 99 bool buffer_full; 100 bool semi_buffer_full; 101 bool mgmt_buffer_full; 102 u32 mgmt_buf_full_counter; 103 u32 buf_semi_full_counter; 104 u8 watch_bufferfull_count; 105 u32 sdio_intr_status_zero; 106 u32 sdio_int_counter; 107 u32 total_sdio_msdu_pending_intr; 108 u32 total_sdio_unknown_intr; 109 u32 buf_full_counter; 110 u32 buf_available_counter; 111 }; 112 113 struct rsi_sdio_rx_q { 114 u8 num_rx_pkts; 115 struct sk_buff_head head; 116 }; 117 118 struct rsi_91x_sdiodev { 119 struct sdio_func *pfunction; 120 struct task_struct *sdio_irq_task; 121 struct receive_info rx_info; 122 u32 next_read_delay; 123 u32 sdio_high_speed_enable; 124 u8 sdio_clock_speed; 125 u32 cardcapability; 126 u8 prev_desc[16]; 127 u16 tx_blk_size; 128 u8 write_fail; 129 bool buff_status_updated; 130 struct rsi_sdio_rx_q rx_q; 131 struct rsi_thread rx_thread; 132 }; 133 134 void rsi_interrupt_handler(struct rsi_hw *adapter); 135 int rsi_init_sdio_slave_regs(struct rsi_hw *adapter); 136 int rsi_sdio_read_register(struct rsi_hw *adapter, u32 addr, u8 *data); 137 int rsi_sdio_host_intf_read_pkt(struct rsi_hw *adapter, u8 *pkt, u32 length); 138 int rsi_sdio_write_register(struct rsi_hw *adapter, u8 function, 139 u32 addr, u8 *data); 140 int rsi_sdio_write_register_multiple(struct rsi_hw *adapter, u32 addr, 141 u8 *data, u16 count); 142 int rsi_sdio_master_access_msword(struct rsi_hw *adapter, u16 ms_word); 143 void rsi_sdio_ack_intr(struct rsi_hw *adapter, u8 int_bit); 144 int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter); 145 int rsi_sdio_check_buffer_status(struct rsi_hw *adapter, u8 q_num); 146 void rsi_sdio_rx_thread(struct rsi_common *common); 147 #endif 148