1 /** 2 * Copyright (c) 2014 Redpine Signals Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __RSI_MGMT_H__ 18 #define __RSI_MGMT_H__ 19 20 #include <linux/sort.h> 21 #include "rsi_boot_params.h" 22 #include "rsi_main.h" 23 24 #define MAX_MGMT_PKT_SIZE 512 25 #define RSI_NEEDED_HEADROOM 80 26 #define RSI_RCV_BUFFER_LEN 2000 27 28 #define RSI_11B_MODE 0 29 #define RSI_11G_MODE BIT(7) 30 #define RETRY_COUNT 8 31 #define RETRY_LONG 4 32 #define RETRY_SHORT 7 33 #define WMM_SHORT_SLOT_TIME 9 34 #define SIFS_DURATION 16 35 36 #define KEY_TYPE_CLEAR 0 37 #define RSI_PAIRWISE_KEY 1 38 #define RSI_GROUP_KEY 2 39 40 /* EPPROM_READ_ADDRESS */ 41 #define WLAN_MAC_EEPROM_ADDR 40 42 #define WLAN_MAC_MAGIC_WORD_LEN 0x01 43 #define WLAN_HOST_MODE_LEN 0x04 44 #define WLAN_FW_VERSION_LEN 0x08 45 #define MAGIC_WORD 0x5A 46 47 /* Receive Frame Types */ 48 #define TA_CONFIRM_TYPE 0x01 49 #define RX_DOT11_MGMT 0x02 50 #define TX_STATUS_IND 0x04 51 #define PROBEREQ_CONFIRM 2 52 #define CARD_READY_IND 0x00 53 54 #define RSI_DELETE_PEER 0x0 55 #define RSI_ADD_PEER 0x1 56 #define START_AMPDU_AGGR 0x1 57 #define STOP_AMPDU_AGGR 0x0 58 #define INTERNAL_MGMT_PKT 0x99 59 60 #define PUT_BBP_RESET 0 61 #define BBP_REG_WRITE 0 62 #define RF_RESET_ENABLE BIT(3) 63 #define RATE_INFO_ENABLE BIT(0) 64 #define RSI_BROADCAST_PKT BIT(9) 65 66 #define UPPER_20_ENABLE (0x2 << 12) 67 #define LOWER_20_ENABLE (0x4 << 12) 68 #define FULL40M_ENABLE 0x6 69 70 #define RSI_LMAC_CLOCK_80MHZ 0x1 71 #define RSI_ENABLE_40MHZ (0x1 << 3) 72 #define ENABLE_SHORTGI_RATE BIT(9) 73 74 #define RX_BA_INDICATION 1 75 #define RSI_TBL_SZ 40 76 #define MAX_RETRIES 8 77 #define RSI_IFTYPE_STATION 0 78 79 #define STD_RATE_MCS7 0x07 80 #define STD_RATE_MCS6 0x06 81 #define STD_RATE_MCS5 0x05 82 #define STD_RATE_MCS4 0x04 83 #define STD_RATE_MCS3 0x03 84 #define STD_RATE_MCS2 0x02 85 #define STD_RATE_MCS1 0x01 86 #define STD_RATE_MCS0 0x00 87 #define STD_RATE_54 0x6c 88 #define STD_RATE_48 0x60 89 #define STD_RATE_36 0x48 90 #define STD_RATE_24 0x30 91 #define STD_RATE_18 0x24 92 #define STD_RATE_12 0x18 93 #define STD_RATE_11 0x16 94 #define STD_RATE_09 0x12 95 #define STD_RATE_06 0x0C 96 #define STD_RATE_5_5 0x0B 97 #define STD_RATE_02 0x04 98 #define STD_RATE_01 0x02 99 100 #define RSI_RF_TYPE 1 101 #define RSI_RATE_00 0x00 102 #define RSI_RATE_1 0x0 103 #define RSI_RATE_2 0x2 104 #define RSI_RATE_5_5 0x4 105 #define RSI_RATE_11 0x6 106 #define RSI_RATE_6 0x8b 107 #define RSI_RATE_9 0x8f 108 #define RSI_RATE_12 0x8a 109 #define RSI_RATE_18 0x8e 110 #define RSI_RATE_24 0x89 111 #define RSI_RATE_36 0x8d 112 #define RSI_RATE_48 0x88 113 #define RSI_RATE_54 0x8c 114 #define RSI_RATE_MCS0 0x100 115 #define RSI_RATE_MCS1 0x101 116 #define RSI_RATE_MCS2 0x102 117 #define RSI_RATE_MCS3 0x103 118 #define RSI_RATE_MCS4 0x104 119 #define RSI_RATE_MCS5 0x105 120 #define RSI_RATE_MCS6 0x106 121 #define RSI_RATE_MCS7 0x107 122 #define RSI_RATE_MCS7_SG 0x307 123 124 #define BW_20MHZ 0 125 #define BW_40MHZ 1 126 127 #define EP_2GHZ_20MHZ 0 128 #define EP_2GHZ_40MHZ 1 129 #define EP_5GHZ_20MHZ 2 130 #define EP_5GHZ_40MHZ 3 131 132 #define SIFS_TX_11N_VALUE 580 133 #define SIFS_TX_11B_VALUE 346 134 #define SHORT_SLOT_VALUE 360 135 #define LONG_SLOT_VALUE 640 136 #define OFDM_ACK_TOUT_VALUE 2720 137 #define CCK_ACK_TOUT_VALUE 9440 138 #define LONG_PREAMBLE 0x0000 139 #define SHORT_PREAMBLE 0x0001 140 141 #define RSI_SUPP_FILTERS (FIF_ALLMULTI | FIF_PROBE_REQ |\ 142 FIF_BCN_PRBRESP_PROMISC) 143 144 #define ANTENNA_SEL_INT 0x02 /* RF_OUT_2 / Integerated */ 145 #define ANTENNA_SEL_UFL 0x03 /* RF_OUT_1 / U.FL */ 146 147 /* Rx filter word definitions */ 148 #define PROMISCOUS_MODE BIT(0) 149 #define ALLOW_DATA_ASSOC_PEER BIT(1) 150 #define ALLOW_MGMT_ASSOC_PEER BIT(2) 151 #define ALLOW_CTRL_ASSOC_PEER BIT(3) 152 #define DISALLOW_BEACONS BIT(4) 153 #define ALLOW_CONN_PEER_MGMT_WHILE_BUF_FULL BIT(5) 154 #define DISALLOW_BROADCAST_DATA BIT(6) 155 156 enum opmode { 157 STA_OPMODE = 1, 158 AP_OPMODE = 2 159 }; 160 161 enum vap_status { 162 VAP_ADD = 1, 163 VAP_DELETE = 2, 164 VAP_UPDATE = 3 165 }; 166 167 extern struct ieee80211_rate rsi_rates[12]; 168 extern const u16 rsi_mcsrates[8]; 169 170 enum sta_notify_events { 171 STA_CONNECTED = 0, 172 STA_DISCONNECTED, 173 STA_TX_ADDBA_DONE, 174 STA_TX_DELBA, 175 STA_RX_ADDBA_DONE, 176 STA_RX_DELBA 177 }; 178 179 /* Send Frames Types */ 180 enum cmd_frame_type { 181 TX_DOT11_MGMT, 182 RESET_MAC_REQ, 183 RADIO_CAPABILITIES, 184 BB_PROG_VALUES_REQUEST, 185 RF_PROG_VALUES_REQUEST, 186 WAKEUP_SLEEP_REQUEST, 187 SCAN_REQUEST, 188 TSF_UPDATE, 189 PEER_NOTIFY, 190 BLOCK_HW_QUEUE, 191 SET_KEY_REQ, 192 AUTO_RATE_IND, 193 BOOTUP_PARAMS_REQUEST, 194 VAP_CAPABILITIES, 195 EEPROM_READ_TYPE , 196 EEPROM_WRITE, 197 GPIO_PIN_CONFIG , 198 SET_RX_FILTER, 199 AMPDU_IND, 200 STATS_REQUEST_FRAME, 201 BB_BUF_PROG_VALUES_REQ, 202 BBP_PROG_IN_TA, 203 BG_SCAN_PARAMS, 204 BG_SCAN_PROBE_REQ, 205 CW_MODE_REQ, 206 PER_CMD_PKT, 207 ANT_SEL_FRAME = 0x20, 208 COMMON_DEV_CONFIG = 0x28, 209 RADIO_PARAMS_UPDATE = 0x29 210 }; 211 212 struct rsi_mac_frame { 213 __le16 desc_word[8]; 214 } __packed; 215 216 struct rsi_boot_params { 217 __le16 desc_word[8]; 218 struct bootup_params bootup_params; 219 } __packed; 220 221 struct rsi_peer_notify { 222 __le16 desc_word[8]; 223 u8 mac_addr[6]; 224 __le16 command; 225 __le16 mpdu_density; 226 __le16 reserved; 227 __le32 sta_flags; 228 } __packed; 229 230 struct rsi_vap_caps { 231 __le16 desc_word[8]; 232 u8 mac_addr[6]; 233 __le16 keep_alive_period; 234 u8 bssid[6]; 235 __le16 reserved; 236 __le32 flags; 237 __le16 frag_threshold; 238 __le16 rts_threshold; 239 __le32 default_mgmt_rate; 240 __le32 default_ctrl_rate; 241 __le32 default_data_rate; 242 __le16 beacon_interval; 243 __le16 dtim_period; 244 } __packed; 245 246 struct rsi_set_key { 247 __le16 desc_word[8]; 248 u8 key[4][32]; 249 u8 tx_mic_key[8]; 250 u8 rx_mic_key[8]; 251 } __packed; 252 253 struct rsi_auto_rate { 254 __le16 desc_word[8]; 255 __le16 failure_limit; 256 __le16 initial_boundary; 257 __le16 max_threshold_limt; 258 __le16 num_supported_rates; 259 __le16 aarf_rssi; 260 __le16 moderate_rate_inx; 261 __le16 collision_tolerance; 262 __le16 supported_rates[40]; 263 } __packed; 264 265 struct qos_params { 266 __le16 cont_win_min_q; 267 __le16 cont_win_max_q; 268 __le16 aifsn_val_q; 269 __le16 txop_q; 270 } __packed; 271 272 struct rsi_radio_caps { 273 __le16 desc_word[8]; 274 struct qos_params qos_params[MAX_HW_QUEUES]; 275 u8 num_11n_rates; 276 u8 num_11ac_rates; 277 __le16 gcpd_per_rate[20]; 278 __le16 sifs_tx_11n; 279 __le16 sifs_tx_11b; 280 __le16 slot_rx_11n; 281 __le16 ofdm_ack_tout; 282 __le16 cck_ack_tout; 283 __le16 preamble_type; 284 } __packed; 285 286 /* ULP GPIO flags */ 287 #define RSI_GPIO_MOTION_SENSOR_ULP_WAKEUP BIT(0) 288 #define RSI_GPIO_SLEEP_IND_FROM_DEVICE BIT(1) 289 #define RSI_GPIO_2_ULP BIT(2) 290 #define RSI_GPIO_PUSH_BUTTON_ULP_WAKEUP BIT(3) 291 292 /* SOC GPIO flags */ 293 #define RSI_GPIO_0_PSPI_CSN_0 BIT(0) 294 #define RSI_GPIO_1_PSPI_CSN_1 BIT(1) 295 #define RSI_GPIO_2_HOST_WAKEUP_INTR BIT(2) 296 #define RSI_GPIO_3_PSPI_DATA_0 BIT(3) 297 #define RSI_GPIO_4_PSPI_DATA_1 BIT(4) 298 #define RSI_GPIO_5_PSPI_DATA_2 BIT(5) 299 #define RSI_GPIO_6_PSPI_DATA_3 BIT(6) 300 #define RSI_GPIO_7_I2C_SCL BIT(7) 301 #define RSI_GPIO_8_I2C_SDA BIT(8) 302 #define RSI_GPIO_9_UART1_RX BIT(9) 303 #define RSI_GPIO_10_UART1_TX BIT(10) 304 #define RSI_GPIO_11_UART1_RTS_I2S_CLK BIT(11) 305 #define RSI_GPIO_12_UART1_CTS_I2S_WS BIT(12) 306 #define RSI_GPIO_13_DBG_UART_RX_I2S_DIN BIT(13) 307 #define RSI_GPIO_14_DBG_UART_RX_I2S_DOUT BIT(14) 308 #define RSI_GPIO_15_LP_WAKEUP_BOOT_BYPASS BIT(15) 309 #define RSI_GPIO_16_LED_0 BIT(16) 310 #define RSI_GPIO_17_BTCOEX_WLAN_ACT_EXT_ANT_SEL BIT(17) 311 #define RSI_GPIO_18_BTCOEX_BT_PRIO_EXT_ANT_SEL BIT(18) 312 #define RSI_GPIO_19_BTCOEX_BT_ACT_EXT_ON_OFF BIT(19) 313 #define RSI_GPIO_20_RF_RESET BIT(20) 314 #define RSI_GPIO_21_SLEEP_IND_FROM_DEVICE BIT(21) 315 316 #define RSI_UNUSED_SOC_GPIO_BITMAP (RSI_GPIO_9_UART1_RX | \ 317 RSI_GPIO_10_UART1_TX | \ 318 RSI_GPIO_11_UART1_RTS_I2S_CLK | \ 319 RSI_GPIO_12_UART1_CTS_I2S_WS | \ 320 RSI_GPIO_13_DBG_UART_RX_I2S_DIN | \ 321 RSI_GPIO_14_DBG_UART_RX_I2S_DOUT | \ 322 RSI_GPIO_15_LP_WAKEUP_BOOT_BYPASS | \ 323 RSI_GPIO_17_BTCOEX_WLAN_ACT_EXT_ANT_SEL | \ 324 RSI_GPIO_18_BTCOEX_BT_PRIO_EXT_ANT_SEL | \ 325 RSI_GPIO_19_BTCOEX_BT_ACT_EXT_ON_OFF | \ 326 RSI_GPIO_21_SLEEP_IND_FROM_DEVICE) 327 328 #define RSI_UNUSED_ULP_GPIO_BITMAP (RSI_GPIO_MOTION_SENSOR_ULP_WAKEUP | \ 329 RSI_GPIO_SLEEP_IND_FROM_DEVICE | \ 330 RSI_GPIO_2_ULP | \ 331 RSI_GPIO_PUSH_BUTTON_ULP_WAKEUP); 332 struct rsi_config_vals { 333 __le16 len_qno; 334 u8 pkt_type; 335 u8 misc_flags; 336 __le16 reserved1[6]; 337 u8 lp_ps_handshake; 338 u8 ulp_ps_handshake; 339 u8 sleep_config_params; /* 0 for no handshake, 340 * 1 for GPIO based handshake, 341 * 2 packet handshake 342 */ 343 u8 unused_ulp_gpio; 344 __le32 unused_soc_gpio_bitmap; 345 u8 ext_pa_or_bt_coex_en; 346 u8 opermode; 347 u8 wlan_rf_pwr_mode; 348 u8 bt_rf_pwr_mode; 349 u8 zigbee_rf_pwr_mode; 350 u8 driver_mode; 351 u8 region_code; 352 u8 antenna_sel_val; 353 u8 reserved2[16]; 354 } __packed; 355 356 static inline u32 rsi_get_queueno(u8 *addr, u16 offset) 357 { 358 return (le16_to_cpu(*(__le16 *)&addr[offset]) & 0x7000) >> 12; 359 } 360 361 static inline u32 rsi_get_length(u8 *addr, u16 offset) 362 { 363 return (le16_to_cpu(*(__le16 *)&addr[offset])) & 0x0fff; 364 } 365 366 static inline u8 rsi_get_extended_desc(u8 *addr, u16 offset) 367 { 368 return le16_to_cpu(*((__le16 *)&addr[offset + 4])) & 0x00ff; 369 } 370 371 static inline u8 rsi_get_rssi(u8 *addr) 372 { 373 return *(u8 *)(addr + FRAME_DESC_SZ); 374 } 375 376 static inline u8 rsi_get_channel(u8 *addr) 377 { 378 return *(char *)(addr + 15); 379 } 380 381 static inline void rsi_set_len_qno(__le16 *addr, u16 len, u8 qno) 382 { 383 *addr = cpu_to_le16(len | ((qno & 7) << 12)); 384 } 385 386 int rsi_mgmt_pkt_recv(struct rsi_common *common, u8 *msg); 387 int rsi_set_vap_capabilities(struct rsi_common *common, enum opmode mode, 388 u8 vap_status); 389 int rsi_send_aggregation_params_frame(struct rsi_common *common, u16 tid, 390 u16 ssn, u8 buf_size, u8 event); 391 int rsi_hal_load_key(struct rsi_common *common, u8 *data, u16 key_len, 392 u8 key_type, u8 key_id, u32 cipher); 393 int rsi_set_channel(struct rsi_common *common, 394 struct ieee80211_channel *channel); 395 int rsi_send_block_unblock_frame(struct rsi_common *common, bool event); 396 void rsi_inform_bss_status(struct rsi_common *common, u8 status, 397 const u8 *bssid, u8 qos_enable, u16 aid); 398 void rsi_indicate_pkt_to_os(struct rsi_common *common, struct sk_buff *skb); 399 int rsi_mac80211_attach(struct rsi_common *common); 400 void rsi_indicate_tx_status(struct rsi_hw *common, struct sk_buff *skb, 401 int status); 402 bool rsi_is_cipher_wep(struct rsi_common *common); 403 void rsi_core_qos_processor(struct rsi_common *common); 404 void rsi_core_xmit(struct rsi_common *common, struct sk_buff *skb); 405 int rsi_send_mgmt_pkt(struct rsi_common *common, struct sk_buff *skb); 406 int rsi_send_data_pkt(struct rsi_common *common, struct sk_buff *skb); 407 int rsi_band_check(struct rsi_common *common); 408 int rsi_send_rx_filter_frame(struct rsi_common *common, u16 rx_filter_word); 409 int rsi_send_radio_params_update(struct rsi_common *common); 410 int rsi_set_antenna(struct rsi_common *common, u8 antenna); 411 #endif 412