1 /** 2 * Copyright (c) 2014 Redpine Signals Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __RSI_MAIN_H__ 18 #define __RSI_MAIN_H__ 19 20 #include <linux/string.h> 21 #include <linux/skbuff.h> 22 #include <net/mac80211.h> 23 24 #define ERR_ZONE BIT(0) /* For Error Msgs */ 25 #define INFO_ZONE BIT(1) /* For General Status Msgs */ 26 #define INIT_ZONE BIT(2) /* For Driver Init Seq Msgs */ 27 #define MGMT_TX_ZONE BIT(3) /* For TX Mgmt Path Msgs */ 28 #define MGMT_RX_ZONE BIT(4) /* For RX Mgmt Path Msgs */ 29 #define DATA_TX_ZONE BIT(5) /* For TX Data Path Msgs */ 30 #define DATA_RX_ZONE BIT(6) /* For RX Data Path Msgs */ 31 #define FSM_ZONE BIT(7) /* For State Machine Msgs */ 32 #define ISR_ZONE BIT(8) /* For Interrupt Msgs */ 33 34 enum RSI_FSM_STATES { 35 FSM_FW_NOT_LOADED, 36 FSM_CARD_NOT_READY, 37 FSM_COMMON_DEV_PARAMS_SENT, 38 FSM_BOOT_PARAMS_SENT, 39 FSM_EEPROM_READ_MAC_ADDR, 40 FSM_RESET_MAC_SENT, 41 FSM_RADIO_CAPS_SENT, 42 FSM_BB_RF_PROG_SENT, 43 FSM_MAC_INIT_DONE 44 }; 45 46 extern u32 rsi_zone_enabled; 47 extern __printf(2, 3) void rsi_dbg(u32 zone, const char *fmt, ...); 48 49 #define RSI_MAX_VIFS 1 50 #define NUM_EDCA_QUEUES 4 51 #define IEEE80211_ADDR_LEN 6 52 #define FRAME_DESC_SZ 16 53 #define MIN_802_11_HDR_LEN 24 54 55 #define DATA_QUEUE_WATER_MARK 400 56 #define MIN_DATA_QUEUE_WATER_MARK 300 57 #define MULTICAST_WATER_MARK 200 58 #define MAC_80211_HDR_FRAME_CONTROL 0 59 #define WME_NUM_AC 4 60 #define NUM_SOFT_QUEUES 5 61 #define MAX_HW_QUEUES 8 62 #define INVALID_QUEUE 0xff 63 #define MAX_CONTINUOUS_VO_PKTS 8 64 #define MAX_CONTINUOUS_VI_PKTS 4 65 66 /* Queue information */ 67 #define RSI_COEX_Q 0x0 68 #define RSI_WIFI_MGMT_Q 0x4 69 #define RSI_WIFI_DATA_Q 0x5 70 #define IEEE80211_MGMT_FRAME 0x00 71 #define IEEE80211_CTL_FRAME 0x04 72 73 #define IEEE80211_QOS_TID 0x0f 74 #define IEEE80211_NONQOS_TID 16 75 76 #define MAX_DEBUGFS_ENTRIES 4 77 78 #define TID_TO_WME_AC(_tid) ( \ 79 ((_tid) == 0 || (_tid) == 3) ? BE_Q : \ 80 ((_tid) < 3) ? BK_Q : \ 81 ((_tid) < 6) ? VI_Q : \ 82 VO_Q) 83 84 #define WME_AC(_q) ( \ 85 ((_q) == BK_Q) ? IEEE80211_AC_BK : \ 86 ((_q) == BE_Q) ? IEEE80211_AC_BE : \ 87 ((_q) == VI_Q) ? IEEE80211_AC_VI : \ 88 IEEE80211_AC_VO) 89 90 #define RSI_DEV_9113 1 91 92 struct version_info { 93 u16 major; 94 u16 minor; 95 u16 release_num; 96 u16 patch_num; 97 } __packed; 98 99 struct skb_info { 100 s8 rssi; 101 u32 flags; 102 u16 channel; 103 s8 tid; 104 s8 sta_id; 105 }; 106 107 enum edca_queue { 108 BK_Q, 109 BE_Q, 110 VI_Q, 111 VO_Q, 112 MGMT_SOFT_Q 113 }; 114 115 struct security_info { 116 bool security_enable; 117 u32 ptk_cipher; 118 u32 gtk_cipher; 119 }; 120 121 struct wmm_qinfo { 122 s32 weight; 123 s32 wme_params; 124 s32 pkt_contended; 125 s32 txop; 126 }; 127 128 struct transmit_q_stats { 129 u32 total_tx_pkt_send[NUM_EDCA_QUEUES + 1]; 130 u32 total_tx_pkt_freed[NUM_EDCA_QUEUES + 1]; 131 }; 132 133 struct vif_priv { 134 bool is_ht; 135 bool sgi; 136 u16 seq_start; 137 }; 138 139 struct rsi_event { 140 atomic_t event_condition; 141 wait_queue_head_t event_queue; 142 }; 143 144 struct rsi_thread { 145 void (*thread_function)(void *); 146 struct completion completion; 147 struct task_struct *task; 148 struct rsi_event event; 149 atomic_t thread_done; 150 }; 151 152 struct cqm_info { 153 s8 last_cqm_event_rssi; 154 int rssi_thold; 155 u32 rssi_hyst; 156 }; 157 158 struct rsi_hw; 159 160 struct rsi_common { 161 struct rsi_hw *priv; 162 struct vif_priv vif_info[RSI_MAX_VIFS]; 163 164 bool mgmt_q_block; 165 struct version_info driver_ver; 166 struct version_info fw_ver; 167 168 struct rsi_thread tx_thread; 169 struct sk_buff_head tx_queue[NUM_EDCA_QUEUES + 1]; 170 /* Mutex declaration */ 171 struct mutex mutex; 172 /* Mutex used between tx/rx threads */ 173 struct mutex tx_rxlock; 174 u8 endpoint; 175 176 /* Channel/band related */ 177 u8 band; 178 u8 channel_width; 179 180 u16 rts_threshold; 181 u16 bitrate_mask[2]; 182 u32 fixedrate_mask[2]; 183 184 u8 rf_reset; 185 struct transmit_q_stats tx_stats; 186 struct security_info secinfo; 187 struct wmm_qinfo tx_qinfo[NUM_EDCA_QUEUES]; 188 struct ieee80211_tx_queue_params edca_params[NUM_EDCA_QUEUES]; 189 u8 mac_addr[IEEE80211_ADDR_LEN]; 190 191 /* state related */ 192 u32 fsm_state; 193 bool init_done; 194 u8 bb_rf_prog_count; 195 bool iface_down; 196 197 /* Generic */ 198 u8 channel; 199 u8 *rx_data_pkt; 200 u8 mac_id; 201 u8 radio_id; 202 u16 rate_pwr[20]; 203 u16 min_rate; 204 205 /* WMM algo related */ 206 u8 selected_qnum; 207 u32 pkt_cnt; 208 u8 min_weight; 209 210 /* bgscan related */ 211 struct cqm_info cqm_info; 212 213 bool hw_data_qs_blocked; 214 u8 driver_mode; 215 u8 coex_mode; 216 u16 oper_mode; 217 u8 lp_ps_handshake_mode; 218 u8 ulp_ps_handshake_mode; 219 u8 rf_power_val; 220 u8 wlan_rf_power_mode; 221 u8 obm_ant_sel_val; 222 int tx_power; 223 u8 ant_in_use; 224 }; 225 226 enum host_intf { 227 RSI_HOST_INTF_SDIO = 0, 228 RSI_HOST_INTF_USB 229 }; 230 231 struct rsi_hw { 232 struct rsi_common *priv; 233 u8 device_model; 234 struct ieee80211_hw *hw; 235 struct ieee80211_vif *vifs[RSI_MAX_VIFS]; 236 struct ieee80211_tx_queue_params edca_params[NUM_EDCA_QUEUES]; 237 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 238 239 struct device *device; 240 u8 sc_nvifs; 241 242 enum host_intf rsi_host_intf; 243 u16 block_size; 244 u32 usb_buffer_status_reg; 245 #ifdef CONFIG_RSI_DEBUGFS 246 struct rsi_debugfs *dfsentry; 247 u8 num_debugfs_entries; 248 #endif 249 char *fw_file_name; 250 struct timer_list bl_cmd_timer; 251 bool blcmd_timer_expired; 252 u32 flash_capacity; 253 u8 dfs_region; 254 void *rsi_dev; 255 struct rsi_host_intf_ops *host_intf_ops; 256 int (*check_hw_queue_status)(struct rsi_hw *adapter, u8 q_num); 257 int (*rx_urb_submit)(struct rsi_hw *adapter); 258 int (*determine_event_timeout)(struct rsi_hw *adapter); 259 }; 260 261 struct rsi_host_intf_ops { 262 int (*read_pkt)(struct rsi_hw *adapter, u8 *pkt, u32 len); 263 int (*write_pkt)(struct rsi_hw *adapter, u8 *pkt, u32 len); 264 int (*master_access_msword)(struct rsi_hw *adapter, u16 ms_word); 265 int (*read_reg_multiple)(struct rsi_hw *adapter, u32 addr, 266 u8 *data, u16 count); 267 int (*write_reg_multiple)(struct rsi_hw *adapter, u32 addr, 268 u8 *data, u16 count); 269 int (*master_reg_read)(struct rsi_hw *adapter, u32 addr, 270 u32 *read_buf, u16 size); 271 int (*master_reg_write)(struct rsi_hw *adapter, 272 unsigned long addr, unsigned long data, 273 u16 size); 274 int (*load_data_master_write)(struct rsi_hw *adapter, u32 addr, 275 u32 instructions_size, u16 block_size, 276 u8 *fw); 277 }; 278 #endif 279