1 /**
2  * Copyright (c) 2014 Redpine Signals Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef __RSI_BOOTPARAMS_HEADER_H__
18 #define __RSI_BOOTPARAMS_HEADER_H__
19 
20 #define CRYSTAL_GOOD_TIME                BIT(0)
21 #define BOOTUP_MODE_INFO                 BIT(1)
22 #define WIFI_TAPLL_CONFIGS               BIT(5)
23 #define WIFI_PLL960_CONFIGS              BIT(6)
24 #define WIFI_AFEPLL_CONFIGS              BIT(7)
25 #define WIFI_SWITCH_CLK_CONFIGS          BIT(8)
26 
27 #define TA_PLL_M_VAL_20                  9
28 #define TA_PLL_N_VAL_20                  0
29 #define TA_PLL_P_VAL_20                  4
30 
31 #define PLL960_M_VAL_20                  0x14
32 #define PLL960_N_VAL_20                  0
33 #define PLL960_P_VAL_20                  5
34 
35 #define UMAC_CLK_40MHZ                   80
36 
37 #define TA_PLL_M_VAL_40                  9
38 #define TA_PLL_N_VAL_40                  0
39 #define TA_PLL_P_VAL_40                  4
40 
41 #define PLL960_M_VAL_40                  0x14
42 #define PLL960_N_VAL_40                  0
43 #define PLL960_P_VAL_40                  5
44 
45 #define UMAC_CLK_20BW \
46 	(((TA_PLL_M_VAL_20 + 1) * 40) / \
47 	 ((TA_PLL_N_VAL_20 + 1) * (TA_PLL_P_VAL_20 + 1)))
48 #define VALID_20 \
49 	(WIFI_TAPLL_CONFIGS | WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | \
50 	 WIFI_SWITCH_CLK_CONFIGS | BOOTUP_MODE_INFO | CRYSTAL_GOOD_TIME)
51 #define UMAC_CLK_40BW   \
52 	(((TA_PLL_M_VAL_40 + 1) * 40) / \
53 	 ((TA_PLL_N_VAL_40 + 1) * (TA_PLL_P_VAL_40 + 1)))
54 #define VALID_40 \
55 	(WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | WIFI_SWITCH_CLK_CONFIGS | \
56 	 WIFI_TAPLL_CONFIGS | CRYSTAL_GOOD_TIME | BOOTUP_MODE_INFO)
57 
58 /* structure to store configs related to TAPLL programming */
59 struct tapll_info {
60 	__le16 pll_reg_1;
61 	__le16 pll_reg_2;
62 } __packed;
63 
64 /* structure to store configs related to PLL960 programming */
65 struct pll960_info {
66 	__le16 pll_reg_1;
67 	__le16 pll_reg_2;
68 	__le16 pll_reg_3;
69 } __packed;
70 
71 /* structure to store configs related to AFEPLL programming */
72 struct afepll_info {
73 	__le16 pll_reg;
74 } __packed;
75 
76 /* structure to store configs related to pll configs */
77 struct pll_config {
78 	struct tapll_info tapll_info_g;
79 	struct pll960_info pll960_info_g;
80 	struct afepll_info afepll_info_g;
81 } __packed;
82 
83 /* structure to store configs related to UMAC clk programming */
84 struct switch_clk {
85 	__le16 switch_clk_info;
86 	/* If switch_bbp_lmac_clk_reg is set then this value will be programmed
87 	 * into reg
88 	 */
89 	__le16 bbp_lmac_clk_reg_val;
90 	/* if switch_umac_clk is set then this value will be programmed */
91 	__le16 umac_clock_reg_config;
92 	/* if switch_qspi_clk is set then this value will be programmed */
93 	__le16 qspi_uart_clock_reg_config;
94 } __packed;
95 
96 struct device_clk_info {
97 	struct pll_config pll_config_g;
98 	struct switch_clk switch_clk_g;
99 } __packed;
100 
101 struct bootup_params {
102 	__le16 magic_number;
103 	__le16 crystal_good_time;
104 	__le32 valid;
105 	__le32 reserved_for_valids;
106 	__le16 bootup_mode_info;
107 	/* configuration used for digital loop back */
108 	__le16 digital_loop_back_params;
109 	__le16 rtls_timestamp_en;
110 	__le16 host_spi_intr_cfg;
111 	struct device_clk_info device_clk_info[3];
112 	/* ulp buckboost wait time  */
113 	__le32 buckboost_wakeup_cnt;
114 	/* pmu wakeup wait time & WDT EN info */
115 	__le16 pmu_wakeup_wait;
116 	u8 shutdown_wait_time;
117 	/* Sleep clock source selection */
118 	u8 pmu_slp_clkout_sel;
119 	/* WDT programming values */
120 	__le32 wdt_prog_value;
121 	/* WDT soc reset delay */
122 	__le32 wdt_soc_rst_delay;
123 	/* dcdc modes configs */
124 	__le32 dcdc_operation_mode;
125 	__le32 soc_reset_wait_cnt;
126 	__le32 waiting_time_at_fresh_sleep;
127 	__le32 max_threshold_to_avoid_sleep;
128 	u8 beacon_resedue_alg_en;
129 } __packed;
130 #endif
131