1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_TXRX_H__ 6 #define __RTW89_TXRX_H__ 7 8 #include "debug.h" 9 10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7) 11 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0) 12 #define DATA_RATE_MODE_NON_HT 0x0 13 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0) 14 #define DATA_RATE_MODE_HT 0x1 15 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4) 16 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0) 17 #define DATA_RATE_MODE_VHT 0x2 18 #define DATA_RATE_MODE_HE 0x3 19 #define GET_DATA_RATE_MODE(r) FIELD_GET(DATA_RATE_MODE_CTRL_MASK, r) 20 #define GET_DATA_RATE_NOT_HT_IDX(r) FIELD_GET(DATA_RATE_NOT_HT_IDX_MASK, r) 21 #define GET_DATA_RATE_HT_IDX(r) FIELD_GET(DATA_RATE_HT_IDX_MASK, r) 22 #define GET_DATA_RATE_VHT_HE_IDX(r) FIELD_GET(DATA_RATE_VHT_HE_IDX_MASK, r) 23 #define GET_DATA_RATE_NSS(r) FIELD_GET(DATA_RATE_VHT_HE_NSS_MASK, r) 24 25 /* TX WD BODY DWORD 0 */ 26 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24) 27 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24) 28 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23) 29 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22) 30 #define RTW89_TXWD_BODY0_FW_DL BIT(20) 31 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16) 32 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11) 33 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7) 34 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5) 35 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2) 36 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0) 37 38 /* TX WD BODY DWORD 1 */ 39 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26) 40 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16) 41 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4) 42 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0) 43 44 /* TX WD BODY DWORD 2 */ 45 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24) 46 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23) 47 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17) 48 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0) 49 50 /* TX WD BODY DWORD 3 */ 51 #define RTW89_TXWD_BODY3_BK BIT(13) 52 #define RTW89_TXWD_BODY3_AGG_EN BIT(12) 53 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0) 54 55 /* TX WD BODY DWORD 4 */ 56 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24) 57 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16) 58 59 /* TX WD BODY DWORD 5 */ 60 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24) 61 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16) 62 #define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8) 63 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0) 64 65 /* TX WD BODY DWORD 6 (V1) */ 66 67 /* TX WD BODY DWORD 7 (V1) */ 68 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31) 69 #define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28) 70 #define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25) 71 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16) 72 73 /* TX WD INFO DWORD 0 */ 74 #define RTW89_TXWD_INFO0_USE_RATE BIT(30) 75 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28) 76 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25) 77 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16) 78 #define RTW89_TXWD_INFO0_DATA_ER BIT(15) 79 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10) 80 #define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8) 81 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4) 82 83 /* TX WD INFO DWORD 1 */ 84 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16) 85 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14) 86 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0) 87 88 /* TX WD INFO DWORD 2 */ 89 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18) 90 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9) 91 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8) 92 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8) 93 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0) 94 95 /* TX WD INFO DWORD 3 */ 96 97 /* TX WD INFO DWORD 4 */ 98 #define RTW89_TXWD_INFO4_RTS_EN BIT(27) 99 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31) 100 101 /* TX WD INFO DWORD 5 */ 102 103 /* RX WD dword0 */ 104 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0) 105 #define AX_RXD_SHIFT_MASK GENMASK(15, 14) 106 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16) 107 #define AX_RXD_BB_SEL BIT(22) 108 #define AX_RXD_MAC_INFO_VLD BIT(23) 109 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24) 110 #define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28) 111 #define AX_RXD_LONG_RXD BIT(31) 112 113 /* RX WD dword1 */ 114 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0) 115 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4) 116 #define AX_RXD_SR_EN BIT(7) 117 #define AX_RXD_USER_ID_MASK GENMASK(15, 8) 118 #define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8) 119 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16) 120 #define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25) 121 #define AX_RXD_NON_SRG_PPDU BIT(28) 122 #define AX_RXD_INTER_PPDU BIT(29) 123 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14) 124 #define AX_RXD_INTER_PPDU_v1 BIT(15) 125 #define AX_RXD_BW_MASK GENMASK(31, 30) 126 #define AX_RXD_BW_v1_MASK GENMASK(31, 29) 127 128 /* RX WD dword2 */ 129 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0) 130 131 /* RX WD dword3 */ 132 #define AX_RXD_A1_MATCH BIT(0) 133 #define AX_RXD_SW_DEC BIT(1) 134 #define AX_RXD_HW_DEC BIT(2) 135 #define AX_RXD_AMPDU BIT(3) 136 #define AX_RXD_AMPDU_END_PKT BIT(4) 137 #define AX_RXD_AMSDU BIT(5) 138 #define AX_RXD_AMSDU_CUT BIT(6) 139 #define AX_RXD_LAST_MSDU BIT(7) 140 #define AX_RXD_BYPASS BIT(8) 141 #define AX_RXD_CRC32_ERR BIT(9) 142 #define AX_RXD_ICV_ERR BIT(10) 143 #define AX_RXD_MAGIC_WAKE BIT(11) 144 #define AX_RXD_UNICAST_WAKE BIT(12) 145 #define AX_RXD_PATTERN_WAKE BIT(13) 146 #define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14) 147 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16) 148 #define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21) 149 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24) 150 #define AX_RXD_WITH_LLC BIT(25) 151 #define AX_RXD_RX_STATISTICS BIT(26) 152 153 /* RX WD dword4 */ 154 #define AX_RXD_TYPE_MASK GENMASK(1, 0) 155 #define AX_RXD_MC BIT(2) 156 #define AX_RXD_BC BIT(3) 157 #define AX_RXD_MD BIT(4) 158 #define AX_RXD_MF BIT(5) 159 #define AX_RXD_PWR BIT(6) 160 #define AX_RXD_QOS BIT(7) 161 #define AX_RXD_TID_MASK GENMASK(11, 8) 162 #define AX_RXD_EOSP BIT(12) 163 #define AX_RXD_HTC BIT(13) 164 #define AX_RXD_QNULL BIT(14) 165 #define AX_RXD_SEQ_MASK GENMASK(27, 16) 166 #define AX_RXD_FRAG_MASK GENMASK(31, 28) 167 168 /* RX WD dword5 */ 169 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0) 170 #define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8) 171 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16) 172 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24) 173 #define AX_RXD_ADDR_CAM_VLD BIT(28) 174 #define AX_RXD_ADDR_FWD_EN BIT(29) 175 #define AX_RXD_RX_PL_MATCH BIT(30) 176 177 /* RX WD dword6 */ 178 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0) 179 180 /* RX WD dword7 */ 181 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0) 182 #define AX_RXD_SMART_ANT BIT(16) 183 #define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17) 184 #define AX_RXD_HDR_CNV BIT(21) 185 #define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22) 186 #define AX_RXD_BIP_KEYID BIT(27) 187 #define AX_RXD_BIP_ENC BIT(28) 188 189 struct rtw89_rxinfo_user { 190 __le32 w0; 191 }; 192 193 #define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0) 194 #define RTW89_RXINFO_USER_DATA BIT(1) 195 #define RTW89_RXINFO_USER_CTRL BIT(2) 196 #define RTW89_RXINFO_USER_MGMT BIT(3) 197 #define RTW89_RXINFO_USER_BCM BIT(4) 198 #define RTW89_RXINFO_USER_MACID GENMASK(15, 8) 199 200 struct rtw89_rxinfo { 201 __le32 w0; 202 __le32 w1; 203 struct rtw89_rxinfo_user user[]; 204 } __packed; 205 206 #define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0) 207 #define RTW89_RXINFO_W0_FW_DEFINE GENMASK(15, 8) 208 #define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16) 209 #define RTW89_RXINFO_W0_IS_TO_SELF BIT(28) 210 #define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29) 211 #define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30) 212 #define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0) 213 #define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16) 214 215 struct rtw89_phy_sts_hdr { 216 __le32 w0; 217 __le32 w1; 218 } __packed; 219 220 #define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0) 221 #define RTW89_PHY_STS_HDR_W0_LEN GENMASK(15, 8) 222 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24) 223 #define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0) 224 #define RTW89_PHY_STS_HDR_W1_RSSI_B GENMASK(15, 8) 225 #define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16) 226 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24) 227 228 struct rtw89_phy_sts_iehdr { 229 __le32 w0; 230 }; 231 232 #define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0) 233 #define RTW89_PHY_STS_IEHDR_LEN GENMASK(11, 5) 234 235 struct rtw89_phy_sts_ie0 { 236 __le32 w0; 237 __le32 w1; 238 __le32 w2; 239 } __packed; 240 241 #define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16) 242 #define RTW89_PHY_STS_IE01_W1_FD_CFO GENMASK(19, 8) 243 #define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20) 244 #define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0) 245 #define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8) 246 #define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16) 247 248 enum rtw89_tx_channel { 249 RTW89_TXCH_ACH0 = 0, 250 RTW89_TXCH_ACH1 = 1, 251 RTW89_TXCH_ACH2 = 2, 252 RTW89_TXCH_ACH3 = 3, 253 RTW89_TXCH_ACH4 = 4, 254 RTW89_TXCH_ACH5 = 5, 255 RTW89_TXCH_ACH6 = 6, 256 RTW89_TXCH_ACH7 = 7, 257 RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */ 258 RTW89_TXCH_CH9 = 9, /* HI Band 0 */ 259 RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */ 260 RTW89_TXCH_CH11 = 11, /* HI Band 1 */ 261 RTW89_TXCH_CH12 = 12, /* FW CMD */ 262 263 /* keep last */ 264 RTW89_TXCH_NUM, 265 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1 266 }; 267 268 enum rtw89_rx_channel { 269 RTW89_RXCH_RXQ = 0, 270 RTW89_RXCH_RPQ = 1, 271 272 /* keep last */ 273 RTW89_RXCH_NUM, 274 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1 275 }; 276 277 enum rtw89_tx_qsel { 278 RTW89_TX_QSEL_BE_0 = 0x00, 279 RTW89_TX_QSEL_BK_0 = 0x01, 280 RTW89_TX_QSEL_VI_0 = 0x02, 281 RTW89_TX_QSEL_VO_0 = 0x03, 282 RTW89_TX_QSEL_BE_1 = 0x04, 283 RTW89_TX_QSEL_BK_1 = 0x05, 284 RTW89_TX_QSEL_VI_1 = 0x06, 285 RTW89_TX_QSEL_VO_1 = 0x07, 286 RTW89_TX_QSEL_BE_2 = 0x08, 287 RTW89_TX_QSEL_BK_2 = 0x09, 288 RTW89_TX_QSEL_VI_2 = 0x0a, 289 RTW89_TX_QSEL_VO_2 = 0x0b, 290 RTW89_TX_QSEL_BE_3 = 0x0c, 291 RTW89_TX_QSEL_BK_3 = 0x0d, 292 RTW89_TX_QSEL_VI_3 = 0x0e, 293 RTW89_TX_QSEL_VO_3 = 0x0f, 294 RTW89_TX_QSEL_B0_BCN = 0x10, 295 RTW89_TX_QSEL_B0_HI = 0x11, 296 RTW89_TX_QSEL_B0_MGMT = 0x12, 297 RTW89_TX_QSEL_B0_NOPS = 0x13, 298 RTW89_TX_QSEL_B0_MGMT_FAST = 0x14, 299 /* reserved */ 300 /* reserved */ 301 /* reserved */ 302 RTW89_TX_QSEL_B1_BCN = 0x18, 303 RTW89_TX_QSEL_B1_HI = 0x19, 304 RTW89_TX_QSEL_B1_MGMT = 0x1a, 305 RTW89_TX_QSEL_B1_NOPS = 0x1b, 306 RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c, 307 /* reserved */ 308 /* reserved */ 309 /* reserved */ 310 }; 311 312 static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) 313 { 314 switch (tid) { 315 default: 316 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 317 fallthrough; 318 case 0: 319 case 3: 320 return RTW89_TX_QSEL_BE_0; 321 case 1: 322 case 2: 323 return RTW89_TX_QSEL_BK_0; 324 case 4: 325 case 5: 326 return RTW89_TX_QSEL_VI_0; 327 case 6: 328 case 7: 329 return RTW89_TX_QSEL_VO_0; 330 } 331 } 332 333 static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 334 { 335 switch (qsel) { 336 default: 337 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 338 fallthrough; 339 case RTW89_TX_QSEL_BE_0: 340 return RTW89_TXCH_ACH0; 341 case RTW89_TX_QSEL_BK_0: 342 return RTW89_TXCH_ACH1; 343 case RTW89_TX_QSEL_VI_0: 344 return RTW89_TXCH_ACH2; 345 case RTW89_TX_QSEL_VO_0: 346 return RTW89_TXCH_ACH3; 347 case RTW89_TX_QSEL_B0_MGMT: 348 return RTW89_TXCH_CH8; 349 case RTW89_TX_QSEL_B0_HI: 350 return RTW89_TXCH_CH9; 351 case RTW89_TX_QSEL_B1_MGMT: 352 return RTW89_TXCH_CH10; 353 case RTW89_TX_QSEL_B1_HI: 354 return RTW89_TXCH_CH11; 355 } 356 } 357 358 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid) 359 { 360 switch (tid) { 361 case 3: 362 case 2: 363 case 5: 364 case 7: 365 return 1; 366 default: 367 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 368 fallthrough; 369 case 0: 370 case 1: 371 case 4: 372 case 6: 373 return 0; 374 } 375 } 376 377 #endif 378