1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_TXRX_H__ 6 #define __RTW89_TXRX_H__ 7 8 #include "debug.h" 9 10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7) 11 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0) 12 #define DATA_RATE_MODE_NON_HT 0x0 13 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0) 14 #define DATA_RATE_MODE_HT 0x1 15 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4) 16 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0) 17 #define DATA_RATE_MODE_VHT 0x2 18 #define DATA_RATE_MODE_HE 0x3 19 #define GET_DATA_RATE_MODE(r) FIELD_GET(DATA_RATE_MODE_CTRL_MASK, r) 20 #define GET_DATA_RATE_NOT_HT_IDX(r) FIELD_GET(DATA_RATE_NOT_HT_IDX_MASK, r) 21 #define GET_DATA_RATE_HT_IDX(r) FIELD_GET(DATA_RATE_HT_IDX_MASK, r) 22 #define GET_DATA_RATE_VHT_HE_IDX(r) FIELD_GET(DATA_RATE_VHT_HE_IDX_MASK, r) 23 #define GET_DATA_RATE_NSS(r) FIELD_GET(DATA_RATE_VHT_HE_NSS_MASK, r) 24 25 /* TX WD BODY DWORD 0 */ 26 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24) 27 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23) 28 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22) 29 #define RTW89_TXWD_BODY0_FW_DL BIT(20) 30 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16) 31 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11) 32 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7) 33 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5) 34 35 /* TX WD BODY DWORD 1 */ 36 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16) 37 38 /* TX WD BODY DWORD 2 */ 39 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24) 40 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23) 41 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17) 42 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0) 43 44 /* TX WD BODY DWORD 3 */ 45 #define RTW89_TXWD_BODY3_BK BIT(13) 46 #define RTW89_TXWD_BODY3_AGG_EN BIT(12) 47 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0) 48 49 /* TX WD BODY DWORD 4 */ 50 51 /* TX WD BODY DWORD 5 */ 52 53 /* TX WD INFO DWORD 0 */ 54 #define RTW89_TXWD_INFO0_USE_RATE BIT(30) 55 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28) 56 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25) 57 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16) 58 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10) 59 60 /* TX WD INFO DWORD 1 */ 61 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16) 62 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14) 63 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0) 64 65 /* TX WD INFO DWORD 2 */ 66 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18) 67 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9) 68 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8) 69 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0) 70 71 /* TX WD INFO DWORD 3 */ 72 73 /* TX WD INFO DWORD 4 */ 74 #define RTW89_TXWD_INFO4_RTS_EN BIT(27) 75 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31) 76 77 /* TX WD INFO DWORD 5 */ 78 79 /* RX DESC helpers */ 80 /* Short Descriptor */ 81 #define RTW89_GET_RXWD_LONG_RXD(rxdesc) \ 82 le32_get_bits((rxdesc)->dword0, BIT(31)) 83 #define RTW89_GET_RXWD_DRV_INFO_SIZE(rxdesc) \ 84 le32_get_bits((rxdesc)->dword0, GENMASK(30, 28)) 85 #define RTW89_GET_RXWD_RPKT_TYPE(rxdesc) \ 86 le32_get_bits((rxdesc)->dword0, GENMASK(27, 24)) 87 #define RTW89_GET_RXWD_MAC_INFO_VALID(rxdesc) \ 88 le32_get_bits((rxdesc)->dword0, BIT(23)) 89 #define RTW89_GET_RXWD_BB_SEL(rxdesc) \ 90 le32_get_bits((rxdesc)->dword0, BIT(22)) 91 #define RTW89_GET_RXWD_HD_IV_LEN(rxdesc) \ 92 le32_get_bits((rxdesc)->dword0, GENMASK(21, 16)) 93 #define RTW89_GET_RXWD_SHIFT(rxdesc) \ 94 le32_get_bits((rxdesc)->dword0, GENMASK(15, 14)) 95 #define RTW89_GET_RXWD_PKT_SIZE(rxdesc) \ 96 le32_get_bits((rxdesc)->dword0, GENMASK(13, 0)) 97 #define RTW89_GET_RXWD_BW(rxdesc) \ 98 le32_get_bits((rxdesc)->dword1, GENMASK(31, 30)) 99 #define RTW89_GET_RXWD_GI_LTF(rxdesc) \ 100 le32_get_bits((rxdesc)->dword1, GENMASK(27, 25)) 101 #define RTW89_GET_RXWD_DATA_RATE(rxdesc) \ 102 le32_get_bits((rxdesc)->dword1, GENMASK(24, 16)) 103 #define RTW89_GET_RXWD_USER_ID(rxdesc) \ 104 le32_get_bits((rxdesc)->dword1, GENMASK(15, 8)) 105 #define RTW89_GET_RXWD_SR_EN(rxdesc) \ 106 le32_get_bits((rxdesc)->dword1, BIT(7)) 107 #define RTW89_GET_RXWD_PPDU_CNT(rxdesc) \ 108 le32_get_bits((rxdesc)->dword1, GENMASK(6, 4)) 109 #define RTW89_GET_RXWD_PPDU_TYPE(rxdesc) \ 110 le32_get_bits((rxdesc)->dword1, GENMASK(3, 0)) 111 #define RTW89_GET_RXWD_FREE_RUN_CNT(rxdesc) \ 112 le32_get_bits((rxdesc)->dword2, GENMASK(31, 0)) 113 #define RTW89_GET_RXWD_ICV_ERR(rxdesc) \ 114 le32_get_bits((rxdesc)->dword3, BIT(10)) 115 #define RTW89_GET_RXWD_CRC32_ERR(rxdesc) \ 116 le32_get_bits((rxdesc)->dword3, BIT(9)) 117 #define RTW89_GET_RXWD_HW_DEC(rxdesc) \ 118 le32_get_bits((rxdesc)->dword3, BIT(2)) 119 #define RTW89_GET_RXWD_SW_DEC(rxdesc) \ 120 le32_get_bits((rxdesc)->dword3, BIT(1)) 121 #define RTW89_GET_RXWD_A1_MATCH(rxdesc) \ 122 le32_get_bits((rxdesc)->dword3, BIT(0)) 123 124 /* Long Descriptor */ 125 #define RTW89_GET_RXWD_FRAG(rxdesc) \ 126 le32_get_bits((rxdesc)->dword4, GENMASK(31, 28)) 127 #define RTW89_GET_RXWD_SEQ(rxdesc) \ 128 le32_get_bits((rxdesc)->dword4, GENMASK(27, 16)) 129 #define RTW89_GET_RXWD_TYPE(rxdesc) \ 130 le32_get_bits((rxdesc)->dword4, GENMASK(1, 0)) 131 #define RTW89_GET_RXWD_ADDR_CAM_VLD(rxdesc) \ 132 le32_get_bits((rxdesc)->dword5, BIT(28)) 133 #define RTW89_GET_RXWD_RX_PL_ID(rxdesc) \ 134 le32_get_bits((rxdesc)->dword5, GENMASK(27, 24)) 135 #define RTW89_GET_RXWD_MAC_ID(rxdesc) \ 136 le32_get_bits((rxdesc)->dword5, GENMASK(23, 16)) 137 #define RTW89_GET_RXWD_ADDR_CAM_ID(rxdesc) \ 138 le32_get_bits((rxdesc)->dword5, GENMASK(15, 8)) 139 #define RTW89_GET_RXWD_SEC_CAM_ID(rxdesc) \ 140 le32_get_bits((rxdesc)->dword5, GENMASK(7, 0)) 141 142 #define RTW89_GET_RXINFO_USR_NUM(rpt) \ 143 le32_get_bits(*((__le32 *)rpt), GENMASK(3, 0)) 144 #define RTW89_GET_RXINFO_FW_DEFINE(rpt) \ 145 le32_get_bits(*((__le32 *)rpt), GENMASK(15, 8)) 146 #define RTW89_GET_RXINFO_LSIG_LEN(rpt) \ 147 le32_get_bits(*((__le32 *)rpt), GENMASK(27, 16)) 148 #define RTW89_GET_RXINFO_IS_TO_SELF(rpt) \ 149 le32_get_bits(*((__le32 *)rpt), BIT(28)) 150 #define RTW89_GET_RXINFO_RX_CNT_VLD(rpt) \ 151 le32_get_bits(*((__le32 *)rpt), BIT(29)) 152 #define RTW89_GET_RXINFO_LONG_RXD(rpt) \ 153 le32_get_bits(*((__le32 *)rpt), GENMASK(31, 30)) 154 #define RTW89_GET_RXINFO_SERVICE(rpt) \ 155 le32_get_bits(*((__le32 *)(rpt) + 1), GENMASK(15, 0)) 156 #define RTW89_GET_RXINFO_PLCP_LEN(rpt) \ 157 le32_get_bits(*((__le32 *)(rpt) + 1), GENMASK(23, 16)) 158 #define RTW89_GET_RXINFO_MAC_ID_VALID(rpt, usr) \ 159 le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(0)) 160 #define RTW89_GET_RXINFO_DATA(rpt, usr) \ 161 le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(1)) 162 #define RTW89_GET_RXINFO_CTRL(rpt, usr) \ 163 le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(2)) 164 #define RTW89_GET_RXINFO_MGMT(rpt, usr) \ 165 le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(3)) 166 #define RTW89_GET_RXINFO_BCM(rpt, usr) \ 167 le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(4)) 168 #define RTW89_GET_RXINFO_MACID(rpt, usr) \ 169 le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), GENMASK(15, 8)) 170 171 #define RTW89_GET_PHY_STS_RSSI_A(sts) \ 172 le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(7, 0)) 173 #define RTW89_GET_PHY_STS_RSSI_B(sts) \ 174 le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(15, 8)) 175 #define RTW89_GET_PHY_STS_RSSI_C(sts) \ 176 le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(23, 16)) 177 #define RTW89_GET_PHY_STS_RSSI_D(sts) \ 178 le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(31, 24)) 179 #define RTW89_GET_PHY_STS_LEN(sts) \ 180 le32_get_bits(*((__le32 *)sts), GENMASK(15, 8)) 181 #define RTW89_GET_PHY_STS_RSSI_AVG(sts) \ 182 le32_get_bits(*((__le32 *)sts), GENMASK(31, 24)) 183 #define RTW89_GET_PHY_STS_IE_TYPE(ie) \ 184 le32_get_bits(*((__le32 *)ie), GENMASK(4, 0)) 185 #define RTW89_GET_PHY_STS_IE_LEN(ie) \ 186 le32_get_bits(*((__le32 *)ie), GENMASK(11, 5)) 187 #define RTW89_GET_PHY_STS_IE0_CFO(ie) \ 188 le32_get_bits(*((__le32 *)(ie) + 1), GENMASK(31, 20)) 189 190 enum rtw89_tx_channel { 191 RTW89_TXCH_ACH0 = 0, 192 RTW89_TXCH_ACH1 = 1, 193 RTW89_TXCH_ACH2 = 2, 194 RTW89_TXCH_ACH3 = 3, 195 RTW89_TXCH_ACH4 = 4, 196 RTW89_TXCH_ACH5 = 5, 197 RTW89_TXCH_ACH6 = 6, 198 RTW89_TXCH_ACH7 = 7, 199 RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */ 200 RTW89_TXCH_CH9 = 9, /* HI Band 0 */ 201 RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */ 202 RTW89_TXCH_CH11 = 11, /* HI Band 1 */ 203 RTW89_TXCH_CH12 = 12, /* FW CMD */ 204 205 /* keep last */ 206 RTW89_TXCH_NUM, 207 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1 208 }; 209 210 enum rtw89_rx_channel { 211 RTW89_RXCH_RXQ = 0, 212 RTW89_RXCH_RPQ = 1, 213 214 /* keep last */ 215 RTW89_RXCH_NUM, 216 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1 217 }; 218 219 enum rtw89_tx_qsel { 220 RTW89_TX_QSEL_BE_0 = 0x00, 221 RTW89_TX_QSEL_BK_0 = 0x01, 222 RTW89_TX_QSEL_VI_0 = 0x02, 223 RTW89_TX_QSEL_VO_0 = 0x03, 224 RTW89_TX_QSEL_BE_1 = 0x04, 225 RTW89_TX_QSEL_BK_1 = 0x05, 226 RTW89_TX_QSEL_VI_1 = 0x06, 227 RTW89_TX_QSEL_VO_1 = 0x07, 228 RTW89_TX_QSEL_BE_2 = 0x08, 229 RTW89_TX_QSEL_BK_2 = 0x09, 230 RTW89_TX_QSEL_VI_2 = 0x0a, 231 RTW89_TX_QSEL_VO_2 = 0x0b, 232 RTW89_TX_QSEL_BE_3 = 0x0c, 233 RTW89_TX_QSEL_BK_3 = 0x0d, 234 RTW89_TX_QSEL_VI_3 = 0x0e, 235 RTW89_TX_QSEL_VO_3 = 0x0f, 236 RTW89_TX_QSEL_B0_BCN = 0x10, 237 RTW89_TX_QSEL_B0_HI = 0x11, 238 RTW89_TX_QSEL_B0_MGMT = 0x12, 239 RTW89_TX_QSEL_B0_NOPS = 0x13, 240 RTW89_TX_QSEL_B0_MGMT_FAST = 0x14, 241 /* reserved */ 242 /* reserved */ 243 /* reserved */ 244 RTW89_TX_QSEL_B1_BCN = 0x18, 245 RTW89_TX_QSEL_B1_HI = 0x19, 246 RTW89_TX_QSEL_B1_MGMT = 0x1a, 247 RTW89_TX_QSEL_B1_NOPS = 0x1b, 248 RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c, 249 /* reserved */ 250 /* reserved */ 251 /* reserved */ 252 }; 253 254 enum rtw89_phy_status_ie_type { 255 RTW89_PHYSTS_IE00_CMN_CCK = 0, 256 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 257 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 258 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 259 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 260 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 261 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 262 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 263 RTW89_PHYSTS_IE08_FTR_CH = 8, 264 RTW89_PHYSTS_IE09_FTR_PLCP_0 = 9, 265 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 266 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 267 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 268 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 269 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 270 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 271 RTW89_PHYSTS_IE16_RSVD16 = 16, 272 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 273 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 274 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 275 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 276 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 277 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 278 RTW89_PHYSTS_IE23_RSVD23 = 23, 279 RTW89_PHYSTS_IE24_DBG_OFDM_TD_PATH_A = 24, 280 RTW89_PHYSTS_IE25_DBG_OFDM_TD_PATH_B = 25, 281 RTW89_PHYSTS_IE26_DBG_OFDM_TD_PATH_C = 26, 282 RTW89_PHYSTS_IE27_DBG_OFDM_TD_PATH_D = 27, 283 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 284 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 285 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 286 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 287 288 /* keep last */ 289 RTW89_PHYSTS_IE_NUM, 290 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 291 }; 292 293 static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) 294 { 295 switch (tid) { 296 default: 297 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 298 fallthrough; 299 case 0: 300 case 3: 301 return RTW89_TX_QSEL_BE_0; 302 case 1: 303 case 2: 304 return RTW89_TX_QSEL_BK_0; 305 case 4: 306 case 5: 307 return RTW89_TX_QSEL_VI_0; 308 case 6: 309 case 7: 310 return RTW89_TX_QSEL_VO_0; 311 } 312 } 313 314 static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 315 { 316 switch (qsel) { 317 default: 318 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 319 fallthrough; 320 case RTW89_TX_QSEL_BE_0: 321 return RTW89_TXCH_ACH0; 322 case RTW89_TX_QSEL_BK_0: 323 return RTW89_TXCH_ACH1; 324 case RTW89_TX_QSEL_VI_0: 325 return RTW89_TXCH_ACH2; 326 case RTW89_TX_QSEL_VO_0: 327 return RTW89_TXCH_ACH3; 328 case RTW89_TX_QSEL_B0_MGMT: 329 return RTW89_TXCH_CH8; 330 case RTW89_TX_QSEL_B0_HI: 331 return RTW89_TXCH_CH9; 332 case RTW89_TX_QSEL_B1_MGMT: 333 return RTW89_TXCH_CH10; 334 case RTW89_TX_QSEL_B1_HI: 335 return RTW89_TXCH_CH11; 336 } 337 } 338 339 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid) 340 { 341 switch (tid) { 342 case 3: 343 case 2: 344 case 5: 345 case 7: 346 return 1; 347 default: 348 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 349 fallthrough; 350 case 0: 351 case 1: 352 case 4: 353 case 6: 354 return 0; 355 } 356 } 357 358 #endif 359