1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_8852C_H__ 6 #define __RTW89_8852C_H__ 7 8 #include "core.h" 9 10 #define RF_PATH_NUM_8852C 2 11 12 struct rtw8852c_u_efuse { 13 u8 rsvd[0x38]; 14 u8 mac_addr[ETH_ALEN]; 15 }; 16 17 struct rtw8852c_e_efuse { 18 u8 mac_addr[ETH_ALEN]; 19 }; 20 21 struct rtw8852c_tssi_offset { 22 u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM]; 23 u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM]; 24 u8 rsvd[7]; 25 u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM]; 26 } __packed; 27 28 struct rtw8852c_efuse { 29 u8 rsvd[0x210]; 30 struct rtw8852c_tssi_offset path_a_tssi; 31 u8 rsvd1[10]; 32 struct rtw8852c_tssi_offset path_b_tssi; 33 u8 rsvd2[94]; 34 u8 channel_plan; 35 u8 xtal_k; 36 u8 rsvd3; 37 u8 iqk_lck; 38 u8 rsvd4[5]; 39 u8 reg_setting:2; 40 u8 tx_diversity:1; 41 u8 rx_diversity:2; 42 u8 ac_mode:1; 43 u8 module_type:2; 44 u8 rsvd5; 45 u8 shared_ant:1; 46 u8 coex_type:3; 47 u8 ant_iso:1; 48 u8 radio_on_off:1; 49 u8 rsvd6:2; 50 u8 eeprom_version; 51 u8 customer_id; 52 u8 tx_bb_swing_2g; 53 u8 tx_bb_swing_5g; 54 u8 tx_cali_pwr_trk_mode; 55 u8 trx_path_selection; 56 u8 rfe_type; 57 u8 country_code[2]; 58 u8 rsvd7[3]; 59 u8 path_a_therm; 60 u8 path_b_therm; 61 u8 rsvd8[46]; 62 u8 bw40_1s_tssi_6g_a[TSSI_MCS_6G_CH_GROUP_NUM]; 63 u8 rsvd9[10]; 64 u8 bw40_1s_tssi_6g_b[TSSI_MCS_6G_CH_GROUP_NUM]; 65 u8 rsvd10[110]; 66 u8 channel_plan_6g; 67 u8 rsvd11[71]; 68 union { 69 struct rtw8852c_u_efuse u; 70 struct rtw8852c_e_efuse e; 71 }; 72 } __packed; 73 74 extern const struct rtw89_chip_info rtw8852c_chip_info; 75 76 #endif 77