1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "reg.h" 11 #include "rtw8852c.h" 12 #include "rtw8852c_rfk.h" 13 #include "rtw8852c_table.h" 14 #include "util.h" 15 16 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 17 {13, 1614, grp_0}, /* ACH 0 */ 18 {13, 1614, grp_0}, /* ACH 1 */ 19 {13, 1614, grp_0}, /* ACH 2 */ 20 {13, 1614, grp_0}, /* ACH 3 */ 21 {13, 1614, grp_1}, /* ACH 4 */ 22 {13, 1614, grp_1}, /* ACH 5 */ 23 {13, 1614, grp_1}, /* ACH 6 */ 24 {13, 1614, grp_1}, /* ACH 7 */ 25 {13, 1614, grp_0}, /* B0MGQ */ 26 {13, 1614, grp_0}, /* B0HIQ */ 27 {13, 1614, grp_1}, /* B1MGQ */ 28 {13, 1614, grp_1}, /* B1HIQ */ 29 {40, 0, 0} /* FWCMDQ */ 30 }; 31 32 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 33 1614, /* Group 0 */ 34 1614, /* Group 1 */ 35 3228, /* Public Max */ 36 0 /* WP threshold */ 37 }; 38 39 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 40 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 41 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 42 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 43 RTW89_HCIFC_POH}, 44 [RTW89_QTA_INVALID] = {NULL}, 45 }; 46 47 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 48 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 49 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 50 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 51 &rtw89_mac_size.ple_qt47}, 52 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 53 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 54 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 55 &rtw89_mac_size.ple_qt45}, 56 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 57 NULL}, 58 }; 59 60 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 61 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 62 R_AX_H2CREG_DATA3_V1 63 }; 64 65 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 66 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 67 R_AX_C2HREG_DATA3_V1 68 }; 69 70 static const struct rtw89_page_regs rtw8852c_page_regs = { 71 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 72 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 73 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 74 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 75 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 76 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 77 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 78 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 79 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 80 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 81 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 82 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 83 }; 84 85 static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 86 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 87 }; 88 89 static const struct rtw89_imr_info rtw8852c_imr_info = { 90 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 91 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 92 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 93 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 94 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 95 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 96 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 97 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 98 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 99 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 100 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 101 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 102 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 103 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 104 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 105 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 106 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 107 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 108 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 109 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 110 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 111 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 112 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 113 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 114 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 115 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 116 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 117 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 118 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 119 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 120 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 121 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 122 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 123 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 124 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 125 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 126 .rmac_imr_reg = R_AX_RX_ERR_IMR, 127 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 128 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 129 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 130 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 131 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 132 }; 133 134 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg); 135 136 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 137 { 138 u32 val32; 139 u32 ret; 140 141 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 142 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 143 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 144 145 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 146 B_AX_AFSM_PCIE_SUS_EN); 147 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 148 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 149 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 150 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 151 152 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 153 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 154 if (ret) 155 return ret; 156 157 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 158 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 159 160 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 161 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 162 if (ret) 163 return ret; 164 165 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 166 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 167 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 168 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 169 170 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 171 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 172 173 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 174 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 175 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 176 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 177 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 178 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 179 B_AX_R_SYM_WLCMAC1_PC_EN); 180 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 181 182 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 183 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 184 if (ret) 185 return ret; 186 187 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 188 189 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 190 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 191 if (ret) 192 return ret; 193 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 194 XTAL_SI_OFF_WEI); 195 if (ret) 196 return ret; 197 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 198 XTAL_SI_OFF_EI); 199 if (ret) 200 return ret; 201 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 202 if (ret) 203 return ret; 204 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 205 XTAL_SI_PON_WEI); 206 if (ret) 207 return ret; 208 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 209 XTAL_SI_PON_EI); 210 if (ret) 211 return ret; 212 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 213 if (ret) 214 return ret; 215 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 216 if (ret) 217 return ret; 218 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 219 if (ret) 220 return ret; 221 222 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 223 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 224 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 225 226 fsleep(1000); 227 228 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 229 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 230 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 231 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 232 B_AX_LED1_PULL_LOW_EN); 233 234 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 235 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 236 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 237 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 238 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 239 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 240 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 241 242 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 243 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 244 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 245 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 246 B_AX_TMAC_EN | B_AX_RMAC_EN); 247 248 return 0; 249 } 250 251 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 252 { 253 u32 val32; 254 u32 ret; 255 256 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 257 XTAL_SI_RFC2RF); 258 if (ret) 259 return ret; 260 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 261 if (ret) 262 return ret; 263 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 264 if (ret) 265 return ret; 266 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 267 if (ret) 268 return ret; 269 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 270 if (ret) 271 return ret; 272 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 273 XTAL_SI_SRAM2RFC); 274 if (ret) 275 return ret; 276 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 277 if (ret) 278 return ret; 279 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 280 if (ret) 281 return ret; 282 283 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 284 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 285 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 286 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 287 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 288 289 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 290 if (ret) 291 return ret; 292 293 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 294 295 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 296 if (ret) 297 return ret; 298 299 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 300 301 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 302 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 303 if (ret) 304 return ret; 305 306 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0); 307 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 308 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 309 310 return 0; 311 } 312 313 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 314 struct rtw8852c_efuse *map) 315 { 316 ether_addr_copy(efuse->addr, map->e.mac_addr); 317 efuse->rfe_type = map->rfe_type; 318 efuse->xtal_cap = map->xtal_k; 319 } 320 321 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 322 struct rtw8852c_efuse *map) 323 { 324 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 325 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 326 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 327 u8 i, j; 328 329 tssi->thermal[RF_PATH_A] = map->path_a_therm; 330 tssi->thermal[RF_PATH_B] = map->path_b_therm; 331 332 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 333 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 334 sizeof(ofst[i]->cck_tssi)); 335 336 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 337 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 338 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 339 i, j, tssi->tssi_cck[i][j]); 340 341 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 342 sizeof(ofst[i]->bw40_tssi)); 343 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 344 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 345 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 346 sizeof(tssi->tssi_6g_mcs[i])); 347 348 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 349 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 350 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 351 i, j, tssi->tssi_mcs[i][j]); 352 } 353 } 354 355 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 356 { 357 if (high) 358 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 359 if (low) 360 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 361 362 return data != 0xff; 363 } 364 365 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 366 struct rtw8852c_efuse *map) 367 { 368 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 369 bool valid = false; 370 371 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 372 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 373 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 374 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 375 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 376 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 377 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 378 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 379 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 380 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 381 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 382 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 383 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 384 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 385 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 386 387 gain->offset_valid = valid; 388 } 389 390 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 391 { 392 struct rtw89_efuse *efuse = &rtwdev->efuse; 393 struct rtw8852c_efuse *map; 394 395 map = (struct rtw8852c_efuse *)log_map; 396 397 efuse->country_code[0] = map->country_code[0]; 398 efuse->country_code[1] = map->country_code[1]; 399 rtw8852c_efuse_parsing_tssi(rtwdev, map); 400 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 401 402 switch (rtwdev->hci.type) { 403 case RTW89_HCI_TYPE_PCIE: 404 rtw8852c_e_efuse_parsing(efuse, map); 405 break; 406 default: 407 return -ENOTSUPP; 408 } 409 410 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 411 412 return 0; 413 } 414 415 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 416 { 417 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 418 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 419 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 420 u32 addr = rtwdev->chip->phycap_addr; 421 bool pg = false; 422 u32 ofst; 423 u8 i, j; 424 425 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 426 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 427 /* addrs are in decreasing order */ 428 ofst = tssi_trim_addr[i] - addr - j; 429 tssi->tssi_trim[i][j] = phycap_map[ofst]; 430 431 if (phycap_map[ofst] != 0xff) 432 pg = true; 433 } 434 435 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 436 /* addrs are in decreasing order */ 437 ofst = tssi_trim_addr_6g[i] - addr - j; 438 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 439 440 if (phycap_map[ofst] != 0xff) 441 pg = true; 442 } 443 } 444 445 if (!pg) { 446 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 447 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 448 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 449 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 450 } 451 452 for (i = 0; i < RF_PATH_NUM_8852C; i++) 453 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 454 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 455 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 456 i, j, tssi->tssi_trim[i][j], 457 tssi_trim_addr[i] - j); 458 } 459 460 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 461 u8 *phycap_map) 462 { 463 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 464 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 465 u32 addr = rtwdev->chip->phycap_addr; 466 u8 i; 467 468 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 469 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 470 471 rtw89_debug(rtwdev, RTW89_DBG_RFK, 472 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 473 i, info->thermal_trim[i]); 474 475 if (info->thermal_trim[i] != 0xff) 476 info->pg_thermal_trim = true; 477 } 478 } 479 480 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 481 { 482 #define __thm_setting(raw) \ 483 ({ \ 484 u8 __v = (raw); \ 485 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 486 }) 487 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 488 u8 i, val; 489 490 if (!info->pg_thermal_trim) { 491 rtw89_debug(rtwdev, RTW89_DBG_RFK, 492 "[THERMAL][TRIM] no PG, do nothing\n"); 493 494 return; 495 } 496 497 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 498 val = __thm_setting(info->thermal_trim[i]); 499 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 500 501 rtw89_debug(rtwdev, RTW89_DBG_RFK, 502 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 503 i, val); 504 } 505 #undef __thm_setting 506 } 507 508 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 509 u8 *phycap_map) 510 { 511 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 512 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 513 u32 addr = rtwdev->chip->phycap_addr; 514 u8 i; 515 516 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 517 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 518 519 rtw89_debug(rtwdev, RTW89_DBG_RFK, 520 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 521 i, info->pa_bias_trim[i]); 522 523 if (info->pa_bias_trim[i] != 0xff) 524 info->pg_pa_bias_trim = true; 525 } 526 } 527 528 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 529 { 530 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 531 u8 pabias_2g, pabias_5g; 532 u8 i; 533 534 if (!info->pg_pa_bias_trim) { 535 rtw89_debug(rtwdev, RTW89_DBG_RFK, 536 "[PA_BIAS][TRIM] no PG, do nothing\n"); 537 538 return; 539 } 540 541 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 542 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 543 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 544 545 rtw89_debug(rtwdev, RTW89_DBG_RFK, 546 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 547 i, pabias_2g, pabias_5g); 548 549 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 550 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 551 } 552 } 553 554 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 555 { 556 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 557 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 558 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 559 560 return 0; 561 } 562 563 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 564 { 565 rtw8852c_thermal_trim(rtwdev); 566 rtw8852c_pa_bias_trim(rtwdev); 567 } 568 569 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 570 struct rtw89_channel_params *param, 571 u8 mac_idx) 572 { 573 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 574 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 575 mac_idx); 576 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 577 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 578 u8 rf_mod_val = 0, chk_rate_mask = 0; 579 u32 txsc; 580 581 switch (param->bandwidth) { 582 case RTW89_CHANNEL_WIDTH_160: 583 txsc80 = rtw89_phy_get_txsc(rtwdev, param, 584 RTW89_CHANNEL_WIDTH_80); 585 fallthrough; 586 case RTW89_CHANNEL_WIDTH_80: 587 txsc40 = rtw89_phy_get_txsc(rtwdev, param, 588 RTW89_CHANNEL_WIDTH_40); 589 fallthrough; 590 case RTW89_CHANNEL_WIDTH_40: 591 txsc20 = rtw89_phy_get_txsc(rtwdev, param, 592 RTW89_CHANNEL_WIDTH_20); 593 break; 594 default: 595 break; 596 } 597 598 switch (param->bandwidth) { 599 case RTW89_CHANNEL_WIDTH_160: 600 rf_mod_val = AX_WMAC_RFMOD_160M; 601 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 602 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 603 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 604 break; 605 case RTW89_CHANNEL_WIDTH_80: 606 rf_mod_val = AX_WMAC_RFMOD_80M; 607 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 608 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 609 break; 610 case RTW89_CHANNEL_WIDTH_40: 611 rf_mod_val = AX_WMAC_RFMOD_40M; 612 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 613 break; 614 case RTW89_CHANNEL_WIDTH_20: 615 default: 616 rf_mod_val = AX_WMAC_RFMOD_20M; 617 txsc = 0; 618 break; 619 } 620 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 621 rtw89_write32(rtwdev, sub_carr, txsc); 622 623 switch (param->band_type) { 624 case RTW89_BAND_2G: 625 chk_rate_mask = B_AX_BAND_MODE; 626 break; 627 case RTW89_BAND_5G: 628 case RTW89_BAND_6G: 629 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 630 break; 631 default: 632 rtw89_warn(rtwdev, "Invalid band_type:%d\n", param->band_type); 633 return; 634 } 635 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 636 B_AX_RTS_LIMIT_IN_OFDM6); 637 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 638 } 639 640 static const u32 rtw8852c_sco_barker_threshold[14] = { 641 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 642 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 643 }; 644 645 static const u32 rtw8852c_sco_cck_threshold[14] = { 646 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 647 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 648 }; 649 650 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 651 u8 primary_ch, enum rtw89_bandwidth bw) 652 { 653 u8 ch_element; 654 655 if (bw == RTW89_CHANNEL_WIDTH_20) { 656 ch_element = central_ch - 1; 657 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 658 if (primary_ch == 1) 659 ch_element = central_ch - 1 + 2; 660 else 661 ch_element = central_ch - 1 - 2; 662 } else { 663 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 664 return -EINVAL; 665 } 666 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 667 rtw8852c_sco_barker_threshold[ch_element]); 668 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 669 rtw8852c_sco_cck_threshold[ch_element]); 670 671 return 0; 672 } 673 674 struct rtw8852c_bb_gain { 675 u32 gain_g[BB_PATH_NUM_8852C]; 676 u32 gain_a[BB_PATH_NUM_8852C]; 677 u32 gain_mask; 678 }; 679 680 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 681 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 682 .gain_mask = 0x00ff0000 }, 683 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 684 .gain_mask = 0xff000000 }, 685 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 686 .gain_mask = 0x000000ff }, 687 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 688 .gain_mask = 0x0000ff00 }, 689 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 690 .gain_mask = 0x00ff0000 }, 691 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 692 .gain_mask = 0xff000000 }, 693 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 694 .gain_mask = 0x000000ff }, 695 }; 696 697 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 698 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 699 .gain_mask = 0x00ff0000 }, 700 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 701 .gain_mask = 0xff000000 }, 702 }; 703 704 struct rtw8852c_bb_gain_bypass { 705 u32 gain_g[BB_PATH_NUM_8852C]; 706 u32 gain_a[BB_PATH_NUM_8852C]; 707 u32 gain_mask_g; 708 u32 gain_mask_a; 709 }; 710 711 static 712 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 713 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 714 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 715 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 716 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 717 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 718 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 719 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 720 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 721 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 722 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 723 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 724 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 725 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 726 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 727 }; 728 729 struct rtw8852c_bb_gain_op1db { 730 struct { 731 u32 lna[BB_PATH_NUM_8852C]; 732 u32 tia_lna[BB_PATH_NUM_8852C]; 733 u32 mask; 734 } reg[LNA_GAIN_NUM]; 735 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 736 u32 mask_tia0_lna6; 737 }; 738 739 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 740 .reg = { 741 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 742 .mask = 0xff}, 743 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 744 .mask = 0xff00}, 745 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 746 .mask = 0xff0000}, 747 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 748 .mask = 0xff000000}, 749 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 750 .mask = 0xff}, 751 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 752 .mask = 0xff00}, 753 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 754 .mask = 0xff0000}, 755 }, 756 .reg_tia0_lna6 = {0x4674, 0x4758}, 757 .mask_tia0_lna6 = 0xff000000, 758 }; 759 760 static enum rtw89_phy_bb_gain_band 761 rtw8852c_mapping_gain_band(enum rtw89_subband subband) 762 { 763 switch (subband) { 764 default: 765 case RTW89_CH_2G: 766 return RTW89_BB_GAIN_BAND_2G; 767 case RTW89_CH_5G_BAND_1: 768 return RTW89_BB_GAIN_BAND_5G_L; 769 case RTW89_CH_5G_BAND_3: 770 return RTW89_BB_GAIN_BAND_5G_M; 771 case RTW89_CH_5G_BAND_4: 772 return RTW89_BB_GAIN_BAND_5G_H; 773 case RTW89_CH_6G_BAND_IDX0: 774 case RTW89_CH_6G_BAND_IDX1: 775 return RTW89_BB_GAIN_BAND_6G_L; 776 case RTW89_CH_6G_BAND_IDX2: 777 case RTW89_CH_6G_BAND_IDX3: 778 return RTW89_BB_GAIN_BAND_6G_M; 779 case RTW89_CH_6G_BAND_IDX4: 780 case RTW89_CH_6G_BAND_IDX5: 781 return RTW89_BB_GAIN_BAND_6G_H; 782 case RTW89_CH_6G_BAND_IDX6: 783 case RTW89_CH_6G_BAND_IDX7: 784 return RTW89_BB_GAIN_BAND_6G_UH; 785 } 786 } 787 788 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 789 enum rtw89_subband subband, 790 enum rtw89_rf_path path) 791 { 792 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 793 u8 gain_band = rtw8852c_mapping_gain_band(subband); 794 s32 val; 795 u32 reg; 796 u32 mask; 797 int i; 798 799 for (i = 0; i < LNA_GAIN_NUM; i++) { 800 if (subband == RTW89_CH_2G) 801 reg = bb_gain_lna[i].gain_g[path]; 802 else 803 reg = bb_gain_lna[i].gain_a[path]; 804 805 mask = bb_gain_lna[i].gain_mask; 806 val = gain->lna_gain[gain_band][path][i]; 807 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 808 809 if (subband == RTW89_CH_2G) { 810 reg = bb_gain_bypass_lna[i].gain_g[path]; 811 mask = bb_gain_bypass_lna[i].gain_mask_g; 812 } else { 813 reg = bb_gain_bypass_lna[i].gain_a[path]; 814 mask = bb_gain_bypass_lna[i].gain_mask_a; 815 } 816 817 val = gain->lna_gain_bypass[gain_band][path][i]; 818 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 819 820 if (subband != RTW89_CH_2G) { 821 reg = bb_gain_op1db_a.reg[i].lna[path]; 822 mask = bb_gain_op1db_a.reg[i].mask; 823 val = gain->lna_op1db[gain_band][path][i]; 824 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 825 826 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 827 mask = bb_gain_op1db_a.reg[i].mask; 828 val = gain->tia_lna_op1db[gain_band][path][i]; 829 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 830 } 831 } 832 833 if (subband != RTW89_CH_2G) { 834 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 835 mask = bb_gain_op1db_a.mask_tia0_lna6; 836 val = gain->tia_lna_op1db[gain_band][path][7]; 837 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 838 } 839 840 for (i = 0; i < TIA_GAIN_NUM; i++) { 841 if (subband == RTW89_CH_2G) 842 reg = bb_gain_tia[i].gain_g[path]; 843 else 844 reg = bb_gain_tia[i].gain_a[path]; 845 846 mask = bb_gain_tia[i].gain_mask; 847 val = gain->tia_gain[gain_band][path][i]; 848 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 849 } 850 } 851 852 static 853 const u8 rtw8852c_ch_base_table[16] = {1, 0xff, 854 36, 100, 132, 149, 0xff, 855 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 856 #define RTW8852C_CH_BASE_IDX_2G 0 857 #define RTW8852C_CH_BASE_IDX_5G_FIRST 2 858 #define RTW8852C_CH_BASE_IDX_5G_LAST 5 859 #define RTW8852C_CH_BASE_IDX_6G_FIRST 7 860 #define RTW8852C_CH_BASE_IDX_6G_LAST 14 861 862 #define RTW8852C_CH_BASE_IDX_MASK GENMASK(7, 4) 863 #define RTW8852C_CH_OFFSET_MASK GENMASK(3, 0) 864 865 static u8 rtw8852c_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 866 { 867 u8 chan_idx; 868 u8 last, first; 869 u8 idx; 870 871 switch (band) { 872 case RTW89_BAND_2G: 873 chan_idx = FIELD_PREP(RTW8852C_CH_BASE_IDX_MASK, RTW8852C_CH_BASE_IDX_2G) | 874 FIELD_PREP(RTW8852C_CH_OFFSET_MASK, central_ch); 875 return chan_idx; 876 case RTW89_BAND_5G: 877 first = RTW8852C_CH_BASE_IDX_5G_FIRST; 878 last = RTW8852C_CH_BASE_IDX_5G_LAST; 879 break; 880 case RTW89_BAND_6G: 881 first = RTW8852C_CH_BASE_IDX_6G_FIRST; 882 last = RTW8852C_CH_BASE_IDX_6G_LAST; 883 break; 884 default: 885 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 886 return 0; 887 } 888 889 for (idx = last; idx >= first; idx--) 890 if (central_ch >= rtw8852c_ch_base_table[idx]) 891 break; 892 893 if (idx < first) { 894 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 895 return 0; 896 } 897 898 chan_idx = FIELD_PREP(RTW8852C_CH_BASE_IDX_MASK, idx) | 899 FIELD_PREP(RTW8852C_CH_OFFSET_MASK, 900 (central_ch - rtw8852c_ch_base_table[idx]) >> 1); 901 return chan_idx; 902 } 903 904 static void rtw8852c_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 905 u8 *ch, enum nl80211_band *band) 906 { 907 u8 idx, offset; 908 909 idx = FIELD_GET(RTW8852C_CH_BASE_IDX_MASK, chan_idx); 910 offset = FIELD_GET(RTW8852C_CH_OFFSET_MASK, chan_idx); 911 912 if (idx == RTW8852C_CH_BASE_IDX_2G) { 913 *band = NL80211_BAND_2GHZ; 914 *ch = offset; 915 return; 916 } 917 918 *band = idx <= RTW8852C_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 919 *ch = rtw8852c_ch_base_table[idx] + (offset << 1); 920 } 921 922 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 923 const struct rtw89_channel_params *param, 924 enum rtw89_phy_idx phy_idx, 925 enum rtw89_rf_path path) 926 { 927 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 928 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 929 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 930 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 931 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 932 enum rtw89_gain_offset gain_band; 933 s32 offset_q0, offset_base_q4; 934 s32 tmp = 0; 935 936 if (!efuse_gain->offset_valid) 937 return; 938 939 if (rtwdev->dbcc_en && path == RF_PATH_B) 940 phy_idx = RTW89_PHY_1; 941 942 if (param->band_type == RTW89_BAND_2G) { 943 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 944 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 945 946 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 947 S8_MIN >> 1, S8_MAX >> 1); 948 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 949 } 950 951 switch (param->subband_type) { 952 default: 953 case RTW89_CH_2G: 954 gain_band = RTW89_GAIN_OFFSET_2G_OFDM; 955 break; 956 case RTW89_CH_5G_BAND_1: 957 gain_band = RTW89_GAIN_OFFSET_5G_LOW; 958 break; 959 case RTW89_CH_5G_BAND_3: 960 gain_band = RTW89_GAIN_OFFSET_5G_MID; 961 break; 962 case RTW89_CH_5G_BAND_4: 963 gain_band = RTW89_GAIN_OFFSET_5G_HIGH; 964 break; 965 } 966 967 offset_q0 = -efuse_gain->offset[path][gain_band]; 968 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 969 970 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 971 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 972 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 973 974 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 975 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 976 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 977 } 978 979 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 980 const struct rtw89_channel_params *param, 981 enum rtw89_phy_idx phy_idx) 982 { 983 u8 sco; 984 u16 central_freq = param->center_freq; 985 u8 central_ch = param->center_chan; 986 u8 band = param->band_type; 987 u8 subband = param->subband_type; 988 bool is_2g = band == RTW89_BAND_2G; 989 u8 chan_idx; 990 991 if (!central_freq) { 992 rtw89_warn(rtwdev, "Invalid central_freq\n"); 993 return; 994 } 995 996 if (phy_idx == RTW89_PHY_0) { 997 /* Path A */ 998 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 999 rtw8852c_set_gain_offset(rtwdev, param, phy_idx, RF_PATH_A); 1000 1001 if (is_2g) 1002 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1003 B_PATH0_BAND_SEL_MSK_V1, 1, 1004 phy_idx); 1005 else 1006 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1007 B_PATH0_BAND_SEL_MSK_V1, 0, 1008 phy_idx); 1009 /* Path B */ 1010 if (!rtwdev->dbcc_en) { 1011 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1012 rtw8852c_set_gain_offset(rtwdev, param, phy_idx, RF_PATH_B); 1013 1014 if (is_2g) 1015 rtw89_phy_write32_idx(rtwdev, 1016 R_PATH1_BAND_SEL_V1, 1017 B_PATH1_BAND_SEL_MSK_V1, 1018 1, phy_idx); 1019 else 1020 rtw89_phy_write32_idx(rtwdev, 1021 R_PATH1_BAND_SEL_V1, 1022 B_PATH1_BAND_SEL_MSK_V1, 1023 0, phy_idx); 1024 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1025 } else { 1026 if (is_2g) 1027 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1028 else 1029 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1030 } 1031 /* SCO compensate FC setting */ 1032 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1033 central_freq, phy_idx); 1034 /* round_up((1/fc0)*pow(2,18)) */ 1035 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1036 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1037 phy_idx); 1038 } else { 1039 /* Path B */ 1040 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1041 rtw8852c_set_gain_offset(rtwdev, param, phy_idx, RF_PATH_B); 1042 1043 if (is_2g) 1044 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1045 B_PATH1_BAND_SEL_MSK_V1, 1046 1, phy_idx); 1047 else 1048 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1049 B_PATH1_BAND_SEL_MSK_V1, 1050 0, phy_idx); 1051 /* SCO compensate FC setting */ 1052 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1053 central_freq, phy_idx); 1054 /* round_up((1/fc0)*pow(2,18)) */ 1055 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1056 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1057 phy_idx); 1058 } 1059 /* CCK parameters */ 1060 if (band == RTW89_BAND_2G) { 1061 if (central_ch == 14) { 1062 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1063 B_PCOEFF01_MSK_V1, 0x3b13ff); 1064 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1065 B_PCOEFF23_MSK_V1, 0x1c42de); 1066 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1067 B_PCOEFF45_MSK_V1, 0xfdb0ad); 1068 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1069 B_PCOEFF67_MSK_V1, 0xf60f6e); 1070 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1071 B_PCOEFF89_MSK_V1, 0xfd8f92); 1072 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1073 B_PCOEFFAB_MSK_V1, 0x2d011); 1074 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1075 B_PCOEFFCD_MSK_V1, 0x1c02c); 1076 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1077 B_PCOEFFEF_MSK_V1, 0xfff00a); 1078 } else { 1079 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1080 B_PCOEFF01_MSK_V1, 0x3d23ff); 1081 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1082 B_PCOEFF23_MSK_V1, 0x29b354); 1083 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1084 B_PCOEFF45_MSK_V1, 0xfc1c8); 1085 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1086 B_PCOEFF67_MSK_V1, 0xfdb053); 1087 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1088 B_PCOEFF89_MSK_V1, 0xf86f9a); 1089 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1090 B_PCOEFFAB_MSK_V1, 0xfaef92); 1091 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1092 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1093 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1094 B_PCOEFFEF_MSK_V1, 0xffdff5); 1095 } 1096 } 1097 1098 chan_idx = rtw8852c_encode_chan_idx(rtwdev, param->primary_chan, band); 1099 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1100 } 1101 1102 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1103 { 1104 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1105 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1106 1107 switch (bw) { 1108 case RTW89_CHANNEL_WIDTH_5: 1109 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1110 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1111 break; 1112 case RTW89_CHANNEL_WIDTH_10: 1113 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1114 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1115 break; 1116 case RTW89_CHANNEL_WIDTH_20: 1117 case RTW89_CHANNEL_WIDTH_40: 1118 case RTW89_CHANNEL_WIDTH_80: 1119 case RTW89_CHANNEL_WIDTH_160: 1120 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1121 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1122 break; 1123 default: 1124 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1125 } 1126 } 1127 1128 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1129 enum rtw89_phy_idx phy_idx) 1130 { 1131 if (bw == RTW89_CHANNEL_WIDTH_20) { 1132 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1133 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1134 } else { 1135 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1136 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1137 } 1138 } 1139 1140 static void 1141 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1142 enum rtw89_phy_idx phy_idx) 1143 { 1144 u8 mod_sbw = 0; 1145 1146 switch (bw) { 1147 case RTW89_CHANNEL_WIDTH_5: 1148 case RTW89_CHANNEL_WIDTH_10: 1149 case RTW89_CHANNEL_WIDTH_20: 1150 if (bw == RTW89_CHANNEL_WIDTH_5) 1151 mod_sbw = 0x1; 1152 else if (bw == RTW89_CHANNEL_WIDTH_10) 1153 mod_sbw = 0x2; 1154 else if (bw == RTW89_CHANNEL_WIDTH_20) 1155 mod_sbw = 0x0; 1156 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1157 phy_idx); 1158 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1159 mod_sbw, phy_idx); 1160 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1161 phy_idx); 1162 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1163 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1164 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1165 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1166 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1167 B_PATH0_BW_SEL_MSK_V1, 0xf); 1168 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1169 B_PATH1_BW_SEL_MSK_V1, 0xf); 1170 break; 1171 case RTW89_CHANNEL_WIDTH_40: 1172 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1173 phy_idx); 1174 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1175 phy_idx); 1176 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1177 pri_ch, 1178 phy_idx); 1179 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1180 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1181 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1182 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1183 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1184 B_PATH0_BW_SEL_MSK_V1, 0xf); 1185 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1186 B_PATH1_BW_SEL_MSK_V1, 0xf); 1187 break; 1188 case RTW89_CHANNEL_WIDTH_80: 1189 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1190 phy_idx); 1191 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1192 phy_idx); 1193 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1194 pri_ch, 1195 phy_idx); 1196 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1197 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1198 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1199 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1200 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1201 B_PATH0_BW_SEL_MSK_V1, 0xd); 1202 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1203 B_PATH1_BW_SEL_MSK_V1, 0xd); 1204 break; 1205 case RTW89_CHANNEL_WIDTH_160: 1206 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1207 phy_idx); 1208 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1209 phy_idx); 1210 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1211 pri_ch, 1212 phy_idx); 1213 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1214 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1215 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1216 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1217 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1218 B_PATH0_BW_SEL_MSK_V1, 0xb); 1219 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1220 B_PATH1_BW_SEL_MSK_V1, 0xb); 1221 break; 1222 default: 1223 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1224 pri_ch); 1225 } 1226 1227 if (bw == RTW89_CHANNEL_WIDTH_40) { 1228 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1229 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1230 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1231 } else { 1232 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1233 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1234 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1235 } 1236 1237 if (phy_idx == RTW89_PHY_0) { 1238 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1239 if (!rtwdev->dbcc_en) 1240 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1241 } else { 1242 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1243 } 1244 1245 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1246 } 1247 1248 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1249 struct rtw89_channel_params *param) 1250 { 1251 u8 center_chan = param->center_chan; 1252 u8 bw = param->bandwidth; 1253 1254 switch (param->band_type) { 1255 case RTW89_BAND_2G: 1256 if (bw == RTW89_CHANNEL_WIDTH_20) { 1257 if (center_chan >= 5 && center_chan <= 8) 1258 return 2440; 1259 if (center_chan == 13) 1260 return 2480; 1261 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1262 if (center_chan >= 3 && center_chan <= 10) 1263 return 2440; 1264 } 1265 break; 1266 case RTW89_BAND_5G: 1267 if (center_chan == 151 || center_chan == 153 || 1268 center_chan == 155 || center_chan == 163) 1269 return 5760; 1270 break; 1271 case RTW89_BAND_6G: 1272 if (center_chan == 195 || center_chan == 197 || 1273 center_chan == 199 || center_chan == 207) 1274 return 6920; 1275 break; 1276 default: 1277 break; 1278 } 1279 1280 return 0; 1281 } 1282 1283 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1284 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1285 #define MAX_TONE_NUM 2048 1286 1287 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1288 struct rtw89_channel_params *param, 1289 enum rtw89_phy_idx phy_idx) 1290 { 1291 u32 spur_freq; 1292 s32 freq_diff, csi_idx, csi_tone_idx; 1293 1294 spur_freq = rtw8852c_spur_freq(rtwdev, param); 1295 if (spur_freq == 0) { 1296 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1297 return; 1298 } 1299 1300 freq_diff = (spur_freq - param->center_freq) * 1000000; 1301 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1302 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1303 1304 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1305 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1306 } 1307 1308 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1309 [RF_PATH_A] = { 1310 .notch1_idx = {0x4C14, 0xFF}, 1311 .notch1_frac_idx = {0x4C14, 0xC00}, 1312 .notch1_en = {0x4C14, 0x1000}, 1313 .notch2_idx = {0x4C20, 0xFF}, 1314 .notch2_frac_idx = {0x4C20, 0xC00}, 1315 .notch2_en = {0x4C20, 0x1000}, 1316 }, 1317 [RF_PATH_B] = { 1318 .notch1_idx = {0x4CD8, 0xFF}, 1319 .notch1_frac_idx = {0x4CD8, 0xC00}, 1320 .notch1_en = {0x4CD8, 0x1000}, 1321 .notch2_idx = {0x4CE4, 0xFF}, 1322 .notch2_frac_idx = {0x4CE4, 0xC00}, 1323 .notch2_en = {0x4CE4, 0x1000}, 1324 }, 1325 }; 1326 1327 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1328 struct rtw89_channel_params *param, 1329 enum rtw89_rf_path path) 1330 { 1331 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1332 u32 spur_freq, fc; 1333 s32 freq_diff; 1334 s32 nbi_idx, nbi_tone_idx; 1335 s32 nbi_frac_idx, nbi_frac_tone_idx; 1336 bool notch2_chk = false; 1337 1338 spur_freq = rtw8852c_spur_freq(rtwdev, param); 1339 if (spur_freq == 0) { 1340 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1341 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1342 return; 1343 } 1344 1345 fc = param->center_freq; 1346 if (param->bandwidth == RTW89_CHANNEL_WIDTH_160) { 1347 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1348 if ((fc > spur_freq && param->center_chan < param->primary_chan) || 1349 (fc < spur_freq && param->center_chan > param->primary_chan)) 1350 notch2_chk = true; 1351 } 1352 1353 freq_diff = (spur_freq - fc) * 1000000; 1354 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1355 1356 if (param->bandwidth == RTW89_CHANNEL_WIDTH_20) { 1357 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1358 } else { 1359 u16 tone_para = (param->bandwidth == RTW89_CHANNEL_WIDTH_40) ? 128 : 256; 1360 1361 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1362 } 1363 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1364 1365 if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1366 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1367 nbi->notch2_idx.mask, nbi_tone_idx); 1368 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1369 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1370 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1371 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1372 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1373 } else { 1374 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1375 nbi->notch1_idx.mask, nbi_tone_idx); 1376 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1377 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1378 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1379 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1380 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1381 } 1382 } 1383 1384 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1385 struct rtw89_channel_params *param, 1386 enum rtw89_phy_idx phy_idx) 1387 { 1388 rtw8852c_set_csi_tone_idx(rtwdev, param, phy_idx); 1389 1390 if (phy_idx == RTW89_PHY_0) { 1391 rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_A); 1392 if (!rtwdev->dbcc_en) 1393 rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_B); 1394 } else { 1395 rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_B); 1396 } 1397 } 1398 1399 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1400 struct rtw89_channel_params *param, 1401 enum rtw89_phy_idx phy_idx) 1402 { 1403 u8 pri_ch = param->primary_chan; 1404 bool mask_5m_low; 1405 bool mask_5m_en; 1406 1407 switch (param->bandwidth) { 1408 case RTW89_CHANNEL_WIDTH_40: 1409 mask_5m_en = true; 1410 mask_5m_low = pri_ch == 2; 1411 break; 1412 case RTW89_CHANNEL_WIDTH_80: 1413 mask_5m_en = ((pri_ch == 3) || (pri_ch == 4)); 1414 mask_5m_low = pri_ch == 4; 1415 break; 1416 default: 1417 mask_5m_en = false; 1418 mask_5m_low = false; 1419 break; 1420 } 1421 1422 if (!mask_5m_en) { 1423 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1424 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1425 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1426 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1427 } else { 1428 if (mask_5m_low) { 1429 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1430 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1431 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1432 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1433 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1434 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1435 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1436 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1437 } else { 1438 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1439 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1440 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1441 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1442 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1443 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1444 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1445 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1446 } 1447 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1448 } 1449 } 1450 1451 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1452 enum rtw89_phy_idx phy_idx) 1453 { 1454 /*HW SI reset*/ 1455 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1456 0x7); 1457 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1458 0x7); 1459 1460 udelay(1); 1461 1462 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1463 phy_idx); 1464 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1465 phy_idx); 1466 /*HW SI reset*/ 1467 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1468 0x0); 1469 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1470 0x0); 1471 1472 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1473 phy_idx); 1474 } 1475 1476 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, 1477 enum rtw89_phy_idx phy_idx, bool en) 1478 { 1479 struct rtw89_hal *hal = &rtwdev->hal; 1480 1481 if (en) { 1482 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1483 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1484 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1485 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1486 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1487 phy_idx); 1488 if (hal->current_band_type == RTW89_BAND_2G) 1489 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1490 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1491 } else { 1492 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1493 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1494 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1495 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1496 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1497 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1498 fsleep(1); 1499 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1500 phy_idx); 1501 } 1502 } 1503 1504 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1505 enum rtw89_phy_idx phy_idx) 1506 { 1507 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1508 } 1509 1510 static 1511 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1512 u8 tx_path_en, u8 trsw_tx, 1513 u8 trsw_rx, u8 trsw, u8 trsw_b) 1514 { 1515 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1516 u32 mask_ofst = 16; 1517 u32 cr; 1518 u32 val; 1519 1520 if (path >= ARRAY_SIZE(path_cr_bases)) 1521 return; 1522 1523 cr = path_cr_bases[path]; 1524 1525 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1526 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1527 1528 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1529 } 1530 1531 enum rtw8852c_rfe_src { 1532 PAPE_RFM, 1533 TRSW_RFM, 1534 LNAON_RFM, 1535 }; 1536 1537 static 1538 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1539 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1540 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1541 { 1542 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1543 static const u32 masks[] = {0, 8, 16}; 1544 u32 mask, mask_ofst; 1545 u32 cr; 1546 u32 val; 1547 1548 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1549 return; 1550 1551 mask_ofst = masks[src]; 1552 cr = path_cr_bases[path]; 1553 1554 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1555 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1556 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1557 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1558 mask = 0xff << mask_ofst; 1559 1560 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1561 } 1562 1563 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1564 { 1565 static const u32 cr_bases[] = {0x5800, 0x7800}; 1566 u32 addr; 1567 u8 i; 1568 1569 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1570 addr = cr_bases[i]; 1571 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1572 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1573 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1574 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1575 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1576 } 1577 1578 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1579 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1580 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1581 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1582 1583 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1584 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1585 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1586 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1587 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1588 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1589 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1590 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1591 1592 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1593 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1594 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1595 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1596 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1597 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1598 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1599 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1600 1601 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1602 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1603 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1604 1605 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1606 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1607 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1608 } 1609 1610 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1611 enum rtw89_phy_idx phy_idx) 1612 { 1613 u32 addr; 1614 1615 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1616 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1617 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1618 } 1619 1620 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1621 { 1622 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1623 1624 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1625 B_DBCC_80P80_SEL_EVM_RPT_EN); 1626 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1627 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1628 1629 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1630 rtw8852c_bb_gpio_init(rtwdev); 1631 1632 /* read these registers after loading BB parameters */ 1633 gain->offset_base[RTW89_PHY_0] = 1634 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1635 gain->offset_base[RTW89_PHY_1] = 1636 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1637 } 1638 1639 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1640 struct rtw89_channel_params *param, 1641 enum rtw89_phy_idx phy_idx) 1642 { 1643 bool cck_en = param->band_type == RTW89_BAND_2G; 1644 u8 pri_ch_idx = param->pri_ch_idx; 1645 u32 mask, reg; 1646 u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1647 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1648 1649 if (param->band_type == RTW89_BAND_2G) 1650 rtw8852c_ctrl_sco_cck(rtwdev, param->center_chan, 1651 param->primary_chan, param->bandwidth); 1652 1653 rtw8852c_ctrl_ch(rtwdev, param, phy_idx); 1654 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, param->bandwidth, phy_idx); 1655 if (cck_en) { 1656 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1657 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1658 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1659 B_PD_ARBITER_OFF, 0x0, phy_idx); 1660 } else { 1661 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1662 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1663 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1664 B_PD_ARBITER_OFF, 0x1, phy_idx); 1665 } 1666 1667 rtw8852c_spur_elimination(rtwdev, param, phy_idx); 1668 rtw8852c_ctrl_btg(rtwdev, param->band_type == RTW89_BAND_2G); 1669 rtw8852c_5m_mask(rtwdev, param, phy_idx); 1670 1671 if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 && 1672 rtwdev->hal.cv != CHIP_CAV) { 1673 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1674 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1675 reg = rtw89_mac_reg_by_idx(R_P80_AT_HIGH_FREQ_BB_WRP, 1676 phy_idx); 1677 if (param->primary_chan > param->center_chan) { 1678 rtw89_phy_write32_mask(rtwdev, 1679 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1680 ru_alloc_msk[phy_idx], 1); 1681 rtw89_write32_mask(rtwdev, reg, 1682 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1683 } else { 1684 rtw89_phy_write32_mask(rtwdev, 1685 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1686 ru_alloc_msk[phy_idx], 0); 1687 rtw89_write32_mask(rtwdev, reg, 1688 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1689 } 1690 } 1691 1692 if (param->band_type == RTW89_BAND_6G && 1693 param->bandwidth == RTW89_CHANNEL_WIDTH_160) 1694 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1695 B_CDD_EVM_CHK_EN, 0, phy_idx); 1696 else 1697 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1698 B_CDD_EVM_CHK_EN, 1, phy_idx); 1699 1700 if (!rtwdev->dbcc_en) { 1701 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1702 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1703 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1704 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1705 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1706 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1707 } else { 1708 if (phy_idx == RTW89_PHY_0) { 1709 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1710 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1711 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1712 } else { 1713 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1714 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1715 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1716 } 1717 } 1718 1719 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1720 } 1721 1722 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1723 struct rtw89_channel_params *params) 1724 { 1725 rtw8852c_set_channel_mac(rtwdev, params, RTW89_MAC_0); 1726 rtw8852c_set_channel_bb(rtwdev, params, RTW89_PHY_0); 1727 rtw8852c_set_channel_rf(rtwdev, params, RTW89_PHY_0); 1728 } 1729 1730 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1731 { 1732 if (en) 1733 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1734 else 1735 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1736 } 1737 1738 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1739 { 1740 if (en) 1741 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1742 0x0); 1743 else 1744 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1745 0xf); 1746 } 1747 1748 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1749 struct rtw89_channel_help_params *p) 1750 { 1751 u8 phy_idx = RTW89_PHY_0; 1752 1753 if (enter) { 1754 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 1755 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 1756 rtw8852c_dfs_en(rtwdev, false); 1757 rtw8852c_adc_en(rtwdev, false); 1758 fsleep(40); 1759 rtw8852c_bb_reset_en(rtwdev, phy_idx, false); 1760 } else { 1761 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 1762 rtw8852c_adc_en(rtwdev, true); 1763 rtw8852c_dfs_en(rtwdev, true); 1764 rtw8852c_bb_reset_en(rtwdev, phy_idx, true); 1765 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 1766 } 1767 } 1768 1769 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1770 { 1771 struct rtw89_mcc_info *mcc_info = &rtwdev->mcc; 1772 1773 memset(mcc_info, 0, sizeof(*mcc_info)); 1774 } 1775 1776 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) 1777 { 1778 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1779 } 1780 1781 static 1782 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1783 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1784 { 1785 s8 pw_ofst_2tx; 1786 s8 val_1t; 1787 s8 val_2t; 1788 u32 reg; 1789 u8 i; 1790 1791 if (pw_ofst < -32 || pw_ofst > 31) { 1792 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1793 return; 1794 } 1795 val_1t = pw_ofst << 2; 1796 pw_ofst_2tx = max(pw_ofst - 3, -32); 1797 val_2t = pw_ofst_2tx << 2; 1798 1799 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1800 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1801 1802 for (i = 0; i < 4; i++) { 1803 /* 1TX */ 1804 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1805 rtw89_write32_mask(rtwdev, reg, 1806 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1807 val_1t); 1808 /* 2TX */ 1809 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1810 rtw89_write32_mask(rtwdev, reg, 1811 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1812 val_2t); 1813 } 1814 } 1815 1816 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 1817 { 1818 struct rtw89_hal *hal = &rtwdev->hal; 1819 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1820 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1821 1822 if (rtwdev->dbcc_en) { 1823 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 1824 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 1825 RTW89_PHY_1); 1826 1827 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 1828 1); 1829 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 1830 1); 1831 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 1832 RTW89_PHY_1); 1833 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 1834 RTW89_PHY_1); 1835 1836 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 1837 B_RXHT_MCS_LIMIT, 0); 1838 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 1839 B_RXVHT_MCS_LIMIT, 0); 1840 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 1841 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1842 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1843 1844 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 1845 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 1846 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 1847 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 1848 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 1849 RTW89_PHY_1); 1850 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 1851 RTW89_PHY_1); 1852 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 1853 RTW89_PHY_1); 1854 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1855 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1856 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1857 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1858 } else { 1859 if (rx_path == RF_PATH_A) { 1860 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 1861 B_ANT_RX_SEG0, 1); 1862 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 1863 B_ANT_RX_1RCCA_SEG0, 1); 1864 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 1865 B_ANT_RX_1RCCA_SEG1, 1); 1866 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 1867 B_RXHT_MCS_LIMIT, 0); 1868 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 1869 B_RXVHT_MCS_LIMIT, 0); 1870 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1871 0); 1872 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1873 0); 1874 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 1875 rst_mask0, 1); 1876 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 1877 rst_mask0, 3); 1878 } else if (rx_path == RF_PATH_B) { 1879 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 1880 B_ANT_RX_SEG0, 2); 1881 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 1882 B_ANT_RX_1RCCA_SEG0, 2); 1883 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 1884 B_ANT_RX_1RCCA_SEG1, 2); 1885 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 1886 B_RXHT_MCS_LIMIT, 0); 1887 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 1888 B_RXVHT_MCS_LIMIT, 0); 1889 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1890 0); 1891 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1892 0); 1893 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 1894 rst_mask1, 1); 1895 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 1896 rst_mask1, 3); 1897 } else { 1898 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 1899 B_ANT_RX_SEG0, 3); 1900 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 1901 B_ANT_RX_1RCCA_SEG0, 3); 1902 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 1903 B_ANT_RX_1RCCA_SEG1, 3); 1904 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 1905 B_RXHT_MCS_LIMIT, 1); 1906 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 1907 B_RXVHT_MCS_LIMIT, 1); 1908 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1909 1); 1910 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1911 1); 1912 rtw8852c_ctrl_btg(rtwdev, hal->current_band_type == RTW89_BAND_2G); 1913 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 1914 rst_mask0, 1); 1915 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 1916 rst_mask0, 3); 1917 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 1918 rst_mask1, 1); 1919 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 1920 rst_mask1, 3); 1921 } 1922 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 1923 } 1924 } 1925 1926 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 1927 enum rtw89_mac_idx mac_idx) 1928 { 1929 struct rtw89_reg2_def path_com[] = { 1930 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 1931 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 1932 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 1933 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 1934 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 1935 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 1936 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 1937 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 1938 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 1939 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 1940 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 1941 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 1942 }; 1943 u32 addr; 1944 u32 reg; 1945 u8 cr_size = ARRAY_SIZE(path_com); 1946 u8 i = 0; 1947 1948 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 1949 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 1950 1951 for (addr = R_AX_MACID_ANT_TABLE; 1952 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 1953 reg = rtw89_mac_reg_by_idx(addr, mac_idx); 1954 rtw89_write32(rtwdev, reg, 0); 1955 } 1956 1957 if (tx_path == RF_PATH_A) { 1958 path_com[0].data = AX_PATH_COM0_PATHA; 1959 path_com[1].data = AX_PATH_COM1_PATHA; 1960 path_com[2].data = AX_PATH_COM2_PATHA; 1961 path_com[7].data = AX_PATH_COM7_PATHA; 1962 path_com[8].data = AX_PATH_COM8_PATHA; 1963 } else if (tx_path == RF_PATH_B) { 1964 path_com[0].data = AX_PATH_COM0_PATHB; 1965 path_com[1].data = AX_PATH_COM1_PATHB; 1966 path_com[2].data = AX_PATH_COM2_PATHB; 1967 path_com[7].data = AX_PATH_COM7_PATHB; 1968 path_com[8].data = AX_PATH_COM8_PATHB; 1969 } else if (tx_path == RF_PATH_AB) { 1970 path_com[0].data = AX_PATH_COM0_PATHAB; 1971 path_com[1].data = AX_PATH_COM1_PATHAB; 1972 path_com[2].data = AX_PATH_COM2_PATHAB; 1973 path_com[7].data = AX_PATH_COM7_PATHAB; 1974 path_com[8].data = AX_PATH_COM8_PATHAB; 1975 } else { 1976 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 1977 return; 1978 } 1979 1980 for (i = 0; i < cr_size; i++) { 1981 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 1982 path_com[i].addr, path_com[i].data); 1983 reg = rtw89_mac_reg_by_idx(path_com[i].addr, mac_idx); 1984 rtw89_write32(rtwdev, reg, path_com[i].data); 1985 } 1986 } 1987 1988 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 1989 { 1990 struct rtw89_hal *hal = &rtwdev->hal; 1991 1992 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 1993 1994 if (hal->rx_nss == 1) { 1995 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1996 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1997 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1998 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1999 } else { 2000 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2001 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2002 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2003 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2004 } 2005 2006 rtw8852c_ctrl_tx_path_tmac(rtwdev, RF_PATH_AB, RTW89_MAC_0); 2007 } 2008 2009 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 2010 { 2011 if (btg) { 2012 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2013 B_PATH0_BT_SHARE_V1, 0x1); 2014 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2015 B_PATH0_BTG_PATH_V1, 0x0); 2016 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2017 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2018 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2019 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2020 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2021 B_PATH1_BT_SHARE_V1, 0x1); 2022 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2023 B_PATH1_BTG_PATH_V1, 0x1); 2024 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2025 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2026 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2027 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2028 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2029 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2030 0x1); 2031 } else { 2032 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2033 B_PATH0_BT_SHARE_V1, 0x0); 2034 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2035 B_PATH0_BTG_PATH_V1, 0x0); 2036 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2037 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2038 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2039 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2040 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2041 B_PATH1_BT_SHARE_V1, 0x0); 2042 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2043 B_PATH1_BTG_PATH_V1, 0x0); 2044 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2045 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2046 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2047 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2048 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2049 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2050 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2051 0x0); 2052 } 2053 } 2054 2055 static 2056 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2057 { 2058 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2059 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2060 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2061 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2062 } 2063 2064 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2065 { 2066 struct rtw89_btc *btc = &rtwdev->btc; 2067 struct rtw89_btc_module *module = &btc->mdinfo; 2068 const struct rtw89_chip_info *chip = rtwdev->chip; 2069 const struct rtw89_mac_ax_coex coex_params = { 2070 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2071 .direction = RTW89_MAC_AX_COEX_INNER, 2072 }; 2073 2074 /* PTA init */ 2075 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2076 2077 /* set WL Tx response = Hi-Pri */ 2078 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2079 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2080 2081 /* set rf gnt debug off */ 2082 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2083 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2084 2085 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2086 if (module->ant.type == BTC_ANT_SHARED) { 2087 rtw8852c_set_trx_mask(rtwdev, 2088 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2089 rtw8852c_set_trx_mask(rtwdev, 2090 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2091 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2092 rtw8852c_set_trx_mask(rtwdev, 2093 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2094 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2095 rtw8852c_set_trx_mask(rtwdev, 2096 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2097 rtw8852c_set_trx_mask(rtwdev, 2098 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2099 } 2100 2101 /* set PTA break table */ 2102 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2103 2104 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2105 rtw89_write32_set(rtwdev, 2106 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2107 B_AX_BT_CNT_RST_V1); 2108 btc->cx.wl.status.map.init_ok = true; 2109 } 2110 2111 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2112 { 2113 int ret; 2114 2115 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2116 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2117 2118 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2119 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2120 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2121 2122 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2123 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2124 2125 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2126 if (ret) 2127 return ret; 2128 2129 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2130 if (ret) 2131 return ret; 2132 2133 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2134 if (ret) 2135 return ret; 2136 2137 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2138 if (ret) 2139 return ret; 2140 2141 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2142 if (ret) 2143 return ret; 2144 2145 return 0; 2146 } 2147 2148 static void rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2149 { 2150 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2151 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2152 } 2153 2154 static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2155 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2156 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2157 .bb_reset = rtw8852c_bb_reset, 2158 .bb_sethw = rtw8852c_bb_sethw, 2159 .set_channel = rtw8852c_set_channel, 2160 .set_channel_help = rtw8852c_set_channel_help, 2161 .read_efuse = rtw8852c_read_efuse, 2162 .read_phycap = rtw8852c_read_phycap, 2163 .rfk_init = rtw8852c_rfk_init, 2164 .rfk_channel = rtw8852c_rfk_channel, 2165 .power_trim = rtw8852c_power_trim, 2166 .read_rf = rtw89_phy_read_rf_v1, 2167 .write_rf = rtw89_phy_write_rf_v1, 2168 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2169 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2170 .pwr_on_func = rtw8852c_pwr_on_func, 2171 .pwr_off_func = rtw8852c_pwr_off_func, 2172 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2173 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2174 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2175 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2176 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2177 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2178 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2179 2180 .btc_init_cfg = rtw8852c_btc_init_cfg, 2181 }; 2182 2183 const struct rtw89_chip_info rtw8852c_chip_info = { 2184 .chip_id = RTL8852C, 2185 .ops = &rtw8852c_chip_ops, 2186 .fw_name = "rtw89/rtw8852c_fw.bin", 2187 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2188 .dle_mem = rtw8852c_dle_mem_pcie, 2189 .rf_base_addr = {0xe000, 0xf000}, 2190 .pwr_on_seq = NULL, 2191 .pwr_off_seq = NULL, 2192 .bb_table = &rtw89_8852c_phy_bb_table, 2193 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2194 .rf_table = {&rtw89_8852c_phy_radiob_table, 2195 &rtw89_8852c_phy_radioa_table,}, 2196 .nctl_table = &rtw89_8852c_phy_nctl_table, 2197 .byr_table = &rtw89_8852c_byr_table, 2198 .txpwr_lmt_2g = &rtw89_8852c_txpwr_lmt_2g, 2199 .txpwr_lmt_5g = &rtw89_8852c_txpwr_lmt_5g, 2200 .txpwr_lmt_6g = &rtw89_8852c_txpwr_lmt_6g, 2201 .txpwr_lmt_ru_2g = &rtw89_8852c_txpwr_lmt_ru_2g, 2202 .txpwr_lmt_ru_5g = &rtw89_8852c_txpwr_lmt_ru_5g, 2203 .txpwr_lmt_ru_6g = &rtw89_8852c_txpwr_lmt_ru_6g, 2204 .txpwr_factor_rf = 2, 2205 .txpwr_factor_mac = 1, 2206 .dig_table = NULL, 2207 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2208 .hw_sec_hdr = true, 2209 .sec_ctrl_efuse_size = 4, 2210 .physical_efuse_size = 1216, 2211 .logical_efuse_size = 2048, 2212 .limit_efuse_size = 1280, 2213 .dav_phy_efuse_size = 96, 2214 .dav_log_efuse_size = 16, 2215 .phycap_addr = 0x590, 2216 .phycap_size = 0x60, 2217 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 2218 BIT(RTW89_PS_MODE_PWR_GATED), 2219 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 2220 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 2221 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 2222 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 2223 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 2224 .h2c_regs = rtw8852c_h2c_regs, 2225 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 2226 .c2h_regs = rtw8852c_c2h_regs, 2227 .page_regs = &rtw8852c_page_regs, 2228 .dcfo_comp = &rtw8852c_dcfo_comp, 2229 .dcfo_comp_sft = 5, 2230 .imr_info = &rtw8852c_imr_info 2231 }; 2232 EXPORT_SYMBOL(rtw8852c_chip_info); 2233 2234 MODULE_FIRMWARE("rtw89/rtw8852c_fw.bin"); 2235 MODULE_AUTHOR("Realtek Corporation"); 2236 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 2237 MODULE_LICENSE("Dual BSD/GPL"); 2238