1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "reg.h" 11 #include "rtw8852c.h" 12 #include "rtw8852c_rfk.h" 13 #include "rtw8852c_table.h" 14 #include "util.h" 15 16 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 17 {13, 1614, grp_0}, /* ACH 0 */ 18 {13, 1614, grp_0}, /* ACH 1 */ 19 {13, 1614, grp_0}, /* ACH 2 */ 20 {13, 1614, grp_0}, /* ACH 3 */ 21 {13, 1614, grp_1}, /* ACH 4 */ 22 {13, 1614, grp_1}, /* ACH 5 */ 23 {13, 1614, grp_1}, /* ACH 6 */ 24 {13, 1614, grp_1}, /* ACH 7 */ 25 {13, 1614, grp_0}, /* B0MGQ */ 26 {13, 1614, grp_0}, /* B0HIQ */ 27 {13, 1614, grp_1}, /* B1MGQ */ 28 {13, 1614, grp_1}, /* B1HIQ */ 29 {40, 0, 0} /* FWCMDQ */ 30 }; 31 32 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 33 1614, /* Group 0 */ 34 1614, /* Group 1 */ 35 3228, /* Public Max */ 36 0 /* WP threshold */ 37 }; 38 39 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 40 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 41 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 42 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 43 RTW89_HCIFC_POH}, 44 [RTW89_QTA_INVALID] = {NULL}, 45 }; 46 47 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 48 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 49 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 50 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 51 &rtw89_mac_size.ple_qt47}, 52 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 53 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 54 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 55 &rtw89_mac_size.ple_qt45}, 56 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 57 NULL}, 58 }; 59 60 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 61 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 62 R_AX_H2CREG_DATA3_V1 63 }; 64 65 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 66 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 67 R_AX_C2HREG_DATA3_V1 68 }; 69 70 static const struct rtw89_page_regs rtw8852c_page_regs = { 71 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 72 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 73 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 74 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 75 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 76 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 77 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 78 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 79 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 80 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 81 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 82 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 83 }; 84 85 static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 86 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 87 }; 88 89 static const struct rtw89_imr_info rtw8852c_imr_info = { 90 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 91 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 92 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 93 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 94 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 95 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 96 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 97 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 98 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 99 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 100 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 101 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 102 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 103 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 104 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 105 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 106 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 107 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 108 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 109 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 110 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 111 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 112 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 113 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 114 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 115 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 116 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 117 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 118 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 119 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 120 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 121 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 122 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 123 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 124 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 125 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 126 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 127 .rmac_imr_reg = R_AX_RX_ERR_IMR, 128 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 129 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 130 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 131 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 132 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 133 }; 134 135 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 136 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 137 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 138 }; 139 140 static const struct rtw89_dig_regs rtw8852c_dig_regs = { 141 .seg0_pd_reg = R_SEG0R_PD, 142 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 143 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 144 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 145 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 146 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 147 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 148 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 149 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 150 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 151 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 152 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 153 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 154 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 155 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 156 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 157 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 158 }; 159 160 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg); 161 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 162 enum rtw89_mac_idx mac_idx); 163 164 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 165 { 166 u32 val32; 167 u32 ret; 168 169 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 170 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 171 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 172 173 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 174 B_AX_AFSM_PCIE_SUS_EN); 175 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 176 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 177 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 178 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 179 180 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 181 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 182 if (ret) 183 return ret; 184 185 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 186 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 187 188 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 189 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 190 if (ret) 191 return ret; 192 193 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 194 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 195 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 196 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 197 198 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 199 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 200 201 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 202 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 203 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 204 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 205 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 206 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 207 B_AX_R_SYM_WLCMAC1_PC_EN); 208 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 209 210 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 211 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 212 if (ret) 213 return ret; 214 215 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 216 217 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 218 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 219 if (ret) 220 return ret; 221 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 222 XTAL_SI_OFF_WEI); 223 if (ret) 224 return ret; 225 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 226 XTAL_SI_OFF_EI); 227 if (ret) 228 return ret; 229 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 230 if (ret) 231 return ret; 232 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 233 XTAL_SI_PON_WEI); 234 if (ret) 235 return ret; 236 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 237 XTAL_SI_PON_EI); 238 if (ret) 239 return ret; 240 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 241 if (ret) 242 return ret; 243 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 244 if (ret) 245 return ret; 246 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 247 if (ret) 248 return ret; 249 250 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 251 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 252 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 253 254 fsleep(1000); 255 256 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 257 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 258 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 259 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 260 B_AX_LED1_PULL_LOW_EN); 261 262 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 263 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 264 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 265 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 266 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 267 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 268 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 269 270 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 271 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 272 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 273 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 274 B_AX_TMAC_EN | B_AX_RMAC_EN); 275 276 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 277 PINMUX_EESK_FUNC_SEL_BT_LOG); 278 279 return 0; 280 } 281 282 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 283 { 284 u32 val32; 285 u32 ret; 286 287 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 288 XTAL_SI_RFC2RF); 289 if (ret) 290 return ret; 291 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 292 if (ret) 293 return ret; 294 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 295 if (ret) 296 return ret; 297 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 298 if (ret) 299 return ret; 300 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 301 if (ret) 302 return ret; 303 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 304 XTAL_SI_SRAM2RFC); 305 if (ret) 306 return ret; 307 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 308 if (ret) 309 return ret; 310 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 311 if (ret) 312 return ret; 313 314 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 315 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 316 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 317 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 318 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 319 320 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 321 if (ret) 322 return ret; 323 324 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 325 326 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 327 if (ret) 328 return ret; 329 330 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 331 332 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 333 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 334 if (ret) 335 return ret; 336 337 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0); 338 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 339 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 340 341 return 0; 342 } 343 344 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 345 struct rtw8852c_efuse *map) 346 { 347 ether_addr_copy(efuse->addr, map->e.mac_addr); 348 efuse->rfe_type = map->rfe_type; 349 efuse->xtal_cap = map->xtal_k; 350 } 351 352 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 353 struct rtw8852c_efuse *map) 354 { 355 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 356 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 357 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 358 u8 i, j; 359 360 tssi->thermal[RF_PATH_A] = map->path_a_therm; 361 tssi->thermal[RF_PATH_B] = map->path_b_therm; 362 363 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 364 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 365 sizeof(ofst[i]->cck_tssi)); 366 367 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 368 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 369 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 370 i, j, tssi->tssi_cck[i][j]); 371 372 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 373 sizeof(ofst[i]->bw40_tssi)); 374 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 375 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 376 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 377 sizeof(tssi->tssi_6g_mcs[i])); 378 379 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 380 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 381 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 382 i, j, tssi->tssi_mcs[i][j]); 383 } 384 } 385 386 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 387 { 388 if (high) 389 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 390 if (low) 391 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 392 393 return data != 0xff; 394 } 395 396 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 397 struct rtw8852c_efuse *map) 398 { 399 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 400 bool valid = false; 401 402 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 403 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 404 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 405 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 406 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 407 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 408 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 409 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 410 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 411 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 412 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 413 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 414 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 415 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 416 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 417 418 gain->offset_valid = valid; 419 } 420 421 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 422 { 423 struct rtw89_efuse *efuse = &rtwdev->efuse; 424 struct rtw8852c_efuse *map; 425 426 map = (struct rtw8852c_efuse *)log_map; 427 428 efuse->country_code[0] = map->country_code[0]; 429 efuse->country_code[1] = map->country_code[1]; 430 rtw8852c_efuse_parsing_tssi(rtwdev, map); 431 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 432 433 switch (rtwdev->hci.type) { 434 case RTW89_HCI_TYPE_PCIE: 435 rtw8852c_e_efuse_parsing(efuse, map); 436 break; 437 default: 438 return -ENOTSUPP; 439 } 440 441 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 442 443 return 0; 444 } 445 446 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 447 { 448 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 449 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 450 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 451 u32 addr = rtwdev->chip->phycap_addr; 452 bool pg = false; 453 u32 ofst; 454 u8 i, j; 455 456 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 457 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 458 /* addrs are in decreasing order */ 459 ofst = tssi_trim_addr[i] - addr - j; 460 tssi->tssi_trim[i][j] = phycap_map[ofst]; 461 462 if (phycap_map[ofst] != 0xff) 463 pg = true; 464 } 465 466 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 467 /* addrs are in decreasing order */ 468 ofst = tssi_trim_addr_6g[i] - addr - j; 469 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 470 471 if (phycap_map[ofst] != 0xff) 472 pg = true; 473 } 474 } 475 476 if (!pg) { 477 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 478 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 479 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 480 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 481 } 482 483 for (i = 0; i < RF_PATH_NUM_8852C; i++) 484 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 485 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 486 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 487 i, j, tssi->tssi_trim[i][j], 488 tssi_trim_addr[i] - j); 489 } 490 491 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 492 u8 *phycap_map) 493 { 494 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 495 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 496 u32 addr = rtwdev->chip->phycap_addr; 497 u8 i; 498 499 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 500 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 501 502 rtw89_debug(rtwdev, RTW89_DBG_RFK, 503 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 504 i, info->thermal_trim[i]); 505 506 if (info->thermal_trim[i] != 0xff) 507 info->pg_thermal_trim = true; 508 } 509 } 510 511 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 512 { 513 #define __thm_setting(raw) \ 514 ({ \ 515 u8 __v = (raw); \ 516 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 517 }) 518 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 519 u8 i, val; 520 521 if (!info->pg_thermal_trim) { 522 rtw89_debug(rtwdev, RTW89_DBG_RFK, 523 "[THERMAL][TRIM] no PG, do nothing\n"); 524 525 return; 526 } 527 528 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 529 val = __thm_setting(info->thermal_trim[i]); 530 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 531 532 rtw89_debug(rtwdev, RTW89_DBG_RFK, 533 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 534 i, val); 535 } 536 #undef __thm_setting 537 } 538 539 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 540 u8 *phycap_map) 541 { 542 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 543 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 544 u32 addr = rtwdev->chip->phycap_addr; 545 u8 i; 546 547 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 548 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 549 550 rtw89_debug(rtwdev, RTW89_DBG_RFK, 551 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 552 i, info->pa_bias_trim[i]); 553 554 if (info->pa_bias_trim[i] != 0xff) 555 info->pg_pa_bias_trim = true; 556 } 557 } 558 559 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 560 { 561 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 562 u8 pabias_2g, pabias_5g; 563 u8 i; 564 565 if (!info->pg_pa_bias_trim) { 566 rtw89_debug(rtwdev, RTW89_DBG_RFK, 567 "[PA_BIAS][TRIM] no PG, do nothing\n"); 568 569 return; 570 } 571 572 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 573 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 574 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 575 576 rtw89_debug(rtwdev, RTW89_DBG_RFK, 577 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 578 i, pabias_2g, pabias_5g); 579 580 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 581 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 582 } 583 } 584 585 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 586 { 587 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 588 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 589 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 590 591 return 0; 592 } 593 594 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 595 { 596 rtw8852c_thermal_trim(rtwdev); 597 rtw8852c_pa_bias_trim(rtwdev); 598 } 599 600 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 601 const struct rtw89_chan *chan, 602 u8 mac_idx) 603 { 604 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 605 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 606 mac_idx); 607 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 608 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 609 u8 rf_mod_val = 0, chk_rate_mask = 0; 610 u32 txsc; 611 612 switch (chan->band_width) { 613 case RTW89_CHANNEL_WIDTH_160: 614 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 615 RTW89_CHANNEL_WIDTH_80); 616 fallthrough; 617 case RTW89_CHANNEL_WIDTH_80: 618 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 619 RTW89_CHANNEL_WIDTH_40); 620 fallthrough; 621 case RTW89_CHANNEL_WIDTH_40: 622 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 623 RTW89_CHANNEL_WIDTH_20); 624 break; 625 default: 626 break; 627 } 628 629 switch (chan->band_width) { 630 case RTW89_CHANNEL_WIDTH_160: 631 rf_mod_val = AX_WMAC_RFMOD_160M; 632 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 633 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 634 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 635 break; 636 case RTW89_CHANNEL_WIDTH_80: 637 rf_mod_val = AX_WMAC_RFMOD_80M; 638 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 639 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 640 break; 641 case RTW89_CHANNEL_WIDTH_40: 642 rf_mod_val = AX_WMAC_RFMOD_40M; 643 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 644 break; 645 case RTW89_CHANNEL_WIDTH_20: 646 default: 647 rf_mod_val = AX_WMAC_RFMOD_20M; 648 txsc = 0; 649 break; 650 } 651 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 652 rtw89_write32(rtwdev, sub_carr, txsc); 653 654 switch (chan->band_type) { 655 case RTW89_BAND_2G: 656 chk_rate_mask = B_AX_BAND_MODE; 657 break; 658 case RTW89_BAND_5G: 659 case RTW89_BAND_6G: 660 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 661 break; 662 default: 663 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 664 return; 665 } 666 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 667 B_AX_RTS_LIMIT_IN_OFDM6); 668 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 669 } 670 671 static const u32 rtw8852c_sco_barker_threshold[14] = { 672 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 673 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 674 }; 675 676 static const u32 rtw8852c_sco_cck_threshold[14] = { 677 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 678 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 679 }; 680 681 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 682 u8 primary_ch, enum rtw89_bandwidth bw) 683 { 684 u8 ch_element; 685 686 if (bw == RTW89_CHANNEL_WIDTH_20) { 687 ch_element = central_ch - 1; 688 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 689 if (primary_ch == 1) 690 ch_element = central_ch - 1 + 2; 691 else 692 ch_element = central_ch - 1 - 2; 693 } else { 694 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 695 return -EINVAL; 696 } 697 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 698 rtw8852c_sco_barker_threshold[ch_element]); 699 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 700 rtw8852c_sco_cck_threshold[ch_element]); 701 702 return 0; 703 } 704 705 struct rtw8852c_bb_gain { 706 u32 gain_g[BB_PATH_NUM_8852C]; 707 u32 gain_a[BB_PATH_NUM_8852C]; 708 u32 gain_mask; 709 }; 710 711 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 712 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 713 .gain_mask = 0x00ff0000 }, 714 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 715 .gain_mask = 0xff000000 }, 716 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 717 .gain_mask = 0x000000ff }, 718 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 719 .gain_mask = 0x0000ff00 }, 720 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 721 .gain_mask = 0x00ff0000 }, 722 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 723 .gain_mask = 0xff000000 }, 724 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 725 .gain_mask = 0x000000ff }, 726 }; 727 728 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 729 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 730 .gain_mask = 0x00ff0000 }, 731 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 732 .gain_mask = 0xff000000 }, 733 }; 734 735 struct rtw8852c_bb_gain_bypass { 736 u32 gain_g[BB_PATH_NUM_8852C]; 737 u32 gain_a[BB_PATH_NUM_8852C]; 738 u32 gain_mask_g; 739 u32 gain_mask_a; 740 }; 741 742 static 743 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 744 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 745 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 746 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 747 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 748 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 749 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 750 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 751 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 752 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 753 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 754 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 755 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 756 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 757 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 758 }; 759 760 struct rtw8852c_bb_gain_op1db { 761 struct { 762 u32 lna[BB_PATH_NUM_8852C]; 763 u32 tia_lna[BB_PATH_NUM_8852C]; 764 u32 mask; 765 } reg[LNA_GAIN_NUM]; 766 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 767 u32 mask_tia0_lna6; 768 }; 769 770 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 771 .reg = { 772 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 773 .mask = 0xff}, 774 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 775 .mask = 0xff00}, 776 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 777 .mask = 0xff0000}, 778 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 779 .mask = 0xff000000}, 780 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 781 .mask = 0xff}, 782 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 783 .mask = 0xff00}, 784 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 785 .mask = 0xff0000}, 786 }, 787 .reg_tia0_lna6 = {0x4674, 0x4758}, 788 .mask_tia0_lna6 = 0xff000000, 789 }; 790 791 static enum rtw89_phy_bb_gain_band 792 rtw8852c_mapping_gain_band(enum rtw89_subband subband) 793 { 794 switch (subband) { 795 default: 796 case RTW89_CH_2G: 797 return RTW89_BB_GAIN_BAND_2G; 798 case RTW89_CH_5G_BAND_1: 799 return RTW89_BB_GAIN_BAND_5G_L; 800 case RTW89_CH_5G_BAND_3: 801 return RTW89_BB_GAIN_BAND_5G_M; 802 case RTW89_CH_5G_BAND_4: 803 return RTW89_BB_GAIN_BAND_5G_H; 804 case RTW89_CH_6G_BAND_IDX0: 805 case RTW89_CH_6G_BAND_IDX1: 806 return RTW89_BB_GAIN_BAND_6G_L; 807 case RTW89_CH_6G_BAND_IDX2: 808 case RTW89_CH_6G_BAND_IDX3: 809 return RTW89_BB_GAIN_BAND_6G_M; 810 case RTW89_CH_6G_BAND_IDX4: 811 case RTW89_CH_6G_BAND_IDX5: 812 return RTW89_BB_GAIN_BAND_6G_H; 813 case RTW89_CH_6G_BAND_IDX6: 814 case RTW89_CH_6G_BAND_IDX7: 815 return RTW89_BB_GAIN_BAND_6G_UH; 816 } 817 } 818 819 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 820 enum rtw89_subband subband, 821 enum rtw89_rf_path path) 822 { 823 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 824 u8 gain_band = rtw8852c_mapping_gain_band(subband); 825 s32 val; 826 u32 reg; 827 u32 mask; 828 int i; 829 830 for (i = 0; i < LNA_GAIN_NUM; i++) { 831 if (subband == RTW89_CH_2G) 832 reg = bb_gain_lna[i].gain_g[path]; 833 else 834 reg = bb_gain_lna[i].gain_a[path]; 835 836 mask = bb_gain_lna[i].gain_mask; 837 val = gain->lna_gain[gain_band][path][i]; 838 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 839 840 if (subband == RTW89_CH_2G) { 841 reg = bb_gain_bypass_lna[i].gain_g[path]; 842 mask = bb_gain_bypass_lna[i].gain_mask_g; 843 } else { 844 reg = bb_gain_bypass_lna[i].gain_a[path]; 845 mask = bb_gain_bypass_lna[i].gain_mask_a; 846 } 847 848 val = gain->lna_gain_bypass[gain_band][path][i]; 849 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 850 851 if (subband != RTW89_CH_2G) { 852 reg = bb_gain_op1db_a.reg[i].lna[path]; 853 mask = bb_gain_op1db_a.reg[i].mask; 854 val = gain->lna_op1db[gain_band][path][i]; 855 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 856 857 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 858 mask = bb_gain_op1db_a.reg[i].mask; 859 val = gain->tia_lna_op1db[gain_band][path][i]; 860 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 861 } 862 } 863 864 if (subband != RTW89_CH_2G) { 865 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 866 mask = bb_gain_op1db_a.mask_tia0_lna6; 867 val = gain->tia_lna_op1db[gain_band][path][7]; 868 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 869 } 870 871 for (i = 0; i < TIA_GAIN_NUM; i++) { 872 if (subband == RTW89_CH_2G) 873 reg = bb_gain_tia[i].gain_g[path]; 874 else 875 reg = bb_gain_tia[i].gain_a[path]; 876 877 mask = bb_gain_tia[i].gain_mask; 878 val = gain->tia_gain[gain_band][path][i]; 879 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 880 } 881 } 882 883 static 884 const u8 rtw8852c_ch_base_table[16] = {1, 0xff, 885 36, 100, 132, 149, 0xff, 886 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 887 #define RTW8852C_CH_BASE_IDX_2G 0 888 #define RTW8852C_CH_BASE_IDX_5G_FIRST 2 889 #define RTW8852C_CH_BASE_IDX_5G_LAST 5 890 #define RTW8852C_CH_BASE_IDX_6G_FIRST 7 891 #define RTW8852C_CH_BASE_IDX_6G_LAST 14 892 893 #define RTW8852C_CH_BASE_IDX_MASK GENMASK(7, 4) 894 #define RTW8852C_CH_OFFSET_MASK GENMASK(3, 0) 895 896 static u8 rtw8852c_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 897 { 898 u8 chan_idx; 899 u8 last, first; 900 u8 idx; 901 902 switch (band) { 903 case RTW89_BAND_2G: 904 chan_idx = FIELD_PREP(RTW8852C_CH_BASE_IDX_MASK, RTW8852C_CH_BASE_IDX_2G) | 905 FIELD_PREP(RTW8852C_CH_OFFSET_MASK, central_ch); 906 return chan_idx; 907 case RTW89_BAND_5G: 908 first = RTW8852C_CH_BASE_IDX_5G_FIRST; 909 last = RTW8852C_CH_BASE_IDX_5G_LAST; 910 break; 911 case RTW89_BAND_6G: 912 first = RTW8852C_CH_BASE_IDX_6G_FIRST; 913 last = RTW8852C_CH_BASE_IDX_6G_LAST; 914 break; 915 default: 916 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 917 return 0; 918 } 919 920 for (idx = last; idx >= first; idx--) 921 if (central_ch >= rtw8852c_ch_base_table[idx]) 922 break; 923 924 if (idx < first) { 925 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 926 return 0; 927 } 928 929 chan_idx = FIELD_PREP(RTW8852C_CH_BASE_IDX_MASK, idx) | 930 FIELD_PREP(RTW8852C_CH_OFFSET_MASK, 931 (central_ch - rtw8852c_ch_base_table[idx]) >> 1); 932 return chan_idx; 933 } 934 935 static void rtw8852c_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 936 u8 *ch, enum nl80211_band *band) 937 { 938 u8 idx, offset; 939 940 idx = FIELD_GET(RTW8852C_CH_BASE_IDX_MASK, chan_idx); 941 offset = FIELD_GET(RTW8852C_CH_OFFSET_MASK, chan_idx); 942 943 if (idx == RTW8852C_CH_BASE_IDX_2G) { 944 *band = NL80211_BAND_2GHZ; 945 *ch = offset; 946 return; 947 } 948 949 *band = idx <= RTW8852C_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 950 *ch = rtw8852c_ch_base_table[idx] + (offset << 1); 951 } 952 953 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 954 const struct rtw89_chan *chan, 955 enum rtw89_phy_idx phy_idx, 956 enum rtw89_rf_path path) 957 { 958 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 959 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 960 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 961 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 962 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 963 enum rtw89_gain_offset gain_band; 964 s32 offset_q0, offset_base_q4; 965 s32 tmp = 0; 966 967 if (!efuse_gain->offset_valid) 968 return; 969 970 if (rtwdev->dbcc_en && path == RF_PATH_B) 971 phy_idx = RTW89_PHY_1; 972 973 if (chan->band_type == RTW89_BAND_2G) { 974 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 975 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 976 977 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 978 S8_MIN >> 1, S8_MAX >> 1); 979 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 980 } 981 982 switch (chan->subband_type) { 983 default: 984 case RTW89_CH_2G: 985 gain_band = RTW89_GAIN_OFFSET_2G_OFDM; 986 break; 987 case RTW89_CH_5G_BAND_1: 988 gain_band = RTW89_GAIN_OFFSET_5G_LOW; 989 break; 990 case RTW89_CH_5G_BAND_3: 991 gain_band = RTW89_GAIN_OFFSET_5G_MID; 992 break; 993 case RTW89_CH_5G_BAND_4: 994 gain_band = RTW89_GAIN_OFFSET_5G_HIGH; 995 break; 996 } 997 998 offset_q0 = -efuse_gain->offset[path][gain_band]; 999 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 1000 1001 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 1002 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 1003 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 1004 1005 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 1006 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 1007 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 1008 } 1009 1010 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 1011 const struct rtw89_chan *chan, 1012 enum rtw89_phy_idx phy_idx) 1013 { 1014 u8 sco; 1015 u16 central_freq = chan->freq; 1016 u8 central_ch = chan->channel; 1017 u8 band = chan->band_type; 1018 u8 subband = chan->subband_type; 1019 bool is_2g = band == RTW89_BAND_2G; 1020 u8 chan_idx; 1021 1022 if (!central_freq) { 1023 rtw89_warn(rtwdev, "Invalid central_freq\n"); 1024 return; 1025 } 1026 1027 if (phy_idx == RTW89_PHY_0) { 1028 /* Path A */ 1029 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 1030 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 1031 1032 if (is_2g) 1033 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1034 B_PATH0_BAND_SEL_MSK_V1, 1, 1035 phy_idx); 1036 else 1037 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1038 B_PATH0_BAND_SEL_MSK_V1, 0, 1039 phy_idx); 1040 /* Path B */ 1041 if (!rtwdev->dbcc_en) { 1042 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1043 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 1044 1045 if (is_2g) 1046 rtw89_phy_write32_idx(rtwdev, 1047 R_PATH1_BAND_SEL_V1, 1048 B_PATH1_BAND_SEL_MSK_V1, 1049 1, phy_idx); 1050 else 1051 rtw89_phy_write32_idx(rtwdev, 1052 R_PATH1_BAND_SEL_V1, 1053 B_PATH1_BAND_SEL_MSK_V1, 1054 0, phy_idx); 1055 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1056 } else { 1057 if (is_2g) 1058 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1059 else 1060 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1061 } 1062 /* SCO compensate FC setting */ 1063 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1064 central_freq, phy_idx); 1065 /* round_up((1/fc0)*pow(2,18)) */ 1066 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1067 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1068 phy_idx); 1069 } else { 1070 /* Path B */ 1071 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1072 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 1073 1074 if (is_2g) 1075 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1076 B_PATH1_BAND_SEL_MSK_V1, 1077 1, phy_idx); 1078 else 1079 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1080 B_PATH1_BAND_SEL_MSK_V1, 1081 0, phy_idx); 1082 /* SCO compensate FC setting */ 1083 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1084 central_freq, phy_idx); 1085 /* round_up((1/fc0)*pow(2,18)) */ 1086 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1087 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1088 phy_idx); 1089 } 1090 /* CCK parameters */ 1091 if (band == RTW89_BAND_2G) { 1092 if (central_ch == 14) { 1093 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1094 B_PCOEFF01_MSK_V1, 0x3b13ff); 1095 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1096 B_PCOEFF23_MSK_V1, 0x1c42de); 1097 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1098 B_PCOEFF45_MSK_V1, 0xfdb0ad); 1099 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1100 B_PCOEFF67_MSK_V1, 0xf60f6e); 1101 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1102 B_PCOEFF89_MSK_V1, 0xfd8f92); 1103 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1104 B_PCOEFFAB_MSK_V1, 0x2d011); 1105 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1106 B_PCOEFFCD_MSK_V1, 0x1c02c); 1107 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1108 B_PCOEFFEF_MSK_V1, 0xfff00a); 1109 } else { 1110 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1111 B_PCOEFF01_MSK_V1, 0x3d23ff); 1112 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1113 B_PCOEFF23_MSK_V1, 0x29b354); 1114 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1115 B_PCOEFF45_MSK_V1, 0xfc1c8); 1116 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1117 B_PCOEFF67_MSK_V1, 0xfdb053); 1118 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1119 B_PCOEFF89_MSK_V1, 0xf86f9a); 1120 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1121 B_PCOEFFAB_MSK_V1, 0xfaef92); 1122 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1123 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1124 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1125 B_PCOEFFEF_MSK_V1, 0xffdff5); 1126 } 1127 } 1128 1129 chan_idx = rtw8852c_encode_chan_idx(rtwdev, chan->primary_channel, band); 1130 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1131 } 1132 1133 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1134 { 1135 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1136 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1137 1138 switch (bw) { 1139 case RTW89_CHANNEL_WIDTH_5: 1140 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1141 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1142 break; 1143 case RTW89_CHANNEL_WIDTH_10: 1144 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1145 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1146 break; 1147 case RTW89_CHANNEL_WIDTH_20: 1148 case RTW89_CHANNEL_WIDTH_40: 1149 case RTW89_CHANNEL_WIDTH_80: 1150 case RTW89_CHANNEL_WIDTH_160: 1151 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1152 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1153 break; 1154 default: 1155 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1156 } 1157 } 1158 1159 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1160 enum rtw89_phy_idx phy_idx) 1161 { 1162 if (bw == RTW89_CHANNEL_WIDTH_20) { 1163 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1164 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1165 } else { 1166 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1167 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1168 } 1169 } 1170 1171 static void 1172 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1173 enum rtw89_phy_idx phy_idx) 1174 { 1175 u8 mod_sbw = 0; 1176 1177 switch (bw) { 1178 case RTW89_CHANNEL_WIDTH_5: 1179 case RTW89_CHANNEL_WIDTH_10: 1180 case RTW89_CHANNEL_WIDTH_20: 1181 if (bw == RTW89_CHANNEL_WIDTH_5) 1182 mod_sbw = 0x1; 1183 else if (bw == RTW89_CHANNEL_WIDTH_10) 1184 mod_sbw = 0x2; 1185 else if (bw == RTW89_CHANNEL_WIDTH_20) 1186 mod_sbw = 0x0; 1187 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1188 phy_idx); 1189 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1190 mod_sbw, phy_idx); 1191 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1192 phy_idx); 1193 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1194 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1195 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1196 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1197 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1198 B_PATH0_BW_SEL_MSK_V1, 0xf); 1199 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1200 B_PATH1_BW_SEL_MSK_V1, 0xf); 1201 break; 1202 case RTW89_CHANNEL_WIDTH_40: 1203 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1204 phy_idx); 1205 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1206 phy_idx); 1207 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1208 pri_ch, 1209 phy_idx); 1210 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1211 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1212 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1213 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1214 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1215 B_PATH0_BW_SEL_MSK_V1, 0xf); 1216 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1217 B_PATH1_BW_SEL_MSK_V1, 0xf); 1218 break; 1219 case RTW89_CHANNEL_WIDTH_80: 1220 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1221 phy_idx); 1222 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1223 phy_idx); 1224 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1225 pri_ch, 1226 phy_idx); 1227 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1228 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1229 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1230 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1231 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1232 B_PATH0_BW_SEL_MSK_V1, 0xd); 1233 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1234 B_PATH1_BW_SEL_MSK_V1, 0xd); 1235 break; 1236 case RTW89_CHANNEL_WIDTH_160: 1237 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1238 phy_idx); 1239 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1240 phy_idx); 1241 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1242 pri_ch, 1243 phy_idx); 1244 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1245 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1246 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1247 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1248 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1249 B_PATH0_BW_SEL_MSK_V1, 0xb); 1250 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1251 B_PATH1_BW_SEL_MSK_V1, 0xb); 1252 break; 1253 default: 1254 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1255 pri_ch); 1256 } 1257 1258 if (bw == RTW89_CHANNEL_WIDTH_40) { 1259 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1260 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1261 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1262 } else { 1263 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1264 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1265 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1266 } 1267 1268 if (phy_idx == RTW89_PHY_0) { 1269 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1270 if (!rtwdev->dbcc_en) 1271 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1272 } else { 1273 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1274 } 1275 1276 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1277 } 1278 1279 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1280 const struct rtw89_chan *chan) 1281 { 1282 u8 center_chan = chan->channel; 1283 u8 bw = chan->band_width; 1284 1285 switch (chan->band_type) { 1286 case RTW89_BAND_2G: 1287 if (bw == RTW89_CHANNEL_WIDTH_20) { 1288 if (center_chan >= 5 && center_chan <= 8) 1289 return 2440; 1290 if (center_chan == 13) 1291 return 2480; 1292 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1293 if (center_chan >= 3 && center_chan <= 10) 1294 return 2440; 1295 } 1296 break; 1297 case RTW89_BAND_5G: 1298 if (center_chan == 151 || center_chan == 153 || 1299 center_chan == 155 || center_chan == 163) 1300 return 5760; 1301 break; 1302 case RTW89_BAND_6G: 1303 if (center_chan == 195 || center_chan == 197 || 1304 center_chan == 199 || center_chan == 207) 1305 return 6920; 1306 break; 1307 default: 1308 break; 1309 } 1310 1311 return 0; 1312 } 1313 1314 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1315 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1316 #define MAX_TONE_NUM 2048 1317 1318 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1319 const struct rtw89_chan *chan, 1320 enum rtw89_phy_idx phy_idx) 1321 { 1322 u32 spur_freq; 1323 s32 freq_diff, csi_idx, csi_tone_idx; 1324 1325 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1326 if (spur_freq == 0) { 1327 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1328 return; 1329 } 1330 1331 freq_diff = (spur_freq - chan->freq) * 1000000; 1332 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1333 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1334 1335 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1336 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1337 } 1338 1339 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1340 [RF_PATH_A] = { 1341 .notch1_idx = {0x4C14, 0xFF}, 1342 .notch1_frac_idx = {0x4C14, 0xC00}, 1343 .notch1_en = {0x4C14, 0x1000}, 1344 .notch2_idx = {0x4C20, 0xFF}, 1345 .notch2_frac_idx = {0x4C20, 0xC00}, 1346 .notch2_en = {0x4C20, 0x1000}, 1347 }, 1348 [RF_PATH_B] = { 1349 .notch1_idx = {0x4CD8, 0xFF}, 1350 .notch1_frac_idx = {0x4CD8, 0xC00}, 1351 .notch1_en = {0x4CD8, 0x1000}, 1352 .notch2_idx = {0x4CE4, 0xFF}, 1353 .notch2_frac_idx = {0x4CE4, 0xC00}, 1354 .notch2_en = {0x4CE4, 0x1000}, 1355 }, 1356 }; 1357 1358 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1359 const struct rtw89_chan *chan, 1360 enum rtw89_rf_path path) 1361 { 1362 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1363 u32 spur_freq, fc; 1364 s32 freq_diff; 1365 s32 nbi_idx, nbi_tone_idx; 1366 s32 nbi_frac_idx, nbi_frac_tone_idx; 1367 bool notch2_chk = false; 1368 1369 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1370 if (spur_freq == 0) { 1371 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1372 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1373 return; 1374 } 1375 1376 fc = chan->freq; 1377 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1378 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1379 if ((fc > spur_freq && 1380 chan->channel < chan->primary_channel) || 1381 (fc < spur_freq && 1382 chan->channel > chan->primary_channel)) 1383 notch2_chk = true; 1384 } 1385 1386 freq_diff = (spur_freq - fc) * 1000000; 1387 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1388 1389 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1390 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1391 } else { 1392 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1393 128 : 256; 1394 1395 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1396 } 1397 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1398 1399 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1400 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1401 nbi->notch2_idx.mask, nbi_tone_idx); 1402 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1403 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1404 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1405 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1406 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1407 } else { 1408 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1409 nbi->notch1_idx.mask, nbi_tone_idx); 1410 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1411 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1412 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1413 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1414 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1415 } 1416 } 1417 1418 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1419 enum rtw89_phy_idx phy_idx) 1420 { 1421 u32 notch; 1422 u32 notch2; 1423 1424 if (phy_idx == RTW89_PHY_0) { 1425 notch = R_PATH0_NOTCH; 1426 notch2 = R_PATH0_NOTCH2; 1427 } else { 1428 notch = R_PATH1_NOTCH; 1429 notch2 = R_PATH1_NOTCH2; 1430 } 1431 1432 rtw89_phy_write32_mask(rtwdev, notch, 1433 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1434 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1435 rtw89_phy_write32_mask(rtwdev, notch2, 1436 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1437 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1438 } 1439 1440 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1441 const struct rtw89_chan *chan, 1442 u8 pri_ch_idx, 1443 enum rtw89_phy_idx phy_idx) 1444 { 1445 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1446 1447 if (phy_idx == RTW89_PHY_0) { 1448 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1449 (pri_ch_idx == RTW89_SC_20_LOWER || 1450 pri_ch_idx == RTW89_SC_20_UP3X)) { 1451 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1452 if (!rtwdev->dbcc_en) 1453 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1454 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1455 (pri_ch_idx == RTW89_SC_20_UPPER || 1456 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1457 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1458 if (!rtwdev->dbcc_en) 1459 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1460 } else { 1461 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1462 if (!rtwdev->dbcc_en) 1463 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1464 RF_PATH_B); 1465 } 1466 } else { 1467 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1468 (pri_ch_idx == RTW89_SC_20_LOWER || 1469 pri_ch_idx == RTW89_SC_20_UP3X)) { 1470 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1471 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1472 (pri_ch_idx == RTW89_SC_20_UPPER || 1473 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1474 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1475 } else { 1476 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1477 } 1478 } 1479 1480 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1481 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1482 else 1483 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1484 } 1485 1486 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1487 const struct rtw89_chan *chan, 1488 enum rtw89_phy_idx phy_idx) 1489 { 1490 u8 pri_ch = chan->primary_channel; 1491 bool mask_5m_low; 1492 bool mask_5m_en; 1493 1494 switch (chan->band_width) { 1495 case RTW89_CHANNEL_WIDTH_40: 1496 mask_5m_en = true; 1497 mask_5m_low = pri_ch == 2; 1498 break; 1499 case RTW89_CHANNEL_WIDTH_80: 1500 mask_5m_en = ((pri_ch == 3) || (pri_ch == 4)); 1501 mask_5m_low = pri_ch == 4; 1502 break; 1503 default: 1504 mask_5m_en = false; 1505 mask_5m_low = false; 1506 break; 1507 } 1508 1509 if (!mask_5m_en) { 1510 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1511 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1512 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1513 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1514 } else { 1515 if (mask_5m_low) { 1516 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1517 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1518 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1519 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1520 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1521 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1522 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1523 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1524 } else { 1525 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1526 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1527 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1528 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1529 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1530 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1531 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1532 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1533 } 1534 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1535 } 1536 } 1537 1538 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1539 enum rtw89_phy_idx phy_idx) 1540 { 1541 /*HW SI reset*/ 1542 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1543 0x7); 1544 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1545 0x7); 1546 1547 udelay(1); 1548 1549 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1550 phy_idx); 1551 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1552 phy_idx); 1553 /*HW SI reset*/ 1554 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1555 0x0); 1556 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1557 0x0); 1558 1559 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1560 phy_idx); 1561 } 1562 1563 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1564 enum rtw89_phy_idx phy_idx, bool en) 1565 { 1566 if (en) { 1567 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1568 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1569 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1570 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1571 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1572 phy_idx); 1573 if (band == RTW89_BAND_2G) 1574 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1575 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1576 } else { 1577 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1578 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1579 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1580 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1581 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1582 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1583 fsleep(1); 1584 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1585 phy_idx); 1586 } 1587 } 1588 1589 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1590 enum rtw89_phy_idx phy_idx) 1591 { 1592 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1593 } 1594 1595 static 1596 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1597 u8 tx_path_en, u8 trsw_tx, 1598 u8 trsw_rx, u8 trsw, u8 trsw_b) 1599 { 1600 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1601 u32 mask_ofst = 16; 1602 u32 cr; 1603 u32 val; 1604 1605 if (path >= ARRAY_SIZE(path_cr_bases)) 1606 return; 1607 1608 cr = path_cr_bases[path]; 1609 1610 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1611 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1612 1613 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1614 } 1615 1616 enum rtw8852c_rfe_src { 1617 PAPE_RFM, 1618 TRSW_RFM, 1619 LNAON_RFM, 1620 }; 1621 1622 static 1623 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1624 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1625 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1626 { 1627 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1628 static const u32 masks[] = {0, 8, 16}; 1629 u32 mask, mask_ofst; 1630 u32 cr; 1631 u32 val; 1632 1633 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1634 return; 1635 1636 mask_ofst = masks[src]; 1637 cr = path_cr_bases[path]; 1638 1639 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1640 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1641 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1642 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1643 mask = 0xff << mask_ofst; 1644 1645 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1646 } 1647 1648 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1649 { 1650 static const u32 cr_bases[] = {0x5800, 0x7800}; 1651 u32 addr; 1652 u8 i; 1653 1654 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1655 addr = cr_bases[i]; 1656 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1657 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1658 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1659 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1660 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1661 } 1662 1663 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1664 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1665 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1666 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1667 1668 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1669 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1670 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1671 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1672 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1673 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1674 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1675 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1676 1677 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1678 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1679 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1680 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1681 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1682 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1683 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1684 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1685 1686 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1687 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1688 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1689 1690 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1691 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1692 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1693 } 1694 1695 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1696 enum rtw89_phy_idx phy_idx) 1697 { 1698 u32 addr; 1699 1700 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1701 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1702 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1703 } 1704 1705 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1706 { 1707 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1708 1709 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1710 B_DBCC_80P80_SEL_EVM_RPT_EN); 1711 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1712 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1713 1714 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1715 rtw8852c_bb_gpio_init(rtwdev); 1716 1717 /* read these registers after loading BB parameters */ 1718 gain->offset_base[RTW89_PHY_0] = 1719 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1720 gain->offset_base[RTW89_PHY_1] = 1721 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1722 } 1723 1724 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1725 const struct rtw89_chan *chan, 1726 enum rtw89_phy_idx phy_idx) 1727 { 1728 struct rtw89_hal *hal = &rtwdev->hal; 1729 bool cck_en = chan->band_type == RTW89_BAND_2G; 1730 u8 pri_ch_idx = chan->pri_ch_idx; 1731 u32 mask, reg; 1732 u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1733 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1734 u8 ntx_path; 1735 1736 if (chan->band_type == RTW89_BAND_2G) 1737 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1738 chan->primary_channel, 1739 chan->band_width); 1740 1741 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1742 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1743 if (cck_en) { 1744 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1745 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1746 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1747 B_PD_ARBITER_OFF, 0x0, phy_idx); 1748 } else { 1749 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1750 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1751 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1752 B_PD_ARBITER_OFF, 0x1, phy_idx); 1753 } 1754 1755 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1756 rtw8852c_ctrl_btg(rtwdev, chan->band_type == RTW89_BAND_2G); 1757 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1758 1759 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1760 rtwdev->hal.cv != CHIP_CAV) { 1761 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1762 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1763 reg = rtw89_mac_reg_by_idx(R_P80_AT_HIGH_FREQ_BB_WRP, 1764 phy_idx); 1765 if (chan->primary_channel > chan->channel) { 1766 rtw89_phy_write32_mask(rtwdev, 1767 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1768 ru_alloc_msk[phy_idx], 1); 1769 rtw89_write32_mask(rtwdev, reg, 1770 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1771 } else { 1772 rtw89_phy_write32_mask(rtwdev, 1773 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1774 ru_alloc_msk[phy_idx], 0); 1775 rtw89_write32_mask(rtwdev, reg, 1776 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1777 } 1778 } 1779 1780 if (chan->band_type == RTW89_BAND_6G && 1781 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1782 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1783 B_CDD_EVM_CHK_EN, 0, phy_idx); 1784 else 1785 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1786 B_CDD_EVM_CHK_EN, 1, phy_idx); 1787 1788 if (!rtwdev->dbcc_en) { 1789 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1790 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1791 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1792 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1793 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1794 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1795 } else { 1796 if (phy_idx == RTW89_PHY_0) { 1797 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1798 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1799 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1800 } else { 1801 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1802 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1803 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1804 } 1805 } 1806 1807 if (chan->band_type == RTW89_BAND_6G) 1808 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1809 else 1810 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1811 1812 if (hal->antenna_tx) 1813 ntx_path = hal->antenna_tx; 1814 else 1815 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1816 1817 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1818 1819 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1820 } 1821 1822 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1823 const struct rtw89_chan *chan, 1824 enum rtw89_mac_idx mac_idx, 1825 enum rtw89_phy_idx phy_idx) 1826 { 1827 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1828 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1829 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1830 } 1831 1832 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1833 { 1834 if (en) 1835 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1836 else 1837 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1838 } 1839 1840 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1841 { 1842 if (en) 1843 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1844 0x0); 1845 else 1846 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1847 0xf); 1848 } 1849 1850 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1851 struct rtw89_channel_help_params *p, 1852 const struct rtw89_chan *chan, 1853 enum rtw89_mac_idx mac_idx, 1854 enum rtw89_phy_idx phy_idx) 1855 { 1856 if (enter) { 1857 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1858 RTW89_SCH_TX_SEL_ALL); 1859 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1860 rtw8852c_dfs_en(rtwdev, false); 1861 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1862 rtw8852c_adc_en(rtwdev, false); 1863 fsleep(40); 1864 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1865 } else { 1866 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1867 rtw8852c_adc_en(rtwdev, true); 1868 rtw8852c_dfs_en(rtwdev, true); 1869 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1870 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1871 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1872 } 1873 } 1874 1875 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1876 { 1877 struct rtw89_mcc_info *mcc_info = &rtwdev->mcc; 1878 1879 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1880 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1881 memset(mcc_info, 0, sizeof(*mcc_info)); 1882 rtw8852c_lck_init(rtwdev); 1883 1884 rtw8852c_rck(rtwdev); 1885 rtw8852c_dack(rtwdev); 1886 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1887 } 1888 1889 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) 1890 { 1891 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1892 1893 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1894 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1895 rtw8852c_iqk(rtwdev, phy_idx); 1896 rtw8852c_tssi(rtwdev, phy_idx); 1897 rtw8852c_dpk(rtwdev, phy_idx); 1898 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1899 } 1900 1901 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1902 enum rtw89_phy_idx phy_idx) 1903 { 1904 rtw8852c_tssi_scan(rtwdev, phy_idx); 1905 } 1906 1907 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1908 { 1909 rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1910 } 1911 1912 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1913 { 1914 rtw8852c_dpk_track(rtwdev); 1915 rtw8852c_lck_track(rtwdev); 1916 rtw8852c_rx_dck_track(rtwdev); 1917 } 1918 1919 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1920 enum rtw89_phy_idx phy_idx, s16 ref) 1921 { 1922 s8 ofst_int = 0; 1923 u8 base_cw_0db = 0x27; 1924 u16 tssi_16dbm_cw = 0x12c; 1925 s16 pwr_s10_3 = 0; 1926 s16 rf_pwr_cw = 0; 1927 u16 bb_pwr_cw = 0; 1928 u32 pwr_cw = 0; 1929 u32 tssi_ofst_cw = 0; 1930 1931 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1932 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1933 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1934 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1935 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1936 1937 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1938 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1939 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1940 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1941 1942 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1943 } 1944 1945 static 1946 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1947 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1948 { 1949 s8 pw_ofst_2tx; 1950 s8 val_1t; 1951 s8 val_2t; 1952 u32 reg; 1953 u8 i; 1954 1955 if (pw_ofst < -32 || pw_ofst > 31) { 1956 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1957 return; 1958 } 1959 val_1t = pw_ofst << 2; 1960 pw_ofst_2tx = max(pw_ofst - 3, -32); 1961 val_2t = pw_ofst_2tx << 2; 1962 1963 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1964 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1965 1966 for (i = 0; i < 4; i++) { 1967 /* 1TX */ 1968 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1969 rtw89_write32_mask(rtwdev, reg, 1970 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1971 val_1t); 1972 /* 2TX */ 1973 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1974 rtw89_write32_mask(rtwdev, reg, 1975 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1976 val_2t); 1977 } 1978 } 1979 1980 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1981 enum rtw89_phy_idx phy_idx) 1982 { 1983 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1984 const u32 mask = 0x7FFFFFF; 1985 const u8 ofst_ofdm = 0x4; 1986 const u8 ofst_cck = 0x8; 1987 s16 ref_ofdm = 0; 1988 s16 ref_cck = 0; 1989 u32 val; 1990 u8 i; 1991 1992 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1993 1994 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1995 GENMASK(27, 10), 0x0); 1996 1997 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1998 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1999 2000 for (i = 0; i < RF_PATH_NUM_8852C; i++) 2001 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 2002 phy_idx); 2003 2004 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 2005 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 2006 2007 for (i = 0; i < RF_PATH_NUM_8852C; i++) 2008 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 2009 phy_idx); 2010 } 2011 2012 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 2013 u8 tx_shape_idx, 2014 enum rtw89_phy_idx phy_idx) 2015 { 2016 #define __DFIR_CFG_MASK 0xffffff 2017 #define __DFIR_CFG_NR 8 2018 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 2019 static const u32 _prefix ## _ ## _name[] = {_val}; \ 2020 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 2021 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 2022 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 2023 2024 __DECL_DFIR_PARAM(flat, 2025 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 2026 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 2027 __DECL_DFIR_PARAM(sharp, 2028 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 2029 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 2030 __DECL_DFIR_PARAM(sharp_14, 2031 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 2032 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 2033 __DECL_DFIR_ADDR(filter, 2034 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 2035 0x45C4, 0x45C8); 2036 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2037 u8 ch = chan->channel; 2038 const u32 *param; 2039 int i; 2040 2041 if (ch > 14) { 2042 rtw89_warn(rtwdev, 2043 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 2044 return; 2045 } 2046 2047 if (ch == 14) 2048 param = param_sharp_14; 2049 else 2050 param = tx_shape_idx == 0 ? param_flat : param_sharp; 2051 2052 for (i = 0; i < __DFIR_CFG_NR; i++) { 2053 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2054 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 2055 param[i]); 2056 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 2057 param[i], phy_idx); 2058 } 2059 2060 #undef __DECL_DFIR_ADDR 2061 #undef __DECL_DFIR_PARAM 2062 #undef __DECL_DFIR_VAR 2063 #undef __DFIR_CFG_NR 2064 #undef __DFIR_CFG_MASK 2065 } 2066 2067 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 2068 const struct rtw89_chan *chan, 2069 enum rtw89_phy_idx phy_idx) 2070 { 2071 u8 band = chan->band_type; 2072 u8 regd = rtw89_regd_get(rtwdev, band); 2073 u8 tx_shape_cck = rtw89_8852c_tx_shape[band][RTW89_RS_CCK][regd]; 2074 u8 tx_shape_ofdm = rtw89_8852c_tx_shape[band][RTW89_RS_OFDM][regd]; 2075 2076 if (band == RTW89_BAND_2G) 2077 rtw8852c_bb_set_tx_shape_dfir(rtwdev, tx_shape_cck, phy_idx); 2078 2079 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2080 (enum rtw89_mac_idx)phy_idx, 2081 tx_shape_ofdm); 2082 } 2083 2084 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 2085 const struct rtw89_chan *chan, 2086 enum rtw89_phy_idx phy_idx) 2087 { 2088 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 2089 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 2090 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 2091 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 2092 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 2093 } 2094 2095 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 2096 enum rtw89_phy_idx phy_idx) 2097 { 2098 rtw8852c_set_txpwr_ref(rtwdev, phy_idx); 2099 } 2100 2101 static void 2102 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2103 { 2104 static const struct rtw89_reg2_def ctrl_ini[] = { 2105 {0xD938, 0x00010100}, 2106 {0xD93C, 0x0500D500}, 2107 {0xD940, 0x00000500}, 2108 {0xD944, 0x00000005}, 2109 {0xD94C, 0x00220000}, 2110 {0xD950, 0x00030000}, 2111 }; 2112 u32 addr; 2113 int i; 2114 2115 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2116 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2117 2118 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2119 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2120 ctrl_ini[i].data); 2121 2122 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2123 (enum rtw89_mac_idx)phy_idx, 2124 RTW89_TSSI_BANDEDGE_FLAT); 2125 } 2126 2127 static int 2128 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2129 { 2130 int ret; 2131 2132 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2133 if (ret) 2134 return ret; 2135 2136 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2137 if (ret) 2138 return ret; 2139 2140 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2141 if (ret) 2142 return ret; 2143 2144 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2145 RTW89_MAC_1 : 2146 RTW89_MAC_0); 2147 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2148 2149 return 0; 2150 } 2151 2152 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2153 { 2154 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2155 u8 band = chan->band_type; 2156 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2157 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2158 2159 if (rtwdev->dbcc_en) { 2160 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2161 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2162 RTW89_PHY_1); 2163 2164 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2165 1); 2166 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2167 1); 2168 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2169 RTW89_PHY_1); 2170 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2171 RTW89_PHY_1); 2172 2173 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2174 B_RXHT_MCS_LIMIT, 0); 2175 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2176 B_RXVHT_MCS_LIMIT, 0); 2177 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2178 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2179 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2180 2181 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2182 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2183 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2184 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2185 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2186 RTW89_PHY_1); 2187 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2188 RTW89_PHY_1); 2189 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2190 RTW89_PHY_1); 2191 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2192 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2193 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2194 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2195 } else { 2196 if (rx_path == RF_PATH_A) { 2197 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2198 B_ANT_RX_SEG0, 1); 2199 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2200 B_ANT_RX_1RCCA_SEG0, 1); 2201 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2202 B_ANT_RX_1RCCA_SEG1, 1); 2203 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2204 B_RXHT_MCS_LIMIT, 0); 2205 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2206 B_RXVHT_MCS_LIMIT, 0); 2207 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2208 0); 2209 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2210 0); 2211 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2212 rst_mask0, 1); 2213 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2214 rst_mask0, 3); 2215 } else if (rx_path == RF_PATH_B) { 2216 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2217 B_ANT_RX_SEG0, 2); 2218 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2219 B_ANT_RX_1RCCA_SEG0, 2); 2220 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2221 B_ANT_RX_1RCCA_SEG1, 2); 2222 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2223 B_RXHT_MCS_LIMIT, 0); 2224 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2225 B_RXVHT_MCS_LIMIT, 0); 2226 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2227 0); 2228 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2229 0); 2230 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2231 rst_mask1, 1); 2232 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2233 rst_mask1, 3); 2234 } else { 2235 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2236 B_ANT_RX_SEG0, 3); 2237 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2238 B_ANT_RX_1RCCA_SEG0, 3); 2239 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2240 B_ANT_RX_1RCCA_SEG1, 3); 2241 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2242 B_RXHT_MCS_LIMIT, 1); 2243 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2244 B_RXVHT_MCS_LIMIT, 1); 2245 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2246 1); 2247 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2248 1); 2249 rtw8852c_ctrl_btg(rtwdev, band == RTW89_BAND_2G); 2250 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2251 rst_mask0, 1); 2252 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2253 rst_mask0, 3); 2254 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2255 rst_mask1, 1); 2256 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2257 rst_mask1, 3); 2258 } 2259 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2260 } 2261 } 2262 2263 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2264 enum rtw89_mac_idx mac_idx) 2265 { 2266 struct rtw89_reg2_def path_com[] = { 2267 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2268 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2269 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2270 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2271 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2272 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2273 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2274 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2275 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2276 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2277 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2278 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2279 }; 2280 u32 addr; 2281 u32 reg; 2282 u8 cr_size = ARRAY_SIZE(path_com); 2283 u8 i = 0; 2284 2285 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2286 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2287 2288 for (addr = R_AX_MACID_ANT_TABLE; 2289 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2290 reg = rtw89_mac_reg_by_idx(addr, mac_idx); 2291 rtw89_write32(rtwdev, reg, 0); 2292 } 2293 2294 if (tx_path == RF_A) { 2295 path_com[0].data = AX_PATH_COM0_PATHA; 2296 path_com[1].data = AX_PATH_COM1_PATHA; 2297 path_com[2].data = AX_PATH_COM2_PATHA; 2298 path_com[7].data = AX_PATH_COM7_PATHA; 2299 path_com[8].data = AX_PATH_COM8_PATHA; 2300 } else if (tx_path == RF_B) { 2301 path_com[0].data = AX_PATH_COM0_PATHB; 2302 path_com[1].data = AX_PATH_COM1_PATHB; 2303 path_com[2].data = AX_PATH_COM2_PATHB; 2304 path_com[7].data = AX_PATH_COM7_PATHB; 2305 path_com[8].data = AX_PATH_COM8_PATHB; 2306 } else if (tx_path == RF_AB) { 2307 path_com[0].data = AX_PATH_COM0_PATHAB; 2308 path_com[1].data = AX_PATH_COM1_PATHAB; 2309 path_com[2].data = AX_PATH_COM2_PATHAB; 2310 path_com[7].data = AX_PATH_COM7_PATHAB; 2311 path_com[8].data = AX_PATH_COM8_PATHAB; 2312 } else { 2313 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2314 return; 2315 } 2316 2317 for (i = 0; i < cr_size; i++) { 2318 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2319 path_com[i].addr, path_com[i].data); 2320 reg = rtw89_mac_reg_by_idx(path_com[i].addr, mac_idx); 2321 rtw89_write32(rtwdev, reg, path_com[i].data); 2322 } 2323 } 2324 2325 static void rtw8852c_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 2326 { 2327 if (bt_en) { 2328 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2329 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2330 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2331 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2332 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2333 B_PATH0_RXBB_MSK_V1, 0xf); 2334 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2335 B_PATH1_RXBB_MSK_V1, 0xf); 2336 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2337 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2338 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2339 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2340 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2341 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2342 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2343 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2344 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2345 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2346 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2347 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2348 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2349 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2350 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2351 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2352 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2353 B_P0_BACKOFF_IBADC_V1, 0x34); 2354 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2355 B_P1_BACKOFF_IBADC_V1, 0x34); 2356 } else { 2357 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2358 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2359 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2360 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2361 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2362 B_PATH0_RXBB_MSK_V1, 0x60); 2363 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2364 B_PATH1_RXBB_MSK_V1, 0x60); 2365 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2366 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2367 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2368 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2369 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2370 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2371 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2372 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2373 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2374 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2375 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2376 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2377 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2378 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2379 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2380 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2381 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2382 B_P0_BACKOFF_IBADC_V1, 0x26); 2383 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2384 B_P1_BACKOFF_IBADC_V1, 0x26); 2385 } 2386 } 2387 2388 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2389 { 2390 struct rtw89_hal *hal = &rtwdev->hal; 2391 2392 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2393 2394 if (hal->rx_nss == 1) { 2395 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2396 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2397 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2398 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2399 } else { 2400 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2401 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2402 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2403 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2404 } 2405 } 2406 2407 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2408 { 2409 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2410 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2411 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2412 2413 fsleep(200); 2414 2415 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2416 } 2417 2418 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2419 { 2420 struct rtw89_btc *btc = &rtwdev->btc; 2421 struct rtw89_btc_module *module = &btc->mdinfo; 2422 2423 module->rfe_type = rtwdev->efuse.rfe_type; 2424 module->cv = rtwdev->hal.cv; 2425 module->bt_solo = 0; 2426 module->switch_type = BTC_SWITCH_INTERNAL; 2427 2428 if (module->rfe_type > 0) 2429 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 2430 else 2431 module->ant.num = 2; 2432 2433 module->ant.diversity = 0; 2434 module->ant.isolation = 10; 2435 2436 if (module->ant.num == 3) { 2437 module->ant.type = BTC_ANT_DEDICATED; 2438 module->bt_pos = BTC_BT_ALONE; 2439 } else { 2440 module->ant.type = BTC_ANT_SHARED; 2441 module->bt_pos = BTC_BT_BTG; 2442 } 2443 } 2444 2445 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 2446 { 2447 if (btg) { 2448 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2449 B_PATH0_BT_SHARE_V1, 0x1); 2450 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2451 B_PATH0_BTG_PATH_V1, 0x0); 2452 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2453 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2454 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2455 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2456 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2457 B_PATH1_BT_SHARE_V1, 0x1); 2458 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2459 B_PATH1_BTG_PATH_V1, 0x1); 2460 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2461 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2462 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2463 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2464 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2465 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2466 0x1); 2467 } else { 2468 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2469 B_PATH0_BT_SHARE_V1, 0x0); 2470 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2471 B_PATH0_BTG_PATH_V1, 0x0); 2472 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2473 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2474 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2475 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2476 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2477 B_PATH1_BT_SHARE_V1, 0x0); 2478 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2479 B_PATH1_BTG_PATH_V1, 0x0); 2480 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2481 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2482 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2483 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2484 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2485 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2486 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2487 0x0); 2488 } 2489 } 2490 2491 static 2492 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2493 { 2494 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2495 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2496 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2497 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2498 } 2499 2500 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2501 { 2502 struct rtw89_btc *btc = &rtwdev->btc; 2503 struct rtw89_btc_module *module = &btc->mdinfo; 2504 const struct rtw89_chip_info *chip = rtwdev->chip; 2505 const struct rtw89_mac_ax_coex coex_params = { 2506 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2507 .direction = RTW89_MAC_AX_COEX_INNER, 2508 }; 2509 2510 /* PTA init */ 2511 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2512 2513 /* set WL Tx response = Hi-Pri */ 2514 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2515 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2516 2517 /* set rf gnt debug off */ 2518 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2519 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2520 2521 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2522 if (module->ant.type == BTC_ANT_SHARED) { 2523 rtw8852c_set_trx_mask(rtwdev, 2524 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2525 rtw8852c_set_trx_mask(rtwdev, 2526 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2527 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2528 rtw8852c_set_trx_mask(rtwdev, 2529 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2530 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2531 rtw8852c_set_trx_mask(rtwdev, 2532 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2533 rtw8852c_set_trx_mask(rtwdev, 2534 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2535 } 2536 2537 /* set PTA break table */ 2538 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2539 2540 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2541 rtw89_write32_set(rtwdev, 2542 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2543 B_AX_BT_CNT_RST_V1); 2544 btc->cx.wl.status.map.init_ok = true; 2545 } 2546 2547 static 2548 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2549 { 2550 u32 bitmap = 0; 2551 u32 reg = 0; 2552 2553 switch (map) { 2554 case BTC_PRI_MASK_TX_RESP: 2555 reg = R_BTC_COEX_WL_REQ; 2556 bitmap = B_BTC_RSP_ACK_HI; 2557 break; 2558 case BTC_PRI_MASK_BEACON: 2559 reg = R_BTC_COEX_WL_REQ; 2560 bitmap = B_BTC_TX_BCN_HI; 2561 break; 2562 default: 2563 return; 2564 } 2565 2566 if (state) 2567 rtw89_write32_set(rtwdev, reg, bitmap); 2568 else 2569 rtw89_write32_clr(rtwdev, reg, bitmap); 2570 } 2571 2572 union rtw8852c_btc_wl_txpwr_ctrl { 2573 u32 txpwr_val; 2574 struct { 2575 union { 2576 u16 ctrl_all_time; 2577 struct { 2578 s16 data:9; 2579 u16 rsvd:6; 2580 u16 flag:1; 2581 } all_time; 2582 }; 2583 union { 2584 u16 ctrl_gnt_bt; 2585 struct { 2586 s16 data:9; 2587 u16 rsvd:7; 2588 } gnt_bt; 2589 }; 2590 }; 2591 } __packed; 2592 2593 static void 2594 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2595 { 2596 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2597 s32 val; 2598 2599 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2600 do { \ 2601 u32 _wrt = FIELD_PREP(_msk, _val); \ 2602 BUILD_BUG_ON((_msk & _en) != 0); \ 2603 if (_cond) \ 2604 _wrt |= _en; \ 2605 else \ 2606 _wrt &= ~_en; \ 2607 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2608 _msk | _en, _wrt); \ 2609 } while (0) 2610 2611 switch (arg.ctrl_all_time) { 2612 case 0xffff: 2613 val = 0; 2614 break; 2615 default: 2616 val = arg.all_time.data; 2617 break; 2618 } 2619 2620 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2621 val, B_AX_FORCE_PWR_BY_RATE_EN, 2622 arg.ctrl_all_time != 0xffff); 2623 2624 switch (arg.ctrl_gnt_bt) { 2625 case 0xffff: 2626 val = 0; 2627 break; 2628 default: 2629 val = arg.gnt_bt.data; 2630 break; 2631 } 2632 2633 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2634 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2635 2636 #undef __write_ctrl 2637 } 2638 2639 static 2640 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2641 { 2642 return clamp_t(s8, val, -100, 0) + 100; 2643 } 2644 2645 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2646 {255, 0, 0, 7}, /* 0 -> original */ 2647 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2648 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2649 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2650 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2651 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2652 {6, 1, 0, 7}, 2653 {13, 1, 0, 7}, 2654 {13, 1, 0, 7} 2655 }; 2656 2657 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2658 {255, 0, 0, 7}, /* 0 -> original */ 2659 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2660 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2661 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2662 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2663 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2664 {255, 1, 0, 7}, 2665 {255, 1, 0, 7}, 2666 {255, 1, 0, 7} 2667 }; 2668 2669 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2670 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2671 2672 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2673 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2674 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2675 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2676 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2677 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2678 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2679 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2680 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2681 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2682 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2683 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2684 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2685 }; 2686 2687 static 2688 void rtw8852c_btc_bt_aci_imp(struct rtw89_dev *rtwdev) 2689 { 2690 struct rtw89_btc *btc = &rtwdev->btc; 2691 struct rtw89_btc_dm *dm = &btc->dm; 2692 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 2693 struct rtw89_btc_bt_link_info *b = &bt->link_info; 2694 2695 /* fix LNA2 = level-5 for BT ACI issue at BTG */ 2696 if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0) 2697 dm->trx_para_level = 1; 2698 } 2699 2700 static 2701 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2702 { 2703 /* Feature move to firmware */ 2704 } 2705 2706 static 2707 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2708 { 2709 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2710 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2711 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2712 2713 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2714 if (state) 2715 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2716 RFREG_MASK, 0x179c); 2717 else 2718 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2719 RFREG_MASK, 0x208); 2720 2721 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2722 } 2723 2724 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2725 { 2726 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2727 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2728 * To improve BT ACI in co-rx 2729 */ 2730 2731 switch (level) { 2732 case 0: /* default */ 2733 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2734 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2735 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2736 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2737 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2738 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2739 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2740 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2741 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2742 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2743 break; 2744 case 1: /* Fix LNA2=5 */ 2745 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2746 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2747 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2748 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2749 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2750 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2751 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2752 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2753 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2754 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2755 break; 2756 } 2757 } 2758 2759 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2760 { 2761 switch (level) { 2762 case 0: /* original */ 2763 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2764 rtw8852c_set_wl_lna2(rtwdev, 0); 2765 break; 2766 case 1: /* for FDD free-run */ 2767 rtw8852c_bb_ctrl_btc_preagc(rtwdev, true); 2768 rtw8852c_set_wl_lna2(rtwdev, 0); 2769 break; 2770 case 2: /* for BTG Co-Rx*/ 2771 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2772 rtw8852c_set_wl_lna2(rtwdev, 1); 2773 break; 2774 } 2775 } 2776 2777 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2778 struct rtw89_rx_phy_ppdu *phy_ppdu, 2779 struct ieee80211_rx_status *status) 2780 { 2781 u8 chan_idx = phy_ppdu->chan_idx; 2782 enum nl80211_band band; 2783 u8 ch; 2784 2785 if (chan_idx == 0) 2786 return; 2787 2788 rtw8852c_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2789 status->freq = ieee80211_channel_to_frequency(ch, band); 2790 status->band = band; 2791 } 2792 2793 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2794 struct rtw89_rx_phy_ppdu *phy_ppdu, 2795 struct ieee80211_rx_status *status) 2796 { 2797 u8 path; 2798 u8 *rx_power = phy_ppdu->rssi; 2799 2800 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2801 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2802 status->chains |= BIT(path); 2803 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2804 } 2805 if (phy_ppdu->valid) 2806 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2807 } 2808 2809 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2810 { 2811 int ret; 2812 2813 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2814 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2815 2816 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2817 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2818 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2819 2820 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2821 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2822 2823 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2824 if (ret) 2825 return ret; 2826 2827 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2828 if (ret) 2829 return ret; 2830 2831 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2832 if (ret) 2833 return ret; 2834 2835 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2836 if (ret) 2837 return ret; 2838 2839 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2840 if (ret) 2841 return ret; 2842 2843 return 0; 2844 } 2845 2846 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2847 { 2848 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2849 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2850 2851 return 0; 2852 } 2853 2854 static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2855 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2856 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2857 .bb_reset = rtw8852c_bb_reset, 2858 .bb_sethw = rtw8852c_bb_sethw, 2859 .read_rf = rtw89_phy_read_rf_v1, 2860 .write_rf = rtw89_phy_write_rf_v1, 2861 .set_channel = rtw8852c_set_channel, 2862 .set_channel_help = rtw8852c_set_channel_help, 2863 .read_efuse = rtw8852c_read_efuse, 2864 .read_phycap = rtw8852c_read_phycap, 2865 .fem_setup = NULL, 2866 .rfk_init = rtw8852c_rfk_init, 2867 .rfk_channel = rtw8852c_rfk_channel, 2868 .rfk_band_changed = rtw8852c_rfk_band_changed, 2869 .rfk_scan = rtw8852c_rfk_scan, 2870 .rfk_track = rtw8852c_rfk_track, 2871 .power_trim = rtw8852c_power_trim, 2872 .set_txpwr = rtw8852c_set_txpwr, 2873 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2874 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2875 .get_thermal = rtw8852c_get_thermal, 2876 .ctrl_btg = rtw8852c_ctrl_btg, 2877 .query_ppdu = rtw8852c_query_ppdu, 2878 .bb_ctrl_btc_preagc = rtw8852c_bb_ctrl_btc_preagc, 2879 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2880 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2881 .pwr_on_func = rtw8852c_pwr_on_func, 2882 .pwr_off_func = rtw8852c_pwr_off_func, 2883 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2884 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2885 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2886 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2887 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2888 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2889 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2890 2891 .btc_set_rfe = rtw8852c_btc_set_rfe, 2892 .btc_init_cfg = rtw8852c_btc_init_cfg, 2893 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2894 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2895 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2896 .btc_bt_aci_imp = rtw8852c_btc_bt_aci_imp, 2897 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2898 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2899 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2900 .btc_set_policy = rtw89_btc_set_policy_v1, 2901 }; 2902 2903 const struct rtw89_chip_info rtw8852c_chip_info = { 2904 .chip_id = RTL8852C, 2905 .ops = &rtw8852c_chip_ops, 2906 .fw_name = "rtw89/rtw8852c_fw.bin", 2907 .fifo_size = 458752, 2908 .dle_scc_rsvd_size = 0, 2909 .max_amsdu_limit = 8000, 2910 .dis_2g_40m_ul_ofdma = false, 2911 .rsvd_ple_ofst = 0x6f800, 2912 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2913 .dle_mem = rtw8852c_dle_mem_pcie, 2914 .rf_base_addr = {0xe000, 0xf000}, 2915 .pwr_on_seq = NULL, 2916 .pwr_off_seq = NULL, 2917 .bb_table = &rtw89_8852c_phy_bb_table, 2918 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2919 .rf_table = {&rtw89_8852c_phy_radiob_table, 2920 &rtw89_8852c_phy_radioa_table,}, 2921 .nctl_table = &rtw89_8852c_phy_nctl_table, 2922 .byr_table = &rtw89_8852c_byr_table, 2923 .txpwr_lmt_2g = &rtw89_8852c_txpwr_lmt_2g, 2924 .txpwr_lmt_5g = &rtw89_8852c_txpwr_lmt_5g, 2925 .txpwr_lmt_6g = &rtw89_8852c_txpwr_lmt_6g, 2926 .txpwr_lmt_ru_2g = &rtw89_8852c_txpwr_lmt_ru_2g, 2927 .txpwr_lmt_ru_5g = &rtw89_8852c_txpwr_lmt_ru_5g, 2928 .txpwr_lmt_ru_6g = &rtw89_8852c_txpwr_lmt_ru_6g, 2929 .txpwr_factor_rf = 2, 2930 .txpwr_factor_mac = 1, 2931 .dig_table = NULL, 2932 .dig_regs = &rtw8852c_dig_regs, 2933 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2934 .support_chanctx_num = 1, 2935 .support_bands = BIT(NL80211_BAND_2GHZ) | 2936 BIT(NL80211_BAND_5GHZ) | 2937 BIT(NL80211_BAND_6GHZ), 2938 .support_bw160 = true, 2939 .hw_sec_hdr = true, 2940 .rf_path_num = 2, 2941 .tx_nss = 2, 2942 .rx_nss = 2, 2943 .acam_num = 128, 2944 .bcam_num = 20, 2945 .scam_num = 128, 2946 .bacam_num = 8, 2947 .bacam_dynamic_num = 8, 2948 .bacam_v1 = true, 2949 .sec_ctrl_efuse_size = 4, 2950 .physical_efuse_size = 1216, 2951 .logical_efuse_size = 2048, 2952 .limit_efuse_size = 1280, 2953 .dav_phy_efuse_size = 96, 2954 .dav_log_efuse_size = 16, 2955 .phycap_addr = 0x590, 2956 .phycap_size = 0x60, 2957 .para_ver = 0x1, 2958 .wlcx_desired = 0x06000000, 2959 .btcx_desired = 0x7, 2960 .scbd = 0x1, 2961 .mailbox = 0x1, 2962 .btc_fwinfo_buf = 1280, 2963 2964 .fcxbtcrpt_ver = 4, 2965 .fcxtdma_ver = 3, 2966 .fcxslots_ver = 1, 2967 .fcxcysta_ver = 3, 2968 .fcxstep_ver = 3, 2969 .fcxnullsta_ver = 2, 2970 .fcxmreg_ver = 1, 2971 .fcxgpiodbg_ver = 1, 2972 .fcxbtver_ver = 1, 2973 .fcxbtscan_ver = 1, 2974 .fcxbtafh_ver = 1, 2975 .fcxbtdevinfo_ver = 1, 2976 2977 .afh_guard_ch = 6, 2978 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 2979 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 2980 .rssi_tol = 2, 2981 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 2982 .mon_reg = rtw89_btc_8852c_mon_reg, 2983 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 2984 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 2985 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 2986 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 2987 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2988 BIT(RTW89_PS_MODE_CLK_GATED) | 2989 BIT(RTW89_PS_MODE_PWR_GATED), 2990 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 2991 BIT(RTW89_PS_MODE_PWR_GATED), 2992 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 2993 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 2994 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 2995 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 2996 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 2997 .h2c_regs = rtw8852c_h2c_regs, 2998 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 2999 .c2h_regs = rtw8852c_c2h_regs, 3000 .page_regs = &rtw8852c_page_regs, 3001 .dcfo_comp = &rtw8852c_dcfo_comp, 3002 .dcfo_comp_sft = 5, 3003 .imr_info = &rtw8852c_imr_info, 3004 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 3005 .dma_ch_mask = 0, 3006 }; 3007 EXPORT_SYMBOL(rtw8852c_chip_info); 3008 3009 MODULE_FIRMWARE("rtw89/rtw8852c_fw.bin"); 3010 MODULE_AUTHOR("Realtek Corporation"); 3011 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 3012 MODULE_LICENSE("Dual BSD/GPL"); 3013