1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "reg.h" 11 #include "rtw8852c.h" 12 #include "rtw8852c_rfk.h" 13 #include "rtw8852c_table.h" 14 #include "util.h" 15 16 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 17 {13, 1614, grp_0}, /* ACH 0 */ 18 {13, 1614, grp_0}, /* ACH 1 */ 19 {13, 1614, grp_0}, /* ACH 2 */ 20 {13, 1614, grp_0}, /* ACH 3 */ 21 {13, 1614, grp_1}, /* ACH 4 */ 22 {13, 1614, grp_1}, /* ACH 5 */ 23 {13, 1614, grp_1}, /* ACH 6 */ 24 {13, 1614, grp_1}, /* ACH 7 */ 25 {13, 1614, grp_0}, /* B0MGQ */ 26 {13, 1614, grp_0}, /* B0HIQ */ 27 {13, 1614, grp_1}, /* B1MGQ */ 28 {13, 1614, grp_1}, /* B1HIQ */ 29 {40, 0, 0} /* FWCMDQ */ 30 }; 31 32 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 33 1614, /* Group 0 */ 34 1614, /* Group 1 */ 35 3228, /* Public Max */ 36 0 /* WP threshold */ 37 }; 38 39 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 40 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 41 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 42 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 43 RTW89_HCIFC_POH}, 44 [RTW89_QTA_INVALID] = {NULL}, 45 }; 46 47 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 48 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 49 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 50 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 51 &rtw89_mac_size.ple_qt47}, 52 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 53 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 54 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 55 &rtw89_mac_size.ple_qt45}, 56 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 57 NULL}, 58 }; 59 60 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 61 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 62 R_AX_H2CREG_DATA3_V1 63 }; 64 65 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 66 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 67 R_AX_C2HREG_DATA3_V1 68 }; 69 70 static const struct rtw89_page_regs rtw8852c_page_regs = { 71 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 72 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 73 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 74 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 75 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 76 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 77 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 78 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 79 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 80 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 81 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 82 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 83 }; 84 85 static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 86 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 87 }; 88 89 static const struct rtw89_imr_info rtw8852c_imr_info = { 90 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 91 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 92 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 93 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 94 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 95 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 96 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 97 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 98 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 99 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 100 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 101 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 102 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 103 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 104 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 105 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 106 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 107 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 108 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 109 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 110 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 111 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 112 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 113 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 114 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 115 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 116 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 117 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 118 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 119 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 120 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 121 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 122 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 123 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 124 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 125 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 126 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 127 .rmac_imr_reg = R_AX_RX_ERR_IMR, 128 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 129 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 130 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 131 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 132 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 133 }; 134 135 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 136 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 137 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 138 }; 139 140 static const struct rtw89_dig_regs rtw8852c_dig_regs = { 141 .seg0_pd_reg = R_SEG0R_PD, 142 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 143 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 144 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 145 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 146 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 147 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 148 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 149 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 150 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 151 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 152 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 153 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 154 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 155 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 156 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 157 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 158 }; 159 160 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg); 161 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 162 enum rtw89_mac_idx mac_idx); 163 164 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 165 { 166 u32 val32; 167 u32 ret; 168 169 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 170 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 171 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 172 173 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 174 B_AX_AFSM_PCIE_SUS_EN); 175 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 176 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 177 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 178 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 179 180 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 181 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 182 if (ret) 183 return ret; 184 185 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 186 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 187 188 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 189 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 190 if (ret) 191 return ret; 192 193 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 194 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 195 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 196 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 197 198 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 199 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 200 201 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 202 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 203 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 204 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 205 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 206 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 207 B_AX_R_SYM_WLCMAC1_PC_EN); 208 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 209 210 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 211 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 212 if (ret) 213 return ret; 214 215 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 216 217 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 218 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 219 if (ret) 220 return ret; 221 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 222 XTAL_SI_OFF_WEI); 223 if (ret) 224 return ret; 225 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 226 XTAL_SI_OFF_EI); 227 if (ret) 228 return ret; 229 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 230 if (ret) 231 return ret; 232 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 233 XTAL_SI_PON_WEI); 234 if (ret) 235 return ret; 236 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 237 XTAL_SI_PON_EI); 238 if (ret) 239 return ret; 240 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 241 if (ret) 242 return ret; 243 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 244 if (ret) 245 return ret; 246 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 247 if (ret) 248 return ret; 249 250 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 251 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 252 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 253 254 fsleep(1000); 255 256 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 257 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 258 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 259 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 260 B_AX_LED1_PULL_LOW_EN); 261 262 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 263 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 264 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 265 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 266 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 267 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 268 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 269 270 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 271 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 272 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 273 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 274 B_AX_TMAC_EN | B_AX_RMAC_EN); 275 276 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 277 PINMUX_EESK_FUNC_SEL_BT_LOG); 278 279 return 0; 280 } 281 282 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 283 { 284 u32 val32; 285 u32 ret; 286 287 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 288 XTAL_SI_RFC2RF); 289 if (ret) 290 return ret; 291 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 292 if (ret) 293 return ret; 294 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 295 if (ret) 296 return ret; 297 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 298 if (ret) 299 return ret; 300 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 301 if (ret) 302 return ret; 303 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 304 XTAL_SI_SRAM2RFC); 305 if (ret) 306 return ret; 307 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 308 if (ret) 309 return ret; 310 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 311 if (ret) 312 return ret; 313 314 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 315 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 316 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 317 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 318 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 319 320 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 321 if (ret) 322 return ret; 323 324 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 325 326 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 327 if (ret) 328 return ret; 329 330 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 331 332 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 333 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 334 if (ret) 335 return ret; 336 337 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0); 338 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 339 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 340 341 return 0; 342 } 343 344 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 345 struct rtw8852c_efuse *map) 346 { 347 ether_addr_copy(efuse->addr, map->e.mac_addr); 348 efuse->rfe_type = map->rfe_type; 349 efuse->xtal_cap = map->xtal_k; 350 } 351 352 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 353 struct rtw8852c_efuse *map) 354 { 355 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 356 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 357 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 358 u8 i, j; 359 360 tssi->thermal[RF_PATH_A] = map->path_a_therm; 361 tssi->thermal[RF_PATH_B] = map->path_b_therm; 362 363 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 364 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 365 sizeof(ofst[i]->cck_tssi)); 366 367 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 368 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 369 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 370 i, j, tssi->tssi_cck[i][j]); 371 372 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 373 sizeof(ofst[i]->bw40_tssi)); 374 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 375 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 376 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 377 sizeof(tssi->tssi_6g_mcs[i])); 378 379 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 380 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 381 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 382 i, j, tssi->tssi_mcs[i][j]); 383 } 384 } 385 386 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 387 { 388 if (high) 389 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 390 if (low) 391 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 392 393 return data != 0xff; 394 } 395 396 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 397 struct rtw8852c_efuse *map) 398 { 399 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 400 bool valid = false; 401 402 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 403 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 404 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 405 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 406 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 407 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 408 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 409 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 410 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 411 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 412 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 413 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 414 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 415 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 416 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 417 418 gain->offset_valid = valid; 419 } 420 421 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 422 { 423 struct rtw89_efuse *efuse = &rtwdev->efuse; 424 struct rtw8852c_efuse *map; 425 426 map = (struct rtw8852c_efuse *)log_map; 427 428 efuse->country_code[0] = map->country_code[0]; 429 efuse->country_code[1] = map->country_code[1]; 430 rtw8852c_efuse_parsing_tssi(rtwdev, map); 431 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 432 433 switch (rtwdev->hci.type) { 434 case RTW89_HCI_TYPE_PCIE: 435 rtw8852c_e_efuse_parsing(efuse, map); 436 break; 437 default: 438 return -ENOTSUPP; 439 } 440 441 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 442 443 return 0; 444 } 445 446 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 447 { 448 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 449 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 450 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 451 u32 addr = rtwdev->chip->phycap_addr; 452 bool pg = false; 453 u32 ofst; 454 u8 i, j; 455 456 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 457 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 458 /* addrs are in decreasing order */ 459 ofst = tssi_trim_addr[i] - addr - j; 460 tssi->tssi_trim[i][j] = phycap_map[ofst]; 461 462 if (phycap_map[ofst] != 0xff) 463 pg = true; 464 } 465 466 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 467 /* addrs are in decreasing order */ 468 ofst = tssi_trim_addr_6g[i] - addr - j; 469 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 470 471 if (phycap_map[ofst] != 0xff) 472 pg = true; 473 } 474 } 475 476 if (!pg) { 477 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 478 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 479 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 480 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 481 } 482 483 for (i = 0; i < RF_PATH_NUM_8852C; i++) 484 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 485 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 486 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 487 i, j, tssi->tssi_trim[i][j], 488 tssi_trim_addr[i] - j); 489 } 490 491 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 492 u8 *phycap_map) 493 { 494 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 495 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 496 u32 addr = rtwdev->chip->phycap_addr; 497 u8 i; 498 499 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 500 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 501 502 rtw89_debug(rtwdev, RTW89_DBG_RFK, 503 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 504 i, info->thermal_trim[i]); 505 506 if (info->thermal_trim[i] != 0xff) 507 info->pg_thermal_trim = true; 508 } 509 } 510 511 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 512 { 513 #define __thm_setting(raw) \ 514 ({ \ 515 u8 __v = (raw); \ 516 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 517 }) 518 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 519 u8 i, val; 520 521 if (!info->pg_thermal_trim) { 522 rtw89_debug(rtwdev, RTW89_DBG_RFK, 523 "[THERMAL][TRIM] no PG, do nothing\n"); 524 525 return; 526 } 527 528 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 529 val = __thm_setting(info->thermal_trim[i]); 530 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 531 532 rtw89_debug(rtwdev, RTW89_DBG_RFK, 533 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 534 i, val); 535 } 536 #undef __thm_setting 537 } 538 539 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 540 u8 *phycap_map) 541 { 542 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 543 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 544 u32 addr = rtwdev->chip->phycap_addr; 545 u8 i; 546 547 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 548 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 549 550 rtw89_debug(rtwdev, RTW89_DBG_RFK, 551 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 552 i, info->pa_bias_trim[i]); 553 554 if (info->pa_bias_trim[i] != 0xff) 555 info->pg_pa_bias_trim = true; 556 } 557 } 558 559 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 560 { 561 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 562 u8 pabias_2g, pabias_5g; 563 u8 i; 564 565 if (!info->pg_pa_bias_trim) { 566 rtw89_debug(rtwdev, RTW89_DBG_RFK, 567 "[PA_BIAS][TRIM] no PG, do nothing\n"); 568 569 return; 570 } 571 572 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 573 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 574 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 575 576 rtw89_debug(rtwdev, RTW89_DBG_RFK, 577 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 578 i, pabias_2g, pabias_5g); 579 580 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 581 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 582 } 583 } 584 585 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 586 { 587 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 588 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 589 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 590 591 return 0; 592 } 593 594 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 595 { 596 rtw8852c_thermal_trim(rtwdev); 597 rtw8852c_pa_bias_trim(rtwdev); 598 } 599 600 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 601 const struct rtw89_chan *chan, 602 u8 mac_idx) 603 { 604 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 605 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 606 mac_idx); 607 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 608 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 609 u8 rf_mod_val = 0, chk_rate_mask = 0; 610 u32 txsc; 611 612 switch (chan->band_width) { 613 case RTW89_CHANNEL_WIDTH_160: 614 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 615 RTW89_CHANNEL_WIDTH_80); 616 fallthrough; 617 case RTW89_CHANNEL_WIDTH_80: 618 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 619 RTW89_CHANNEL_WIDTH_40); 620 fallthrough; 621 case RTW89_CHANNEL_WIDTH_40: 622 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 623 RTW89_CHANNEL_WIDTH_20); 624 break; 625 default: 626 break; 627 } 628 629 switch (chan->band_width) { 630 case RTW89_CHANNEL_WIDTH_160: 631 rf_mod_val = AX_WMAC_RFMOD_160M; 632 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 633 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 634 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 635 break; 636 case RTW89_CHANNEL_WIDTH_80: 637 rf_mod_val = AX_WMAC_RFMOD_80M; 638 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 639 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 640 break; 641 case RTW89_CHANNEL_WIDTH_40: 642 rf_mod_val = AX_WMAC_RFMOD_40M; 643 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 644 break; 645 case RTW89_CHANNEL_WIDTH_20: 646 default: 647 rf_mod_val = AX_WMAC_RFMOD_20M; 648 txsc = 0; 649 break; 650 } 651 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 652 rtw89_write32(rtwdev, sub_carr, txsc); 653 654 switch (chan->band_type) { 655 case RTW89_BAND_2G: 656 chk_rate_mask = B_AX_BAND_MODE; 657 break; 658 case RTW89_BAND_5G: 659 case RTW89_BAND_6G: 660 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 661 break; 662 default: 663 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 664 return; 665 } 666 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 667 B_AX_RTS_LIMIT_IN_OFDM6); 668 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 669 } 670 671 static const u32 rtw8852c_sco_barker_threshold[14] = { 672 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 673 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 674 }; 675 676 static const u32 rtw8852c_sco_cck_threshold[14] = { 677 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 678 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 679 }; 680 681 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 682 u8 primary_ch, enum rtw89_bandwidth bw) 683 { 684 u8 ch_element; 685 686 if (bw == RTW89_CHANNEL_WIDTH_20) { 687 ch_element = central_ch - 1; 688 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 689 if (primary_ch == 1) 690 ch_element = central_ch - 1 + 2; 691 else 692 ch_element = central_ch - 1 - 2; 693 } else { 694 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 695 return -EINVAL; 696 } 697 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 698 rtw8852c_sco_barker_threshold[ch_element]); 699 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 700 rtw8852c_sco_cck_threshold[ch_element]); 701 702 return 0; 703 } 704 705 struct rtw8852c_bb_gain { 706 u32 gain_g[BB_PATH_NUM_8852C]; 707 u32 gain_a[BB_PATH_NUM_8852C]; 708 u32 gain_mask; 709 }; 710 711 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 712 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 713 .gain_mask = 0x00ff0000 }, 714 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 715 .gain_mask = 0xff000000 }, 716 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 717 .gain_mask = 0x000000ff }, 718 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 719 .gain_mask = 0x0000ff00 }, 720 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 721 .gain_mask = 0x00ff0000 }, 722 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 723 .gain_mask = 0xff000000 }, 724 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 725 .gain_mask = 0x000000ff }, 726 }; 727 728 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 729 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 730 .gain_mask = 0x00ff0000 }, 731 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 732 .gain_mask = 0xff000000 }, 733 }; 734 735 struct rtw8852c_bb_gain_bypass { 736 u32 gain_g[BB_PATH_NUM_8852C]; 737 u32 gain_a[BB_PATH_NUM_8852C]; 738 u32 gain_mask_g; 739 u32 gain_mask_a; 740 }; 741 742 static 743 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 744 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 745 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 746 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 747 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 748 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 749 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 750 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 751 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 752 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 753 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 754 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 755 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 756 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 757 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 758 }; 759 760 struct rtw8852c_bb_gain_op1db { 761 struct { 762 u32 lna[BB_PATH_NUM_8852C]; 763 u32 tia_lna[BB_PATH_NUM_8852C]; 764 u32 mask; 765 } reg[LNA_GAIN_NUM]; 766 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 767 u32 mask_tia0_lna6; 768 }; 769 770 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 771 .reg = { 772 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 773 .mask = 0xff}, 774 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 775 .mask = 0xff00}, 776 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 777 .mask = 0xff0000}, 778 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 779 .mask = 0xff000000}, 780 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 781 .mask = 0xff}, 782 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 783 .mask = 0xff00}, 784 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 785 .mask = 0xff0000}, 786 }, 787 .reg_tia0_lna6 = {0x4674, 0x4758}, 788 .mask_tia0_lna6 = 0xff000000, 789 }; 790 791 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 792 enum rtw89_subband subband, 793 enum rtw89_rf_path path) 794 { 795 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 796 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 797 s32 val; 798 u32 reg; 799 u32 mask; 800 int i; 801 802 for (i = 0; i < LNA_GAIN_NUM; i++) { 803 if (subband == RTW89_CH_2G) 804 reg = bb_gain_lna[i].gain_g[path]; 805 else 806 reg = bb_gain_lna[i].gain_a[path]; 807 808 mask = bb_gain_lna[i].gain_mask; 809 val = gain->lna_gain[gain_band][path][i]; 810 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 811 812 if (subband == RTW89_CH_2G) { 813 reg = bb_gain_bypass_lna[i].gain_g[path]; 814 mask = bb_gain_bypass_lna[i].gain_mask_g; 815 } else { 816 reg = bb_gain_bypass_lna[i].gain_a[path]; 817 mask = bb_gain_bypass_lna[i].gain_mask_a; 818 } 819 820 val = gain->lna_gain_bypass[gain_band][path][i]; 821 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 822 823 if (subband != RTW89_CH_2G) { 824 reg = bb_gain_op1db_a.reg[i].lna[path]; 825 mask = bb_gain_op1db_a.reg[i].mask; 826 val = gain->lna_op1db[gain_band][path][i]; 827 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 828 829 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 830 mask = bb_gain_op1db_a.reg[i].mask; 831 val = gain->tia_lna_op1db[gain_band][path][i]; 832 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 833 } 834 } 835 836 if (subband != RTW89_CH_2G) { 837 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 838 mask = bb_gain_op1db_a.mask_tia0_lna6; 839 val = gain->tia_lna_op1db[gain_band][path][7]; 840 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 841 } 842 843 for (i = 0; i < TIA_GAIN_NUM; i++) { 844 if (subband == RTW89_CH_2G) 845 reg = bb_gain_tia[i].gain_g[path]; 846 else 847 reg = bb_gain_tia[i].gain_a[path]; 848 849 mask = bb_gain_tia[i].gain_mask; 850 val = gain->tia_gain[gain_band][path][i]; 851 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 852 } 853 } 854 855 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 856 const struct rtw89_chan *chan, 857 enum rtw89_phy_idx phy_idx, 858 enum rtw89_rf_path path) 859 { 860 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 861 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 862 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 863 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 864 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 865 enum rtw89_gain_offset gain_band; 866 s32 offset_q0, offset_base_q4; 867 s32 tmp = 0; 868 869 if (!efuse_gain->offset_valid) 870 return; 871 872 if (rtwdev->dbcc_en && path == RF_PATH_B) 873 phy_idx = RTW89_PHY_1; 874 875 if (chan->band_type == RTW89_BAND_2G) { 876 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 877 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 878 879 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 880 S8_MIN >> 1, S8_MAX >> 1); 881 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 882 } 883 884 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type); 885 886 offset_q0 = -efuse_gain->offset[path][gain_band]; 887 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 888 889 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 890 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 891 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 892 893 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 894 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 895 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 896 } 897 898 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 899 const struct rtw89_chan *chan, 900 enum rtw89_phy_idx phy_idx) 901 { 902 u8 sco; 903 u16 central_freq = chan->freq; 904 u8 central_ch = chan->channel; 905 u8 band = chan->band_type; 906 u8 subband = chan->subband_type; 907 bool is_2g = band == RTW89_BAND_2G; 908 u8 chan_idx; 909 910 if (!central_freq) { 911 rtw89_warn(rtwdev, "Invalid central_freq\n"); 912 return; 913 } 914 915 if (phy_idx == RTW89_PHY_0) { 916 /* Path A */ 917 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 918 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 919 920 if (is_2g) 921 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 922 B_PATH0_BAND_SEL_MSK_V1, 1, 923 phy_idx); 924 else 925 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 926 B_PATH0_BAND_SEL_MSK_V1, 0, 927 phy_idx); 928 /* Path B */ 929 if (!rtwdev->dbcc_en) { 930 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 931 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 932 933 if (is_2g) 934 rtw89_phy_write32_idx(rtwdev, 935 R_PATH1_BAND_SEL_V1, 936 B_PATH1_BAND_SEL_MSK_V1, 937 1, phy_idx); 938 else 939 rtw89_phy_write32_idx(rtwdev, 940 R_PATH1_BAND_SEL_V1, 941 B_PATH1_BAND_SEL_MSK_V1, 942 0, phy_idx); 943 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 944 } else { 945 if (is_2g) 946 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 947 else 948 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 949 } 950 /* SCO compensate FC setting */ 951 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 952 central_freq, phy_idx); 953 /* round_up((1/fc0)*pow(2,18)) */ 954 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 955 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 956 phy_idx); 957 } else { 958 /* Path B */ 959 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 960 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 961 962 if (is_2g) 963 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 964 B_PATH1_BAND_SEL_MSK_V1, 965 1, phy_idx); 966 else 967 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 968 B_PATH1_BAND_SEL_MSK_V1, 969 0, phy_idx); 970 /* SCO compensate FC setting */ 971 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 972 central_freq, phy_idx); 973 /* round_up((1/fc0)*pow(2,18)) */ 974 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 975 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 976 phy_idx); 977 } 978 /* CCK parameters */ 979 if (band == RTW89_BAND_2G) { 980 if (central_ch == 14) { 981 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 982 B_PCOEFF01_MSK_V1, 0x3b13ff); 983 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 984 B_PCOEFF23_MSK_V1, 0x1c42de); 985 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 986 B_PCOEFF45_MSK_V1, 0xfdb0ad); 987 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 988 B_PCOEFF67_MSK_V1, 0xf60f6e); 989 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 990 B_PCOEFF89_MSK_V1, 0xfd8f92); 991 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 992 B_PCOEFFAB_MSK_V1, 0x2d011); 993 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 994 B_PCOEFFCD_MSK_V1, 0x1c02c); 995 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 996 B_PCOEFFEF_MSK_V1, 0xfff00a); 997 } else { 998 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 999 B_PCOEFF01_MSK_V1, 0x3d23ff); 1000 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1001 B_PCOEFF23_MSK_V1, 0x29b354); 1002 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1003 B_PCOEFF45_MSK_V1, 0xfc1c8); 1004 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1005 B_PCOEFF67_MSK_V1, 0xfdb053); 1006 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1007 B_PCOEFF89_MSK_V1, 0xf86f9a); 1008 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1009 B_PCOEFFAB_MSK_V1, 0xfaef92); 1010 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1011 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1012 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1013 B_PCOEFFEF_MSK_V1, 0xffdff5); 1014 } 1015 } 1016 1017 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1018 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1019 } 1020 1021 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1022 { 1023 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1024 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1025 1026 switch (bw) { 1027 case RTW89_CHANNEL_WIDTH_5: 1028 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1029 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1030 break; 1031 case RTW89_CHANNEL_WIDTH_10: 1032 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1033 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1034 break; 1035 case RTW89_CHANNEL_WIDTH_20: 1036 case RTW89_CHANNEL_WIDTH_40: 1037 case RTW89_CHANNEL_WIDTH_80: 1038 case RTW89_CHANNEL_WIDTH_160: 1039 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1040 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1041 break; 1042 default: 1043 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1044 } 1045 } 1046 1047 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1048 enum rtw89_phy_idx phy_idx) 1049 { 1050 if (bw == RTW89_CHANNEL_WIDTH_20) { 1051 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1052 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1053 } else { 1054 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1055 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1056 } 1057 } 1058 1059 static void 1060 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1061 enum rtw89_phy_idx phy_idx) 1062 { 1063 u8 mod_sbw = 0; 1064 1065 switch (bw) { 1066 case RTW89_CHANNEL_WIDTH_5: 1067 case RTW89_CHANNEL_WIDTH_10: 1068 case RTW89_CHANNEL_WIDTH_20: 1069 if (bw == RTW89_CHANNEL_WIDTH_5) 1070 mod_sbw = 0x1; 1071 else if (bw == RTW89_CHANNEL_WIDTH_10) 1072 mod_sbw = 0x2; 1073 else if (bw == RTW89_CHANNEL_WIDTH_20) 1074 mod_sbw = 0x0; 1075 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1076 phy_idx); 1077 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1078 mod_sbw, phy_idx); 1079 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1080 phy_idx); 1081 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1082 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1083 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1084 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1085 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1086 B_PATH0_BW_SEL_MSK_V1, 0xf); 1087 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1088 B_PATH1_BW_SEL_MSK_V1, 0xf); 1089 break; 1090 case RTW89_CHANNEL_WIDTH_40: 1091 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1092 phy_idx); 1093 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1094 phy_idx); 1095 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1096 pri_ch, 1097 phy_idx); 1098 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1099 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1100 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1101 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1102 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1103 B_PATH0_BW_SEL_MSK_V1, 0xf); 1104 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1105 B_PATH1_BW_SEL_MSK_V1, 0xf); 1106 break; 1107 case RTW89_CHANNEL_WIDTH_80: 1108 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1109 phy_idx); 1110 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1111 phy_idx); 1112 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1113 pri_ch, 1114 phy_idx); 1115 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1116 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1117 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1118 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1119 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1120 B_PATH0_BW_SEL_MSK_V1, 0xd); 1121 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1122 B_PATH1_BW_SEL_MSK_V1, 0xd); 1123 break; 1124 case RTW89_CHANNEL_WIDTH_160: 1125 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1126 phy_idx); 1127 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1128 phy_idx); 1129 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1130 pri_ch, 1131 phy_idx); 1132 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1133 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1134 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1135 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1136 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1137 B_PATH0_BW_SEL_MSK_V1, 0xb); 1138 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1139 B_PATH1_BW_SEL_MSK_V1, 0xb); 1140 break; 1141 default: 1142 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1143 pri_ch); 1144 } 1145 1146 if (bw == RTW89_CHANNEL_WIDTH_40) { 1147 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1148 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1149 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1150 } else { 1151 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1152 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1153 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1154 } 1155 1156 if (phy_idx == RTW89_PHY_0) { 1157 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1158 if (!rtwdev->dbcc_en) 1159 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1160 } else { 1161 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1162 } 1163 1164 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1165 } 1166 1167 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1168 const struct rtw89_chan *chan) 1169 { 1170 u8 center_chan = chan->channel; 1171 u8 bw = chan->band_width; 1172 1173 switch (chan->band_type) { 1174 case RTW89_BAND_2G: 1175 if (bw == RTW89_CHANNEL_WIDTH_20) { 1176 if (center_chan >= 5 && center_chan <= 8) 1177 return 2440; 1178 if (center_chan == 13) 1179 return 2480; 1180 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1181 if (center_chan >= 3 && center_chan <= 10) 1182 return 2440; 1183 } 1184 break; 1185 case RTW89_BAND_5G: 1186 if (center_chan == 151 || center_chan == 153 || 1187 center_chan == 155 || center_chan == 163) 1188 return 5760; 1189 break; 1190 case RTW89_BAND_6G: 1191 if (center_chan == 195 || center_chan == 197 || 1192 center_chan == 199 || center_chan == 207) 1193 return 6920; 1194 break; 1195 default: 1196 break; 1197 } 1198 1199 return 0; 1200 } 1201 1202 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1203 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1204 #define MAX_TONE_NUM 2048 1205 1206 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1207 const struct rtw89_chan *chan, 1208 enum rtw89_phy_idx phy_idx) 1209 { 1210 u32 spur_freq; 1211 s32 freq_diff, csi_idx, csi_tone_idx; 1212 1213 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1214 if (spur_freq == 0) { 1215 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1216 return; 1217 } 1218 1219 freq_diff = (spur_freq - chan->freq) * 1000000; 1220 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1221 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1222 1223 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1224 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1225 } 1226 1227 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1228 [RF_PATH_A] = { 1229 .notch1_idx = {0x4C14, 0xFF}, 1230 .notch1_frac_idx = {0x4C14, 0xC00}, 1231 .notch1_en = {0x4C14, 0x1000}, 1232 .notch2_idx = {0x4C20, 0xFF}, 1233 .notch2_frac_idx = {0x4C20, 0xC00}, 1234 .notch2_en = {0x4C20, 0x1000}, 1235 }, 1236 [RF_PATH_B] = { 1237 .notch1_idx = {0x4CD8, 0xFF}, 1238 .notch1_frac_idx = {0x4CD8, 0xC00}, 1239 .notch1_en = {0x4CD8, 0x1000}, 1240 .notch2_idx = {0x4CE4, 0xFF}, 1241 .notch2_frac_idx = {0x4CE4, 0xC00}, 1242 .notch2_en = {0x4CE4, 0x1000}, 1243 }, 1244 }; 1245 1246 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1247 const struct rtw89_chan *chan, 1248 enum rtw89_rf_path path) 1249 { 1250 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1251 u32 spur_freq, fc; 1252 s32 freq_diff; 1253 s32 nbi_idx, nbi_tone_idx; 1254 s32 nbi_frac_idx, nbi_frac_tone_idx; 1255 bool notch2_chk = false; 1256 1257 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1258 if (spur_freq == 0) { 1259 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1260 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1261 return; 1262 } 1263 1264 fc = chan->freq; 1265 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1266 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1267 if ((fc > spur_freq && 1268 chan->channel < chan->primary_channel) || 1269 (fc < spur_freq && 1270 chan->channel > chan->primary_channel)) 1271 notch2_chk = true; 1272 } 1273 1274 freq_diff = (spur_freq - fc) * 1000000; 1275 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1276 1277 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1278 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1279 } else { 1280 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1281 128 : 256; 1282 1283 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1284 } 1285 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1286 1287 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1288 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1289 nbi->notch2_idx.mask, nbi_tone_idx); 1290 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1291 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1292 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1293 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1294 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1295 } else { 1296 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1297 nbi->notch1_idx.mask, nbi_tone_idx); 1298 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1299 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1300 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1301 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1302 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1303 } 1304 } 1305 1306 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1307 enum rtw89_phy_idx phy_idx) 1308 { 1309 u32 notch; 1310 u32 notch2; 1311 1312 if (phy_idx == RTW89_PHY_0) { 1313 notch = R_PATH0_NOTCH; 1314 notch2 = R_PATH0_NOTCH2; 1315 } else { 1316 notch = R_PATH1_NOTCH; 1317 notch2 = R_PATH1_NOTCH2; 1318 } 1319 1320 rtw89_phy_write32_mask(rtwdev, notch, 1321 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1322 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1323 rtw89_phy_write32_mask(rtwdev, notch2, 1324 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1325 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1326 } 1327 1328 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1329 const struct rtw89_chan *chan, 1330 u8 pri_ch_idx, 1331 enum rtw89_phy_idx phy_idx) 1332 { 1333 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1334 1335 if (phy_idx == RTW89_PHY_0) { 1336 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1337 (pri_ch_idx == RTW89_SC_20_LOWER || 1338 pri_ch_idx == RTW89_SC_20_UP3X)) { 1339 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1340 if (!rtwdev->dbcc_en) 1341 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1342 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1343 (pri_ch_idx == RTW89_SC_20_UPPER || 1344 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1345 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1346 if (!rtwdev->dbcc_en) 1347 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1348 } else { 1349 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1350 if (!rtwdev->dbcc_en) 1351 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1352 RF_PATH_B); 1353 } 1354 } else { 1355 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1356 (pri_ch_idx == RTW89_SC_20_LOWER || 1357 pri_ch_idx == RTW89_SC_20_UP3X)) { 1358 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1359 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1360 (pri_ch_idx == RTW89_SC_20_UPPER || 1361 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1362 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1363 } else { 1364 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1365 } 1366 } 1367 1368 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1369 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1370 else 1371 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1372 } 1373 1374 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1375 const struct rtw89_chan *chan, 1376 enum rtw89_phy_idx phy_idx) 1377 { 1378 u8 pri_ch = chan->primary_channel; 1379 bool mask_5m_low; 1380 bool mask_5m_en; 1381 1382 switch (chan->band_width) { 1383 case RTW89_CHANNEL_WIDTH_40: 1384 mask_5m_en = true; 1385 mask_5m_low = pri_ch == 2; 1386 break; 1387 case RTW89_CHANNEL_WIDTH_80: 1388 mask_5m_en = ((pri_ch == 3) || (pri_ch == 4)); 1389 mask_5m_low = pri_ch == 4; 1390 break; 1391 default: 1392 mask_5m_en = false; 1393 mask_5m_low = false; 1394 break; 1395 } 1396 1397 if (!mask_5m_en) { 1398 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1399 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1400 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1401 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1402 } else { 1403 if (mask_5m_low) { 1404 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1405 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1406 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1407 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1408 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1409 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1410 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1411 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1412 } else { 1413 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1414 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1415 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1416 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1417 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1418 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1419 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1420 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1421 } 1422 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1423 } 1424 } 1425 1426 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1427 enum rtw89_phy_idx phy_idx) 1428 { 1429 /*HW SI reset*/ 1430 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1431 0x7); 1432 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1433 0x7); 1434 1435 udelay(1); 1436 1437 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1438 phy_idx); 1439 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1440 phy_idx); 1441 /*HW SI reset*/ 1442 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1443 0x0); 1444 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1445 0x0); 1446 1447 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1448 phy_idx); 1449 } 1450 1451 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1452 enum rtw89_phy_idx phy_idx, bool en) 1453 { 1454 if (en) { 1455 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1456 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1457 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1458 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1459 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1460 phy_idx); 1461 if (band == RTW89_BAND_2G) 1462 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1463 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1464 } else { 1465 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1466 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1467 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1468 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1469 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1470 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1471 fsleep(1); 1472 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1473 phy_idx); 1474 } 1475 } 1476 1477 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1478 enum rtw89_phy_idx phy_idx) 1479 { 1480 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1481 } 1482 1483 static 1484 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1485 u8 tx_path_en, u8 trsw_tx, 1486 u8 trsw_rx, u8 trsw, u8 trsw_b) 1487 { 1488 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1489 u32 mask_ofst = 16; 1490 u32 cr; 1491 u32 val; 1492 1493 if (path >= ARRAY_SIZE(path_cr_bases)) 1494 return; 1495 1496 cr = path_cr_bases[path]; 1497 1498 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1499 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1500 1501 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1502 } 1503 1504 enum rtw8852c_rfe_src { 1505 PAPE_RFM, 1506 TRSW_RFM, 1507 LNAON_RFM, 1508 }; 1509 1510 static 1511 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1512 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1513 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1514 { 1515 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1516 static const u32 masks[] = {0, 8, 16}; 1517 u32 mask, mask_ofst; 1518 u32 cr; 1519 u32 val; 1520 1521 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1522 return; 1523 1524 mask_ofst = masks[src]; 1525 cr = path_cr_bases[path]; 1526 1527 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1528 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1529 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1530 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1531 mask = 0xff << mask_ofst; 1532 1533 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1534 } 1535 1536 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1537 { 1538 static const u32 cr_bases[] = {0x5800, 0x7800}; 1539 u32 addr; 1540 u8 i; 1541 1542 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1543 addr = cr_bases[i]; 1544 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1545 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1546 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1547 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1548 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1549 } 1550 1551 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1552 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1553 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1554 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1555 1556 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1557 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1558 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1559 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1560 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1561 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1562 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1563 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1564 1565 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1566 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1567 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1568 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1569 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1570 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1571 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1572 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1573 1574 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1575 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1576 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1577 1578 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1579 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1580 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1581 } 1582 1583 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1584 enum rtw89_phy_idx phy_idx) 1585 { 1586 u32 addr; 1587 1588 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1589 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1590 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1591 } 1592 1593 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1594 { 1595 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1596 1597 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1598 B_DBCC_80P80_SEL_EVM_RPT_EN); 1599 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1600 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1601 1602 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1603 rtw8852c_bb_gpio_init(rtwdev); 1604 1605 /* read these registers after loading BB parameters */ 1606 gain->offset_base[RTW89_PHY_0] = 1607 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1608 gain->offset_base[RTW89_PHY_1] = 1609 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1610 } 1611 1612 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1613 const struct rtw89_chan *chan, 1614 enum rtw89_phy_idx phy_idx) 1615 { 1616 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1617 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1618 struct rtw89_hal *hal = &rtwdev->hal; 1619 bool cck_en = chan->band_type == RTW89_BAND_2G; 1620 u8 pri_ch_idx = chan->pri_ch_idx; 1621 u32 mask, reg; 1622 u8 ntx_path; 1623 1624 if (chan->band_type == RTW89_BAND_2G) 1625 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1626 chan->primary_channel, 1627 chan->band_width); 1628 1629 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1630 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1631 if (cck_en) { 1632 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1633 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1634 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1635 B_PD_ARBITER_OFF, 0x0, phy_idx); 1636 } else { 1637 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1638 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1639 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1640 B_PD_ARBITER_OFF, 0x1, phy_idx); 1641 } 1642 1643 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1644 rtw8852c_ctrl_btg(rtwdev, chan->band_type == RTW89_BAND_2G); 1645 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1646 1647 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1648 rtwdev->hal.cv != CHIP_CAV) { 1649 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1650 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1651 reg = rtw89_mac_reg_by_idx(R_P80_AT_HIGH_FREQ_BB_WRP, 1652 phy_idx); 1653 if (chan->primary_channel > chan->channel) { 1654 rtw89_phy_write32_mask(rtwdev, 1655 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1656 ru_alloc_msk[phy_idx], 1); 1657 rtw89_write32_mask(rtwdev, reg, 1658 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1659 } else { 1660 rtw89_phy_write32_mask(rtwdev, 1661 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1662 ru_alloc_msk[phy_idx], 0); 1663 rtw89_write32_mask(rtwdev, reg, 1664 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1665 } 1666 } 1667 1668 if (chan->band_type == RTW89_BAND_6G && 1669 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1670 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1671 B_CDD_EVM_CHK_EN, 0, phy_idx); 1672 else 1673 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1674 B_CDD_EVM_CHK_EN, 1, phy_idx); 1675 1676 if (!rtwdev->dbcc_en) { 1677 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1678 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1679 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1680 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1681 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1682 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1683 } else { 1684 if (phy_idx == RTW89_PHY_0) { 1685 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1686 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1687 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1688 } else { 1689 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1690 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1691 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1692 } 1693 } 1694 1695 if (chan->band_type == RTW89_BAND_6G) 1696 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1697 else 1698 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1699 1700 if (hal->antenna_tx) 1701 ntx_path = hal->antenna_tx; 1702 else 1703 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1704 1705 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1706 1707 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1708 } 1709 1710 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1711 const struct rtw89_chan *chan, 1712 enum rtw89_mac_idx mac_idx, 1713 enum rtw89_phy_idx phy_idx) 1714 { 1715 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1716 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1717 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1718 } 1719 1720 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1721 { 1722 if (en) 1723 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1724 else 1725 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1726 } 1727 1728 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1729 { 1730 if (en) 1731 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1732 0x0); 1733 else 1734 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1735 0xf); 1736 } 1737 1738 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1739 struct rtw89_channel_help_params *p, 1740 const struct rtw89_chan *chan, 1741 enum rtw89_mac_idx mac_idx, 1742 enum rtw89_phy_idx phy_idx) 1743 { 1744 if (enter) { 1745 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1746 RTW89_SCH_TX_SEL_ALL); 1747 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1748 rtw8852c_dfs_en(rtwdev, false); 1749 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1750 rtw8852c_adc_en(rtwdev, false); 1751 fsleep(40); 1752 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1753 } else { 1754 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1755 rtw8852c_adc_en(rtwdev, true); 1756 rtw8852c_dfs_en(rtwdev, true); 1757 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1758 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1759 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1760 } 1761 } 1762 1763 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1764 { 1765 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1766 1767 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1768 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1769 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 1770 rtw8852c_lck_init(rtwdev); 1771 1772 rtw8852c_rck(rtwdev); 1773 rtw8852c_dack(rtwdev); 1774 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1775 } 1776 1777 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) 1778 { 1779 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1780 1781 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1782 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1783 rtw8852c_iqk(rtwdev, phy_idx); 1784 rtw8852c_tssi(rtwdev, phy_idx); 1785 rtw8852c_dpk(rtwdev, phy_idx); 1786 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1787 } 1788 1789 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1790 enum rtw89_phy_idx phy_idx) 1791 { 1792 rtw8852c_tssi_scan(rtwdev, phy_idx); 1793 } 1794 1795 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1796 { 1797 rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1798 } 1799 1800 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1801 { 1802 rtw8852c_dpk_track(rtwdev); 1803 rtw8852c_lck_track(rtwdev); 1804 rtw8852c_rx_dck_track(rtwdev); 1805 } 1806 1807 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1808 enum rtw89_phy_idx phy_idx, s16 ref) 1809 { 1810 s8 ofst_int = 0; 1811 u8 base_cw_0db = 0x27; 1812 u16 tssi_16dbm_cw = 0x12c; 1813 s16 pwr_s10_3 = 0; 1814 s16 rf_pwr_cw = 0; 1815 u16 bb_pwr_cw = 0; 1816 u32 pwr_cw = 0; 1817 u32 tssi_ofst_cw = 0; 1818 1819 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1820 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1821 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1822 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1823 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1824 1825 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1826 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1827 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1828 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1829 1830 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1831 } 1832 1833 static 1834 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1835 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1836 { 1837 s8 pw_ofst_2tx; 1838 s8 val_1t; 1839 s8 val_2t; 1840 u32 reg; 1841 u8 i; 1842 1843 if (pw_ofst < -32 || pw_ofst > 31) { 1844 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1845 return; 1846 } 1847 val_1t = pw_ofst << 2; 1848 pw_ofst_2tx = max(pw_ofst - 3, -32); 1849 val_2t = pw_ofst_2tx << 2; 1850 1851 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1852 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1853 1854 for (i = 0; i < 4; i++) { 1855 /* 1TX */ 1856 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1857 rtw89_write32_mask(rtwdev, reg, 1858 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1859 val_1t); 1860 /* 2TX */ 1861 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1862 rtw89_write32_mask(rtwdev, reg, 1863 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1864 val_2t); 1865 } 1866 } 1867 1868 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1869 enum rtw89_phy_idx phy_idx) 1870 { 1871 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1872 const u32 mask = 0x7FFFFFF; 1873 const u8 ofst_ofdm = 0x4; 1874 const u8 ofst_cck = 0x8; 1875 s16 ref_ofdm = 0; 1876 s16 ref_cck = 0; 1877 u32 val; 1878 u8 i; 1879 1880 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1881 1882 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1883 GENMASK(27, 10), 0x0); 1884 1885 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1886 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1887 1888 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1889 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1890 phy_idx); 1891 1892 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1893 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1894 1895 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1896 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1897 phy_idx); 1898 } 1899 1900 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1901 const struct rtw89_chan *chan, 1902 u8 tx_shape_idx, 1903 enum rtw89_phy_idx phy_idx) 1904 { 1905 #define __DFIR_CFG_MASK 0xffffff 1906 #define __DFIR_CFG_NR 8 1907 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 1908 static const u32 _prefix ## _ ## _name[] = {_val}; \ 1909 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 1910 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 1911 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 1912 1913 __DECL_DFIR_PARAM(flat, 1914 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1915 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1916 __DECL_DFIR_PARAM(sharp, 1917 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1918 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 1919 __DECL_DFIR_PARAM(sharp_14, 1920 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1921 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 1922 __DECL_DFIR_ADDR(filter, 1923 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 1924 0x45C4, 0x45C8); 1925 u8 ch = chan->channel; 1926 const u32 *param; 1927 int i; 1928 1929 if (ch > 14) { 1930 rtw89_warn(rtwdev, 1931 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1932 return; 1933 } 1934 1935 if (ch == 14) 1936 param = param_sharp_14; 1937 else 1938 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1939 1940 for (i = 0; i < __DFIR_CFG_NR; i++) { 1941 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1942 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 1943 param[i]); 1944 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 1945 param[i], phy_idx); 1946 } 1947 1948 #undef __DECL_DFIR_ADDR 1949 #undef __DECL_DFIR_PARAM 1950 #undef __DECL_DFIR_VAR 1951 #undef __DFIR_CFG_NR 1952 #undef __DFIR_CFG_MASK 1953 } 1954 1955 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 1956 const struct rtw89_chan *chan, 1957 enum rtw89_phy_idx phy_idx) 1958 { 1959 u8 band = chan->band_type; 1960 u8 regd = rtw89_regd_get(rtwdev, band); 1961 u8 tx_shape_cck = rtw89_8852c_tx_shape[band][RTW89_RS_CCK][regd]; 1962 u8 tx_shape_ofdm = rtw89_8852c_tx_shape[band][RTW89_RS_OFDM][regd]; 1963 1964 if (band == RTW89_BAND_2G) 1965 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1966 1967 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 1968 (enum rtw89_mac_idx)phy_idx, 1969 tx_shape_ofdm); 1970 } 1971 1972 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 1973 const struct rtw89_chan *chan, 1974 enum rtw89_phy_idx phy_idx) 1975 { 1976 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1977 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1978 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 1979 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1980 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1981 } 1982 1983 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1984 enum rtw89_phy_idx phy_idx) 1985 { 1986 rtw8852c_set_txpwr_ref(rtwdev, phy_idx); 1987 } 1988 1989 static void 1990 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1991 { 1992 static const struct rtw89_reg2_def ctrl_ini[] = { 1993 {0xD938, 0x00010100}, 1994 {0xD93C, 0x0500D500}, 1995 {0xD940, 0x00000500}, 1996 {0xD944, 0x00000005}, 1997 {0xD94C, 0x00220000}, 1998 {0xD950, 0x00030000}, 1999 }; 2000 u32 addr; 2001 int i; 2002 2003 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2004 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2005 2006 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2007 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2008 ctrl_ini[i].data); 2009 2010 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2011 (enum rtw89_mac_idx)phy_idx, 2012 RTW89_TSSI_BANDEDGE_FLAT); 2013 } 2014 2015 static int 2016 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2017 { 2018 int ret; 2019 2020 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2021 if (ret) 2022 return ret; 2023 2024 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2025 if (ret) 2026 return ret; 2027 2028 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2029 if (ret) 2030 return ret; 2031 2032 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2033 RTW89_MAC_1 : 2034 RTW89_MAC_0); 2035 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2036 2037 return 0; 2038 } 2039 2040 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2041 { 2042 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2043 u8 band = chan->band_type; 2044 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2045 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2046 2047 if (rtwdev->dbcc_en) { 2048 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2049 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2050 RTW89_PHY_1); 2051 2052 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2053 1); 2054 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2055 1); 2056 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2057 RTW89_PHY_1); 2058 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2059 RTW89_PHY_1); 2060 2061 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2062 B_RXHT_MCS_LIMIT, 0); 2063 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2064 B_RXVHT_MCS_LIMIT, 0); 2065 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2066 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2067 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2068 2069 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2070 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2071 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2072 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2073 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2074 RTW89_PHY_1); 2075 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2076 RTW89_PHY_1); 2077 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2078 RTW89_PHY_1); 2079 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2080 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2081 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2082 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2083 } else { 2084 if (rx_path == RF_PATH_A) { 2085 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2086 B_ANT_RX_SEG0, 1); 2087 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2088 B_ANT_RX_1RCCA_SEG0, 1); 2089 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2090 B_ANT_RX_1RCCA_SEG1, 1); 2091 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2092 B_RXHT_MCS_LIMIT, 0); 2093 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2094 B_RXVHT_MCS_LIMIT, 0); 2095 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2096 0); 2097 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2098 0); 2099 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2100 rst_mask0, 1); 2101 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2102 rst_mask0, 3); 2103 } else if (rx_path == RF_PATH_B) { 2104 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2105 B_ANT_RX_SEG0, 2); 2106 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2107 B_ANT_RX_1RCCA_SEG0, 2); 2108 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2109 B_ANT_RX_1RCCA_SEG1, 2); 2110 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2111 B_RXHT_MCS_LIMIT, 0); 2112 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2113 B_RXVHT_MCS_LIMIT, 0); 2114 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2115 0); 2116 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2117 0); 2118 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2119 rst_mask1, 1); 2120 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2121 rst_mask1, 3); 2122 } else { 2123 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2124 B_ANT_RX_SEG0, 3); 2125 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2126 B_ANT_RX_1RCCA_SEG0, 3); 2127 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2128 B_ANT_RX_1RCCA_SEG1, 3); 2129 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2130 B_RXHT_MCS_LIMIT, 1); 2131 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2132 B_RXVHT_MCS_LIMIT, 1); 2133 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2134 1); 2135 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2136 1); 2137 rtw8852c_ctrl_btg(rtwdev, band == RTW89_BAND_2G); 2138 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2139 rst_mask0, 1); 2140 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2141 rst_mask0, 3); 2142 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2143 rst_mask1, 1); 2144 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2145 rst_mask1, 3); 2146 } 2147 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2148 } 2149 } 2150 2151 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2152 enum rtw89_mac_idx mac_idx) 2153 { 2154 struct rtw89_reg2_def path_com[] = { 2155 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2156 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2157 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2158 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2159 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2160 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2161 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2162 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2163 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2164 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2165 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2166 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2167 }; 2168 u32 addr; 2169 u32 reg; 2170 u8 cr_size = ARRAY_SIZE(path_com); 2171 u8 i = 0; 2172 2173 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2174 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2175 2176 for (addr = R_AX_MACID_ANT_TABLE; 2177 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2178 reg = rtw89_mac_reg_by_idx(addr, mac_idx); 2179 rtw89_write32(rtwdev, reg, 0); 2180 } 2181 2182 if (tx_path == RF_A) { 2183 path_com[0].data = AX_PATH_COM0_PATHA; 2184 path_com[1].data = AX_PATH_COM1_PATHA; 2185 path_com[2].data = AX_PATH_COM2_PATHA; 2186 path_com[7].data = AX_PATH_COM7_PATHA; 2187 path_com[8].data = AX_PATH_COM8_PATHA; 2188 } else if (tx_path == RF_B) { 2189 path_com[0].data = AX_PATH_COM0_PATHB; 2190 path_com[1].data = AX_PATH_COM1_PATHB; 2191 path_com[2].data = AX_PATH_COM2_PATHB; 2192 path_com[7].data = AX_PATH_COM7_PATHB; 2193 path_com[8].data = AX_PATH_COM8_PATHB; 2194 } else if (tx_path == RF_AB) { 2195 path_com[0].data = AX_PATH_COM0_PATHAB; 2196 path_com[1].data = AX_PATH_COM1_PATHAB; 2197 path_com[2].data = AX_PATH_COM2_PATHAB; 2198 path_com[7].data = AX_PATH_COM7_PATHAB; 2199 path_com[8].data = AX_PATH_COM8_PATHAB; 2200 } else { 2201 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2202 return; 2203 } 2204 2205 for (i = 0; i < cr_size; i++) { 2206 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2207 path_com[i].addr, path_com[i].data); 2208 reg = rtw89_mac_reg_by_idx(path_com[i].addr, mac_idx); 2209 rtw89_write32(rtwdev, reg, path_com[i].data); 2210 } 2211 } 2212 2213 static void rtw8852c_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 2214 { 2215 if (bt_en) { 2216 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2217 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2218 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2219 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2220 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2221 B_PATH0_RXBB_MSK_V1, 0xf); 2222 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2223 B_PATH1_RXBB_MSK_V1, 0xf); 2224 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2225 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2226 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2227 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2228 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2229 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2230 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2231 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2232 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2233 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2234 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2235 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2236 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2237 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2238 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2239 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2240 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2241 B_P0_BACKOFF_IBADC_V1, 0x34); 2242 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2243 B_P1_BACKOFF_IBADC_V1, 0x34); 2244 } else { 2245 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2246 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2247 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2248 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2249 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2250 B_PATH0_RXBB_MSK_V1, 0x60); 2251 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2252 B_PATH1_RXBB_MSK_V1, 0x60); 2253 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2254 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2255 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2256 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2257 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2258 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2259 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2260 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2261 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2262 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2263 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2264 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2265 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2266 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2267 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2268 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2269 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2270 B_P0_BACKOFF_IBADC_V1, 0x26); 2271 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2272 B_P1_BACKOFF_IBADC_V1, 0x26); 2273 } 2274 } 2275 2276 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2277 { 2278 struct rtw89_hal *hal = &rtwdev->hal; 2279 2280 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2281 2282 if (hal->rx_nss == 1) { 2283 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2284 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2285 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2286 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2287 } else { 2288 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2289 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2290 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2291 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2292 } 2293 } 2294 2295 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2296 { 2297 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2298 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2299 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2300 2301 fsleep(200); 2302 2303 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2304 } 2305 2306 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2307 { 2308 struct rtw89_btc *btc = &rtwdev->btc; 2309 struct rtw89_btc_module *module = &btc->mdinfo; 2310 2311 module->rfe_type = rtwdev->efuse.rfe_type; 2312 module->cv = rtwdev->hal.cv; 2313 module->bt_solo = 0; 2314 module->switch_type = BTC_SWITCH_INTERNAL; 2315 2316 if (module->rfe_type > 0) 2317 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 2318 else 2319 module->ant.num = 2; 2320 2321 module->ant.diversity = 0; 2322 module->ant.isolation = 10; 2323 2324 if (module->ant.num == 3) { 2325 module->ant.type = BTC_ANT_DEDICATED; 2326 module->bt_pos = BTC_BT_ALONE; 2327 } else { 2328 module->ant.type = BTC_ANT_SHARED; 2329 module->bt_pos = BTC_BT_BTG; 2330 } 2331 } 2332 2333 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 2334 { 2335 if (btg) { 2336 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2337 B_PATH0_BT_SHARE_V1, 0x1); 2338 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2339 B_PATH0_BTG_PATH_V1, 0x0); 2340 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2341 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2342 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2343 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2344 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2345 B_PATH1_BT_SHARE_V1, 0x1); 2346 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2347 B_PATH1_BTG_PATH_V1, 0x1); 2348 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2349 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2350 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2351 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2352 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2353 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2354 0x1); 2355 } else { 2356 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2357 B_PATH0_BT_SHARE_V1, 0x0); 2358 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2359 B_PATH0_BTG_PATH_V1, 0x0); 2360 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2361 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2362 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2363 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2364 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2365 B_PATH1_BT_SHARE_V1, 0x0); 2366 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2367 B_PATH1_BTG_PATH_V1, 0x0); 2368 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2369 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2370 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2371 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2372 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2373 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2374 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2375 0x0); 2376 } 2377 } 2378 2379 static 2380 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2381 { 2382 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2383 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2384 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2385 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2386 } 2387 2388 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2389 { 2390 struct rtw89_btc *btc = &rtwdev->btc; 2391 struct rtw89_btc_module *module = &btc->mdinfo; 2392 const struct rtw89_chip_info *chip = rtwdev->chip; 2393 const struct rtw89_mac_ax_coex coex_params = { 2394 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2395 .direction = RTW89_MAC_AX_COEX_INNER, 2396 }; 2397 2398 /* PTA init */ 2399 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2400 2401 /* set WL Tx response = Hi-Pri */ 2402 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2403 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2404 2405 /* set rf gnt debug off */ 2406 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2407 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2408 2409 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2410 if (module->ant.type == BTC_ANT_SHARED) { 2411 rtw8852c_set_trx_mask(rtwdev, 2412 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2413 rtw8852c_set_trx_mask(rtwdev, 2414 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2415 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2416 rtw8852c_set_trx_mask(rtwdev, 2417 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2418 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2419 rtw8852c_set_trx_mask(rtwdev, 2420 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2421 rtw8852c_set_trx_mask(rtwdev, 2422 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2423 } 2424 2425 /* set PTA break table */ 2426 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2427 2428 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2429 rtw89_write32_set(rtwdev, 2430 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2431 B_AX_BT_CNT_RST_V1); 2432 btc->cx.wl.status.map.init_ok = true; 2433 } 2434 2435 static 2436 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2437 { 2438 u32 bitmap = 0; 2439 u32 reg = 0; 2440 2441 switch (map) { 2442 case BTC_PRI_MASK_TX_RESP: 2443 reg = R_BTC_COEX_WL_REQ; 2444 bitmap = B_BTC_RSP_ACK_HI; 2445 break; 2446 case BTC_PRI_MASK_BEACON: 2447 reg = R_BTC_COEX_WL_REQ; 2448 bitmap = B_BTC_TX_BCN_HI; 2449 break; 2450 default: 2451 return; 2452 } 2453 2454 if (state) 2455 rtw89_write32_set(rtwdev, reg, bitmap); 2456 else 2457 rtw89_write32_clr(rtwdev, reg, bitmap); 2458 } 2459 2460 union rtw8852c_btc_wl_txpwr_ctrl { 2461 u32 txpwr_val; 2462 struct { 2463 union { 2464 u16 ctrl_all_time; 2465 struct { 2466 s16 data:9; 2467 u16 rsvd:6; 2468 u16 flag:1; 2469 } all_time; 2470 }; 2471 union { 2472 u16 ctrl_gnt_bt; 2473 struct { 2474 s16 data:9; 2475 u16 rsvd:7; 2476 } gnt_bt; 2477 }; 2478 }; 2479 } __packed; 2480 2481 static void 2482 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2483 { 2484 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2485 s32 val; 2486 2487 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2488 do { \ 2489 u32 _wrt = FIELD_PREP(_msk, _val); \ 2490 BUILD_BUG_ON((_msk & _en) != 0); \ 2491 if (_cond) \ 2492 _wrt |= _en; \ 2493 else \ 2494 _wrt &= ~_en; \ 2495 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2496 _msk | _en, _wrt); \ 2497 } while (0) 2498 2499 switch (arg.ctrl_all_time) { 2500 case 0xffff: 2501 val = 0; 2502 break; 2503 default: 2504 val = arg.all_time.data; 2505 break; 2506 } 2507 2508 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2509 val, B_AX_FORCE_PWR_BY_RATE_EN, 2510 arg.ctrl_all_time != 0xffff); 2511 2512 switch (arg.ctrl_gnt_bt) { 2513 case 0xffff: 2514 val = 0; 2515 break; 2516 default: 2517 val = arg.gnt_bt.data; 2518 break; 2519 } 2520 2521 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2522 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2523 2524 #undef __write_ctrl 2525 } 2526 2527 static 2528 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2529 { 2530 return clamp_t(s8, val, -100, 0) + 100; 2531 } 2532 2533 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2534 {255, 0, 0, 7}, /* 0 -> original */ 2535 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2536 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2537 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2538 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2539 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2540 {6, 1, 0, 7}, 2541 {13, 1, 0, 7}, 2542 {13, 1, 0, 7} 2543 }; 2544 2545 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2546 {255, 0, 0, 7}, /* 0 -> original */ 2547 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2548 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2549 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2550 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2551 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2552 {255, 1, 0, 7}, 2553 {255, 1, 0, 7}, 2554 {255, 1, 0, 7} 2555 }; 2556 2557 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2558 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2559 2560 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2561 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2562 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2563 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2564 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2565 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2566 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2567 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2568 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2569 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2570 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2571 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2572 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2573 }; 2574 2575 static 2576 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2577 { 2578 /* Feature move to firmware */ 2579 } 2580 2581 static 2582 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2583 { 2584 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2585 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2586 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2587 2588 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2589 if (state) 2590 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2591 RFREG_MASK, 0x179c); 2592 else 2593 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2594 RFREG_MASK, 0x208); 2595 2596 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2597 } 2598 2599 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2600 { 2601 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2602 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2603 * To improve BT ACI in co-rx 2604 */ 2605 2606 switch (level) { 2607 case 0: /* default */ 2608 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2609 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2610 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2611 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2612 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2613 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2614 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2615 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2616 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2617 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2618 break; 2619 case 1: /* Fix LNA2=5 */ 2620 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2621 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2622 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2623 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2624 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2625 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2626 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2627 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2628 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2629 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2630 break; 2631 } 2632 } 2633 2634 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2635 { 2636 struct rtw89_btc *btc = &rtwdev->btc; 2637 2638 switch (level) { 2639 case 0: /* original */ 2640 default: 2641 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2642 btc->dm.wl_lna2 = 0; 2643 break; 2644 case 1: /* for FDD free-run */ 2645 rtw8852c_bb_ctrl_btc_preagc(rtwdev, true); 2646 btc->dm.wl_lna2 = 0; 2647 break; 2648 case 2: /* for BTG Co-Rx*/ 2649 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2650 btc->dm.wl_lna2 = 1; 2651 break; 2652 } 2653 2654 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2655 } 2656 2657 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2658 struct rtw89_rx_phy_ppdu *phy_ppdu, 2659 struct ieee80211_rx_status *status) 2660 { 2661 u8 chan_idx = phy_ppdu->chan_idx; 2662 enum nl80211_band band; 2663 u8 ch; 2664 2665 if (chan_idx == 0) 2666 return; 2667 2668 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2669 status->freq = ieee80211_channel_to_frequency(ch, band); 2670 status->band = band; 2671 } 2672 2673 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2674 struct rtw89_rx_phy_ppdu *phy_ppdu, 2675 struct ieee80211_rx_status *status) 2676 { 2677 u8 path; 2678 u8 *rx_power = phy_ppdu->rssi; 2679 2680 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2681 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2682 status->chains |= BIT(path); 2683 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2684 } 2685 if (phy_ppdu->valid) 2686 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2687 } 2688 2689 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2690 { 2691 int ret; 2692 2693 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2694 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2695 2696 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2697 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2698 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2699 2700 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2701 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2702 2703 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2704 if (ret) 2705 return ret; 2706 2707 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2708 if (ret) 2709 return ret; 2710 2711 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2712 if (ret) 2713 return ret; 2714 2715 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2716 if (ret) 2717 return ret; 2718 2719 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2720 if (ret) 2721 return ret; 2722 2723 return 0; 2724 } 2725 2726 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2727 { 2728 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2729 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2730 2731 return 0; 2732 } 2733 2734 #ifdef CONFIG_PM 2735 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = { 2736 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2737 .n_patterns = RTW89_MAX_PATTERN_NUM, 2738 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2739 .pattern_min_len = 1, 2740 }; 2741 #endif 2742 2743 static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2744 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2745 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2746 .bb_reset = rtw8852c_bb_reset, 2747 .bb_sethw = rtw8852c_bb_sethw, 2748 .read_rf = rtw89_phy_read_rf_v1, 2749 .write_rf = rtw89_phy_write_rf_v1, 2750 .set_channel = rtw8852c_set_channel, 2751 .set_channel_help = rtw8852c_set_channel_help, 2752 .read_efuse = rtw8852c_read_efuse, 2753 .read_phycap = rtw8852c_read_phycap, 2754 .fem_setup = NULL, 2755 .rfk_init = rtw8852c_rfk_init, 2756 .rfk_channel = rtw8852c_rfk_channel, 2757 .rfk_band_changed = rtw8852c_rfk_band_changed, 2758 .rfk_scan = rtw8852c_rfk_scan, 2759 .rfk_track = rtw8852c_rfk_track, 2760 .power_trim = rtw8852c_power_trim, 2761 .set_txpwr = rtw8852c_set_txpwr, 2762 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2763 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2764 .get_thermal = rtw8852c_get_thermal, 2765 .ctrl_btg = rtw8852c_ctrl_btg, 2766 .query_ppdu = rtw8852c_query_ppdu, 2767 .bb_ctrl_btc_preagc = rtw8852c_bb_ctrl_btc_preagc, 2768 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2769 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2770 .pwr_on_func = rtw8852c_pwr_on_func, 2771 .pwr_off_func = rtw8852c_pwr_off_func, 2772 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2773 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2774 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2775 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2776 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2777 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2778 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2779 2780 .btc_set_rfe = rtw8852c_btc_set_rfe, 2781 .btc_init_cfg = rtw8852c_btc_init_cfg, 2782 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2783 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2784 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2785 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2786 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2787 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2788 .btc_set_policy = rtw89_btc_set_policy_v1, 2789 }; 2790 2791 const struct rtw89_chip_info rtw8852c_chip_info = { 2792 .chip_id = RTL8852C, 2793 .ops = &rtw8852c_chip_ops, 2794 .fw_name = "rtw89/rtw8852c_fw.bin", 2795 .try_ce_fw = false, 2796 .fifo_size = 458752, 2797 .dle_scc_rsvd_size = 0, 2798 .max_amsdu_limit = 8000, 2799 .dis_2g_40m_ul_ofdma = false, 2800 .rsvd_ple_ofst = 0x6f800, 2801 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2802 .dle_mem = rtw8852c_dle_mem_pcie, 2803 .wde_qempty_acq_num = 16, 2804 .wde_qempty_mgq_sel = 16, 2805 .rf_base_addr = {0xe000, 0xf000}, 2806 .pwr_on_seq = NULL, 2807 .pwr_off_seq = NULL, 2808 .bb_table = &rtw89_8852c_phy_bb_table, 2809 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2810 .rf_table = {&rtw89_8852c_phy_radiob_table, 2811 &rtw89_8852c_phy_radioa_table,}, 2812 .nctl_table = &rtw89_8852c_phy_nctl_table, 2813 .byr_table = &rtw89_8852c_byr_table, 2814 .txpwr_lmt_2g = &rtw89_8852c_txpwr_lmt_2g, 2815 .txpwr_lmt_5g = &rtw89_8852c_txpwr_lmt_5g, 2816 .txpwr_lmt_6g = &rtw89_8852c_txpwr_lmt_6g, 2817 .txpwr_lmt_ru_2g = &rtw89_8852c_txpwr_lmt_ru_2g, 2818 .txpwr_lmt_ru_5g = &rtw89_8852c_txpwr_lmt_ru_5g, 2819 .txpwr_lmt_ru_6g = &rtw89_8852c_txpwr_lmt_ru_6g, 2820 .txpwr_factor_rf = 2, 2821 .txpwr_factor_mac = 1, 2822 .dig_table = NULL, 2823 .dig_regs = &rtw8852c_dig_regs, 2824 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2825 .support_chanctx_num = 1, 2826 .support_bands = BIT(NL80211_BAND_2GHZ) | 2827 BIT(NL80211_BAND_5GHZ) | 2828 BIT(NL80211_BAND_6GHZ), 2829 .support_bw160 = true, 2830 .support_ul_tb_ctrl = false, 2831 .hw_sec_hdr = true, 2832 .rf_path_num = 2, 2833 .tx_nss = 2, 2834 .rx_nss = 2, 2835 .acam_num = 128, 2836 .bcam_num = 20, 2837 .scam_num = 128, 2838 .bacam_num = 8, 2839 .bacam_dynamic_num = 8, 2840 .bacam_v1 = true, 2841 .sec_ctrl_efuse_size = 4, 2842 .physical_efuse_size = 1216, 2843 .logical_efuse_size = 2048, 2844 .limit_efuse_size = 1280, 2845 .dav_phy_efuse_size = 96, 2846 .dav_log_efuse_size = 16, 2847 .phycap_addr = 0x590, 2848 .phycap_size = 0x60, 2849 .para_ver = 0x1, 2850 .wlcx_desired = 0x06000000, 2851 .btcx_desired = 0x7, 2852 .scbd = 0x1, 2853 .mailbox = 0x1, 2854 2855 .afh_guard_ch = 6, 2856 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 2857 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 2858 .rssi_tol = 2, 2859 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 2860 .mon_reg = rtw89_btc_8852c_mon_reg, 2861 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 2862 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 2863 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 2864 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 2865 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2866 BIT(RTW89_PS_MODE_CLK_GATED) | 2867 BIT(RTW89_PS_MODE_PWR_GATED), 2868 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 2869 BIT(RTW89_PS_MODE_PWR_GATED), 2870 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 2871 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 2872 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 2873 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 2874 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 2875 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2876 .h2c_regs = rtw8852c_h2c_regs, 2877 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 2878 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2879 .c2h_regs = rtw8852c_c2h_regs, 2880 .page_regs = &rtw8852c_page_regs, 2881 .cfo_src_fd = false, 2882 .dcfo_comp = &rtw8852c_dcfo_comp, 2883 .dcfo_comp_sft = 5, 2884 .imr_info = &rtw8852c_imr_info, 2885 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 2886 .bss_clr_map_reg = R_BSS_CLR_MAP, 2887 .dma_ch_mask = 0, 2888 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL, 2889 #ifdef CONFIG_PM 2890 .wowlan_stub = &rtw_wowlan_stub_8852c, 2891 #endif 2892 }; 2893 EXPORT_SYMBOL(rtw8852c_chip_info); 2894 2895 MODULE_FIRMWARE("rtw89/rtw8852c_fw.bin"); 2896 MODULE_AUTHOR("Realtek Corporation"); 2897 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 2898 MODULE_LICENSE("Dual BSD/GPL"); 2899