1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022  Realtek Corporation
3  */
4 
5 #include "coex.h"
6 #include "debug.h"
7 #include "fw.h"
8 #include "mac.h"
9 #include "phy.h"
10 #include "reg.h"
11 #include "rtw8852c.h"
12 #include "rtw8852c_rfk.h"
13 #include "rtw8852c_table.h"
14 #include "util.h"
15 
16 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = {
17 	{13, 1614, grp_0}, /* ACH 0 */
18 	{13, 1614, grp_0}, /* ACH 1 */
19 	{13, 1614, grp_0}, /* ACH 2 */
20 	{13, 1614, grp_0}, /* ACH 3 */
21 	{13, 1614, grp_1}, /* ACH 4 */
22 	{13, 1614, grp_1}, /* ACH 5 */
23 	{13, 1614, grp_1}, /* ACH 6 */
24 	{13, 1614, grp_1}, /* ACH 7 */
25 	{13, 1614, grp_0}, /* B0MGQ */
26 	{13, 1614, grp_0}, /* B0HIQ */
27 	{13, 1614, grp_1}, /* B1MGQ */
28 	{13, 1614, grp_1}, /* B1HIQ */
29 	{40, 0, 0} /* FWCMDQ */
30 };
31 
32 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = {
33 	1614, /* Group 0 */
34 	1614, /* Group 1 */
35 	3228, /* Public Max */
36 	0 /* WP threshold */
37 };
38 
39 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = {
40 	[RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie,
41 			   &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
42 	[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
43 			    RTW89_HCIFC_POH},
44 	[RTW89_QTA_INVALID] = {NULL},
45 };
46 
47 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = {
48 	[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19,
49 			   &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18,
50 			   &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46,
51 			   &rtw89_mac_size.ple_qt47},
52 	[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
53 			    &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
54 			    &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
55 			    &rtw89_mac_size.ple_qt45},
56 	[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
57 			       NULL},
58 };
59 
60 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = {
61 	R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1,
62 	R_AX_H2CREG_DATA3_V1
63 };
64 
65 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = {
66 	R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1,
67 	R_AX_C2HREG_DATA3_V1
68 };
69 
70 static const struct rtw89_page_regs rtw8852c_page_regs = {
71 	.hci_fc_ctrl	= R_AX_HCI_FC_CTRL_V1,
72 	.ch_page_ctrl	= R_AX_CH_PAGE_CTRL_V1,
73 	.ach_page_ctrl	= R_AX_ACH0_PAGE_CTRL_V1,
74 	.ach_page_info	= R_AX_ACH0_PAGE_INFO_V1,
75 	.pub_page_info3	= R_AX_PUB_PAGE_INFO3_V1,
76 	.pub_page_ctrl1	= R_AX_PUB_PAGE_CTRL1_V1,
77 	.pub_page_ctrl2	= R_AX_PUB_PAGE_CTRL2_V1,
78 	.pub_page_info1	= R_AX_PUB_PAGE_INFO1_V1,
79 	.pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1,
80 	.wp_page_ctrl1	= R_AX_WP_PAGE_CTRL1_V1,
81 	.wp_page_ctrl2	= R_AX_WP_PAGE_CTRL2_V1,
82 	.wp_page_info1	= R_AX_WP_PAGE_INFO1_V1,
83 };
84 
85 static const struct rtw89_reg_def rtw8852c_dcfo_comp = {
86 	R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK
87 };
88 
89 static const struct rtw89_imr_info rtw8852c_imr_info = {
90 	.wdrls_imr_set		= B_AX_WDRLS_IMR_SET_V1,
91 	.wsec_imr_reg		= R_AX_SEC_ERROR_FLAG_IMR,
92 	.wsec_imr_set		= B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR,
93 	.mpdu_tx_imr_set	= B_AX_MPDU_TX_IMR_SET_V1,
94 	.mpdu_rx_imr_set	= B_AX_MPDU_RX_IMR_SET_V1,
95 	.sta_sch_imr_set	= B_AX_STA_SCHEDULER_IMR_SET,
96 	.txpktctl_imr_b0_reg	= R_AX_TXPKTCTL_B0_ERRFLAG_IMR,
97 	.txpktctl_imr_b0_clr	= B_AX_TXPKTCTL_IMR_B0_CLR_V1,
98 	.txpktctl_imr_b0_set	= B_AX_TXPKTCTL_IMR_B0_SET_V1,
99 	.txpktctl_imr_b1_reg	= R_AX_TXPKTCTL_B1_ERRFLAG_IMR,
100 	.txpktctl_imr_b1_clr	= B_AX_TXPKTCTL_IMR_B1_CLR_V1,
101 	.txpktctl_imr_b1_set	= B_AX_TXPKTCTL_IMR_B1_SET_V1,
102 	.wde_imr_clr		= B_AX_WDE_IMR_CLR_V1,
103 	.wde_imr_set		= B_AX_WDE_IMR_SET_V1,
104 	.ple_imr_clr		= B_AX_PLE_IMR_CLR_V1,
105 	.ple_imr_set		= B_AX_PLE_IMR_SET_V1,
106 	.host_disp_imr_clr	= B_AX_HOST_DISP_IMR_CLR_V1,
107 	.host_disp_imr_set	= B_AX_HOST_DISP_IMR_SET_V1,
108 	.cpu_disp_imr_clr	= B_AX_CPU_DISP_IMR_CLR_V1,
109 	.cpu_disp_imr_set	= B_AX_CPU_DISP_IMR_SET_V1,
110 	.other_disp_imr_clr	= B_AX_OTHER_DISP_IMR_CLR_V1,
111 	.other_disp_imr_set	= B_AX_OTHER_DISP_IMR_SET_V1,
112 	.bbrpt_com_err_imr_reg	= R_AX_BBRPT_COM_ERR_IMR,
113 	.bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR,
114 	.bbrpt_err_imr_set	= R_AX_BBRPT_CHINFO_IMR_SET_V1,
115 	.bbrpt_dfs_err_imr_reg	= R_AX_BBRPT_DFS_ERR_IMR,
116 	.ptcl_imr_clr		= B_AX_PTCL_IMR_CLR_V1,
117 	.ptcl_imr_set		= B_AX_PTCL_IMR_SET_V1,
118 	.cdma_imr_0_reg		= R_AX_RX_ERR_FLAG_IMR,
119 	.cdma_imr_0_clr		= B_AX_RX_ERR_IMR_CLR_V1,
120 	.cdma_imr_0_set		= B_AX_RX_ERR_IMR_SET_V1,
121 	.cdma_imr_1_reg		= R_AX_TX_ERR_FLAG_IMR,
122 	.cdma_imr_1_clr		= B_AX_TX_ERR_IMR_CLR_V1,
123 	.cdma_imr_1_set		= B_AX_TX_ERR_IMR_SET_V1,
124 	.phy_intf_imr_reg	= R_AX_PHYINFO_ERR_IMR_V1,
125 	.phy_intf_imr_clr	= B_AX_PHYINFO_IMR_CLR_V1,
126 	.phy_intf_imr_set	= B_AX_PHYINFO_IMR_SET_V1,
127 	.rmac_imr_reg		= R_AX_RX_ERR_IMR,
128 	.rmac_imr_clr		= B_AX_RMAC_IMR_CLR_V1,
129 	.rmac_imr_set		= B_AX_RMAC_IMR_SET_V1,
130 	.tmac_imr_reg		= R_AX_TRXPTCL_ERROR_INDICA_MASK,
131 	.tmac_imr_clr		= B_AX_TMAC_IMR_CLR_V1,
132 	.tmac_imr_set		= B_AX_TMAC_IMR_SET_V1,
133 };
134 
135 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = {
136 	.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
137 	.rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2},
138 };
139 
140 static const struct rtw89_dig_regs rtw8852c_dig_regs = {
141 	.seg0_pd_reg = R_SEG0R_PD,
142 	.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
143 	.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
144 	.p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
145 	.p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
146 	.p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
147 	.p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
148 	.p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
149 	.p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
150 	.p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1,
151 			      B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
152 	.p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1,
153 			      B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
154 	.p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1,
155 			      B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
156 	.p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1,
157 			      B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
158 };
159 
160 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg);
161 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path,
162 				       enum rtw89_mac_idx mac_idx);
163 
164 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
165 {
166 	u32 val32;
167 	u32 ret;
168 
169 	val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK);
170 	if (val32 == MAC_AX_HCI_SEL_PCIE_USB)
171 		rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L);
172 
173 	rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
174 						    B_AX_AFSM_PCIE_SUS_EN);
175 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
176 	rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
177 	rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
178 	rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
179 
180 	ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
181 				1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
182 	if (ret)
183 		return ret;
184 
185 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
186 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
187 
188 	ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
189 				1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
190 	if (ret)
191 		return ret;
192 
193 	rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
194 	rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
195 	rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
196 	rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
197 
198 	rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
199 	rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
200 
201 	rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN);
202 	rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP);
203 	rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN |
204 						  B_AX_R_SYM_WLCMAC1_P3_PC_EN |
205 						  B_AX_R_SYM_WLCMAC1_P2_PC_EN |
206 						  B_AX_R_SYM_WLCMAC1_P1_PC_EN |
207 						  B_AX_R_SYM_WLCMAC1_PC_EN);
208 	rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
209 
210 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
211 				      XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
212 	if (ret)
213 		return ret;
214 
215 	rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
216 
217 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
218 				      XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
219 	if (ret)
220 		return ret;
221 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
222 				      XTAL_SI_OFF_WEI);
223 	if (ret)
224 		return ret;
225 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
226 				      XTAL_SI_OFF_EI);
227 	if (ret)
228 		return ret;
229 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
230 	if (ret)
231 		return ret;
232 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
233 				      XTAL_SI_PON_WEI);
234 	if (ret)
235 		return ret;
236 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
237 				      XTAL_SI_PON_EI);
238 	if (ret)
239 		return ret;
240 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
241 	if (ret)
242 		return ret;
243 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
244 	if (ret)
245 		return ret;
246 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
247 	if (ret)
248 		return ret;
249 
250 	rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
251 	rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
252 	rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
253 
254 	fsleep(1000);
255 
256 	rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
257 	rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
258 	rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
259 			  B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN |
260 			  B_AX_LED1_PULL_LOW_EN);
261 
262 	rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
263 			  B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
264 			  B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
265 			  B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
266 			  B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
267 			  B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
268 			  B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN);
269 
270 	rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
271 			  B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
272 			  B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN |
273 			  B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN |
274 			  B_AX_TMAC_EN | B_AX_RMAC_EN);
275 
276 	rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK,
277 			   PINMUX_EESK_FUNC_SEL_BT_LOG);
278 
279 	return 0;
280 }
281 
282 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
283 {
284 	u32 val32;
285 	u32 ret;
286 
287 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
288 				      XTAL_SI_RFC2RF);
289 	if (ret)
290 		return ret;
291 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
292 	if (ret)
293 		return ret;
294 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
295 	if (ret)
296 		return ret;
297 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
298 	if (ret)
299 		return ret;
300 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
301 	if (ret)
302 		return ret;
303 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
304 				      XTAL_SI_SRAM2RFC);
305 	if (ret)
306 		return ret;
307 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
308 	if (ret)
309 		return ret;
310 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
311 	if (ret)
312 		return ret;
313 
314 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
315 	rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
316 	rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
317 			  B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1);
318 	rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
319 
320 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
321 	if (ret)
322 		return ret;
323 
324 	rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
325 
326 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
327 	if (ret)
328 		return ret;
329 
330 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
331 
332 	ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
333 				1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
334 	if (ret)
335 		return ret;
336 
337 	rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0);
338 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
339 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
340 
341 	return 0;
342 }
343 
344 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse,
345 				     struct rtw8852c_efuse *map)
346 {
347 	ether_addr_copy(efuse->addr, map->e.mac_addr);
348 	efuse->rfe_type = map->rfe_type;
349 	efuse->xtal_cap = map->xtal_k;
350 }
351 
352 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
353 					struct rtw8852c_efuse *map)
354 {
355 	struct rtw89_tssi_info *tssi = &rtwdev->tssi;
356 	struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
357 	u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b};
358 	u8 i, j;
359 
360 	tssi->thermal[RF_PATH_A] = map->path_a_therm;
361 	tssi->thermal[RF_PATH_B] = map->path_b_therm;
362 
363 	for (i = 0; i < RF_PATH_NUM_8852C; i++) {
364 		memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
365 		       sizeof(ofst[i]->cck_tssi));
366 
367 		for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
368 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
369 				    "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
370 				    i, j, tssi->tssi_cck[i][j]);
371 
372 		memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
373 		       sizeof(ofst[i]->bw40_tssi));
374 		memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
375 		       ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
376 		memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i],
377 		       sizeof(tssi->tssi_6g_mcs[i]));
378 
379 		for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
380 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
381 				    "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
382 				    i, j, tssi->tssi_mcs[i][j]);
383 	}
384 }
385 
386 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
387 {
388 	if (high)
389 		*high = sign_extend32(FIELD_GET(GENMASK(7,  4), data), 3);
390 	if (low)
391 		*low = sign_extend32(FIELD_GET(GENMASK(3,  0), data), 3);
392 
393 	return data != 0xff;
394 }
395 
396 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
397 					       struct rtw8852c_efuse *map)
398 {
399 	struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
400 	bool valid = false;
401 
402 	valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
403 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
404 				    &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
405 	valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
406 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
407 				    &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
408 	valid |= _decode_efuse_gain(map->rx_gain_5g_low,
409 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
410 				    &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
411 	valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
412 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
413 				    &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
414 	valid |= _decode_efuse_gain(map->rx_gain_5g_high,
415 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
416 				    &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
417 
418 	gain->offset_valid = valid;
419 }
420 
421 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
422 {
423 	struct rtw89_efuse *efuse = &rtwdev->efuse;
424 	struct rtw8852c_efuse *map;
425 
426 	map = (struct rtw8852c_efuse *)log_map;
427 
428 	efuse->country_code[0] = map->country_code[0];
429 	efuse->country_code[1] = map->country_code[1];
430 	rtw8852c_efuse_parsing_tssi(rtwdev, map);
431 	rtw8852c_efuse_parsing_gain_offset(rtwdev, map);
432 
433 	switch (rtwdev->hci.type) {
434 	case RTW89_HCI_TYPE_PCIE:
435 		rtw8852c_e_efuse_parsing(efuse, map);
436 		break;
437 	default:
438 		return -ENOTSUPP;
439 	}
440 
441 	rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
442 
443 	return 0;
444 }
445 
446 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
447 {
448 	struct rtw89_tssi_info *tssi = &rtwdev->tssi;
449 	static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB};
450 	static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3};
451 	u32 addr = rtwdev->chip->phycap_addr;
452 	bool pg = false;
453 	u32 ofst;
454 	u8 i, j;
455 
456 	for (i = 0; i < RF_PATH_NUM_8852C; i++) {
457 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
458 			/* addrs are in decreasing order */
459 			ofst = tssi_trim_addr[i] - addr - j;
460 			tssi->tssi_trim[i][j] = phycap_map[ofst];
461 
462 			if (phycap_map[ofst] != 0xff)
463 				pg = true;
464 		}
465 
466 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) {
467 			/* addrs are in decreasing order */
468 			ofst = tssi_trim_addr_6g[i] - addr - j;
469 			tssi->tssi_trim_6g[i][j] = phycap_map[ofst];
470 
471 			if (phycap_map[ofst] != 0xff)
472 				pg = true;
473 		}
474 	}
475 
476 	if (!pg) {
477 		memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
478 		memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g));
479 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
480 			    "[TSSI][TRIM] no PG, set all trim info to 0\n");
481 	}
482 
483 	for (i = 0; i < RF_PATH_NUM_8852C; i++)
484 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
485 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
486 				    "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
487 				    i, j, tssi->tssi_trim[i][j],
488 				    tssi_trim_addr[i] - j);
489 }
490 
491 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
492 						 u8 *phycap_map)
493 {
494 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
495 	static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC};
496 	u32 addr = rtwdev->chip->phycap_addr;
497 	u8 i;
498 
499 	for (i = 0; i < RF_PATH_NUM_8852C; i++) {
500 		info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
501 
502 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
503 			    "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
504 			    i, info->thermal_trim[i]);
505 
506 		if (info->thermal_trim[i] != 0xff)
507 			info->pg_thermal_trim = true;
508 	}
509 }
510 
511 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev)
512 {
513 #define __thm_setting(raw)				\
514 ({							\
515 	u8 __v = (raw);					\
516 	((__v & 0x1) << 3) | ((__v & 0x1f) >> 1);	\
517 })
518 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
519 	u8 i, val;
520 
521 	if (!info->pg_thermal_trim) {
522 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
523 			    "[THERMAL][TRIM] no PG, do nothing\n");
524 
525 		return;
526 	}
527 
528 	for (i = 0; i < RF_PATH_NUM_8852C; i++) {
529 		val = __thm_setting(info->thermal_trim[i]);
530 		rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
531 
532 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
533 			    "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
534 			    i, val);
535 	}
536 #undef __thm_setting
537 }
538 
539 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
540 						 u8 *phycap_map)
541 {
542 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
543 	static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB};
544 	u32 addr = rtwdev->chip->phycap_addr;
545 	u8 i;
546 
547 	for (i = 0; i < RF_PATH_NUM_8852C; i++) {
548 		info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
549 
550 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
551 			    "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
552 			    i, info->pa_bias_trim[i]);
553 
554 		if (info->pa_bias_trim[i] != 0xff)
555 			info->pg_pa_bias_trim = true;
556 	}
557 }
558 
559 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev)
560 {
561 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
562 	u8 pabias_2g, pabias_5g;
563 	u8 i;
564 
565 	if (!info->pg_pa_bias_trim) {
566 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
567 			    "[PA_BIAS][TRIM] no PG, do nothing\n");
568 
569 		return;
570 	}
571 
572 	for (i = 0; i < RF_PATH_NUM_8852C; i++) {
573 		pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
574 		pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
575 
576 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
577 			    "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
578 			    i, pabias_2g, pabias_5g);
579 
580 		rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
581 		rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
582 	}
583 }
584 
585 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
586 {
587 	rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map);
588 	rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map);
589 	rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
590 
591 	return 0;
592 }
593 
594 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev)
595 {
596 	rtw8852c_thermal_trim(rtwdev);
597 	rtw8852c_pa_bias_trim(rtwdev);
598 }
599 
600 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev,
601 				     const struct rtw89_chan *chan,
602 				     u8 mac_idx)
603 {
604 	u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
605 	u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE,
606 					     mac_idx);
607 	u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
608 	u8 txsc20 = 0, txsc40 = 0, txsc80 = 0;
609 	u8 rf_mod_val = 0, chk_rate_mask = 0;
610 	u32 txsc;
611 
612 	switch (chan->band_width) {
613 	case RTW89_CHANNEL_WIDTH_160:
614 		txsc80 = rtw89_phy_get_txsc(rtwdev, chan,
615 					    RTW89_CHANNEL_WIDTH_80);
616 		fallthrough;
617 	case RTW89_CHANNEL_WIDTH_80:
618 		txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
619 					    RTW89_CHANNEL_WIDTH_40);
620 		fallthrough;
621 	case RTW89_CHANNEL_WIDTH_40:
622 		txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
623 					    RTW89_CHANNEL_WIDTH_20);
624 		break;
625 	default:
626 		break;
627 	}
628 
629 	switch (chan->band_width) {
630 	case RTW89_CHANNEL_WIDTH_160:
631 		rf_mod_val = AX_WMAC_RFMOD_160M;
632 		txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) |
633 		       FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) |
634 		       FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80);
635 		break;
636 	case RTW89_CHANNEL_WIDTH_80:
637 		rf_mod_val = AX_WMAC_RFMOD_80M;
638 		txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) |
639 		       FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40);
640 		break;
641 	case RTW89_CHANNEL_WIDTH_40:
642 		rf_mod_val = AX_WMAC_RFMOD_40M;
643 		txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20);
644 		break;
645 	case RTW89_CHANNEL_WIDTH_20:
646 	default:
647 		rf_mod_val = AX_WMAC_RFMOD_20M;
648 		txsc = 0;
649 		break;
650 	}
651 	rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val);
652 	rtw89_write32(rtwdev, sub_carr, txsc);
653 
654 	switch (chan->band_type) {
655 	case RTW89_BAND_2G:
656 		chk_rate_mask = B_AX_BAND_MODE;
657 		break;
658 	case RTW89_BAND_5G:
659 	case RTW89_BAND_6G:
660 		chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6;
661 		break;
662 	default:
663 		rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type);
664 		return;
665 	}
666 	rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN |
667 					   B_AX_RTS_LIMIT_IN_OFDM6);
668 	rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask);
669 }
670 
671 static const u32 rtw8852c_sco_barker_threshold[14] = {
672 	0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
673 	0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
674 };
675 
676 static const u32 rtw8852c_sco_cck_threshold[14] = {
677 	0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
678 	0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
679 };
680 
681 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
682 				 u8 primary_ch, enum rtw89_bandwidth bw)
683 {
684 	u8 ch_element;
685 
686 	if (bw == RTW89_CHANNEL_WIDTH_20) {
687 		ch_element = central_ch - 1;
688 	} else if (bw == RTW89_CHANNEL_WIDTH_40) {
689 		if (primary_ch == 1)
690 			ch_element = central_ch - 1 + 2;
691 		else
692 			ch_element = central_ch - 1 - 2;
693 	} else {
694 		rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
695 		return -EINVAL;
696 	}
697 	rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1,
698 			       rtw8852c_sco_barker_threshold[ch_element]);
699 	rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1,
700 			       rtw8852c_sco_cck_threshold[ch_element]);
701 
702 	return 0;
703 }
704 
705 struct rtw8852c_bb_gain {
706 	u32 gain_g[BB_PATH_NUM_8852C];
707 	u32 gain_a[BB_PATH_NUM_8852C];
708 	u32 gain_mask;
709 };
710 
711 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
712 	{ .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
713 	  .gain_mask = 0x00ff0000 },
714 	{ .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
715 	  .gain_mask = 0xff000000 },
716 	{ .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
717 	  .gain_mask = 0x000000ff },
718 	{ .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
719 	  .gain_mask = 0x0000ff00 },
720 	{ .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
721 	  .gain_mask = 0x00ff0000 },
722 	{ .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
723 	  .gain_mask = 0xff000000 },
724 	{ .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
725 	  .gain_mask = 0x000000ff },
726 };
727 
728 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
729 	{ .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
730 	  .gain_mask = 0x00ff0000 },
731 	{ .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
732 	  .gain_mask = 0xff000000 },
733 };
734 
735 struct rtw8852c_bb_gain_bypass {
736 	u32 gain_g[BB_PATH_NUM_8852C];
737 	u32 gain_a[BB_PATH_NUM_8852C];
738 	u32 gain_mask_g;
739 	u32 gain_mask_a;
740 };
741 
742 static
743 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = {
744 	{ .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78},
745 	  .gain_mask_g = 0xff000000, .gain_mask_a = 0xff},
746 	{ .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
747 	  .gain_mask_g = 0xff, .gain_mask_a = 0xff00},
748 	{ .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
749 	  .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000},
750 	{ .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
751 	  .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000},
752 	{ .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C},
753 	  .gain_mask_g = 0xff000000, .gain_mask_a = 0xff},
754 	{ .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C},
755 	  .gain_mask_g = 0xff, .gain_mask_a = 0xff00},
756 	{ .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C},
757 	  .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000},
758 };
759 
760 struct rtw8852c_bb_gain_op1db {
761 	struct {
762 		u32 lna[BB_PATH_NUM_8852C];
763 		u32 tia_lna[BB_PATH_NUM_8852C];
764 		u32 mask;
765 	} reg[LNA_GAIN_NUM];
766 	u32 reg_tia0_lna6[BB_PATH_NUM_8852C];
767 	u32 mask_tia0_lna6;
768 };
769 
770 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = {
771 	.reg = {
772 		{ .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
773 		  .mask = 0xff},
774 		{ .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
775 		  .mask = 0xff00},
776 		{ .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
777 		  .mask = 0xff0000},
778 		{ .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
779 		  .mask = 0xff000000},
780 		{ .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
781 		  .mask = 0xff},
782 		{ .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
783 		  .mask = 0xff00},
784 		{ .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
785 		  .mask = 0xff0000},
786 	},
787 	.reg_tia0_lna6 = {0x4674, 0x4758},
788 	.mask_tia0_lna6 = 0xff000000,
789 };
790 
791 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev,
792 				    enum rtw89_subband subband,
793 				    enum rtw89_rf_path path)
794 {
795 	const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
796 	u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
797 	s32 val;
798 	u32 reg;
799 	u32 mask;
800 	int i;
801 
802 	for (i = 0; i < LNA_GAIN_NUM; i++) {
803 		if (subband == RTW89_CH_2G)
804 			reg = bb_gain_lna[i].gain_g[path];
805 		else
806 			reg = bb_gain_lna[i].gain_a[path];
807 
808 		mask = bb_gain_lna[i].gain_mask;
809 		val = gain->lna_gain[gain_band][path][i];
810 		rtw89_phy_write32_mask(rtwdev, reg, mask, val);
811 
812 		if (subband == RTW89_CH_2G) {
813 			reg = bb_gain_bypass_lna[i].gain_g[path];
814 			mask = bb_gain_bypass_lna[i].gain_mask_g;
815 		} else {
816 			reg = bb_gain_bypass_lna[i].gain_a[path];
817 			mask = bb_gain_bypass_lna[i].gain_mask_a;
818 		}
819 
820 		val = gain->lna_gain_bypass[gain_band][path][i];
821 		rtw89_phy_write32_mask(rtwdev, reg, mask, val);
822 
823 		if (subband != RTW89_CH_2G) {
824 			reg = bb_gain_op1db_a.reg[i].lna[path];
825 			mask = bb_gain_op1db_a.reg[i].mask;
826 			val = gain->lna_op1db[gain_band][path][i];
827 			rtw89_phy_write32_mask(rtwdev, reg, mask, val);
828 
829 			reg = bb_gain_op1db_a.reg[i].tia_lna[path];
830 			mask = bb_gain_op1db_a.reg[i].mask;
831 			val = gain->tia_lna_op1db[gain_band][path][i];
832 			rtw89_phy_write32_mask(rtwdev, reg, mask, val);
833 		}
834 	}
835 
836 	if (subband != RTW89_CH_2G) {
837 		reg = bb_gain_op1db_a.reg_tia0_lna6[path];
838 		mask = bb_gain_op1db_a.mask_tia0_lna6;
839 		val = gain->tia_lna_op1db[gain_band][path][7];
840 		rtw89_phy_write32_mask(rtwdev, reg, mask, val);
841 	}
842 
843 	for (i = 0; i < TIA_GAIN_NUM; i++) {
844 		if (subband == RTW89_CH_2G)
845 			reg = bb_gain_tia[i].gain_g[path];
846 		else
847 			reg = bb_gain_tia[i].gain_a[path];
848 
849 		mask = bb_gain_tia[i].gain_mask;
850 		val = gain->tia_gain[gain_band][path][i];
851 		rtw89_phy_write32_mask(rtwdev, reg, mask, val);
852 	}
853 }
854 
855 static
856 const u8 rtw8852c_ch_base_table[16] = {1, 0xff,
857 				       36, 100, 132, 149, 0xff,
858 				       1, 33, 65, 97, 129, 161, 193, 225, 0xff};
859 #define RTW8852C_CH_BASE_IDX_2G		0
860 #define RTW8852C_CH_BASE_IDX_5G_FIRST	2
861 #define RTW8852C_CH_BASE_IDX_5G_LAST	5
862 #define RTW8852C_CH_BASE_IDX_6G_FIRST	7
863 #define RTW8852C_CH_BASE_IDX_6G_LAST	14
864 
865 #define RTW8852C_CH_BASE_IDX_MASK	GENMASK(7, 4)
866 #define RTW8852C_CH_OFFSET_MASK		GENMASK(3, 0)
867 
868 static u8 rtw8852c_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
869 {
870 	u8 chan_idx;
871 	u8 last, first;
872 	u8 idx;
873 
874 	switch (band) {
875 	case RTW89_BAND_2G:
876 		chan_idx = FIELD_PREP(RTW8852C_CH_BASE_IDX_MASK, RTW8852C_CH_BASE_IDX_2G) |
877 			   FIELD_PREP(RTW8852C_CH_OFFSET_MASK, central_ch);
878 		return chan_idx;
879 	case RTW89_BAND_5G:
880 		first = RTW8852C_CH_BASE_IDX_5G_FIRST;
881 		last = RTW8852C_CH_BASE_IDX_5G_LAST;
882 		break;
883 	case RTW89_BAND_6G:
884 		first = RTW8852C_CH_BASE_IDX_6G_FIRST;
885 		last = RTW8852C_CH_BASE_IDX_6G_LAST;
886 		break;
887 	default:
888 		rtw89_warn(rtwdev, "Unsupported band %d\n", band);
889 		return 0;
890 	}
891 
892 	for (idx = last; idx >= first; idx--)
893 		if (central_ch >= rtw8852c_ch_base_table[idx])
894 			break;
895 
896 	if (idx < first) {
897 		rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
898 		return 0;
899 	}
900 
901 	chan_idx = FIELD_PREP(RTW8852C_CH_BASE_IDX_MASK, idx) |
902 		   FIELD_PREP(RTW8852C_CH_OFFSET_MASK,
903 			      (central_ch - rtw8852c_ch_base_table[idx]) >> 1);
904 	return chan_idx;
905 }
906 
907 static void rtw8852c_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
908 				     u8 *ch, enum nl80211_band *band)
909 {
910 	u8 idx, offset;
911 
912 	idx = FIELD_GET(RTW8852C_CH_BASE_IDX_MASK, chan_idx);
913 	offset = FIELD_GET(RTW8852C_CH_OFFSET_MASK, chan_idx);
914 
915 	if (idx == RTW8852C_CH_BASE_IDX_2G) {
916 		*band = NL80211_BAND_2GHZ;
917 		*ch = offset;
918 		return;
919 	}
920 
921 	*band = idx <= RTW8852C_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ;
922 	*ch = rtw8852c_ch_base_table[idx] + (offset << 1);
923 }
924 
925 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev,
926 				     const struct rtw89_chan *chan,
927 				     enum rtw89_phy_idx phy_idx,
928 				     enum rtw89_rf_path path)
929 {
930 	static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1,
931 					      R_PATH1_G_TIA0_LNA6_OP1DB_V1};
932 	static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK};
933 	static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK};
934 	struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
935 	enum rtw89_gain_offset gain_band;
936 	s32 offset_q0, offset_base_q4;
937 	s32 tmp = 0;
938 
939 	if (!efuse_gain->offset_valid)
940 		return;
941 
942 	if (rtwdev->dbcc_en && path == RF_PATH_B)
943 		phy_idx = RTW89_PHY_1;
944 
945 	if (chan->band_type == RTW89_BAND_2G) {
946 		offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK];
947 		offset_base_q4 = efuse_gain->offset_base[phy_idx];
948 
949 		tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1),
950 			      S8_MIN >> 1, S8_MAX >> 1);
951 		rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f);
952 	}
953 
954 	gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
955 
956 	offset_q0 = -efuse_gain->offset[path][gain_band];
957 	offset_base_q4 = efuse_gain->offset_base[phy_idx];
958 
959 	tmp = (offset_q0 << 2) + (offset_base_q4 >> 2);
960 	tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX);
961 	rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff);
962 
963 	tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX);
964 	rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx);
965 	rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx);
966 }
967 
968 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev,
969 			     const struct rtw89_chan *chan,
970 			     enum rtw89_phy_idx phy_idx)
971 {
972 	u8 sco;
973 	u16 central_freq = chan->freq;
974 	u8 central_ch = chan->channel;
975 	u8 band = chan->band_type;
976 	u8 subband = chan->subband_type;
977 	bool is_2g = band == RTW89_BAND_2G;
978 	u8 chan_idx;
979 
980 	if (!central_freq) {
981 		rtw89_warn(rtwdev, "Invalid central_freq\n");
982 		return;
983 	}
984 
985 	if (phy_idx == RTW89_PHY_0) {
986 		/* Path A */
987 		rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A);
988 		rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A);
989 
990 		if (is_2g)
991 			rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
992 					      B_PATH0_BAND_SEL_MSK_V1, 1,
993 					      phy_idx);
994 		else
995 			rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
996 					      B_PATH0_BAND_SEL_MSK_V1, 0,
997 					      phy_idx);
998 		/* Path B */
999 		if (!rtwdev->dbcc_en) {
1000 			rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
1001 			rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B);
1002 
1003 			if (is_2g)
1004 				rtw89_phy_write32_idx(rtwdev,
1005 						      R_PATH1_BAND_SEL_V1,
1006 						      B_PATH1_BAND_SEL_MSK_V1,
1007 						      1, phy_idx);
1008 			else
1009 				rtw89_phy_write32_idx(rtwdev,
1010 						      R_PATH1_BAND_SEL_V1,
1011 						      B_PATH1_BAND_SEL_MSK_V1,
1012 						      0, phy_idx);
1013 			rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1014 		} else {
1015 			if (is_2g)
1016 				rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1017 			else
1018 				rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1019 		}
1020 		/* SCO compensate FC setting */
1021 		rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
1022 				      central_freq, phy_idx);
1023 		/* round_up((1/fc0)*pow(2,18)) */
1024 		sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1025 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
1026 				      phy_idx);
1027 	} else {
1028 		/* Path B */
1029 		rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
1030 		rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B);
1031 
1032 		if (is_2g)
1033 			rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1034 					      B_PATH1_BAND_SEL_MSK_V1,
1035 					      1, phy_idx);
1036 		else
1037 			rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1038 					      B_PATH1_BAND_SEL_MSK_V1,
1039 					      0, phy_idx);
1040 		/* SCO compensate FC setting */
1041 		rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
1042 				      central_freq, phy_idx);
1043 		/* round_up((1/fc0)*pow(2,18)) */
1044 		sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1045 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
1046 				      phy_idx);
1047 	}
1048 	/* CCK parameters */
1049 	if (band == RTW89_BAND_2G) {
1050 		if (central_ch == 14) {
1051 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
1052 					       B_PCOEFF01_MSK_V1, 0x3b13ff);
1053 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
1054 					       B_PCOEFF23_MSK_V1, 0x1c42de);
1055 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
1056 					       B_PCOEFF45_MSK_V1, 0xfdb0ad);
1057 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
1058 					       B_PCOEFF67_MSK_V1, 0xf60f6e);
1059 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
1060 					       B_PCOEFF89_MSK_V1, 0xfd8f92);
1061 			rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1062 					       B_PCOEFFAB_MSK_V1, 0x2d011);
1063 			rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1064 					       B_PCOEFFCD_MSK_V1, 0x1c02c);
1065 			rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1066 					       B_PCOEFFEF_MSK_V1, 0xfff00a);
1067 		} else {
1068 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
1069 					       B_PCOEFF01_MSK_V1, 0x3d23ff);
1070 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
1071 					       B_PCOEFF23_MSK_V1, 0x29b354);
1072 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
1073 					       B_PCOEFF45_MSK_V1, 0xfc1c8);
1074 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
1075 					       B_PCOEFF67_MSK_V1, 0xfdb053);
1076 			rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
1077 					       B_PCOEFF89_MSK_V1, 0xf86f9a);
1078 			rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1079 					       B_PCOEFFAB_MSK_V1, 0xfaef92);
1080 			rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1081 					       B_PCOEFFCD_MSK_V1, 0xfe5fcc);
1082 			rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1083 					       B_PCOEFFEF_MSK_V1, 0xffdff5);
1084 		}
1085 	}
1086 
1087 	chan_idx = rtw8852c_encode_chan_idx(rtwdev, chan->primary_channel, band);
1088 	rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx);
1089 }
1090 
1091 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
1092 {
1093 	static const u32 adc_sel[2] = {0xC0EC, 0xC1EC};
1094 	static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
1095 
1096 	switch (bw) {
1097 	case RTW89_CHANNEL_WIDTH_5:
1098 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
1099 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
1100 		break;
1101 	case RTW89_CHANNEL_WIDTH_10:
1102 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
1103 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
1104 		break;
1105 	case RTW89_CHANNEL_WIDTH_20:
1106 	case RTW89_CHANNEL_WIDTH_40:
1107 	case RTW89_CHANNEL_WIDTH_80:
1108 	case RTW89_CHANNEL_WIDTH_160:
1109 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1110 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1111 		break;
1112 	default:
1113 		rtw89_warn(rtwdev, "Fail to set ADC\n");
1114 	}
1115 }
1116 
1117 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw,
1118 					     enum rtw89_phy_idx phy_idx)
1119 {
1120 	if (bw == RTW89_CHANNEL_WIDTH_20) {
1121 		rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx);
1122 		rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1123 	} else {
1124 		rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx);
1125 		rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1126 	}
1127 }
1128 
1129 static void
1130 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1131 		 enum rtw89_phy_idx phy_idx)
1132 {
1133 	u8 mod_sbw = 0;
1134 
1135 	switch (bw) {
1136 	case RTW89_CHANNEL_WIDTH_5:
1137 	case RTW89_CHANNEL_WIDTH_10:
1138 	case RTW89_CHANNEL_WIDTH_20:
1139 		if (bw == RTW89_CHANNEL_WIDTH_5)
1140 			mod_sbw = 0x1;
1141 		else if (bw == RTW89_CHANNEL_WIDTH_10)
1142 			mod_sbw = 0x2;
1143 		else if (bw == RTW89_CHANNEL_WIDTH_20)
1144 			mod_sbw = 0x0;
1145 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1146 				      phy_idx);
1147 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW,
1148 				      mod_sbw, phy_idx);
1149 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0,
1150 				      phy_idx);
1151 		rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1152 				       B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3);
1153 		rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1154 				       B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3);
1155 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1156 				       B_PATH0_BW_SEL_MSK_V1, 0xf);
1157 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1158 				       B_PATH1_BW_SEL_MSK_V1, 0xf);
1159 		break;
1160 	case RTW89_CHANNEL_WIDTH_40:
1161 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1162 				      phy_idx);
1163 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1164 				      phy_idx);
1165 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1166 				      pri_ch,
1167 				      phy_idx);
1168 		rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1169 				       B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3);
1170 		rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1171 				       B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3);
1172 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1173 				       B_PATH0_BW_SEL_MSK_V1, 0xf);
1174 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1175 				       B_PATH1_BW_SEL_MSK_V1, 0xf);
1176 		break;
1177 	case RTW89_CHANNEL_WIDTH_80:
1178 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1179 				      phy_idx);
1180 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1181 				      phy_idx);
1182 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1183 				      pri_ch,
1184 				      phy_idx);
1185 		rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1186 				       B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2);
1187 		rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1188 				       B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2);
1189 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1190 				       B_PATH0_BW_SEL_MSK_V1, 0xd);
1191 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1192 				       B_PATH1_BW_SEL_MSK_V1, 0xd);
1193 		break;
1194 	case RTW89_CHANNEL_WIDTH_160:
1195 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3,
1196 				      phy_idx);
1197 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1198 				      phy_idx);
1199 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1200 				      pri_ch,
1201 				      phy_idx);
1202 		rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1203 				       B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1);
1204 		rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1205 				       B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1);
1206 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1207 				       B_PATH0_BW_SEL_MSK_V1, 0xb);
1208 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1209 				       B_PATH1_BW_SEL_MSK_V1, 0xb);
1210 		break;
1211 	default:
1212 		rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1213 			   pri_ch);
1214 	}
1215 
1216 	if (bw == RTW89_CHANNEL_WIDTH_40) {
1217 		rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1218 				      B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx);
1219 		rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx);
1220 	} else {
1221 		rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1222 				      B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx);
1223 		rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx);
1224 	}
1225 
1226 	if (phy_idx == RTW89_PHY_0) {
1227 		rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A);
1228 		if (!rtwdev->dbcc_en)
1229 			rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1230 	} else {
1231 		rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1232 	}
1233 
1234 	rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx);
1235 }
1236 
1237 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev,
1238 			      const struct rtw89_chan *chan)
1239 {
1240 	u8 center_chan = chan->channel;
1241 	u8 bw = chan->band_width;
1242 
1243 	switch (chan->band_type) {
1244 	case RTW89_BAND_2G:
1245 		if (bw == RTW89_CHANNEL_WIDTH_20) {
1246 			if (center_chan >= 5 && center_chan <= 8)
1247 				return 2440;
1248 			if (center_chan == 13)
1249 				return 2480;
1250 		} else if (bw == RTW89_CHANNEL_WIDTH_40) {
1251 			if (center_chan >= 3 && center_chan <= 10)
1252 				return 2440;
1253 		}
1254 		break;
1255 	case RTW89_BAND_5G:
1256 		if (center_chan == 151 || center_chan == 153 ||
1257 		    center_chan == 155 || center_chan == 163)
1258 			return 5760;
1259 		break;
1260 	case RTW89_BAND_6G:
1261 		if (center_chan == 195 || center_chan == 197 ||
1262 		    center_chan == 199 || center_chan == 207)
1263 			return 6920;
1264 		break;
1265 	default:
1266 		break;
1267 	}
1268 
1269 	return 0;
1270 }
1271 
1272 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1273 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1274 #define MAX_TONE_NUM 2048
1275 
1276 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1277 				      const struct rtw89_chan *chan,
1278 				      enum rtw89_phy_idx phy_idx)
1279 {
1280 	u32 spur_freq;
1281 	s32 freq_diff, csi_idx, csi_tone_idx;
1282 
1283 	spur_freq = rtw8852c_spur_freq(rtwdev, chan);
1284 	if (spur_freq == 0) {
1285 		rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx);
1286 		return;
1287 	}
1288 
1289 	freq_diff = (spur_freq - chan->freq) * 1000000;
1290 	csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1291 	s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1292 
1293 	rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx);
1294 	rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx);
1295 }
1296 
1297 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = {
1298 	[RF_PATH_A] = {
1299 		.notch1_idx = {0x4C14, 0xFF},
1300 		.notch1_frac_idx = {0x4C14, 0xC00},
1301 		.notch1_en = {0x4C14, 0x1000},
1302 		.notch2_idx = {0x4C20, 0xFF},
1303 		.notch2_frac_idx = {0x4C20, 0xC00},
1304 		.notch2_en = {0x4C20, 0x1000},
1305 	},
1306 	[RF_PATH_B] = {
1307 		.notch1_idx = {0x4CD8, 0xFF},
1308 		.notch1_frac_idx = {0x4CD8, 0xC00},
1309 		.notch1_en = {0x4CD8, 0x1000},
1310 		.notch2_idx = {0x4CE4, 0xFF},
1311 		.notch2_frac_idx = {0x4CE4, 0xC00},
1312 		.notch2_en = {0x4CE4, 0x1000},
1313 	},
1314 };
1315 
1316 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1317 				      const struct rtw89_chan *chan,
1318 				      enum rtw89_rf_path path)
1319 {
1320 	const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path];
1321 	u32 spur_freq, fc;
1322 	s32 freq_diff;
1323 	s32 nbi_idx, nbi_tone_idx;
1324 	s32 nbi_frac_idx, nbi_frac_tone_idx;
1325 	bool notch2_chk = false;
1326 
1327 	spur_freq = rtw8852c_spur_freq(rtwdev, chan);
1328 	if (spur_freq == 0) {
1329 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1330 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1331 		return;
1332 	}
1333 
1334 	fc = chan->freq;
1335 	if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1336 		fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1337 		if ((fc > spur_freq &&
1338 		     chan->channel < chan->primary_channel) ||
1339 		    (fc < spur_freq &&
1340 		     chan->channel > chan->primary_channel))
1341 			notch2_chk = true;
1342 	}
1343 
1344 	freq_diff = (spur_freq - fc) * 1000000;
1345 	nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx);
1346 
1347 	if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1348 		s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1349 	} else {
1350 		u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1351 				128 : 256;
1352 
1353 		s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1354 	}
1355 	nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125);
1356 
1357 	if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1358 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1359 				       nbi->notch2_idx.mask, nbi_tone_idx);
1360 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1361 				       nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1362 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1363 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1);
1364 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1365 	} else {
1366 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1367 				       nbi->notch1_idx.mask, nbi_tone_idx);
1368 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1369 				       nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1370 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1371 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1);
1372 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1373 	}
1374 }
1375 
1376 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val,
1377 				enum rtw89_phy_idx phy_idx)
1378 {
1379 	u32 notch;
1380 	u32 notch2;
1381 
1382 	if (phy_idx == RTW89_PHY_0) {
1383 		notch = R_PATH0_NOTCH;
1384 		notch2 = R_PATH0_NOTCH2;
1385 	} else {
1386 		notch = R_PATH1_NOTCH;
1387 		notch2 = R_PATH1_NOTCH2;
1388 	}
1389 
1390 	rtw89_phy_write32_mask(rtwdev, notch,
1391 			       B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val);
1392 	rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN);
1393 	rtw89_phy_write32_mask(rtwdev, notch2,
1394 			       B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val);
1395 	rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN);
1396 }
1397 
1398 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev,
1399 				      const struct rtw89_chan *chan,
1400 				      u8 pri_ch_idx,
1401 				      enum rtw89_phy_idx phy_idx)
1402 {
1403 	rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx);
1404 
1405 	if (phy_idx == RTW89_PHY_0) {
1406 		if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1407 		    (pri_ch_idx == RTW89_SC_20_LOWER ||
1408 		     pri_ch_idx == RTW89_SC_20_UP3X)) {
1409 			rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0);
1410 			if (!rtwdev->dbcc_en)
1411 				rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1412 		} else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1413 			   (pri_ch_idx == RTW89_SC_20_UPPER ||
1414 			    pri_ch_idx == RTW89_SC_20_LOW3X)) {
1415 			rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0);
1416 			if (!rtwdev->dbcc_en)
1417 				rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1418 		} else {
1419 			rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A);
1420 			if (!rtwdev->dbcc_en)
1421 				rtw8852c_set_nbi_tone_idx(rtwdev, chan,
1422 							  RF_PATH_B);
1423 		}
1424 	} else {
1425 		if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1426 		    (pri_ch_idx == RTW89_SC_20_LOWER ||
1427 		     pri_ch_idx == RTW89_SC_20_UP3X)) {
1428 			rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1429 		} else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1430 			   (pri_ch_idx == RTW89_SC_20_UPPER ||
1431 			    pri_ch_idx == RTW89_SC_20_LOW3X)) {
1432 			rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1433 		} else {
1434 			rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B);
1435 		}
1436 	}
1437 
1438 	if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X)
1439 		rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx);
1440 	else
1441 		rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx);
1442 }
1443 
1444 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev,
1445 			     const struct rtw89_chan *chan,
1446 			     enum rtw89_phy_idx phy_idx)
1447 {
1448 	u8 pri_ch = chan->primary_channel;
1449 	bool mask_5m_low;
1450 	bool mask_5m_en;
1451 
1452 	switch (chan->band_width) {
1453 	case RTW89_CHANNEL_WIDTH_40:
1454 		mask_5m_en = true;
1455 		mask_5m_low = pri_ch == 2;
1456 		break;
1457 	case RTW89_CHANNEL_WIDTH_80:
1458 		mask_5m_en = ((pri_ch == 3) || (pri_ch == 4));
1459 		mask_5m_low = pri_ch == 4;
1460 		break;
1461 	default:
1462 		mask_5m_en = false;
1463 		mask_5m_low = false;
1464 		break;
1465 	}
1466 
1467 	if (!mask_5m_en) {
1468 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0);
1469 		rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0);
1470 		rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT,
1471 				      B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx);
1472 	} else {
1473 		if (mask_5m_low) {
1474 			rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1475 			rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1476 			rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0);
1477 			rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1);
1478 			rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1479 			rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1480 			rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0);
1481 			rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1);
1482 		} else {
1483 			rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1484 			rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1485 			rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1);
1486 			rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0);
1487 			rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1488 			rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1489 			rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1);
1490 			rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0);
1491 		}
1492 		rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx);
1493 	}
1494 }
1495 
1496 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev,
1497 				  enum rtw89_phy_idx phy_idx)
1498 {
1499 	/*HW SI reset*/
1500 	rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1501 			       0x7);
1502 	rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1503 			       0x7);
1504 
1505 	udelay(1);
1506 
1507 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1508 			      phy_idx);
1509 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1510 			      phy_idx);
1511 	/*HW SI reset*/
1512 	rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1513 			       0x0);
1514 	rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1515 			       0x0);
1516 
1517 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1518 			      phy_idx);
1519 }
1520 
1521 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1522 				 enum rtw89_phy_idx phy_idx, bool en)
1523 {
1524 	if (en) {
1525 		rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1526 				      B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1527 		rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1528 				      B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1529 		rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1530 				      phy_idx);
1531 		if (band == RTW89_BAND_2G)
1532 			rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0);
1533 		rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1534 	} else {
1535 		rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1);
1536 		rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1537 		rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1538 				      B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1539 		rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1540 				      B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1541 		fsleep(1);
1542 		rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1543 				      phy_idx);
1544 	}
1545 }
1546 
1547 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev,
1548 			      enum rtw89_phy_idx phy_idx)
1549 {
1550 	rtw8852c_bb_reset_all(rtwdev, phy_idx);
1551 }
1552 
1553 static
1554 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1555 			   u8 tx_path_en, u8 trsw_tx,
1556 			   u8 trsw_rx, u8 trsw, u8 trsw_b)
1557 {
1558 	static const u32 path_cr_bases[] = {0x5868, 0x7868};
1559 	u32 mask_ofst = 16;
1560 	u32 cr;
1561 	u32 val;
1562 
1563 	if (path >= ARRAY_SIZE(path_cr_bases))
1564 		return;
1565 
1566 	cr = path_cr_bases[path];
1567 
1568 	mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
1569 	val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b);
1570 
1571 	rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1572 }
1573 
1574 enum rtw8852c_rfe_src {
1575 	PAPE_RFM,
1576 	TRSW_RFM,
1577 	LNAON_RFM,
1578 };
1579 
1580 static
1581 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1582 			  enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl,
1583 			  u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val)
1584 {
1585 	static const u32 path_cr_bases[] = {0x5894, 0x7894};
1586 	static const u32 masks[] = {0, 8, 16};
1587 	u32 mask, mask_ofst;
1588 	u32 cr;
1589 	u32 val;
1590 
1591 	if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases))
1592 		return;
1593 
1594 	mask_ofst = masks[src];
1595 	cr = path_cr_bases[path];
1596 
1597 	val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) |
1598 	      FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) |
1599 	      FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) |
1600 	      FIELD_PREP(B_P0_RFM_OUT, rfm_output_val);
1601 	mask = 0xff << mask_ofst;
1602 
1603 	rtw89_phy_write32_mask(rtwdev, cr, mask, val);
1604 }
1605 
1606 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev)
1607 {
1608 	static const u32 cr_bases[] = {0x5800, 0x7800};
1609 	u32 addr;
1610 	u8 i;
1611 
1612 	for (i = 0; i < ARRAY_SIZE(cr_bases); i++) {
1613 		addr = cr_bases[i];
1614 		rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A);
1615 		rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X);
1616 		rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2);
1617 		rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777);
1618 		rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777);
1619 	}
1620 
1621 	rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1622 	rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1623 	rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1624 	rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1625 
1626 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1627 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1628 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1629 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1630 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1631 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1632 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1633 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1634 
1635 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1);
1636 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0);
1637 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0);
1638 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0);
1639 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1);
1640 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0);
1641 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0);
1642 	rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0);
1643 
1644 	rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0);
1645 	rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4);
1646 	rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8);
1647 
1648 	rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0);
1649 	rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4);
1650 	rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8);
1651 }
1652 
1653 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1654 					enum rtw89_phy_idx phy_idx)
1655 {
1656 	u32 addr;
1657 
1658 	for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1659 	     addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1660 		rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1661 }
1662 
1663 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev)
1664 {
1665 	struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1666 
1667 	rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT,
1668 			      B_DBCC_80P80_SEL_EVM_RPT_EN);
1669 	rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2,
1670 			      B_DBCC_80P80_SEL_EVM_RPT2_EN);
1671 
1672 	rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1673 	rtw8852c_bb_gpio_init(rtwdev);
1674 
1675 	/* read these registers after loading BB parameters */
1676 	gain->offset_base[RTW89_PHY_0] =
1677 		rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK);
1678 	gain->offset_base[RTW89_PHY_1] =
1679 		rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK);
1680 }
1681 
1682 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev,
1683 				    const struct rtw89_chan *chan,
1684 				    enum rtw89_phy_idx phy_idx)
1685 {
1686 	static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0,
1687 					    B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1};
1688 	struct rtw89_hal *hal = &rtwdev->hal;
1689 	bool cck_en = chan->band_type == RTW89_BAND_2G;
1690 	u8 pri_ch_idx = chan->pri_ch_idx;
1691 	u32 mask, reg;
1692 	u8 ntx_path;
1693 
1694 	if (chan->band_type == RTW89_BAND_2G)
1695 		rtw8852c_ctrl_sco_cck(rtwdev, chan->channel,
1696 				      chan->primary_channel,
1697 				      chan->band_width);
1698 
1699 	rtw8852c_ctrl_ch(rtwdev, chan, phy_idx);
1700 	rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1701 	if (cck_en) {
1702 		rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1703 		rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0);
1704 		rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1705 				      B_PD_ARBITER_OFF, 0x0, phy_idx);
1706 	} else {
1707 		rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1708 		rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1);
1709 		rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1710 				      B_PD_ARBITER_OFF, 0x1, phy_idx);
1711 	}
1712 
1713 	rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx);
1714 	rtw8852c_ctrl_btg(rtwdev, chan->band_type == RTW89_BAND_2G);
1715 	rtw8852c_5m_mask(rtwdev, chan, phy_idx);
1716 
1717 	if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1718 	    rtwdev->hal.cv != CHIP_CAV) {
1719 		rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ,
1720 				      B_P80_AT_HIGH_FREQ, 0x0, phy_idx);
1721 		reg = rtw89_mac_reg_by_idx(R_P80_AT_HIGH_FREQ_BB_WRP,
1722 					   phy_idx);
1723 		if (chan->primary_channel > chan->channel) {
1724 			rtw89_phy_write32_mask(rtwdev,
1725 					       R_P80_AT_HIGH_FREQ_RU_ALLOC,
1726 					       ru_alloc_msk[phy_idx], 1);
1727 			rtw89_write32_mask(rtwdev, reg,
1728 					   B_P80_AT_HIGH_FREQ_BB_WRP, 1);
1729 		} else {
1730 			rtw89_phy_write32_mask(rtwdev,
1731 					       R_P80_AT_HIGH_FREQ_RU_ALLOC,
1732 					       ru_alloc_msk[phy_idx], 0);
1733 			rtw89_write32_mask(rtwdev, reg,
1734 					   B_P80_AT_HIGH_FREQ_BB_WRP, 0);
1735 		}
1736 	}
1737 
1738 	if (chan->band_type == RTW89_BAND_6G &&
1739 	    chan->band_width == RTW89_CHANNEL_WIDTH_160)
1740 		rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1741 				      B_CDD_EVM_CHK_EN, 0, phy_idx);
1742 	else
1743 		rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1744 				      B_CDD_EVM_CHK_EN, 1, phy_idx);
1745 
1746 	if (!rtwdev->dbcc_en) {
1747 		mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON;
1748 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1749 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1750 		mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON;
1751 		rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1752 		rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1753 	} else {
1754 		if (phy_idx == RTW89_PHY_0) {
1755 			mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON;
1756 			rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1757 			rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1758 		} else {
1759 			mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON;
1760 			rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1761 			rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1762 		}
1763 	}
1764 
1765 	if (chan->band_type == RTW89_BAND_6G)
1766 		rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN);
1767 	else
1768 		rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN);
1769 
1770 	if (hal->antenna_tx)
1771 		ntx_path = hal->antenna_tx;
1772 	else
1773 		ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB;
1774 
1775 	rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx);
1776 
1777 	rtw8852c_bb_reset_all(rtwdev, phy_idx);
1778 }
1779 
1780 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev,
1781 				 const struct rtw89_chan *chan,
1782 				 enum rtw89_mac_idx mac_idx,
1783 				 enum rtw89_phy_idx phy_idx)
1784 {
1785 	rtw8852c_set_channel_mac(rtwdev, chan, mac_idx);
1786 	rtw8852c_set_channel_bb(rtwdev, chan, phy_idx);
1787 	rtw8852c_set_channel_rf(rtwdev, chan, phy_idx);
1788 }
1789 
1790 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en)
1791 {
1792 	if (en)
1793 		rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1794 	else
1795 		rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1796 }
1797 
1798 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en)
1799 {
1800 	if (en)
1801 		rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1802 				       0x0);
1803 	else
1804 		rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1805 				       0xf);
1806 }
1807 
1808 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1809 				      struct rtw89_channel_help_params *p,
1810 				      const struct rtw89_chan *chan,
1811 				      enum rtw89_mac_idx mac_idx,
1812 				      enum rtw89_phy_idx phy_idx)
1813 {
1814 	if (enter) {
1815 		rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1816 				       RTW89_SCH_TX_SEL_ALL);
1817 		rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1818 		rtw8852c_dfs_en(rtwdev, false);
1819 		rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
1820 		rtw8852c_adc_en(rtwdev, false);
1821 		fsleep(40);
1822 		rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1823 	} else {
1824 		rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1825 		rtw8852c_adc_en(rtwdev, true);
1826 		rtw8852c_dfs_en(rtwdev, true);
1827 		rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
1828 		rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1829 		rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1830 	}
1831 }
1832 
1833 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev)
1834 {
1835 	struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
1836 
1837 	rtwdev->is_tssi_mode[RF_PATH_A] = false;
1838 	rtwdev->is_tssi_mode[RF_PATH_B] = false;
1839 	memset(rfk_mcc, 0, sizeof(*rfk_mcc));
1840 	rtw8852c_lck_init(rtwdev);
1841 
1842 	rtw8852c_rck(rtwdev);
1843 	rtw8852c_dack(rtwdev);
1844 	rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false);
1845 }
1846 
1847 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev)
1848 {
1849 	enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1850 
1851 	rtw8852c_mcc_get_ch_info(rtwdev, phy_idx);
1852 	rtw8852c_rx_dck(rtwdev, phy_idx, false);
1853 	rtw8852c_iqk(rtwdev, phy_idx);
1854 	rtw8852c_tssi(rtwdev, phy_idx);
1855 	rtw8852c_dpk(rtwdev, phy_idx);
1856 	rtw89_fw_h2c_rf_ntfy_mcc(rtwdev);
1857 }
1858 
1859 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev,
1860 				      enum rtw89_phy_idx phy_idx)
1861 {
1862 	rtw8852c_tssi_scan(rtwdev, phy_idx);
1863 }
1864 
1865 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1866 {
1867 	rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1868 }
1869 
1870 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev)
1871 {
1872 	rtw8852c_dpk_track(rtwdev);
1873 	rtw8852c_lck_track(rtwdev);
1874 	rtw8852c_rx_dck_track(rtwdev);
1875 }
1876 
1877 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1878 				     enum rtw89_phy_idx phy_idx, s16 ref)
1879 {
1880 	s8 ofst_int = 0;
1881 	u8 base_cw_0db = 0x27;
1882 	u16 tssi_16dbm_cw = 0x12c;
1883 	s16 pwr_s10_3 = 0;
1884 	s16 rf_pwr_cw = 0;
1885 	u16 bb_pwr_cw = 0;
1886 	u32 pwr_cw = 0;
1887 	u32 tssi_ofst_cw = 0;
1888 
1889 	pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1890 	bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1891 	rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1892 	rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1893 	pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1894 
1895 	tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1896 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1897 		    "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1898 		    tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1899 
1900 	return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
1901 }
1902 
1903 static
1904 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1905 				     s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1906 {
1907 	s8 pw_ofst_2tx;
1908 	s8 val_1t;
1909 	s8 val_2t;
1910 	u32 reg;
1911 	u8 i;
1912 
1913 	if (pw_ofst < -32 || pw_ofst > 31) {
1914 		rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1915 		return;
1916 	}
1917 	val_1t = pw_ofst << 2;
1918 	pw_ofst_2tx = max(pw_ofst - 3, -32);
1919 	val_2t = pw_ofst_2tx << 2;
1920 
1921 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t);
1922 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t);
1923 
1924 	for (i = 0; i < 4; i++) {
1925 		/* 1TX */
1926 		reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
1927 		rtw89_write32_mask(rtwdev, reg,
1928 				   B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i),
1929 				   val_1t);
1930 		/* 2TX */
1931 		reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
1932 		rtw89_write32_mask(rtwdev, reg,
1933 				   B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i),
1934 				   val_2t);
1935 	}
1936 }
1937 
1938 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev,
1939 				   enum rtw89_phy_idx phy_idx)
1940 {
1941 	static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800};
1942 	const u32 mask = 0x7FFFFFF;
1943 	const u8 ofst_ofdm = 0x4;
1944 	const u8 ofst_cck = 0x8;
1945 	s16 ref_ofdm = 0;
1946 	s16 ref_cck = 0;
1947 	u32 val;
1948 	u8 i;
1949 
1950 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1951 
1952 	rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1953 				     GENMASK(27, 10), 0x0);
1954 
1955 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1956 	val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1957 
1958 	for (i = 0; i < RF_PATH_NUM_8852C; i++)
1959 		rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1960 				      phy_idx);
1961 
1962 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1963 	val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1964 
1965 	for (i = 0; i < RF_PATH_NUM_8852C; i++)
1966 		rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1967 				      phy_idx);
1968 }
1969 
1970 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1971 					  u8 tx_shape_idx,
1972 					  enum rtw89_phy_idx phy_idx)
1973 {
1974 #define __DFIR_CFG_MASK 0xffffff
1975 #define __DFIR_CFG_NR 8
1976 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \
1977 	static const u32 _prefix ## _ ## _name[] = {_val}; \
1978 	static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR)
1979 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val)
1980 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val)
1981 
1982 	__DECL_DFIR_PARAM(flat,
1983 			  0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1984 			  0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1985 	__DECL_DFIR_PARAM(sharp,
1986 			  0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1987 			  0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5);
1988 	__DECL_DFIR_PARAM(sharp_14,
1989 			  0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1990 			  0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A);
1991 	__DECL_DFIR_ADDR(filter,
1992 			 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0,
1993 			 0x45C4, 0x45C8);
1994 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1995 	u8 ch = chan->channel;
1996 	const u32 *param;
1997 	int i;
1998 
1999 	if (ch > 14) {
2000 		rtw89_warn(rtwdev,
2001 			   "set tx shape dfir by unknown ch: %d on 2G\n", ch);
2002 		return;
2003 	}
2004 
2005 	if (ch == 14)
2006 		param = param_sharp_14;
2007 	else
2008 		param = tx_shape_idx == 0 ? param_flat : param_sharp;
2009 
2010 	for (i = 0; i < __DFIR_CFG_NR; i++) {
2011 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2012 			    "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i],
2013 			    param[i]);
2014 		rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK,
2015 				      param[i], phy_idx);
2016 	}
2017 
2018 #undef __DECL_DFIR_ADDR
2019 #undef __DECL_DFIR_PARAM
2020 #undef __DECL_DFIR_VAR
2021 #undef __DFIR_CFG_NR
2022 #undef __DFIR_CFG_MASK
2023 }
2024 
2025 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev,
2026 				  const struct rtw89_chan *chan,
2027 				  enum rtw89_phy_idx phy_idx)
2028 {
2029 	u8 band = chan->band_type;
2030 	u8 regd = rtw89_regd_get(rtwdev, band);
2031 	u8 tx_shape_cck = rtw89_8852c_tx_shape[band][RTW89_RS_CCK][regd];
2032 	u8 tx_shape_ofdm = rtw89_8852c_tx_shape[band][RTW89_RS_OFDM][regd];
2033 
2034 	if (band == RTW89_BAND_2G)
2035 		rtw8852c_bb_set_tx_shape_dfir(rtwdev, tx_shape_cck, phy_idx);
2036 
2037 	rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
2038 					     (enum rtw89_mac_idx)phy_idx,
2039 					     tx_shape_ofdm);
2040 }
2041 
2042 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,
2043 			       const struct rtw89_chan *chan,
2044 			       enum rtw89_phy_idx phy_idx)
2045 {
2046 	rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
2047 	rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
2048 	rtw8852c_set_tx_shape(rtwdev, chan, phy_idx);
2049 	rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
2050 	rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
2051 }
2052 
2053 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
2054 				    enum rtw89_phy_idx phy_idx)
2055 {
2056 	rtw8852c_set_txpwr_ref(rtwdev, phy_idx);
2057 }
2058 
2059 static void
2060 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2061 {
2062 	static const struct rtw89_reg2_def ctrl_ini[] = {
2063 		{0xD938, 0x00010100},
2064 		{0xD93C, 0x0500D500},
2065 		{0xD940, 0x00000500},
2066 		{0xD944, 0x00000005},
2067 		{0xD94C, 0x00220000},
2068 		{0xD950, 0x00030000},
2069 	};
2070 	u32 addr;
2071 	int i;
2072 
2073 	for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4)
2074 		rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
2075 
2076 	for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++)
2077 		rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr,
2078 					ctrl_ini[i].data);
2079 
2080 	rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
2081 					     (enum rtw89_mac_idx)phy_idx,
2082 					     RTW89_TSSI_BANDEDGE_FLAT);
2083 }
2084 
2085 static int
2086 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2087 {
2088 	int ret;
2089 
2090 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
2091 	if (ret)
2092 		return ret;
2093 
2094 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
2095 	if (ret)
2096 		return ret;
2097 
2098 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
2099 	if (ret)
2100 		return ret;
2101 
2102 	rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
2103 							      RTW89_MAC_1 :
2104 							      RTW89_MAC_0);
2105 	rtw8852c_init_tssi_ctrl(rtwdev, phy_idx);
2106 
2107 	return 0;
2108 }
2109 
2110 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path)
2111 {
2112 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
2113 	u8 band = chan->band_type;
2114 	u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
2115 	u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
2116 
2117 	if (rtwdev->dbcc_en) {
2118 		rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1);
2119 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2,
2120 				      RTW89_PHY_1);
2121 
2122 		rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0,
2123 				       1);
2124 		rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1,
2125 				       1);
2126 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2,
2127 				      RTW89_PHY_1);
2128 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2,
2129 				      RTW89_PHY_1);
2130 
2131 		rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2132 				       B_RXHT_MCS_LIMIT, 0);
2133 		rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2134 				       B_RXVHT_MCS_LIMIT, 0);
2135 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2136 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2137 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2138 
2139 		rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT,
2140 				      B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1);
2141 		rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT,
2142 				      B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1);
2143 		rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1,
2144 				      RTW89_PHY_1);
2145 		rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0,
2146 				      RTW89_PHY_1);
2147 		rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0,
2148 				      RTW89_PHY_1);
2149 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
2150 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
2151 		rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
2152 		rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
2153 	} else {
2154 		if (rx_path == RF_PATH_A) {
2155 			rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2156 					       B_ANT_RX_SEG0, 1);
2157 			rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2158 					       B_ANT_RX_1RCCA_SEG0, 1);
2159 			rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2160 					       B_ANT_RX_1RCCA_SEG1, 1);
2161 			rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2162 					       B_RXHT_MCS_LIMIT, 0);
2163 			rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2164 					       B_RXVHT_MCS_LIMIT, 0);
2165 			rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2166 					       0);
2167 			rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2168 					       0);
2169 			rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2170 					       rst_mask0, 1);
2171 			rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2172 					       rst_mask0, 3);
2173 		} else if (rx_path == RF_PATH_B) {
2174 			rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2175 					       B_ANT_RX_SEG0, 2);
2176 			rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2177 					       B_ANT_RX_1RCCA_SEG0, 2);
2178 			rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2179 					       B_ANT_RX_1RCCA_SEG1, 2);
2180 			rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2181 					       B_RXHT_MCS_LIMIT, 0);
2182 			rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2183 					       B_RXVHT_MCS_LIMIT, 0);
2184 			rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2185 					       0);
2186 			rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2187 					       0);
2188 			rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2189 					       rst_mask1, 1);
2190 			rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2191 					       rst_mask1, 3);
2192 		} else {
2193 			rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2194 					       B_ANT_RX_SEG0, 3);
2195 			rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2196 					       B_ANT_RX_1RCCA_SEG0, 3);
2197 			rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2198 					       B_ANT_RX_1RCCA_SEG1, 3);
2199 			rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2200 					       B_RXHT_MCS_LIMIT, 1);
2201 			rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2202 					       B_RXVHT_MCS_LIMIT, 1);
2203 			rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2204 					       1);
2205 			rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2206 					       1);
2207 			rtw8852c_ctrl_btg(rtwdev, band == RTW89_BAND_2G);
2208 			rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2209 					       rst_mask0, 1);
2210 			rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2211 					       rst_mask0, 3);
2212 			rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2213 					       rst_mask1, 1);
2214 			rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2215 					       rst_mask1, 3);
2216 		}
2217 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2218 	}
2219 }
2220 
2221 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path,
2222 				       enum rtw89_mac_idx mac_idx)
2223 {
2224 	struct rtw89_reg2_def path_com[] = {
2225 		{R_AX_PATH_COM0, AX_PATH_COM0_DFVAL},
2226 		{R_AX_PATH_COM1, AX_PATH_COM1_DFVAL},
2227 		{R_AX_PATH_COM2, AX_PATH_COM2_DFVAL},
2228 		{R_AX_PATH_COM3, AX_PATH_COM3_DFVAL},
2229 		{R_AX_PATH_COM4, AX_PATH_COM4_DFVAL},
2230 		{R_AX_PATH_COM5, AX_PATH_COM5_DFVAL},
2231 		{R_AX_PATH_COM6, AX_PATH_COM6_DFVAL},
2232 		{R_AX_PATH_COM7, AX_PATH_COM7_DFVAL},
2233 		{R_AX_PATH_COM8, AX_PATH_COM8_DFVAL},
2234 		{R_AX_PATH_COM9, AX_PATH_COM9_DFVAL},
2235 		{R_AX_PATH_COM10, AX_PATH_COM10_DFVAL},
2236 		{R_AX_PATH_COM11, AX_PATH_COM11_DFVAL},
2237 	};
2238 	u32 addr;
2239 	u32 reg;
2240 	u8 cr_size = ARRAY_SIZE(path_com);
2241 	u8 i = 0;
2242 
2243 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0);
2244 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1);
2245 
2246 	for (addr = R_AX_MACID_ANT_TABLE;
2247 	     addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) {
2248 		reg = rtw89_mac_reg_by_idx(addr, mac_idx);
2249 		rtw89_write32(rtwdev, reg, 0);
2250 	}
2251 
2252 	if (tx_path == RF_A) {
2253 		path_com[0].data = AX_PATH_COM0_PATHA;
2254 		path_com[1].data = AX_PATH_COM1_PATHA;
2255 		path_com[2].data = AX_PATH_COM2_PATHA;
2256 		path_com[7].data = AX_PATH_COM7_PATHA;
2257 		path_com[8].data = AX_PATH_COM8_PATHA;
2258 	} else if (tx_path == RF_B) {
2259 		path_com[0].data = AX_PATH_COM0_PATHB;
2260 		path_com[1].data = AX_PATH_COM1_PATHB;
2261 		path_com[2].data = AX_PATH_COM2_PATHB;
2262 		path_com[7].data = AX_PATH_COM7_PATHB;
2263 		path_com[8].data = AX_PATH_COM8_PATHB;
2264 	} else if (tx_path == RF_AB) {
2265 		path_com[0].data = AX_PATH_COM0_PATHAB;
2266 		path_com[1].data = AX_PATH_COM1_PATHAB;
2267 		path_com[2].data = AX_PATH_COM2_PATHAB;
2268 		path_com[7].data = AX_PATH_COM7_PATHAB;
2269 		path_com[8].data = AX_PATH_COM8_PATHAB;
2270 	} else {
2271 		rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path);
2272 		return;
2273 	}
2274 
2275 	for (i = 0; i < cr_size; i++) {
2276 		rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n",
2277 			    path_com[i].addr, path_com[i].data);
2278 		reg = rtw89_mac_reg_by_idx(path_com[i].addr, mac_idx);
2279 		rtw89_write32(rtwdev, reg, path_com[i].data);
2280 	}
2281 }
2282 
2283 static void rtw8852c_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
2284 {
2285 	if (bt_en) {
2286 		rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2287 				       B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3);
2288 		rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2289 				       B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3);
2290 		rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2291 				       B_PATH0_RXBB_MSK_V1, 0xf);
2292 		rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2293 				       B_PATH1_RXBB_MSK_V1, 0xf);
2294 		rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2295 				       B_PATH0_G_LNA6_OP1DB_V1, 0x80);
2296 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2297 				       B_PATH1_G_LNA6_OP1DB_V1, 0x80);
2298 		rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2299 				       B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
2300 		rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2301 				       B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80);
2302 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2303 				       B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80);
2304 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2305 				       B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80);
2306 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2307 				       B_PATH0_BT_BACKOFF_V1, 0x780D1E);
2308 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2309 				       B_PATH1_BT_BACKOFF_V1, 0x780D1E);
2310 		rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2311 				       B_P0_BACKOFF_IBADC_V1, 0x34);
2312 		rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2313 				       B_P1_BACKOFF_IBADC_V1, 0x34);
2314 	} else {
2315 		rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2316 				       B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0);
2317 		rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2318 				       B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0);
2319 		rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2320 				       B_PATH0_RXBB_MSK_V1, 0x60);
2321 		rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2322 				       B_PATH1_RXBB_MSK_V1, 0x60);
2323 		rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2324 				       B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
2325 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2326 				       B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
2327 		rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2328 				       B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2329 		rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2330 				       B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a);
2331 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2332 				       B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2333 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2334 				       B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a);
2335 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2336 				       B_PATH0_BT_BACKOFF_V1, 0x79E99E);
2337 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2338 				       B_PATH1_BT_BACKOFF_V1, 0x79E99E);
2339 		rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2340 				       B_P0_BACKOFF_IBADC_V1, 0x26);
2341 		rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2342 				       B_P1_BACKOFF_IBADC_V1, 0x26);
2343 	}
2344 }
2345 
2346 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2347 {
2348 	struct rtw89_hal *hal = &rtwdev->hal;
2349 
2350 	rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB);
2351 
2352 	if (hal->rx_nss == 1) {
2353 		rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
2354 		rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
2355 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2356 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2357 	} else {
2358 		rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
2359 		rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
2360 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
2361 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
2362 	}
2363 }
2364 
2365 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2366 {
2367 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2368 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
2369 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2370 
2371 	fsleep(200);
2372 
2373 	return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
2374 }
2375 
2376 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev)
2377 {
2378 	struct rtw89_btc *btc = &rtwdev->btc;
2379 	struct rtw89_btc_module *module = &btc->mdinfo;
2380 
2381 	module->rfe_type = rtwdev->efuse.rfe_type;
2382 	module->cv = rtwdev->hal.cv;
2383 	module->bt_solo = 0;
2384 	module->switch_type = BTC_SWITCH_INTERNAL;
2385 
2386 	if (module->rfe_type > 0)
2387 		module->ant.num = (module->rfe_type % 2 ? 2 : 3);
2388 	else
2389 		module->ant.num = 2;
2390 
2391 	module->ant.diversity = 0;
2392 	module->ant.isolation = 10;
2393 
2394 	if (module->ant.num == 3) {
2395 		module->ant.type = BTC_ANT_DEDICATED;
2396 		module->bt_pos = BTC_BT_ALONE;
2397 	} else {
2398 		module->ant.type = BTC_ANT_SHARED;
2399 		module->bt_pos = BTC_BT_BTG;
2400 	}
2401 }
2402 
2403 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
2404 {
2405 	if (btg) {
2406 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2407 				       B_PATH0_BT_SHARE_V1, 0x1);
2408 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2409 				       B_PATH0_BTG_PATH_V1, 0x0);
2410 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2411 				       B_PATH1_G_LNA6_OP1DB_V1, 0x20);
2412 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2413 				       B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
2414 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2415 				       B_PATH1_BT_SHARE_V1, 0x1);
2416 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2417 				       B_PATH1_BTG_PATH_V1, 0x1);
2418 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
2419 		rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1);
2420 		rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2);
2421 		rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2422 				       B_BT_DYN_DC_EST_EN_MSK, 0x1);
2423 		rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2424 				       0x1);
2425 	} else {
2426 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2427 				       B_PATH0_BT_SHARE_V1, 0x0);
2428 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2429 				       B_PATH0_BTG_PATH_V1, 0x0);
2430 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2431 				       B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
2432 		rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2433 				       B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2434 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2435 				       B_PATH1_BT_SHARE_V1, 0x0);
2436 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2437 				       B_PATH1_BTG_PATH_V1, 0x0);
2438 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
2439 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
2440 		rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0);
2441 		rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0);
2442 		rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2443 				       B_BT_DYN_DC_EST_EN_MSK, 0x0);
2444 		rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2445 				       0x0);
2446 	}
2447 }
2448 
2449 static
2450 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2451 {
2452 	rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
2453 	rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2454 	rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2455 	rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
2456 }
2457 
2458 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev)
2459 {
2460 	struct rtw89_btc *btc = &rtwdev->btc;
2461 	struct rtw89_btc_module *module = &btc->mdinfo;
2462 	const struct rtw89_chip_info *chip = rtwdev->chip;
2463 	const struct rtw89_mac_ax_coex coex_params = {
2464 		.pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
2465 		.direction = RTW89_MAC_AX_COEX_INNER,
2466 	};
2467 
2468 	/* PTA init  */
2469 	rtw89_mac_coex_init_v1(rtwdev, &coex_params);
2470 
2471 	/* set WL Tx response = Hi-Pri */
2472 	chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2473 	chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2474 
2475 	/* set rf gnt debug off */
2476 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
2477 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
2478 
2479 	/* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
2480 	if (module->ant.type == BTC_ANT_SHARED) {
2481 		rtw8852c_set_trx_mask(rtwdev,
2482 				      RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
2483 		rtw8852c_set_trx_mask(rtwdev,
2484 				      RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
2485 		/* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
2486 		rtw8852c_set_trx_mask(rtwdev,
2487 				      RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
2488 	} else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
2489 		rtw8852c_set_trx_mask(rtwdev,
2490 				      RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
2491 		rtw8852c_set_trx_mask(rtwdev,
2492 				      RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
2493 	}
2494 
2495 	/* set PTA break table */
2496 	rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM);
2497 
2498 	 /* enable BT counter 0xda10[1:0] = 2b'11 */
2499 	rtw89_write32_set(rtwdev,
2500 			  R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN |
2501 			  B_AX_BT_CNT_RST_V1);
2502 	btc->cx.wl.status.map.init_ok = true;
2503 }
2504 
2505 static
2506 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2507 {
2508 	u32 bitmap = 0;
2509 	u32 reg = 0;
2510 
2511 	switch (map) {
2512 	case BTC_PRI_MASK_TX_RESP:
2513 		reg = R_BTC_COEX_WL_REQ;
2514 		bitmap = B_BTC_RSP_ACK_HI;
2515 		break;
2516 	case BTC_PRI_MASK_BEACON:
2517 		reg = R_BTC_COEX_WL_REQ;
2518 		bitmap = B_BTC_TX_BCN_HI;
2519 		break;
2520 	default:
2521 		return;
2522 	}
2523 
2524 	if (state)
2525 		rtw89_write32_set(rtwdev, reg, bitmap);
2526 	else
2527 		rtw89_write32_clr(rtwdev, reg, bitmap);
2528 }
2529 
2530 union rtw8852c_btc_wl_txpwr_ctrl {
2531 	u32 txpwr_val;
2532 	struct {
2533 		union {
2534 			u16 ctrl_all_time;
2535 			struct {
2536 				s16 data:9;
2537 				u16 rsvd:6;
2538 				u16 flag:1;
2539 			} all_time;
2540 		};
2541 		union {
2542 			u16 ctrl_gnt_bt;
2543 			struct {
2544 				s16 data:9;
2545 				u16 rsvd:7;
2546 			} gnt_bt;
2547 		};
2548 	};
2549 } __packed;
2550 
2551 static void
2552 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2553 {
2554 	union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2555 	s32 val;
2556 
2557 #define __write_ctrl(_reg, _msk, _val, _en, _cond)		\
2558 do {								\
2559 	u32 _wrt = FIELD_PREP(_msk, _val);			\
2560 	BUILD_BUG_ON((_msk & _en) != 0);			\
2561 	if (_cond)						\
2562 		_wrt |= _en;					\
2563 	else							\
2564 		_wrt &= ~_en;					\
2565 	rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg,	\
2566 				     _msk | _en, _wrt);		\
2567 } while (0)
2568 
2569 	switch (arg.ctrl_all_time) {
2570 	case 0xffff:
2571 		val = 0;
2572 		break;
2573 	default:
2574 		val = arg.all_time.data;
2575 		break;
2576 	}
2577 
2578 	__write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2579 		     val, B_AX_FORCE_PWR_BY_RATE_EN,
2580 		     arg.ctrl_all_time != 0xffff);
2581 
2582 	switch (arg.ctrl_gnt_bt) {
2583 	case 0xffff:
2584 		val = 0;
2585 		break;
2586 	default:
2587 		val = arg.gnt_bt.data;
2588 		break;
2589 	}
2590 
2591 	__write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2592 		     B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2593 
2594 #undef __write_ctrl
2595 }
2596 
2597 static
2598 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2599 {
2600 	return clamp_t(s8, val, -100, 0) + 100;
2601 }
2602 
2603 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = {
2604 	{255, 0, 0, 7}, /* 0 -> original */
2605 	{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2606 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2607 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2608 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2609 	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
2610 	{6, 1, 0, 7},
2611 	{13, 1, 0, 7},
2612 	{13, 1, 0, 7}
2613 };
2614 
2615 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = {
2616 	{255, 0, 0, 7}, /* 0 -> original */
2617 	{255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2618 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2619 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2620 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2621 	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
2622 	{255, 1, 0, 7},
2623 	{255, 1, 0, 7},
2624 	{255, 1, 0, 7}
2625 };
2626 
2627 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
2628 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
2629 
2630 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = {
2631 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00),
2632 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04),
2633 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
2634 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
2635 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
2636 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38),
2637 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44),
2638 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48),
2639 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
2640 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
2641 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
2642 	RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2643 };
2644 
2645 static
2646 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2647 {
2648 	/* Feature move to firmware */
2649 }
2650 
2651 static
2652 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2653 {
2654 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2655 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2656 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620);
2657 
2658 	/* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2659 	if (state)
2660 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2661 			       RFREG_MASK, 0x179c);
2662 	else
2663 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2664 			       RFREG_MASK, 0x208);
2665 
2666 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2667 }
2668 
2669 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
2670 {
2671 	/* level=0 Default:    TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2672 	 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2673 	 * To improve BT ACI in co-rx
2674 	 */
2675 
2676 	switch (level) {
2677 	case 0: /* default */
2678 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2679 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
2680 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2681 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2682 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2683 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2684 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2685 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2686 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2687 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2688 		break;
2689 	case 1: /* Fix LNA2=5  */
2690 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2691 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
2692 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2693 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2694 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2695 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2696 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2697 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2698 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2699 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2700 		break;
2701 	}
2702 }
2703 
2704 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2705 {
2706 	switch (level) {
2707 	case 0: /* original */
2708 		rtw8852c_bb_ctrl_btc_preagc(rtwdev, false);
2709 		rtw8852c_set_wl_lna2(rtwdev, 0);
2710 		break;
2711 	case 1: /* for FDD free-run */
2712 		rtw8852c_bb_ctrl_btc_preagc(rtwdev, true);
2713 		rtw8852c_set_wl_lna2(rtwdev, 0);
2714 		break;
2715 	case 2: /* for BTG Co-Rx*/
2716 		rtw8852c_bb_ctrl_btc_preagc(rtwdev, false);
2717 		rtw8852c_set_wl_lna2(rtwdev, 1);
2718 		break;
2719 	}
2720 }
2721 
2722 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2723 					 struct rtw89_rx_phy_ppdu *phy_ppdu,
2724 					 struct ieee80211_rx_status *status)
2725 {
2726 	u8 chan_idx = phy_ppdu->chan_idx;
2727 	enum nl80211_band band;
2728 	u8 ch;
2729 
2730 	if (chan_idx == 0)
2731 		return;
2732 
2733 	rtw8852c_decode_chan_idx(rtwdev, chan_idx, &ch, &band);
2734 	status->freq = ieee80211_channel_to_frequency(ch, band);
2735 	status->band = band;
2736 }
2737 
2738 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev,
2739 				struct rtw89_rx_phy_ppdu *phy_ppdu,
2740 				struct ieee80211_rx_status *status)
2741 {
2742 	u8 path;
2743 	u8 *rx_power = phy_ppdu->rssi;
2744 
2745 	status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
2746 	for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2747 		status->chains |= BIT(path);
2748 		status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2749 	}
2750 	if (phy_ppdu->valid)
2751 		rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2752 }
2753 
2754 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2755 {
2756 	int ret;
2757 
2758 	rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2759 			 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2760 
2761 	rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2762 	rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2763 	rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2764 
2765 	rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1);
2766 	rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1);
2767 
2768 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK);
2769 	if (ret)
2770 		return ret;
2771 
2772 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK);
2773 	if (ret)
2774 		return ret;
2775 
2776 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK);
2777 	if (ret)
2778 		return ret;
2779 
2780 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK);
2781 	if (ret)
2782 		return ret;
2783 
2784 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK);
2785 	if (ret)
2786 		return ret;
2787 
2788 	return 0;
2789 }
2790 
2791 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2792 {
2793 	rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2794 			 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2795 
2796 	return 0;
2797 }
2798 
2799 #ifdef CONFIG_PM
2800 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = {
2801 	.flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2802 	.n_patterns = RTW89_MAX_PATTERN_NUM,
2803 	.pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2804 	.pattern_min_len = 1,
2805 };
2806 #endif
2807 
2808 static const struct rtw89_chip_ops rtw8852c_chip_ops = {
2809 	.enable_bb_rf		= rtw8852c_mac_enable_bb_rf,
2810 	.disable_bb_rf		= rtw8852c_mac_disable_bb_rf,
2811 	.bb_reset		= rtw8852c_bb_reset,
2812 	.bb_sethw		= rtw8852c_bb_sethw,
2813 	.read_rf		= rtw89_phy_read_rf_v1,
2814 	.write_rf		= rtw89_phy_write_rf_v1,
2815 	.set_channel		= rtw8852c_set_channel,
2816 	.set_channel_help	= rtw8852c_set_channel_help,
2817 	.read_efuse		= rtw8852c_read_efuse,
2818 	.read_phycap		= rtw8852c_read_phycap,
2819 	.fem_setup		= NULL,
2820 	.rfk_init		= rtw8852c_rfk_init,
2821 	.rfk_channel		= rtw8852c_rfk_channel,
2822 	.rfk_band_changed	= rtw8852c_rfk_band_changed,
2823 	.rfk_scan		= rtw8852c_rfk_scan,
2824 	.rfk_track		= rtw8852c_rfk_track,
2825 	.power_trim		= rtw8852c_power_trim,
2826 	.set_txpwr		= rtw8852c_set_txpwr,
2827 	.set_txpwr_ctrl		= rtw8852c_set_txpwr_ctrl,
2828 	.init_txpwr_unit	= rtw8852c_init_txpwr_unit,
2829 	.get_thermal		= rtw8852c_get_thermal,
2830 	.ctrl_btg		= rtw8852c_ctrl_btg,
2831 	.query_ppdu		= rtw8852c_query_ppdu,
2832 	.bb_ctrl_btc_preagc	= rtw8852c_bb_ctrl_btc_preagc,
2833 	.cfg_txrx_path		= rtw8852c_bb_cfg_txrx_path,
2834 	.set_txpwr_ul_tb_offset	= rtw8852c_set_txpwr_ul_tb_offset,
2835 	.pwr_on_func		= rtw8852c_pwr_on_func,
2836 	.pwr_off_func		= rtw8852c_pwr_off_func,
2837 	.fill_txdesc		= rtw89_core_fill_txdesc_v1,
2838 	.fill_txdesc_fwcmd	= rtw89_core_fill_txdesc_fwcmd_v1,
2839 	.cfg_ctrl_path		= rtw89_mac_cfg_ctrl_path_v1,
2840 	.mac_cfg_gnt		= rtw89_mac_cfg_gnt_v1,
2841 	.stop_sch_tx		= rtw89_mac_stop_sch_tx_v1,
2842 	.resume_sch_tx		= rtw89_mac_resume_sch_tx_v1,
2843 	.h2c_dctl_sec_cam	= rtw89_fw_h2c_dctl_sec_cam_v1,
2844 
2845 	.btc_set_rfe		= rtw8852c_btc_set_rfe,
2846 	.btc_init_cfg		= rtw8852c_btc_init_cfg,
2847 	.btc_set_wl_pri		= rtw8852c_btc_set_wl_pri,
2848 	.btc_set_wl_txpwr_ctrl	= rtw8852c_btc_set_wl_txpwr_ctrl,
2849 	.btc_get_bt_rssi	= rtw8852c_btc_get_bt_rssi,
2850 	.btc_update_bt_cnt	= rtw8852c_btc_update_bt_cnt,
2851 	.btc_wl_s1_standby	= rtw8852c_btc_wl_s1_standby,
2852 	.btc_set_wl_rx_gain	= rtw8852c_btc_set_wl_rx_gain,
2853 	.btc_set_policy		= rtw89_btc_set_policy_v1,
2854 };
2855 
2856 const struct rtw89_chip_info rtw8852c_chip_info = {
2857 	.chip_id		= RTL8852C,
2858 	.ops			= &rtw8852c_chip_ops,
2859 	.fw_name		= "rtw89/rtw8852c_fw.bin",
2860 	.fifo_size		= 458752,
2861 	.dle_scc_rsvd_size	= 0,
2862 	.max_amsdu_limit	= 8000,
2863 	.dis_2g_40m_ul_ofdma	= false,
2864 	.rsvd_ple_ofst		= 0x6f800,
2865 	.hfc_param_ini		= rtw8852c_hfc_param_ini_pcie,
2866 	.dle_mem		= rtw8852c_dle_mem_pcie,
2867 	.wde_qempty_acq_num     = 16,
2868 	.wde_qempty_mgq_sel     = 16,
2869 	.rf_base_addr		= {0xe000, 0xf000},
2870 	.pwr_on_seq		= NULL,
2871 	.pwr_off_seq		= NULL,
2872 	.bb_table		= &rtw89_8852c_phy_bb_table,
2873 	.bb_gain_table		= &rtw89_8852c_phy_bb_gain_table,
2874 	.rf_table		= {&rtw89_8852c_phy_radiob_table,
2875 				   &rtw89_8852c_phy_radioa_table,},
2876 	.nctl_table		= &rtw89_8852c_phy_nctl_table,
2877 	.byr_table		= &rtw89_8852c_byr_table,
2878 	.txpwr_lmt_2g		= &rtw89_8852c_txpwr_lmt_2g,
2879 	.txpwr_lmt_5g		= &rtw89_8852c_txpwr_lmt_5g,
2880 	.txpwr_lmt_6g		= &rtw89_8852c_txpwr_lmt_6g,
2881 	.txpwr_lmt_ru_2g	= &rtw89_8852c_txpwr_lmt_ru_2g,
2882 	.txpwr_lmt_ru_5g	= &rtw89_8852c_txpwr_lmt_ru_5g,
2883 	.txpwr_lmt_ru_6g	= &rtw89_8852c_txpwr_lmt_ru_6g,
2884 	.txpwr_factor_rf	= 2,
2885 	.txpwr_factor_mac	= 1,
2886 	.dig_table		= NULL,
2887 	.dig_regs		= &rtw8852c_dig_regs,
2888 	.tssi_dbw_table		= &rtw89_8852c_tssi_dbw_table,
2889 	.support_chanctx_num	= 1,
2890 	.support_bands		= BIT(NL80211_BAND_2GHZ) |
2891 				  BIT(NL80211_BAND_5GHZ) |
2892 				  BIT(NL80211_BAND_6GHZ),
2893 	.support_bw160		= true,
2894 	.support_ul_tb_ctrl     = false,
2895 	.hw_sec_hdr		= true,
2896 	.rf_path_num		= 2,
2897 	.tx_nss			= 2,
2898 	.rx_nss			= 2,
2899 	.acam_num		= 128,
2900 	.bcam_num		= 20,
2901 	.scam_num		= 128,
2902 	.bacam_num		= 8,
2903 	.bacam_dynamic_num	= 8,
2904 	.bacam_v1		= true,
2905 	.sec_ctrl_efuse_size	= 4,
2906 	.physical_efuse_size	= 1216,
2907 	.logical_efuse_size	= 2048,
2908 	.limit_efuse_size	= 1280,
2909 	.dav_phy_efuse_size	= 96,
2910 	.dav_log_efuse_size	= 16,
2911 	.phycap_addr		= 0x590,
2912 	.phycap_size		= 0x60,
2913 	.para_ver		= 0x1,
2914 	.wlcx_desired		= 0x06000000,
2915 	.btcx_desired		= 0x7,
2916 	.scbd			= 0x1,
2917 	.mailbox		= 0x1,
2918 	.btc_fwinfo_buf		= 1280,
2919 
2920 	.fcxbtcrpt_ver		= 4,
2921 	.fcxtdma_ver		= 3,
2922 	.fcxslots_ver		= 1,
2923 	.fcxcysta_ver		= 3,
2924 	.fcxstep_ver		= 3,
2925 	.fcxnullsta_ver		= 2,
2926 	.fcxmreg_ver		= 1,
2927 	.fcxgpiodbg_ver		= 1,
2928 	.fcxbtver_ver		= 1,
2929 	.fcxbtscan_ver		= 1,
2930 	.fcxbtafh_ver		= 1,
2931 	.fcxbtdevinfo_ver	= 1,
2932 
2933 	.afh_guard_ch		= 6,
2934 	.wl_rssi_thres		= rtw89_btc_8852c_wl_rssi_thres,
2935 	.bt_rssi_thres		= rtw89_btc_8852c_bt_rssi_thres,
2936 	.rssi_tol		= 2,
2937 	.mon_reg_num		= ARRAY_SIZE(rtw89_btc_8852c_mon_reg),
2938 	.mon_reg		= rtw89_btc_8852c_mon_reg,
2939 	.rf_para_ulink_num	= ARRAY_SIZE(rtw89_btc_8852c_rf_ul),
2940 	.rf_para_ulink		= rtw89_btc_8852c_rf_ul,
2941 	.rf_para_dlink_num	= ARRAY_SIZE(rtw89_btc_8852c_rf_dl),
2942 	.rf_para_dlink		= rtw89_btc_8852c_rf_dl,
2943 	.ps_mode_supported	= BIT(RTW89_PS_MODE_RFOFF) |
2944 				  BIT(RTW89_PS_MODE_CLK_GATED) |
2945 				  BIT(RTW89_PS_MODE_PWR_GATED),
2946 	.low_power_hci_modes	= BIT(RTW89_PS_MODE_CLK_GATED) |
2947 				  BIT(RTW89_PS_MODE_PWR_GATED),
2948 	.h2c_cctl_func_id	= H2C_FUNC_MAC_CCTLINFO_UD_V1,
2949 	.hci_func_en_addr	= R_AX_HCI_FUNC_EN_V1,
2950 	.h2c_desc_size		= sizeof(struct rtw89_rxdesc_short),
2951 	.txwd_body_size		= sizeof(struct rtw89_txwd_body_v1),
2952 	.h2c_ctrl_reg		= R_AX_H2CREG_CTRL_V1,
2953 	.h2c_regs		= rtw8852c_h2c_regs,
2954 	.c2h_ctrl_reg		= R_AX_C2HREG_CTRL_V1,
2955 	.c2h_regs		= rtw8852c_c2h_regs,
2956 	.page_regs		= &rtw8852c_page_regs,
2957 	.cfo_src_fd		= false,
2958 	.dcfo_comp		= &rtw8852c_dcfo_comp,
2959 	.dcfo_comp_sft		= 5,
2960 	.imr_info		= &rtw8852c_imr_info,
2961 	.rrsr_cfgs		= &rtw8852c_rrsr_cfgs,
2962 	.dma_ch_mask		= 0,
2963 #ifdef CONFIG_PM
2964 	.wowlan_stub		= &rtw_wowlan_stub_8852c,
2965 #endif
2966 };
2967 EXPORT_SYMBOL(rtw8852c_chip_info);
2968 
2969 MODULE_FIRMWARE("rtw89/rtw8852c_fw.bin");
2970 MODULE_AUTHOR("Realtek Corporation");
2971 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver");
2972 MODULE_LICENSE("Dual BSD/GPL");
2973