1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "reg.h" 11 #include "rtw8852c.h" 12 #include "rtw8852c_rfk.h" 13 #include "rtw8852c_table.h" 14 #include "util.h" 15 16 #define RTW8852C_FW_FORMAT_MAX 0 17 #define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw" 18 #define RTW8852C_MODULE_FIRMWARE \ 19 RTW8852C_FW_BASENAME ".bin" 20 21 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 22 {13, 1614, grp_0}, /* ACH 0 */ 23 {13, 1614, grp_0}, /* ACH 1 */ 24 {13, 1614, grp_0}, /* ACH 2 */ 25 {13, 1614, grp_0}, /* ACH 3 */ 26 {13, 1614, grp_1}, /* ACH 4 */ 27 {13, 1614, grp_1}, /* ACH 5 */ 28 {13, 1614, grp_1}, /* ACH 6 */ 29 {13, 1614, grp_1}, /* ACH 7 */ 30 {13, 1614, grp_0}, /* B0MGQ */ 31 {13, 1614, grp_0}, /* B0HIQ */ 32 {13, 1614, grp_1}, /* B1MGQ */ 33 {13, 1614, grp_1}, /* B1HIQ */ 34 {40, 0, 0} /* FWCMDQ */ 35 }; 36 37 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 38 1614, /* Group 0 */ 39 1614, /* Group 1 */ 40 3228, /* Public Max */ 41 0 /* WP threshold */ 42 }; 43 44 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 45 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 46 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 47 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 48 RTW89_HCIFC_POH}, 49 [RTW89_QTA_INVALID] = {NULL}, 50 }; 51 52 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 53 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 54 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 55 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 56 &rtw89_mac_size.ple_qt47}, 57 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 58 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 59 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 60 &rtw89_mac_size.ple_qt45}, 61 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 62 NULL}, 63 }; 64 65 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 66 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 67 R_AX_H2CREG_DATA3_V1 68 }; 69 70 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 71 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 72 R_AX_C2HREG_DATA3_V1 73 }; 74 75 static const struct rtw89_page_regs rtw8852c_page_regs = { 76 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 77 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 78 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 79 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 80 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 81 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 82 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 83 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 84 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 85 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 86 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 87 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 88 }; 89 90 static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 91 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 92 }; 93 94 static const struct rtw89_imr_info rtw8852c_imr_info = { 95 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 96 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 97 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 98 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 99 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 100 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 101 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 102 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 103 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 104 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 105 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 106 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 107 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 108 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 109 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 110 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 111 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 112 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 113 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 114 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 115 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 116 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 117 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 118 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 119 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 120 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 121 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 122 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 123 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 124 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 125 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 126 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 127 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 128 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 129 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 130 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 131 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 132 .rmac_imr_reg = R_AX_RX_ERR_IMR, 133 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 134 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 135 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 136 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 137 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 138 }; 139 140 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 141 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 142 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 143 }; 144 145 static const struct rtw89_dig_regs rtw8852c_dig_regs = { 146 .seg0_pd_reg = R_SEG0R_PD, 147 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 148 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 149 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 150 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 151 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 152 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 153 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 154 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 155 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 156 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 157 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 158 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 159 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 160 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 161 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 162 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 163 }; 164 165 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg); 166 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 167 enum rtw89_mac_idx mac_idx); 168 169 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 170 { 171 u32 val32; 172 u32 ret; 173 174 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 175 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 176 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 177 178 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 179 B_AX_AFSM_PCIE_SUS_EN); 180 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 181 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 182 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 183 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 184 185 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 186 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 187 if (ret) 188 return ret; 189 190 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 191 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 192 193 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 194 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 195 if (ret) 196 return ret; 197 198 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 199 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 200 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 201 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 202 203 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 204 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 205 206 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 207 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 208 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 209 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 210 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 211 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 212 B_AX_R_SYM_WLCMAC1_PC_EN); 213 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 214 215 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 216 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 217 if (ret) 218 return ret; 219 220 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 221 222 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 223 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 224 if (ret) 225 return ret; 226 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 227 XTAL_SI_OFF_WEI); 228 if (ret) 229 return ret; 230 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 231 XTAL_SI_OFF_EI); 232 if (ret) 233 return ret; 234 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 235 if (ret) 236 return ret; 237 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 238 XTAL_SI_PON_WEI); 239 if (ret) 240 return ret; 241 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 242 XTAL_SI_PON_EI); 243 if (ret) 244 return ret; 245 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 246 if (ret) 247 return ret; 248 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 249 if (ret) 250 return ret; 251 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 252 if (ret) 253 return ret; 254 255 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 256 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 257 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 258 259 fsleep(1000); 260 261 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 262 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 263 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 264 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 265 B_AX_LED1_PULL_LOW_EN); 266 267 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 268 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 269 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 270 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 271 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 272 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 273 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 274 275 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 276 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 277 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 278 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 279 B_AX_TMAC_EN | B_AX_RMAC_EN); 280 281 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 282 PINMUX_EESK_FUNC_SEL_BT_LOG); 283 284 return 0; 285 } 286 287 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 288 { 289 u32 val32; 290 u32 ret; 291 292 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 293 XTAL_SI_RFC2RF); 294 if (ret) 295 return ret; 296 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 297 if (ret) 298 return ret; 299 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 300 if (ret) 301 return ret; 302 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 303 if (ret) 304 return ret; 305 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 306 if (ret) 307 return ret; 308 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 309 XTAL_SI_SRAM2RFC); 310 if (ret) 311 return ret; 312 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 313 if (ret) 314 return ret; 315 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 316 if (ret) 317 return ret; 318 319 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 320 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 321 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 322 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 323 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 324 325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 326 if (ret) 327 return ret; 328 329 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 330 331 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 332 if (ret) 333 return ret; 334 335 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 336 337 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 338 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 339 if (ret) 340 return ret; 341 342 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0); 343 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 344 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 345 346 return 0; 347 } 348 349 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 350 struct rtw8852c_efuse *map) 351 { 352 ether_addr_copy(efuse->addr, map->e.mac_addr); 353 efuse->rfe_type = map->rfe_type; 354 efuse->xtal_cap = map->xtal_k; 355 } 356 357 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 358 struct rtw8852c_efuse *map) 359 { 360 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 361 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 362 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 363 u8 i, j; 364 365 tssi->thermal[RF_PATH_A] = map->path_a_therm; 366 tssi->thermal[RF_PATH_B] = map->path_b_therm; 367 368 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 369 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 370 sizeof(ofst[i]->cck_tssi)); 371 372 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 373 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 374 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 375 i, j, tssi->tssi_cck[i][j]); 376 377 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 378 sizeof(ofst[i]->bw40_tssi)); 379 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 380 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 381 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 382 sizeof(tssi->tssi_6g_mcs[i])); 383 384 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 385 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 386 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 387 i, j, tssi->tssi_mcs[i][j]); 388 } 389 } 390 391 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 392 { 393 if (high) 394 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 395 if (low) 396 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 397 398 return data != 0xff; 399 } 400 401 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 402 struct rtw8852c_efuse *map) 403 { 404 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 405 bool valid = false; 406 407 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 408 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 409 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 410 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 411 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 412 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 413 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 414 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 415 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 416 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 417 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 418 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 419 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 420 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 421 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 422 423 gain->offset_valid = valid; 424 } 425 426 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 427 { 428 struct rtw89_efuse *efuse = &rtwdev->efuse; 429 struct rtw8852c_efuse *map; 430 431 map = (struct rtw8852c_efuse *)log_map; 432 433 efuse->country_code[0] = map->country_code[0]; 434 efuse->country_code[1] = map->country_code[1]; 435 rtw8852c_efuse_parsing_tssi(rtwdev, map); 436 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 437 438 switch (rtwdev->hci.type) { 439 case RTW89_HCI_TYPE_PCIE: 440 rtw8852c_e_efuse_parsing(efuse, map); 441 break; 442 default: 443 return -ENOTSUPP; 444 } 445 446 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 447 448 return 0; 449 } 450 451 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 452 { 453 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 454 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 455 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 456 u32 addr = rtwdev->chip->phycap_addr; 457 bool pg = false; 458 u32 ofst; 459 u8 i, j; 460 461 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 462 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 463 /* addrs are in decreasing order */ 464 ofst = tssi_trim_addr[i] - addr - j; 465 tssi->tssi_trim[i][j] = phycap_map[ofst]; 466 467 if (phycap_map[ofst] != 0xff) 468 pg = true; 469 } 470 471 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 472 /* addrs are in decreasing order */ 473 ofst = tssi_trim_addr_6g[i] - addr - j; 474 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 475 476 if (phycap_map[ofst] != 0xff) 477 pg = true; 478 } 479 } 480 481 if (!pg) { 482 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 483 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 484 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 485 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 486 } 487 488 for (i = 0; i < RF_PATH_NUM_8852C; i++) 489 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 490 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 491 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 492 i, j, tssi->tssi_trim[i][j], 493 tssi_trim_addr[i] - j); 494 } 495 496 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 497 u8 *phycap_map) 498 { 499 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 500 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 501 u32 addr = rtwdev->chip->phycap_addr; 502 u8 i; 503 504 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 505 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 506 507 rtw89_debug(rtwdev, RTW89_DBG_RFK, 508 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 509 i, info->thermal_trim[i]); 510 511 if (info->thermal_trim[i] != 0xff) 512 info->pg_thermal_trim = true; 513 } 514 } 515 516 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 517 { 518 #define __thm_setting(raw) \ 519 ({ \ 520 u8 __v = (raw); \ 521 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 522 }) 523 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 524 u8 i, val; 525 526 if (!info->pg_thermal_trim) { 527 rtw89_debug(rtwdev, RTW89_DBG_RFK, 528 "[THERMAL][TRIM] no PG, do nothing\n"); 529 530 return; 531 } 532 533 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 534 val = __thm_setting(info->thermal_trim[i]); 535 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 536 537 rtw89_debug(rtwdev, RTW89_DBG_RFK, 538 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 539 i, val); 540 } 541 #undef __thm_setting 542 } 543 544 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 545 u8 *phycap_map) 546 { 547 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 548 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 549 u32 addr = rtwdev->chip->phycap_addr; 550 u8 i; 551 552 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 553 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 554 555 rtw89_debug(rtwdev, RTW89_DBG_RFK, 556 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 557 i, info->pa_bias_trim[i]); 558 559 if (info->pa_bias_trim[i] != 0xff) 560 info->pg_pa_bias_trim = true; 561 } 562 } 563 564 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 565 { 566 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 567 u8 pabias_2g, pabias_5g; 568 u8 i; 569 570 if (!info->pg_pa_bias_trim) { 571 rtw89_debug(rtwdev, RTW89_DBG_RFK, 572 "[PA_BIAS][TRIM] no PG, do nothing\n"); 573 574 return; 575 } 576 577 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 578 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 579 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 580 581 rtw89_debug(rtwdev, RTW89_DBG_RFK, 582 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 583 i, pabias_2g, pabias_5g); 584 585 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 586 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 587 } 588 } 589 590 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 591 { 592 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 593 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 594 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 595 596 return 0; 597 } 598 599 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 600 { 601 rtw8852c_thermal_trim(rtwdev); 602 rtw8852c_pa_bias_trim(rtwdev); 603 } 604 605 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 606 const struct rtw89_chan *chan, 607 u8 mac_idx) 608 { 609 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 610 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 611 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 612 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 613 u8 rf_mod_val = 0, chk_rate_mask = 0; 614 u32 txsc; 615 616 switch (chan->band_width) { 617 case RTW89_CHANNEL_WIDTH_160: 618 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 619 RTW89_CHANNEL_WIDTH_80); 620 fallthrough; 621 case RTW89_CHANNEL_WIDTH_80: 622 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 623 RTW89_CHANNEL_WIDTH_40); 624 fallthrough; 625 case RTW89_CHANNEL_WIDTH_40: 626 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 627 RTW89_CHANNEL_WIDTH_20); 628 break; 629 default: 630 break; 631 } 632 633 switch (chan->band_width) { 634 case RTW89_CHANNEL_WIDTH_160: 635 rf_mod_val = AX_WMAC_RFMOD_160M; 636 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 637 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 638 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 639 break; 640 case RTW89_CHANNEL_WIDTH_80: 641 rf_mod_val = AX_WMAC_RFMOD_80M; 642 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 643 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 644 break; 645 case RTW89_CHANNEL_WIDTH_40: 646 rf_mod_val = AX_WMAC_RFMOD_40M; 647 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 648 break; 649 case RTW89_CHANNEL_WIDTH_20: 650 default: 651 rf_mod_val = AX_WMAC_RFMOD_20M; 652 txsc = 0; 653 break; 654 } 655 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 656 rtw89_write32(rtwdev, sub_carr, txsc); 657 658 switch (chan->band_type) { 659 case RTW89_BAND_2G: 660 chk_rate_mask = B_AX_BAND_MODE; 661 break; 662 case RTW89_BAND_5G: 663 case RTW89_BAND_6G: 664 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 665 break; 666 default: 667 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 668 return; 669 } 670 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 671 B_AX_RTS_LIMIT_IN_OFDM6); 672 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 673 } 674 675 static const u32 rtw8852c_sco_barker_threshold[14] = { 676 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 677 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 678 }; 679 680 static const u32 rtw8852c_sco_cck_threshold[14] = { 681 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 682 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 683 }; 684 685 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 686 u8 primary_ch, enum rtw89_bandwidth bw) 687 { 688 u8 ch_element; 689 690 if (bw == RTW89_CHANNEL_WIDTH_20) { 691 ch_element = central_ch - 1; 692 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 693 if (primary_ch == 1) 694 ch_element = central_ch - 1 + 2; 695 else 696 ch_element = central_ch - 1 - 2; 697 } else { 698 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 699 return -EINVAL; 700 } 701 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 702 rtw8852c_sco_barker_threshold[ch_element]); 703 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 704 rtw8852c_sco_cck_threshold[ch_element]); 705 706 return 0; 707 } 708 709 struct rtw8852c_bb_gain { 710 u32 gain_g[BB_PATH_NUM_8852C]; 711 u32 gain_a[BB_PATH_NUM_8852C]; 712 u32 gain_mask; 713 }; 714 715 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 716 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 717 .gain_mask = 0x00ff0000 }, 718 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 719 .gain_mask = 0xff000000 }, 720 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 721 .gain_mask = 0x000000ff }, 722 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 723 .gain_mask = 0x0000ff00 }, 724 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 725 .gain_mask = 0x00ff0000 }, 726 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 727 .gain_mask = 0xff000000 }, 728 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 729 .gain_mask = 0x000000ff }, 730 }; 731 732 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 733 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 734 .gain_mask = 0x00ff0000 }, 735 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 736 .gain_mask = 0xff000000 }, 737 }; 738 739 struct rtw8852c_bb_gain_bypass { 740 u32 gain_g[BB_PATH_NUM_8852C]; 741 u32 gain_a[BB_PATH_NUM_8852C]; 742 u32 gain_mask_g; 743 u32 gain_mask_a; 744 }; 745 746 static 747 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 748 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 749 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 750 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 751 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 752 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 753 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 754 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 755 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 756 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 757 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 758 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 759 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 760 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 761 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 762 }; 763 764 struct rtw8852c_bb_gain_op1db { 765 struct { 766 u32 lna[BB_PATH_NUM_8852C]; 767 u32 tia_lna[BB_PATH_NUM_8852C]; 768 u32 mask; 769 } reg[LNA_GAIN_NUM]; 770 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 771 u32 mask_tia0_lna6; 772 }; 773 774 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 775 .reg = { 776 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 777 .mask = 0xff}, 778 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 779 .mask = 0xff00}, 780 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 781 .mask = 0xff0000}, 782 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 783 .mask = 0xff000000}, 784 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 785 .mask = 0xff}, 786 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 787 .mask = 0xff00}, 788 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 789 .mask = 0xff0000}, 790 }, 791 .reg_tia0_lna6 = {0x4674, 0x4758}, 792 .mask_tia0_lna6 = 0xff000000, 793 }; 794 795 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 796 enum rtw89_subband subband, 797 enum rtw89_rf_path path) 798 { 799 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 800 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 801 s32 val; 802 u32 reg; 803 u32 mask; 804 int i; 805 806 for (i = 0; i < LNA_GAIN_NUM; i++) { 807 if (subband == RTW89_CH_2G) 808 reg = bb_gain_lna[i].gain_g[path]; 809 else 810 reg = bb_gain_lna[i].gain_a[path]; 811 812 mask = bb_gain_lna[i].gain_mask; 813 val = gain->lna_gain[gain_band][path][i]; 814 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 815 816 if (subband == RTW89_CH_2G) { 817 reg = bb_gain_bypass_lna[i].gain_g[path]; 818 mask = bb_gain_bypass_lna[i].gain_mask_g; 819 } else { 820 reg = bb_gain_bypass_lna[i].gain_a[path]; 821 mask = bb_gain_bypass_lna[i].gain_mask_a; 822 } 823 824 val = gain->lna_gain_bypass[gain_band][path][i]; 825 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 826 827 if (subband != RTW89_CH_2G) { 828 reg = bb_gain_op1db_a.reg[i].lna[path]; 829 mask = bb_gain_op1db_a.reg[i].mask; 830 val = gain->lna_op1db[gain_band][path][i]; 831 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 832 833 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 834 mask = bb_gain_op1db_a.reg[i].mask; 835 val = gain->tia_lna_op1db[gain_band][path][i]; 836 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 837 } 838 } 839 840 if (subband != RTW89_CH_2G) { 841 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 842 mask = bb_gain_op1db_a.mask_tia0_lna6; 843 val = gain->tia_lna_op1db[gain_band][path][7]; 844 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 845 } 846 847 for (i = 0; i < TIA_GAIN_NUM; i++) { 848 if (subband == RTW89_CH_2G) 849 reg = bb_gain_tia[i].gain_g[path]; 850 else 851 reg = bb_gain_tia[i].gain_a[path]; 852 853 mask = bb_gain_tia[i].gain_mask; 854 val = gain->tia_gain[gain_band][path][i]; 855 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 856 } 857 } 858 859 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 860 const struct rtw89_chan *chan, 861 enum rtw89_phy_idx phy_idx, 862 enum rtw89_rf_path path) 863 { 864 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 865 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 866 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 867 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 868 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 869 enum rtw89_gain_offset gain_band; 870 s32 offset_q0, offset_base_q4; 871 s32 tmp = 0; 872 873 if (!efuse_gain->offset_valid) 874 return; 875 876 if (rtwdev->dbcc_en && path == RF_PATH_B) 877 phy_idx = RTW89_PHY_1; 878 879 if (chan->band_type == RTW89_BAND_2G) { 880 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 881 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 882 883 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 884 S8_MIN >> 1, S8_MAX >> 1); 885 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 886 } 887 888 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type); 889 890 offset_q0 = -efuse_gain->offset[path][gain_band]; 891 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 892 893 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 894 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 895 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 896 897 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 898 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 899 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 900 } 901 902 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 903 const struct rtw89_chan *chan, 904 enum rtw89_phy_idx phy_idx) 905 { 906 u8 sco; 907 u16 central_freq = chan->freq; 908 u8 central_ch = chan->channel; 909 u8 band = chan->band_type; 910 u8 subband = chan->subband_type; 911 bool is_2g = band == RTW89_BAND_2G; 912 u8 chan_idx; 913 914 if (!central_freq) { 915 rtw89_warn(rtwdev, "Invalid central_freq\n"); 916 return; 917 } 918 919 if (phy_idx == RTW89_PHY_0) { 920 /* Path A */ 921 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 922 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 923 924 if (is_2g) 925 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 926 B_PATH0_BAND_SEL_MSK_V1, 1, 927 phy_idx); 928 else 929 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 930 B_PATH0_BAND_SEL_MSK_V1, 0, 931 phy_idx); 932 /* Path B */ 933 if (!rtwdev->dbcc_en) { 934 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 935 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 936 937 if (is_2g) 938 rtw89_phy_write32_idx(rtwdev, 939 R_PATH1_BAND_SEL_V1, 940 B_PATH1_BAND_SEL_MSK_V1, 941 1, phy_idx); 942 else 943 rtw89_phy_write32_idx(rtwdev, 944 R_PATH1_BAND_SEL_V1, 945 B_PATH1_BAND_SEL_MSK_V1, 946 0, phy_idx); 947 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 948 } else { 949 if (is_2g) 950 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 951 else 952 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 953 } 954 /* SCO compensate FC setting */ 955 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 956 central_freq, phy_idx); 957 /* round_up((1/fc0)*pow(2,18)) */ 958 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 959 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 960 phy_idx); 961 } else { 962 /* Path B */ 963 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 964 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 965 966 if (is_2g) 967 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 968 B_PATH1_BAND_SEL_MSK_V1, 969 1, phy_idx); 970 else 971 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 972 B_PATH1_BAND_SEL_MSK_V1, 973 0, phy_idx); 974 /* SCO compensate FC setting */ 975 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 976 central_freq, phy_idx); 977 /* round_up((1/fc0)*pow(2,18)) */ 978 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 979 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 980 phy_idx); 981 } 982 /* CCK parameters */ 983 if (band == RTW89_BAND_2G) { 984 if (central_ch == 14) { 985 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 986 B_PCOEFF01_MSK_V1, 0x3b13ff); 987 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 988 B_PCOEFF23_MSK_V1, 0x1c42de); 989 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 990 B_PCOEFF45_MSK_V1, 0xfdb0ad); 991 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 992 B_PCOEFF67_MSK_V1, 0xf60f6e); 993 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 994 B_PCOEFF89_MSK_V1, 0xfd8f92); 995 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 996 B_PCOEFFAB_MSK_V1, 0x2d011); 997 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 998 B_PCOEFFCD_MSK_V1, 0x1c02c); 999 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1000 B_PCOEFFEF_MSK_V1, 0xfff00a); 1001 } else { 1002 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1003 B_PCOEFF01_MSK_V1, 0x3d23ff); 1004 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1005 B_PCOEFF23_MSK_V1, 0x29b354); 1006 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1007 B_PCOEFF45_MSK_V1, 0xfc1c8); 1008 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1009 B_PCOEFF67_MSK_V1, 0xfdb053); 1010 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1011 B_PCOEFF89_MSK_V1, 0xf86f9a); 1012 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1013 B_PCOEFFAB_MSK_V1, 0xfaef92); 1014 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1015 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1016 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1017 B_PCOEFFEF_MSK_V1, 0xffdff5); 1018 } 1019 } 1020 1021 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1022 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1023 } 1024 1025 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1026 { 1027 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1028 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1029 1030 switch (bw) { 1031 case RTW89_CHANNEL_WIDTH_5: 1032 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1033 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1034 break; 1035 case RTW89_CHANNEL_WIDTH_10: 1036 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1037 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1038 break; 1039 case RTW89_CHANNEL_WIDTH_20: 1040 case RTW89_CHANNEL_WIDTH_40: 1041 case RTW89_CHANNEL_WIDTH_80: 1042 case RTW89_CHANNEL_WIDTH_160: 1043 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1044 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1045 break; 1046 default: 1047 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1048 } 1049 } 1050 1051 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1052 enum rtw89_phy_idx phy_idx) 1053 { 1054 if (bw == RTW89_CHANNEL_WIDTH_20) { 1055 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1056 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1057 } else { 1058 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1059 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1060 } 1061 } 1062 1063 static void 1064 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1065 enum rtw89_phy_idx phy_idx) 1066 { 1067 u8 mod_sbw = 0; 1068 1069 switch (bw) { 1070 case RTW89_CHANNEL_WIDTH_5: 1071 case RTW89_CHANNEL_WIDTH_10: 1072 case RTW89_CHANNEL_WIDTH_20: 1073 if (bw == RTW89_CHANNEL_WIDTH_5) 1074 mod_sbw = 0x1; 1075 else if (bw == RTW89_CHANNEL_WIDTH_10) 1076 mod_sbw = 0x2; 1077 else if (bw == RTW89_CHANNEL_WIDTH_20) 1078 mod_sbw = 0x0; 1079 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1080 phy_idx); 1081 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1082 mod_sbw, phy_idx); 1083 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1084 phy_idx); 1085 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1086 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1087 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1088 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1089 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1090 B_PATH0_BW_SEL_MSK_V1, 0xf); 1091 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1092 B_PATH1_BW_SEL_MSK_V1, 0xf); 1093 break; 1094 case RTW89_CHANNEL_WIDTH_40: 1095 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1096 phy_idx); 1097 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1098 phy_idx); 1099 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1100 pri_ch, 1101 phy_idx); 1102 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1103 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1104 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1105 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1106 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1107 B_PATH0_BW_SEL_MSK_V1, 0xf); 1108 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1109 B_PATH1_BW_SEL_MSK_V1, 0xf); 1110 break; 1111 case RTW89_CHANNEL_WIDTH_80: 1112 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1113 phy_idx); 1114 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1115 phy_idx); 1116 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1117 pri_ch, 1118 phy_idx); 1119 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1120 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1121 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1122 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1123 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1124 B_PATH0_BW_SEL_MSK_V1, 0xd); 1125 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1126 B_PATH1_BW_SEL_MSK_V1, 0xd); 1127 break; 1128 case RTW89_CHANNEL_WIDTH_160: 1129 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1130 phy_idx); 1131 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1132 phy_idx); 1133 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1134 pri_ch, 1135 phy_idx); 1136 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1137 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1138 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1139 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1140 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1141 B_PATH0_BW_SEL_MSK_V1, 0xb); 1142 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1143 B_PATH1_BW_SEL_MSK_V1, 0xb); 1144 break; 1145 default: 1146 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1147 pri_ch); 1148 } 1149 1150 if (bw == RTW89_CHANNEL_WIDTH_40) { 1151 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1152 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1153 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1154 } else { 1155 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1156 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1157 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1158 } 1159 1160 if (phy_idx == RTW89_PHY_0) { 1161 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1162 if (!rtwdev->dbcc_en) 1163 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1164 } else { 1165 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1166 } 1167 1168 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1169 } 1170 1171 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1172 const struct rtw89_chan *chan) 1173 { 1174 u8 center_chan = chan->channel; 1175 u8 bw = chan->band_width; 1176 1177 switch (chan->band_type) { 1178 case RTW89_BAND_2G: 1179 if (bw == RTW89_CHANNEL_WIDTH_20) { 1180 if (center_chan >= 5 && center_chan <= 8) 1181 return 2440; 1182 if (center_chan == 13) 1183 return 2480; 1184 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1185 if (center_chan >= 3 && center_chan <= 10) 1186 return 2440; 1187 } 1188 break; 1189 case RTW89_BAND_5G: 1190 if (center_chan == 151 || center_chan == 153 || 1191 center_chan == 155 || center_chan == 163) 1192 return 5760; 1193 break; 1194 case RTW89_BAND_6G: 1195 if (center_chan == 195 || center_chan == 197 || 1196 center_chan == 199 || center_chan == 207) 1197 return 6920; 1198 break; 1199 default: 1200 break; 1201 } 1202 1203 return 0; 1204 } 1205 1206 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1207 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1208 #define MAX_TONE_NUM 2048 1209 1210 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1211 const struct rtw89_chan *chan, 1212 enum rtw89_phy_idx phy_idx) 1213 { 1214 u32 spur_freq; 1215 s32 freq_diff, csi_idx, csi_tone_idx; 1216 1217 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1218 if (spur_freq == 0) { 1219 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1220 return; 1221 } 1222 1223 freq_diff = (spur_freq - chan->freq) * 1000000; 1224 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1225 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1226 1227 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1228 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1229 } 1230 1231 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1232 [RF_PATH_A] = { 1233 .notch1_idx = {0x4C14, 0xFF}, 1234 .notch1_frac_idx = {0x4C14, 0xC00}, 1235 .notch1_en = {0x4C14, 0x1000}, 1236 .notch2_idx = {0x4C20, 0xFF}, 1237 .notch2_frac_idx = {0x4C20, 0xC00}, 1238 .notch2_en = {0x4C20, 0x1000}, 1239 }, 1240 [RF_PATH_B] = { 1241 .notch1_idx = {0x4CD8, 0xFF}, 1242 .notch1_frac_idx = {0x4CD8, 0xC00}, 1243 .notch1_en = {0x4CD8, 0x1000}, 1244 .notch2_idx = {0x4CE4, 0xFF}, 1245 .notch2_frac_idx = {0x4CE4, 0xC00}, 1246 .notch2_en = {0x4CE4, 0x1000}, 1247 }, 1248 }; 1249 1250 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1251 const struct rtw89_chan *chan, 1252 enum rtw89_rf_path path) 1253 { 1254 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1255 u32 spur_freq, fc; 1256 s32 freq_diff; 1257 s32 nbi_idx, nbi_tone_idx; 1258 s32 nbi_frac_idx, nbi_frac_tone_idx; 1259 bool notch2_chk = false; 1260 1261 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1262 if (spur_freq == 0) { 1263 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1264 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1265 return; 1266 } 1267 1268 fc = chan->freq; 1269 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1270 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1271 if ((fc > spur_freq && 1272 chan->channel < chan->primary_channel) || 1273 (fc < spur_freq && 1274 chan->channel > chan->primary_channel)) 1275 notch2_chk = true; 1276 } 1277 1278 freq_diff = (spur_freq - fc) * 1000000; 1279 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1280 1281 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1282 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1283 } else { 1284 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1285 128 : 256; 1286 1287 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1288 } 1289 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1290 1291 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1292 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1293 nbi->notch2_idx.mask, nbi_tone_idx); 1294 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1295 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1296 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1297 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1298 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1299 } else { 1300 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1301 nbi->notch1_idx.mask, nbi_tone_idx); 1302 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1303 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1304 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1305 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1306 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1307 } 1308 } 1309 1310 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1311 enum rtw89_phy_idx phy_idx) 1312 { 1313 u32 notch; 1314 u32 notch2; 1315 1316 if (phy_idx == RTW89_PHY_0) { 1317 notch = R_PATH0_NOTCH; 1318 notch2 = R_PATH0_NOTCH2; 1319 } else { 1320 notch = R_PATH1_NOTCH; 1321 notch2 = R_PATH1_NOTCH2; 1322 } 1323 1324 rtw89_phy_write32_mask(rtwdev, notch, 1325 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1326 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1327 rtw89_phy_write32_mask(rtwdev, notch2, 1328 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1329 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1330 } 1331 1332 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1333 const struct rtw89_chan *chan, 1334 u8 pri_ch_idx, 1335 enum rtw89_phy_idx phy_idx) 1336 { 1337 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1338 1339 if (phy_idx == RTW89_PHY_0) { 1340 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1341 (pri_ch_idx == RTW89_SC_20_LOWER || 1342 pri_ch_idx == RTW89_SC_20_UP3X)) { 1343 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1344 if (!rtwdev->dbcc_en) 1345 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1346 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1347 (pri_ch_idx == RTW89_SC_20_UPPER || 1348 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1349 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1350 if (!rtwdev->dbcc_en) 1351 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1352 } else { 1353 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1354 if (!rtwdev->dbcc_en) 1355 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1356 RF_PATH_B); 1357 } 1358 } else { 1359 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1360 (pri_ch_idx == RTW89_SC_20_LOWER || 1361 pri_ch_idx == RTW89_SC_20_UP3X)) { 1362 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1363 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1364 (pri_ch_idx == RTW89_SC_20_UPPER || 1365 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1366 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1367 } else { 1368 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1369 } 1370 } 1371 1372 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1373 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1374 else 1375 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1376 } 1377 1378 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1379 const struct rtw89_chan *chan, 1380 enum rtw89_phy_idx phy_idx) 1381 { 1382 u8 pri_ch = chan->pri_ch_idx; 1383 bool mask_5m_low; 1384 bool mask_5m_en; 1385 1386 switch (chan->band_width) { 1387 case RTW89_CHANNEL_WIDTH_40: 1388 mask_5m_en = true; 1389 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1390 break; 1391 case RTW89_CHANNEL_WIDTH_80: 1392 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1393 pri_ch == RTW89_SC_20_LOWEST; 1394 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1395 break; 1396 default: 1397 mask_5m_en = false; 1398 mask_5m_low = false; 1399 break; 1400 } 1401 1402 if (!mask_5m_en) { 1403 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1404 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1405 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1406 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1407 } else { 1408 if (mask_5m_low) { 1409 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1410 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1411 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1412 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1413 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1414 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1415 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1416 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1417 } else { 1418 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1419 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1420 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1421 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1422 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1423 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1424 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1425 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1426 } 1427 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1428 } 1429 } 1430 1431 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1432 enum rtw89_phy_idx phy_idx) 1433 { 1434 /*HW SI reset*/ 1435 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1436 0x7); 1437 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1438 0x7); 1439 1440 udelay(1); 1441 1442 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1443 phy_idx); 1444 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1445 phy_idx); 1446 /*HW SI reset*/ 1447 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1448 0x0); 1449 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1450 0x0); 1451 1452 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1453 phy_idx); 1454 } 1455 1456 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1457 enum rtw89_phy_idx phy_idx, bool en) 1458 { 1459 if (en) { 1460 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1461 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1462 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1463 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1464 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1465 phy_idx); 1466 if (band == RTW89_BAND_2G) 1467 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1468 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1469 } else { 1470 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1471 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1472 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1473 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1474 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1475 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1476 fsleep(1); 1477 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1478 phy_idx); 1479 } 1480 } 1481 1482 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1483 enum rtw89_phy_idx phy_idx) 1484 { 1485 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1486 } 1487 1488 static 1489 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1490 u8 tx_path_en, u8 trsw_tx, 1491 u8 trsw_rx, u8 trsw, u8 trsw_b) 1492 { 1493 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1494 u32 mask_ofst = 16; 1495 u32 cr; 1496 u32 val; 1497 1498 if (path >= ARRAY_SIZE(path_cr_bases)) 1499 return; 1500 1501 cr = path_cr_bases[path]; 1502 1503 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1504 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1505 1506 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1507 } 1508 1509 enum rtw8852c_rfe_src { 1510 PAPE_RFM, 1511 TRSW_RFM, 1512 LNAON_RFM, 1513 }; 1514 1515 static 1516 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1517 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1518 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1519 { 1520 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1521 static const u32 masks[] = {0, 8, 16}; 1522 u32 mask, mask_ofst; 1523 u32 cr; 1524 u32 val; 1525 1526 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1527 return; 1528 1529 mask_ofst = masks[src]; 1530 cr = path_cr_bases[path]; 1531 1532 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1533 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1534 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1535 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1536 mask = 0xff << mask_ofst; 1537 1538 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1539 } 1540 1541 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1542 { 1543 static const u32 cr_bases[] = {0x5800, 0x7800}; 1544 u32 addr; 1545 u8 i; 1546 1547 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1548 addr = cr_bases[i]; 1549 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1550 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1551 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1552 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1553 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1554 } 1555 1556 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1557 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1558 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1559 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1560 1561 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1562 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1563 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1564 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1565 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1566 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1567 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1568 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1569 1570 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1571 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1572 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1573 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1574 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1575 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1576 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1577 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1578 1579 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1580 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1581 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1582 1583 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1584 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1585 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1586 } 1587 1588 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1589 enum rtw89_phy_idx phy_idx) 1590 { 1591 u32 addr; 1592 1593 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1594 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1595 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1596 } 1597 1598 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1599 { 1600 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1601 1602 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1603 B_DBCC_80P80_SEL_EVM_RPT_EN); 1604 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1605 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1606 1607 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1608 rtw8852c_bb_gpio_init(rtwdev); 1609 1610 /* read these registers after loading BB parameters */ 1611 gain->offset_base[RTW89_PHY_0] = 1612 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1613 gain->offset_base[RTW89_PHY_1] = 1614 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1615 } 1616 1617 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1618 const struct rtw89_chan *chan, 1619 enum rtw89_phy_idx phy_idx) 1620 { 1621 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1622 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1623 struct rtw89_hal *hal = &rtwdev->hal; 1624 bool cck_en = chan->band_type == RTW89_BAND_2G; 1625 u8 pri_ch_idx = chan->pri_ch_idx; 1626 u32 mask, reg; 1627 u8 ntx_path; 1628 1629 if (chan->band_type == RTW89_BAND_2G) 1630 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1631 chan->primary_channel, 1632 chan->band_width); 1633 1634 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1635 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1636 if (cck_en) { 1637 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1638 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1639 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1640 B_PD_ARBITER_OFF, 0x0, phy_idx); 1641 } else { 1642 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1643 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1644 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1645 B_PD_ARBITER_OFF, 0x1, phy_idx); 1646 } 1647 1648 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1649 rtw8852c_ctrl_btg(rtwdev, chan->band_type == RTW89_BAND_2G); 1650 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1651 1652 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1653 rtwdev->hal.cv != CHIP_CAV) { 1654 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1655 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1656 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx); 1657 if (chan->primary_channel > chan->channel) { 1658 rtw89_phy_write32_mask(rtwdev, 1659 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1660 ru_alloc_msk[phy_idx], 1); 1661 rtw89_write32_mask(rtwdev, reg, 1662 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1663 } else { 1664 rtw89_phy_write32_mask(rtwdev, 1665 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1666 ru_alloc_msk[phy_idx], 0); 1667 rtw89_write32_mask(rtwdev, reg, 1668 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1669 } 1670 } 1671 1672 if (chan->band_type == RTW89_BAND_6G && 1673 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1674 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1675 B_CDD_EVM_CHK_EN, 0, phy_idx); 1676 else 1677 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1678 B_CDD_EVM_CHK_EN, 1, phy_idx); 1679 1680 if (!rtwdev->dbcc_en) { 1681 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1682 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1683 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1684 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1685 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1686 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1687 } else { 1688 if (phy_idx == RTW89_PHY_0) { 1689 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1690 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1691 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1692 } else { 1693 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1694 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1695 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1696 } 1697 } 1698 1699 if (chan->band_type == RTW89_BAND_6G) 1700 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1701 else 1702 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1703 1704 if (hal->antenna_tx) 1705 ntx_path = hal->antenna_tx; 1706 else 1707 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1708 1709 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1710 1711 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1712 } 1713 1714 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1715 const struct rtw89_chan *chan, 1716 enum rtw89_mac_idx mac_idx, 1717 enum rtw89_phy_idx phy_idx) 1718 { 1719 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1720 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1721 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1722 } 1723 1724 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1725 { 1726 if (en) 1727 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1728 else 1729 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1730 } 1731 1732 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1733 { 1734 if (en) 1735 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1736 0x0); 1737 else 1738 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1739 0xf); 1740 } 1741 1742 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1743 struct rtw89_channel_help_params *p, 1744 const struct rtw89_chan *chan, 1745 enum rtw89_mac_idx mac_idx, 1746 enum rtw89_phy_idx phy_idx) 1747 { 1748 if (enter) { 1749 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1750 RTW89_SCH_TX_SEL_ALL); 1751 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1752 rtw8852c_dfs_en(rtwdev, false); 1753 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1754 rtw8852c_adc_en(rtwdev, false); 1755 fsleep(40); 1756 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1757 } else { 1758 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1759 rtw8852c_adc_en(rtwdev, true); 1760 rtw8852c_dfs_en(rtwdev, true); 1761 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1762 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1763 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1764 } 1765 } 1766 1767 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1768 { 1769 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1770 1771 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1772 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1773 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 1774 rtw8852c_lck_init(rtwdev); 1775 1776 rtw8852c_rck(rtwdev); 1777 rtw8852c_dack(rtwdev); 1778 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1779 } 1780 1781 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) 1782 { 1783 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1784 1785 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1786 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1787 rtw8852c_iqk(rtwdev, phy_idx); 1788 rtw8852c_tssi(rtwdev, phy_idx); 1789 rtw8852c_dpk(rtwdev, phy_idx); 1790 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1791 } 1792 1793 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1794 enum rtw89_phy_idx phy_idx) 1795 { 1796 rtw8852c_tssi_scan(rtwdev, phy_idx); 1797 } 1798 1799 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1800 { 1801 rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1802 } 1803 1804 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1805 { 1806 rtw8852c_dpk_track(rtwdev); 1807 rtw8852c_lck_track(rtwdev); 1808 rtw8852c_rx_dck_track(rtwdev); 1809 } 1810 1811 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1812 enum rtw89_phy_idx phy_idx, s16 ref) 1813 { 1814 s8 ofst_int = 0; 1815 u8 base_cw_0db = 0x27; 1816 u16 tssi_16dbm_cw = 0x12c; 1817 s16 pwr_s10_3 = 0; 1818 s16 rf_pwr_cw = 0; 1819 u16 bb_pwr_cw = 0; 1820 u32 pwr_cw = 0; 1821 u32 tssi_ofst_cw = 0; 1822 1823 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1824 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1825 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1826 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1827 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1828 1829 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1830 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1831 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1832 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1833 1834 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1835 } 1836 1837 static 1838 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1839 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1840 { 1841 s8 pw_ofst_2tx; 1842 s8 val_1t; 1843 s8 val_2t; 1844 u32 reg; 1845 u8 i; 1846 1847 if (pw_ofst < -32 || pw_ofst > 31) { 1848 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1849 return; 1850 } 1851 val_1t = pw_ofst << 2; 1852 pw_ofst_2tx = max(pw_ofst - 3, -32); 1853 val_2t = pw_ofst_2tx << 2; 1854 1855 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1856 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1857 1858 for (i = 0; i < 4; i++) { 1859 /* 1TX */ 1860 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1861 rtw89_write32_mask(rtwdev, reg, 1862 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1863 val_1t); 1864 /* 2TX */ 1865 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1866 rtw89_write32_mask(rtwdev, reg, 1867 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1868 val_2t); 1869 } 1870 } 1871 1872 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1873 enum rtw89_phy_idx phy_idx) 1874 { 1875 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1876 const u32 mask = 0x7FFFFFF; 1877 const u8 ofst_ofdm = 0x4; 1878 const u8 ofst_cck = 0x8; 1879 s16 ref_ofdm = 0; 1880 s16 ref_cck = 0; 1881 u32 val; 1882 u8 i; 1883 1884 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1885 1886 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1887 GENMASK(27, 10), 0x0); 1888 1889 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1890 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1891 1892 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1893 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1894 phy_idx); 1895 1896 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1897 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1898 1899 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1900 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1901 phy_idx); 1902 } 1903 1904 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1905 const struct rtw89_chan *chan, 1906 u8 tx_shape_idx, 1907 enum rtw89_phy_idx phy_idx) 1908 { 1909 #define __DFIR_CFG_MASK 0xffffff 1910 #define __DFIR_CFG_NR 8 1911 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 1912 static const u32 _prefix ## _ ## _name[] = {_val}; \ 1913 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 1914 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 1915 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 1916 1917 __DECL_DFIR_PARAM(flat, 1918 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1919 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1920 __DECL_DFIR_PARAM(sharp, 1921 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1922 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 1923 __DECL_DFIR_PARAM(sharp_14, 1924 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1925 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 1926 __DECL_DFIR_ADDR(filter, 1927 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 1928 0x45C4, 0x45C8); 1929 u8 ch = chan->channel; 1930 const u32 *param; 1931 int i; 1932 1933 if (ch > 14) { 1934 rtw89_warn(rtwdev, 1935 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1936 return; 1937 } 1938 1939 if (ch == 14) 1940 param = param_sharp_14; 1941 else 1942 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1943 1944 for (i = 0; i < __DFIR_CFG_NR; i++) { 1945 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1946 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 1947 param[i]); 1948 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 1949 param[i], phy_idx); 1950 } 1951 1952 #undef __DECL_DFIR_ADDR 1953 #undef __DECL_DFIR_PARAM 1954 #undef __DECL_DFIR_VAR 1955 #undef __DFIR_CFG_NR 1956 #undef __DFIR_CFG_MASK 1957 } 1958 1959 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 1960 const struct rtw89_chan *chan, 1961 enum rtw89_phy_idx phy_idx) 1962 { 1963 u8 band = chan->band_type; 1964 u8 regd = rtw89_regd_get(rtwdev, band); 1965 u8 tx_shape_cck = rtw89_8852c_tx_shape[band][RTW89_RS_CCK][regd]; 1966 u8 tx_shape_ofdm = rtw89_8852c_tx_shape[band][RTW89_RS_OFDM][regd]; 1967 1968 if (band == RTW89_BAND_2G) 1969 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1970 1971 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 1972 (enum rtw89_mac_idx)phy_idx, 1973 tx_shape_ofdm); 1974 } 1975 1976 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 1977 const struct rtw89_chan *chan, 1978 enum rtw89_phy_idx phy_idx) 1979 { 1980 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1981 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1982 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 1983 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1984 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1985 } 1986 1987 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1988 enum rtw89_phy_idx phy_idx) 1989 { 1990 rtw8852c_set_txpwr_ref(rtwdev, phy_idx); 1991 } 1992 1993 static void 1994 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1995 { 1996 static const struct rtw89_reg2_def ctrl_ini[] = { 1997 {0xD938, 0x00010100}, 1998 {0xD93C, 0x0500D500}, 1999 {0xD940, 0x00000500}, 2000 {0xD944, 0x00000005}, 2001 {0xD94C, 0x00220000}, 2002 {0xD950, 0x00030000}, 2003 }; 2004 u32 addr; 2005 int i; 2006 2007 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2008 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2009 2010 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2011 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2012 ctrl_ini[i].data); 2013 2014 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2015 (enum rtw89_mac_idx)phy_idx, 2016 RTW89_TSSI_BANDEDGE_FLAT); 2017 } 2018 2019 static int 2020 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2021 { 2022 int ret; 2023 2024 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2025 if (ret) 2026 return ret; 2027 2028 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2029 if (ret) 2030 return ret; 2031 2032 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2033 if (ret) 2034 return ret; 2035 2036 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2037 RTW89_MAC_1 : 2038 RTW89_MAC_0); 2039 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2040 2041 return 0; 2042 } 2043 2044 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2045 { 2046 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2047 u8 band = chan->band_type; 2048 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2049 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2050 2051 if (rtwdev->dbcc_en) { 2052 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2053 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2054 RTW89_PHY_1); 2055 2056 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2057 1); 2058 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2059 1); 2060 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2061 RTW89_PHY_1); 2062 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2063 RTW89_PHY_1); 2064 2065 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2066 B_RXHT_MCS_LIMIT, 0); 2067 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2068 B_RXVHT_MCS_LIMIT, 0); 2069 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2070 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2071 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2072 2073 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2074 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2075 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2076 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2077 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2078 RTW89_PHY_1); 2079 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2080 RTW89_PHY_1); 2081 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2082 RTW89_PHY_1); 2083 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2084 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2085 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2086 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2087 } else { 2088 if (rx_path == RF_PATH_A) { 2089 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2090 B_ANT_RX_SEG0, 1); 2091 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2092 B_ANT_RX_1RCCA_SEG0, 1); 2093 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2094 B_ANT_RX_1RCCA_SEG1, 1); 2095 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2096 B_RXHT_MCS_LIMIT, 0); 2097 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2098 B_RXVHT_MCS_LIMIT, 0); 2099 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2100 0); 2101 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2102 0); 2103 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2104 rst_mask0, 1); 2105 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2106 rst_mask0, 3); 2107 } else if (rx_path == RF_PATH_B) { 2108 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2109 B_ANT_RX_SEG0, 2); 2110 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2111 B_ANT_RX_1RCCA_SEG0, 2); 2112 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2113 B_ANT_RX_1RCCA_SEG1, 2); 2114 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2115 B_RXHT_MCS_LIMIT, 0); 2116 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2117 B_RXVHT_MCS_LIMIT, 0); 2118 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2119 0); 2120 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2121 0); 2122 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2123 rst_mask1, 1); 2124 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2125 rst_mask1, 3); 2126 } else { 2127 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2128 B_ANT_RX_SEG0, 3); 2129 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2130 B_ANT_RX_1RCCA_SEG0, 3); 2131 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2132 B_ANT_RX_1RCCA_SEG1, 3); 2133 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2134 B_RXHT_MCS_LIMIT, 1); 2135 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2136 B_RXVHT_MCS_LIMIT, 1); 2137 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2138 1); 2139 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2140 1); 2141 rtw8852c_ctrl_btg(rtwdev, band == RTW89_BAND_2G); 2142 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2143 rst_mask0, 1); 2144 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2145 rst_mask0, 3); 2146 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2147 rst_mask1, 1); 2148 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2149 rst_mask1, 3); 2150 } 2151 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2152 } 2153 } 2154 2155 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2156 enum rtw89_mac_idx mac_idx) 2157 { 2158 struct rtw89_reg2_def path_com[] = { 2159 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2160 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2161 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2162 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2163 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2164 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2165 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2166 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2167 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2168 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2169 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2170 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2171 }; 2172 u32 addr; 2173 u32 reg; 2174 u8 cr_size = ARRAY_SIZE(path_com); 2175 u8 i = 0; 2176 2177 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2178 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2179 2180 for (addr = R_AX_MACID_ANT_TABLE; 2181 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2182 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 2183 rtw89_write32(rtwdev, reg, 0); 2184 } 2185 2186 if (tx_path == RF_A) { 2187 path_com[0].data = AX_PATH_COM0_PATHA; 2188 path_com[1].data = AX_PATH_COM1_PATHA; 2189 path_com[2].data = AX_PATH_COM2_PATHA; 2190 path_com[7].data = AX_PATH_COM7_PATHA; 2191 path_com[8].data = AX_PATH_COM8_PATHA; 2192 } else if (tx_path == RF_B) { 2193 path_com[0].data = AX_PATH_COM0_PATHB; 2194 path_com[1].data = AX_PATH_COM1_PATHB; 2195 path_com[2].data = AX_PATH_COM2_PATHB; 2196 path_com[7].data = AX_PATH_COM7_PATHB; 2197 path_com[8].data = AX_PATH_COM8_PATHB; 2198 } else if (tx_path == RF_AB) { 2199 path_com[0].data = AX_PATH_COM0_PATHAB; 2200 path_com[1].data = AX_PATH_COM1_PATHAB; 2201 path_com[2].data = AX_PATH_COM2_PATHAB; 2202 path_com[7].data = AX_PATH_COM7_PATHAB; 2203 path_com[8].data = AX_PATH_COM8_PATHAB; 2204 } else { 2205 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2206 return; 2207 } 2208 2209 for (i = 0; i < cr_size; i++) { 2210 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2211 path_com[i].addr, path_com[i].data); 2212 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx); 2213 rtw89_write32(rtwdev, reg, path_com[i].data); 2214 } 2215 } 2216 2217 static void rtw8852c_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 2218 { 2219 if (bt_en) { 2220 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2221 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2222 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2223 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2224 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2225 B_PATH0_RXBB_MSK_V1, 0xf); 2226 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2227 B_PATH1_RXBB_MSK_V1, 0xf); 2228 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2229 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2230 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2231 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2232 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2233 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2234 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2235 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2236 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2237 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2238 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2239 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2240 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2241 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2242 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2243 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2244 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2245 B_P0_BACKOFF_IBADC_V1, 0x34); 2246 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2247 B_P1_BACKOFF_IBADC_V1, 0x34); 2248 } else { 2249 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2250 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2251 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2252 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2253 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2254 B_PATH0_RXBB_MSK_V1, 0x60); 2255 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2256 B_PATH1_RXBB_MSK_V1, 0x60); 2257 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2258 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2259 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2260 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2261 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2262 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2263 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2264 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2265 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2266 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2267 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2268 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2269 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2270 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2271 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2272 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2273 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2274 B_P0_BACKOFF_IBADC_V1, 0x26); 2275 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2276 B_P1_BACKOFF_IBADC_V1, 0x26); 2277 } 2278 } 2279 2280 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2281 { 2282 struct rtw89_hal *hal = &rtwdev->hal; 2283 2284 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2285 2286 if (hal->rx_nss == 1) { 2287 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2288 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2289 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2290 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2291 } else { 2292 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2293 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2294 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2295 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2296 } 2297 } 2298 2299 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2300 { 2301 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2302 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2303 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2304 2305 fsleep(200); 2306 2307 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2308 } 2309 2310 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2311 { 2312 struct rtw89_btc *btc = &rtwdev->btc; 2313 struct rtw89_btc_module *module = &btc->mdinfo; 2314 2315 module->rfe_type = rtwdev->efuse.rfe_type; 2316 module->cv = rtwdev->hal.cv; 2317 module->bt_solo = 0; 2318 module->switch_type = BTC_SWITCH_INTERNAL; 2319 2320 if (module->rfe_type > 0) 2321 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 2322 else 2323 module->ant.num = 2; 2324 2325 module->ant.diversity = 0; 2326 module->ant.isolation = 10; 2327 2328 if (module->ant.num == 3) { 2329 module->ant.type = BTC_ANT_DEDICATED; 2330 module->bt_pos = BTC_BT_ALONE; 2331 } else { 2332 module->ant.type = BTC_ANT_SHARED; 2333 module->bt_pos = BTC_BT_BTG; 2334 } 2335 } 2336 2337 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 2338 { 2339 if (btg) { 2340 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2341 B_PATH0_BT_SHARE_V1, 0x1); 2342 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2343 B_PATH0_BTG_PATH_V1, 0x0); 2344 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2345 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2346 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2347 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2348 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2349 B_PATH1_BT_SHARE_V1, 0x1); 2350 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2351 B_PATH1_BTG_PATH_V1, 0x1); 2352 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2353 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2354 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2355 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2356 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2357 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2358 0x1); 2359 } else { 2360 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2361 B_PATH0_BT_SHARE_V1, 0x0); 2362 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2363 B_PATH0_BTG_PATH_V1, 0x0); 2364 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2365 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2366 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2367 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2368 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2369 B_PATH1_BT_SHARE_V1, 0x0); 2370 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2371 B_PATH1_BTG_PATH_V1, 0x0); 2372 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2373 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2374 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2375 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2376 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2377 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2378 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2379 0x0); 2380 } 2381 } 2382 2383 static 2384 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2385 { 2386 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2387 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2388 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2389 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2390 } 2391 2392 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2393 { 2394 struct rtw89_btc *btc = &rtwdev->btc; 2395 struct rtw89_btc_module *module = &btc->mdinfo; 2396 const struct rtw89_chip_info *chip = rtwdev->chip; 2397 const struct rtw89_mac_ax_coex coex_params = { 2398 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2399 .direction = RTW89_MAC_AX_COEX_INNER, 2400 }; 2401 2402 /* PTA init */ 2403 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2404 2405 /* set WL Tx response = Hi-Pri */ 2406 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2407 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2408 2409 /* set rf gnt debug off */ 2410 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2411 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2412 2413 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2414 if (module->ant.type == BTC_ANT_SHARED) { 2415 rtw8852c_set_trx_mask(rtwdev, 2416 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2417 rtw8852c_set_trx_mask(rtwdev, 2418 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2419 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2420 rtw8852c_set_trx_mask(rtwdev, 2421 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2422 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2423 rtw8852c_set_trx_mask(rtwdev, 2424 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2425 rtw8852c_set_trx_mask(rtwdev, 2426 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2427 } 2428 2429 /* set PTA break table */ 2430 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2431 2432 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2433 rtw89_write32_set(rtwdev, 2434 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2435 B_AX_BT_CNT_RST_V1); 2436 btc->cx.wl.status.map.init_ok = true; 2437 } 2438 2439 static 2440 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2441 { 2442 u32 bitmap = 0; 2443 u32 reg = 0; 2444 2445 switch (map) { 2446 case BTC_PRI_MASK_TX_RESP: 2447 reg = R_BTC_COEX_WL_REQ; 2448 bitmap = B_BTC_RSP_ACK_HI; 2449 break; 2450 case BTC_PRI_MASK_BEACON: 2451 reg = R_BTC_COEX_WL_REQ; 2452 bitmap = B_BTC_TX_BCN_HI; 2453 break; 2454 default: 2455 return; 2456 } 2457 2458 if (state) 2459 rtw89_write32_set(rtwdev, reg, bitmap); 2460 else 2461 rtw89_write32_clr(rtwdev, reg, bitmap); 2462 } 2463 2464 union rtw8852c_btc_wl_txpwr_ctrl { 2465 u32 txpwr_val; 2466 struct { 2467 union { 2468 u16 ctrl_all_time; 2469 struct { 2470 s16 data:9; 2471 u16 rsvd:6; 2472 u16 flag:1; 2473 } all_time; 2474 }; 2475 union { 2476 u16 ctrl_gnt_bt; 2477 struct { 2478 s16 data:9; 2479 u16 rsvd:7; 2480 } gnt_bt; 2481 }; 2482 }; 2483 } __packed; 2484 2485 static void 2486 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2487 { 2488 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2489 s32 val; 2490 2491 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2492 do { \ 2493 u32 _wrt = FIELD_PREP(_msk, _val); \ 2494 BUILD_BUG_ON((_msk & _en) != 0); \ 2495 if (_cond) \ 2496 _wrt |= _en; \ 2497 else \ 2498 _wrt &= ~_en; \ 2499 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2500 _msk | _en, _wrt); \ 2501 } while (0) 2502 2503 switch (arg.ctrl_all_time) { 2504 case 0xffff: 2505 val = 0; 2506 break; 2507 default: 2508 val = arg.all_time.data; 2509 break; 2510 } 2511 2512 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2513 val, B_AX_FORCE_PWR_BY_RATE_EN, 2514 arg.ctrl_all_time != 0xffff); 2515 2516 switch (arg.ctrl_gnt_bt) { 2517 case 0xffff: 2518 val = 0; 2519 break; 2520 default: 2521 val = arg.gnt_bt.data; 2522 break; 2523 } 2524 2525 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2526 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2527 2528 #undef __write_ctrl 2529 } 2530 2531 static 2532 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2533 { 2534 /* +6 for compensate offset */ 2535 return clamp_t(s8, val + 6, -100, 0) + 100; 2536 } 2537 2538 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2539 {255, 0, 0, 7}, /* 0 -> original */ 2540 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2541 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2542 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2543 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2544 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2545 {6, 1, 0, 7}, 2546 {13, 1, 0, 7}, 2547 {13, 1, 0, 7} 2548 }; 2549 2550 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2551 {255, 0, 0, 7}, /* 0 -> original */ 2552 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2553 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2554 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2555 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2556 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2557 {255, 1, 0, 7}, 2558 {255, 1, 0, 7}, 2559 {255, 1, 0, 7} 2560 }; 2561 2562 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2563 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2564 2565 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2566 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2567 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2568 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2569 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2570 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2571 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2572 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2573 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2574 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2575 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2576 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2577 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2578 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 2579 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 2580 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 2581 }; 2582 2583 static 2584 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2585 { 2586 /* Feature move to firmware */ 2587 } 2588 2589 static 2590 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2591 { 2592 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2593 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2594 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2595 2596 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2597 if (state) 2598 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2599 RFREG_MASK, 0x179c); 2600 else 2601 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2602 RFREG_MASK, 0x208); 2603 2604 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2605 } 2606 2607 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2608 { 2609 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2610 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2611 * To improve BT ACI in co-rx 2612 */ 2613 2614 switch (level) { 2615 case 0: /* default */ 2616 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2617 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2618 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2619 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2620 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2621 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2622 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2623 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2624 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2625 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2626 break; 2627 case 1: /* Fix LNA2=5 */ 2628 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2629 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2630 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2631 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2632 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2633 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2634 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2635 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2636 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2637 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2638 break; 2639 } 2640 } 2641 2642 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2643 { 2644 struct rtw89_btc *btc = &rtwdev->btc; 2645 2646 switch (level) { 2647 case 0: /* original */ 2648 default: 2649 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2650 btc->dm.wl_lna2 = 0; 2651 break; 2652 case 1: /* for FDD free-run */ 2653 rtw8852c_bb_ctrl_btc_preagc(rtwdev, true); 2654 btc->dm.wl_lna2 = 0; 2655 break; 2656 case 2: /* for BTG Co-Rx*/ 2657 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2658 btc->dm.wl_lna2 = 1; 2659 break; 2660 } 2661 2662 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2663 } 2664 2665 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2666 struct rtw89_rx_phy_ppdu *phy_ppdu, 2667 struct ieee80211_rx_status *status) 2668 { 2669 u8 chan_idx = phy_ppdu->chan_idx; 2670 enum nl80211_band band; 2671 u8 ch; 2672 2673 if (chan_idx == 0) 2674 return; 2675 2676 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2677 status->freq = ieee80211_channel_to_frequency(ch, band); 2678 status->band = band; 2679 } 2680 2681 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2682 struct rtw89_rx_phy_ppdu *phy_ppdu, 2683 struct ieee80211_rx_status *status) 2684 { 2685 u8 path; 2686 u8 *rx_power = phy_ppdu->rssi; 2687 2688 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2689 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2690 status->chains |= BIT(path); 2691 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2692 } 2693 if (phy_ppdu->valid) 2694 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2695 } 2696 2697 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2698 { 2699 int ret; 2700 2701 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2702 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2703 2704 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2705 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2706 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2707 2708 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2709 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2710 2711 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2712 if (ret) 2713 return ret; 2714 2715 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2716 if (ret) 2717 return ret; 2718 2719 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2720 if (ret) 2721 return ret; 2722 2723 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2724 if (ret) 2725 return ret; 2726 2727 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2728 if (ret) 2729 return ret; 2730 2731 return 0; 2732 } 2733 2734 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2735 { 2736 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2737 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2738 2739 return 0; 2740 } 2741 2742 #ifdef CONFIG_PM 2743 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = { 2744 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2745 .n_patterns = RTW89_MAX_PATTERN_NUM, 2746 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2747 .pattern_min_len = 1, 2748 }; 2749 #endif 2750 2751 static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2752 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2753 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2754 .bb_reset = rtw8852c_bb_reset, 2755 .bb_sethw = rtw8852c_bb_sethw, 2756 .read_rf = rtw89_phy_read_rf_v1, 2757 .write_rf = rtw89_phy_write_rf_v1, 2758 .set_channel = rtw8852c_set_channel, 2759 .set_channel_help = rtw8852c_set_channel_help, 2760 .read_efuse = rtw8852c_read_efuse, 2761 .read_phycap = rtw8852c_read_phycap, 2762 .fem_setup = NULL, 2763 .rfe_gpio = NULL, 2764 .rfk_init = rtw8852c_rfk_init, 2765 .rfk_channel = rtw8852c_rfk_channel, 2766 .rfk_band_changed = rtw8852c_rfk_band_changed, 2767 .rfk_scan = rtw8852c_rfk_scan, 2768 .rfk_track = rtw8852c_rfk_track, 2769 .power_trim = rtw8852c_power_trim, 2770 .set_txpwr = rtw8852c_set_txpwr, 2771 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2772 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2773 .get_thermal = rtw8852c_get_thermal, 2774 .ctrl_btg = rtw8852c_ctrl_btg, 2775 .query_ppdu = rtw8852c_query_ppdu, 2776 .bb_ctrl_btc_preagc = rtw8852c_bb_ctrl_btc_preagc, 2777 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2778 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2779 .pwr_on_func = rtw8852c_pwr_on_func, 2780 .pwr_off_func = rtw8852c_pwr_off_func, 2781 .query_rxdesc = rtw89_core_query_rxdesc, 2782 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2783 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2784 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2785 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2786 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2787 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2788 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2789 2790 .btc_set_rfe = rtw8852c_btc_set_rfe, 2791 .btc_init_cfg = rtw8852c_btc_init_cfg, 2792 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2793 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2794 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2795 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2796 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2797 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2798 .btc_set_policy = rtw89_btc_set_policy_v1, 2799 }; 2800 2801 const struct rtw89_chip_info rtw8852c_chip_info = { 2802 .chip_id = RTL8852C, 2803 .chip_gen = RTW89_CHIP_AX, 2804 .ops = &rtw8852c_chip_ops, 2805 .mac_def = &rtw89_mac_gen_ax, 2806 .phy_def = &rtw89_phy_gen_ax, 2807 .fw_basename = RTW8852C_FW_BASENAME, 2808 .fw_format_max = RTW8852C_FW_FORMAT_MAX, 2809 .try_ce_fw = false, 2810 .needed_fw_elms = 0, 2811 .fifo_size = 458752, 2812 .small_fifo_size = false, 2813 .dle_scc_rsvd_size = 0, 2814 .max_amsdu_limit = 8000, 2815 .dis_2g_40m_ul_ofdma = false, 2816 .rsvd_ple_ofst = 0x6f800, 2817 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2818 .dle_mem = rtw8852c_dle_mem_pcie, 2819 .wde_qempty_acq_num = 16, 2820 .wde_qempty_mgq_sel = 16, 2821 .rf_base_addr = {0xe000, 0xf000}, 2822 .pwr_on_seq = NULL, 2823 .pwr_off_seq = NULL, 2824 .bb_table = &rtw89_8852c_phy_bb_table, 2825 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2826 .rf_table = {&rtw89_8852c_phy_radiob_table, 2827 &rtw89_8852c_phy_radioa_table,}, 2828 .nctl_table = &rtw89_8852c_phy_nctl_table, 2829 .nctl_post_table = NULL, 2830 .byr_table = &rtw89_8852c_byr_table, 2831 .dflt_parms = &rtw89_8852c_dflt_parms, 2832 .rfe_parms_conf = NULL, 2833 .txpwr_factor_rf = 2, 2834 .txpwr_factor_mac = 1, 2835 .dig_table = NULL, 2836 .dig_regs = &rtw8852c_dig_regs, 2837 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2838 .support_chanctx_num = 1, 2839 .support_bands = BIT(NL80211_BAND_2GHZ) | 2840 BIT(NL80211_BAND_5GHZ) | 2841 BIT(NL80211_BAND_6GHZ), 2842 .support_bw160 = true, 2843 .support_unii4 = true, 2844 .support_ul_tb_ctrl = false, 2845 .hw_sec_hdr = true, 2846 .rf_path_num = 2, 2847 .tx_nss = 2, 2848 .rx_nss = 2, 2849 .acam_num = 128, 2850 .bcam_num = 20, 2851 .scam_num = 128, 2852 .bacam_num = 8, 2853 .bacam_dynamic_num = 8, 2854 .bacam_ver = RTW89_BACAM_V0_EXT, 2855 .sec_ctrl_efuse_size = 4, 2856 .physical_efuse_size = 1216, 2857 .logical_efuse_size = 2048, 2858 .limit_efuse_size = 1280, 2859 .dav_phy_efuse_size = 96, 2860 .dav_log_efuse_size = 16, 2861 .phycap_addr = 0x590, 2862 .phycap_size = 0x60, 2863 .para_ver = 0x1, 2864 .wlcx_desired = 0x06000000, 2865 .btcx_desired = 0x7, 2866 .scbd = 0x1, 2867 .mailbox = 0x1, 2868 2869 .afh_guard_ch = 6, 2870 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 2871 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 2872 .rssi_tol = 2, 2873 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 2874 .mon_reg = rtw89_btc_8852c_mon_reg, 2875 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 2876 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 2877 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 2878 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 2879 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2880 BIT(RTW89_PS_MODE_CLK_GATED) | 2881 BIT(RTW89_PS_MODE_PWR_GATED), 2882 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 2883 BIT(RTW89_PS_MODE_PWR_GATED), 2884 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 2885 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 2886 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 2887 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 2888 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 2889 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2890 .h2c_regs = rtw8852c_h2c_regs, 2891 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 2892 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2893 .c2h_regs = rtw8852c_c2h_regs, 2894 .page_regs = &rtw8852c_page_regs, 2895 .cfo_src_fd = false, 2896 .cfo_hw_comp = false, 2897 .dcfo_comp = &rtw8852c_dcfo_comp, 2898 .dcfo_comp_sft = 12, 2899 .imr_info = &rtw8852c_imr_info, 2900 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 2901 .bss_clr_map_reg = R_BSS_CLR_MAP, 2902 .dma_ch_mask = 0, 2903 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL, 2904 #ifdef CONFIG_PM 2905 .wowlan_stub = &rtw_wowlan_stub_8852c, 2906 #endif 2907 .xtal_info = NULL, 2908 }; 2909 EXPORT_SYMBOL(rtw8852c_chip_info); 2910 2911 MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE); 2912 MODULE_AUTHOR("Realtek Corporation"); 2913 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 2914 MODULE_LICENSE("Dual BSD/GPL"); 2915