1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #include "coex.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852a.h"
11 #include "rtw8852a_rfk.h"
12 #include "rtw8852a_table.h"
13 #include "txrx.h"
14 
15 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
16 	{128, 1896, grp_0}, /* ACH 0 */
17 	{128, 1896, grp_0}, /* ACH 1 */
18 	{128, 1896, grp_0}, /* ACH 2 */
19 	{128, 1896, grp_0}, /* ACH 3 */
20 	{128, 1896, grp_1}, /* ACH 4 */
21 	{128, 1896, grp_1}, /* ACH 5 */
22 	{128, 1896, grp_1}, /* ACH 6 */
23 	{128, 1896, grp_1}, /* ACH 7 */
24 	{32, 1896, grp_0}, /* B0MGQ */
25 	{128, 1896, grp_0}, /* B0HIQ */
26 	{32, 1896, grp_1}, /* B1MGQ */
27 	{128, 1896, grp_1}, /* B1HIQ */
28 	{40, 0, 0} /* FWCMDQ */
29 };
30 
31 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = {
32 	1896, /* Group 0 */
33 	1896, /* Group 1 */
34 	3792, /* Public Max */
35 	0 /* WP threshold */
36 };
37 
38 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = {
39 	[RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie,
40 			   &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
41 	[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
42 			    RTW89_HCIFC_POH},
43 	[RTW89_QTA_INVALID] = {NULL},
44 };
45 
46 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {
47 	[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0,
48 			   &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
49 			   &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
50 			   &rtw89_mac_size.ple_qt5},
51 	[RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
52 			   &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
53 			   &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
54 			   &rtw89_mac_size.ple_qt_52a_wow},
55 	[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
56 			    &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
57 			    &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
58 			    &rtw89_mac_size.ple_qt13},
59 	[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
60 			       NULL},
61 };
62 
63 static const struct rtw89_reg2_def  rtw8852a_pmac_ht20_mcs7_tbl[] = {
64 	{0x44AC, 0x00000000},
65 	{0x44B0, 0x00000000},
66 	{0x44B4, 0x00000000},
67 	{0x44B8, 0x00000000},
68 	{0x44BC, 0x00000000},
69 	{0x44C0, 0x00000000},
70 	{0x44C4, 0x00000000},
71 	{0x44C8, 0x00000000},
72 	{0x44CC, 0x00000000},
73 	{0x44D0, 0x00000000},
74 	{0x44D4, 0x00000000},
75 	{0x44D8, 0x00000000},
76 	{0x44DC, 0x00000000},
77 	{0x44E0, 0x00000000},
78 	{0x44E4, 0x00000000},
79 	{0x44E8, 0x00000000},
80 	{0x44EC, 0x00000000},
81 	{0x44F0, 0x00000000},
82 	{0x44F4, 0x00000000},
83 	{0x44F8, 0x00000000},
84 	{0x44FC, 0x00000000},
85 	{0x4500, 0x00000000},
86 	{0x4504, 0x00000000},
87 	{0x4508, 0x00000000},
88 	{0x450C, 0x00000000},
89 	{0x4510, 0x00000000},
90 	{0x4514, 0x00000000},
91 	{0x4518, 0x00000000},
92 	{0x451C, 0x00000000},
93 	{0x4520, 0x00000000},
94 	{0x4524, 0x00000000},
95 	{0x4528, 0x00000000},
96 	{0x452C, 0x00000000},
97 	{0x4530, 0x4E1F3E81},
98 	{0x4534, 0x00000000},
99 	{0x4538, 0x0000005A},
100 	{0x453C, 0x00000000},
101 	{0x4540, 0x00000000},
102 	{0x4544, 0x00000000},
103 	{0x4548, 0x00000000},
104 	{0x454C, 0x00000000},
105 	{0x4550, 0x00000000},
106 	{0x4554, 0x00000000},
107 	{0x4558, 0x00000000},
108 	{0x455C, 0x00000000},
109 	{0x4560, 0x4060001A},
110 	{0x4564, 0x40000000},
111 	{0x4568, 0x00000000},
112 	{0x456C, 0x00000000},
113 	{0x4570, 0x04000007},
114 	{0x4574, 0x0000DC87},
115 	{0x4578, 0x00000BAB},
116 	{0x457C, 0x03E00000},
117 	{0x4580, 0x00000048},
118 	{0x4584, 0x00000000},
119 	{0x4588, 0x000003E8},
120 	{0x458C, 0x30000000},
121 	{0x4590, 0x00000000},
122 	{0x4594, 0x10000000},
123 	{0x4598, 0x00000001},
124 	{0x459C, 0x00030000},
125 	{0x45A0, 0x01000000},
126 	{0x45A4, 0x03000200},
127 	{0x45A8, 0xC00001C0},
128 	{0x45AC, 0x78018000},
129 	{0x45B0, 0x80000000},
130 	{0x45B4, 0x01C80600},
131 	{0x45B8, 0x00000002},
132 	{0x4594, 0x10000000}
133 };
134 
135 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = {
136 	{0x4624, GENMASK(20, 14), 0x40},
137 	{0x46f8, GENMASK(20, 14), 0x40},
138 	{0x4674, GENMASK(20, 19), 0x2},
139 	{0x4748, GENMASK(20, 19), 0x2},
140 	{0x4650, GENMASK(14, 10), 0x18},
141 	{0x4724, GENMASK(14, 10), 0x18},
142 	{0x4688, GENMASK(1, 0), 0x3},
143 	{0x475c, GENMASK(1, 0), 0x3},
144 };
145 
146 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs);
147 
148 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = {
149 	{0x4624, GENMASK(20, 14), 0x1a},
150 	{0x46f8, GENMASK(20, 14), 0x1a},
151 	{0x4674, GENMASK(20, 19), 0x1},
152 	{0x4748, GENMASK(20, 19), 0x1},
153 	{0x4650, GENMASK(14, 10), 0x12},
154 	{0x4724, GENMASK(14, 10), 0x12},
155 	{0x4688, GENMASK(1, 0), 0x0},
156 	{0x475c, GENMASK(1, 0), 0x0},
157 };
158 
159 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs);
160 
161 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = {
162 	{0x00C6,
163 	 PWR_CV_MSK_B,
164 	 PWR_INTF_MSK_PCIE,
165 	 PWR_BASE_MAC,
166 	 PWR_CMD_WRITE, BIT(6), BIT(6)},
167 	{0x1086,
168 	 PWR_CV_MSK_ALL,
169 	 PWR_INTF_MSK_SDIO,
170 	 PWR_BASE_MAC,
171 	 PWR_CMD_WRITE, BIT(0), 0},
172 	{0x1086,
173 	 PWR_CV_MSK_ALL,
174 	 PWR_INTF_MSK_SDIO,
175 	 PWR_BASE_MAC,
176 	 PWR_CMD_POLL, BIT(1), BIT(1)},
177 	{0x0005,
178 	 PWR_CV_MSK_ALL,
179 	 PWR_INTF_MSK_ALL,
180 	 PWR_BASE_MAC,
181 	 PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
182 	{0x0005,
183 	 PWR_CV_MSK_ALL,
184 	 PWR_INTF_MSK_ALL,
185 	 PWR_BASE_MAC,
186 	 PWR_CMD_WRITE, BIT(7), 0},
187 	{0x0005,
188 	 PWR_CV_MSK_ALL,
189 	 PWR_INTF_MSK_ALL,
190 	 PWR_BASE_MAC,
191 	 PWR_CMD_WRITE, BIT(2), 0},
192 	{0x0006,
193 	 PWR_CV_MSK_ALL,
194 	 PWR_INTF_MSK_ALL,
195 	 PWR_BASE_MAC,
196 	 PWR_CMD_POLL, BIT(1), BIT(1)},
197 	{0x0006,
198 	 PWR_CV_MSK_ALL,
199 	 PWR_INTF_MSK_ALL,
200 	 PWR_BASE_MAC,
201 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
202 	{0x0005,
203 	 PWR_CV_MSK_ALL,
204 	 PWR_INTF_MSK_ALL,
205 	 PWR_BASE_MAC,
206 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
207 	{0x0005,
208 	 PWR_CV_MSK_ALL,
209 	 PWR_INTF_MSK_ALL,
210 	 PWR_BASE_MAC,
211 	 PWR_CMD_POLL, BIT(0), 0},
212 	{0x106D,
213 	 PWR_CV_MSK_B | PWR_CV_MSK_C,
214 	 PWR_INTF_MSK_USB,
215 	 PWR_BASE_MAC,
216 	 PWR_CMD_WRITE, BIT(6), 0},
217 	{0x0088,
218 	 PWR_CV_MSK_ALL,
219 	 PWR_INTF_MSK_ALL,
220 	 PWR_BASE_MAC,
221 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
222 	{0x0088,
223 	 PWR_CV_MSK_ALL,
224 	 PWR_INTF_MSK_ALL,
225 	 PWR_BASE_MAC,
226 	 PWR_CMD_WRITE, BIT(0), 0},
227 	{0x0088,
228 	 PWR_CV_MSK_ALL,
229 	 PWR_INTF_MSK_ALL,
230 	 PWR_BASE_MAC,
231 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
232 	{0x0088,
233 	 PWR_CV_MSK_ALL,
234 	 PWR_INTF_MSK_ALL,
235 	 PWR_BASE_MAC,
236 	 PWR_CMD_WRITE, BIT(0), 0},
237 	{0x0088,
238 	 PWR_CV_MSK_ALL,
239 	 PWR_INTF_MSK_ALL,
240 	 PWR_BASE_MAC,
241 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
242 	{0x0083,
243 	 PWR_CV_MSK_ALL,
244 	 PWR_INTF_MSK_ALL,
245 	 PWR_BASE_MAC,
246 	 PWR_CMD_WRITE, BIT(6), 0},
247 	{0x0080,
248 	 PWR_CV_MSK_ALL,
249 	 PWR_INTF_MSK_ALL,
250 	 PWR_BASE_MAC,
251 	 PWR_CMD_WRITE, BIT(5), BIT(5)},
252 	{0x0024,
253 	 PWR_CV_MSK_ALL,
254 	 PWR_INTF_MSK_ALL,
255 	 PWR_BASE_MAC,
256 	 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
257 	{0x02A0,
258 	 PWR_CV_MSK_ALL,
259 	 PWR_INTF_MSK_ALL,
260 	 PWR_BASE_MAC,
261 	 PWR_CMD_WRITE, BIT(1), BIT(1)},
262 	{0x02A2,
263 	 PWR_CV_MSK_ALL,
264 	 PWR_INTF_MSK_ALL,
265 	 PWR_BASE_MAC,
266 	 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
267 	{0x0071,
268 	 PWR_CV_MSK_ALL,
269 	 PWR_INTF_MSK_PCIE,
270 	 PWR_BASE_MAC,
271 	 PWR_CMD_WRITE, BIT(4), 0},
272 	{0x0010,
273 	 PWR_CV_MSK_A,
274 	 PWR_INTF_MSK_PCIE,
275 	 PWR_BASE_MAC,
276 	 PWR_CMD_WRITE, BIT(2), BIT(2)},
277 	{0x02A0,
278 	 PWR_CV_MSK_A,
279 	 PWR_INTF_MSK_ALL,
280 	 PWR_BASE_MAC,
281 	 PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
282 	{0xFFFF,
283 	 PWR_CV_MSK_ALL,
284 	 PWR_INTF_MSK_ALL,
285 	 0,
286 	 PWR_CMD_END, 0, 0},
287 };
288 
289 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = {
290 	{0x02F0,
291 	 PWR_CV_MSK_ALL,
292 	 PWR_INTF_MSK_ALL,
293 	 PWR_BASE_MAC,
294 	 PWR_CMD_WRITE, 0xFF, 0},
295 	{0x02F1,
296 	 PWR_CV_MSK_ALL,
297 	 PWR_INTF_MSK_ALL,
298 	 PWR_BASE_MAC,
299 	 PWR_CMD_WRITE, 0xFF, 0},
300 	{0x0006,
301 	 PWR_CV_MSK_ALL,
302 	 PWR_INTF_MSK_ALL,
303 	 PWR_BASE_MAC,
304 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
305 	{0x0002,
306 	 PWR_CV_MSK_ALL,
307 	 PWR_INTF_MSK_ALL,
308 	 PWR_BASE_MAC,
309 	 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
310 	{0x0082,
311 	 PWR_CV_MSK_ALL,
312 	 PWR_INTF_MSK_ALL,
313 	 PWR_BASE_MAC,
314 	 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
315 	{0x106D,
316 	 PWR_CV_MSK_B | PWR_CV_MSK_C,
317 	 PWR_INTF_MSK_USB,
318 	 PWR_BASE_MAC,
319 	 PWR_CMD_WRITE, BIT(6), BIT(6)},
320 	{0x0005,
321 	 PWR_CV_MSK_ALL,
322 	 PWR_INTF_MSK_ALL,
323 	 PWR_BASE_MAC,
324 	 PWR_CMD_WRITE, BIT(1), BIT(1)},
325 	{0x0005,
326 	 PWR_CV_MSK_ALL,
327 	 PWR_INTF_MSK_ALL,
328 	 PWR_BASE_MAC,
329 	 PWR_CMD_POLL, BIT(1), 0},
330 	{0x0091,
331 	 PWR_CV_MSK_ALL,
332 	 PWR_INTF_MSK_PCIE,
333 	 PWR_BASE_MAC,
334 	 PWR_CMD_WRITE, BIT(0), 0},
335 	{0x0005,
336 	 PWR_CV_MSK_ALL,
337 	 PWR_INTF_MSK_PCIE,
338 	 PWR_BASE_MAC,
339 	 PWR_CMD_WRITE, BIT(2), BIT(2)},
340 	{0x0007,
341 	 PWR_CV_MSK_ALL,
342 	 PWR_INTF_MSK_USB,
343 	 PWR_BASE_MAC,
344 	 PWR_CMD_WRITE, BIT(4), 0},
345 	{0x0007,
346 	 PWR_CV_MSK_ALL,
347 	 PWR_INTF_MSK_SDIO,
348 	 PWR_BASE_MAC,
349 	 PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
350 	{0x0005,
351 	 PWR_CV_MSK_ALL,
352 	 PWR_INTF_MSK_SDIO,
353 	 PWR_BASE_MAC,
354 	 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
355 	{0x0005,
356 	 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F |
357 	 PWR_CV_MSK_G,
358 	 PWR_INTF_MSK_USB,
359 	 PWR_BASE_MAC,
360 	 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
361 	{0x1086,
362 	 PWR_CV_MSK_ALL,
363 	 PWR_INTF_MSK_SDIO,
364 	 PWR_BASE_MAC,
365 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
366 	{0x1086,
367 	 PWR_CV_MSK_ALL,
368 	 PWR_INTF_MSK_SDIO,
369 	 PWR_BASE_MAC,
370 	 PWR_CMD_POLL, BIT(1), 0},
371 	{0xFFFF,
372 	 PWR_CV_MSK_ALL,
373 	 PWR_INTF_MSK_ALL,
374 	 0,
375 	 PWR_CMD_END, 0, 0},
376 };
377 
378 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = {
379 	rtw8852a_pwron, NULL
380 };
381 
382 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = {
383 	rtw8852a_pwroff, NULL
384 };
385 
386 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = {
387 	R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1,  R_AX_H2CREG_DATA2,
388 	R_AX_H2CREG_DATA3
389 };
390 
391 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
392 	R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
393 	R_AX_C2HREG_DATA3
394 };
395 
396 static const struct rtw89_page_regs rtw8852a_page_regs = {
397 	.hci_fc_ctrl	= R_AX_HCI_FC_CTRL,
398 	.ch_page_ctrl	= R_AX_CH_PAGE_CTRL,
399 	.ach_page_ctrl	= R_AX_ACH0_PAGE_CTRL,
400 	.ach_page_info	= R_AX_ACH0_PAGE_INFO,
401 	.pub_page_info3	= R_AX_PUB_PAGE_INFO3,
402 	.pub_page_ctrl1	= R_AX_PUB_PAGE_CTRL1,
403 	.pub_page_ctrl2	= R_AX_PUB_PAGE_CTRL2,
404 	.pub_page_info1	= R_AX_PUB_PAGE_INFO1,
405 	.pub_page_info2 = R_AX_PUB_PAGE_INFO2,
406 	.wp_page_ctrl1	= R_AX_WP_PAGE_CTRL1,
407 	.wp_page_ctrl2	= R_AX_WP_PAGE_CTRL2,
408 	.wp_page_info1	= R_AX_WP_PAGE_INFO1,
409 };
410 
411 static const struct rtw89_reg_def rtw8852a_dcfo_comp = {
412 	R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
413 };
414 
415 static const struct rtw89_imr_info rtw8852a_imr_info = {
416 	.wdrls_imr_set		= B_AX_WDRLS_IMR_SET,
417 	.wsec_imr_reg		= R_AX_SEC_DEBUG,
418 	.wsec_imr_set		= B_AX_IMR_ERROR,
419 	.mpdu_tx_imr_set	= 0,
420 	.mpdu_rx_imr_set	= 0,
421 	.sta_sch_imr_set	= B_AX_STA_SCHEDULER_IMR_SET,
422 	.txpktctl_imr_b0_reg	= R_AX_TXPKTCTL_ERR_IMR_ISR,
423 	.txpktctl_imr_b0_clr	= B_AX_TXPKTCTL_IMR_B0_CLR,
424 	.txpktctl_imr_b0_set	= B_AX_TXPKTCTL_IMR_B0_SET,
425 	.txpktctl_imr_b1_reg	= R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
426 	.txpktctl_imr_b1_clr	= B_AX_TXPKTCTL_IMR_B1_CLR,
427 	.txpktctl_imr_b1_set	= B_AX_TXPKTCTL_IMR_B1_SET,
428 	.wde_imr_clr		= B_AX_WDE_IMR_CLR,
429 	.wde_imr_set		= B_AX_WDE_IMR_SET,
430 	.ple_imr_clr		= B_AX_PLE_IMR_CLR,
431 	.ple_imr_set		= B_AX_PLE_IMR_SET,
432 	.host_disp_imr_clr	= B_AX_HOST_DISP_IMR_CLR,
433 	.host_disp_imr_set	= B_AX_HOST_DISP_IMR_SET,
434 	.cpu_disp_imr_clr	= B_AX_CPU_DISP_IMR_CLR,
435 	.cpu_disp_imr_set	= B_AX_CPU_DISP_IMR_SET,
436 	.other_disp_imr_clr	= B_AX_OTHER_DISP_IMR_CLR,
437 	.other_disp_imr_set	= 0,
438 	.bbrpt_com_err_imr_reg	= R_AX_BBRPT_COM_ERR_IMR_ISR,
439 	.bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
440 	.bbrpt_err_imr_set	= 0,
441 	.bbrpt_dfs_err_imr_reg	= R_AX_BBRPT_DFS_ERR_IMR_ISR,
442 	.ptcl_imr_clr		= B_AX_PTCL_IMR_CLR,
443 	.ptcl_imr_set		= B_AX_PTCL_IMR_SET,
444 	.cdma_imr_0_reg		= R_AX_DLE_CTRL,
445 	.cdma_imr_0_clr		= B_AX_DLE_IMR_CLR,
446 	.cdma_imr_0_set		= B_AX_DLE_IMR_SET,
447 	.cdma_imr_1_reg		= 0,
448 	.cdma_imr_1_clr		= 0,
449 	.cdma_imr_1_set		= 0,
450 	.phy_intf_imr_reg	= R_AX_PHYINFO_ERR_IMR,
451 	.phy_intf_imr_clr	= 0,
452 	.phy_intf_imr_set	= 0,
453 	.rmac_imr_reg		= R_AX_RMAC_ERR_ISR,
454 	.rmac_imr_clr		= B_AX_RMAC_IMR_CLR,
455 	.rmac_imr_set		= B_AX_RMAC_IMR_SET,
456 	.tmac_imr_reg		= R_AX_TMAC_ERR_IMR_ISR,
457 	.tmac_imr_clr		= B_AX_TMAC_IMR_CLR,
458 	.tmac_imr_set		= B_AX_TMAC_IMR_SET,
459 };
460 
461 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
462 	.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
463 	.rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
464 };
465 
466 static const struct rtw89_dig_regs rtw8852a_dig_regs = {
467 	.seg0_pd_reg = R_SEG0R_PD,
468 	.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
469 	.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
470 	.p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK},
471 	.p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK},
472 	.p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK},
473 	.p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK},
474 	.p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK},
475 	.p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK},
476 	.p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC,
477 			      B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
478 	.p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC,
479 			      B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
480 	.p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC,
481 			      B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
482 	.p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC,
483 			      B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
484 };
485 
486 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
487 				    struct rtw8852a_efuse *map)
488 {
489 	ether_addr_copy(efuse->addr, map->e.mac_addr);
490 	efuse->rfe_type = map->rfe_type;
491 	efuse->xtal_cap = map->xtal_k;
492 }
493 
494 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
495 					struct rtw8852a_efuse *map)
496 {
497 	struct rtw89_tssi_info *tssi = &rtwdev->tssi;
498 	struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
499 	u8 i, j;
500 
501 	tssi->thermal[RF_PATH_A] = map->path_a_therm;
502 	tssi->thermal[RF_PATH_B] = map->path_b_therm;
503 
504 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
505 		memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
506 		       sizeof(ofst[i]->cck_tssi));
507 
508 		for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
509 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
510 				    "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
511 				    i, j, tssi->tssi_cck[i][j]);
512 
513 		memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
514 		       sizeof(ofst[i]->bw40_tssi));
515 		memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
516 		       ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
517 
518 		for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
519 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
520 				    "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
521 				    i, j, tssi->tssi_mcs[i][j]);
522 	}
523 }
524 
525 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
526 {
527 	struct rtw89_efuse *efuse = &rtwdev->efuse;
528 	struct rtw8852a_efuse *map;
529 
530 	map = (struct rtw8852a_efuse *)log_map;
531 
532 	efuse->country_code[0] = map->country_code[0];
533 	efuse->country_code[1] = map->country_code[1];
534 	rtw8852a_efuse_parsing_tssi(rtwdev, map);
535 
536 	switch (rtwdev->hci.type) {
537 	case RTW89_HCI_TYPE_PCIE:
538 		rtw8852ae_efuse_parsing(efuse, map);
539 		break;
540 	default:
541 		return -ENOTSUPP;
542 	}
543 
544 	rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
545 
546 	return 0;
547 }
548 
549 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
550 {
551 	struct rtw89_tssi_info *tssi = &rtwdev->tssi;
552 	static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB};
553 	u32 addr = rtwdev->chip->phycap_addr;
554 	bool pg = false;
555 	u32 ofst;
556 	u8 i, j;
557 
558 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
559 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
560 			/* addrs are in decreasing order */
561 			ofst = tssi_trim_addr[i] - addr - j;
562 			tssi->tssi_trim[i][j] = phycap_map[ofst];
563 
564 			if (phycap_map[ofst] != 0xff)
565 				pg = true;
566 		}
567 	}
568 
569 	if (!pg) {
570 		memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
571 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
572 			    "[TSSI][TRIM] no PG, set all trim info to 0\n");
573 	}
574 
575 	for (i = 0; i < RF_PATH_NUM_8852A; i++)
576 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
577 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
578 				    "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
579 				    i, j, tssi->tssi_trim[i][j],
580 				    tssi_trim_addr[i] - j);
581 }
582 
583 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
584 						 u8 *phycap_map)
585 {
586 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
587 	static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC};
588 	u32 addr = rtwdev->chip->phycap_addr;
589 	u8 i;
590 
591 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
592 		info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
593 
594 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
595 			    "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
596 			    i, info->thermal_trim[i]);
597 
598 		if (info->thermal_trim[i] != 0xff)
599 			info->pg_thermal_trim = true;
600 	}
601 }
602 
603 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
604 {
605 #define __thm_setting(raw)				\
606 ({							\
607 	u8 __v = (raw);					\
608 	((__v & 0x1) << 3) | ((__v & 0x1f) >> 1);	\
609 })
610 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
611 	u8 i, val;
612 
613 	if (!info->pg_thermal_trim) {
614 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
615 			    "[THERMAL][TRIM] no PG, do nothing\n");
616 
617 		return;
618 	}
619 
620 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
621 		val = __thm_setting(info->thermal_trim[i]);
622 		rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
623 
624 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
625 			    "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
626 			    i, val);
627 	}
628 #undef __thm_setting
629 }
630 
631 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
632 						 u8 *phycap_map)
633 {
634 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
635 	static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB};
636 	u32 addr = rtwdev->chip->phycap_addr;
637 	u8 i;
638 
639 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
640 		info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
641 
642 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
643 			    "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
644 			    i, info->pa_bias_trim[i]);
645 
646 		if (info->pa_bias_trim[i] != 0xff)
647 			info->pg_pa_bias_trim = true;
648 	}
649 }
650 
651 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
652 {
653 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
654 	u8 pabias_2g, pabias_5g;
655 	u8 i;
656 
657 	if (!info->pg_pa_bias_trim) {
658 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
659 			    "[PA_BIAS][TRIM] no PG, do nothing\n");
660 
661 		return;
662 	}
663 
664 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {
665 		pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
666 		pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
667 
668 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
669 			    "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
670 			    i, pabias_2g, pabias_5g);
671 
672 		rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
673 		rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
674 	}
675 }
676 
677 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
678 {
679 	rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
680 	rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
681 	rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
682 
683 	return 0;
684 }
685 
686 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
687 {
688 	rtw8852a_thermal_trim(rtwdev);
689 	rtw8852a_pa_bias_trim(rtwdev);
690 }
691 
692 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
693 				     const struct rtw89_chan *chan,
694 				     u8 mac_idx)
695 {
696 	u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
697 	u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE,
698 					     mac_idx);
699 	u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
700 	u8 txsc20 = 0, txsc40 = 0;
701 
702 	switch (chan->band_width) {
703 	case RTW89_CHANNEL_WIDTH_80:
704 		txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
705 					    RTW89_CHANNEL_WIDTH_40);
706 		fallthrough;
707 	case RTW89_CHANNEL_WIDTH_40:
708 		txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
709 					    RTW89_CHANNEL_WIDTH_20);
710 		break;
711 	default:
712 		break;
713 	}
714 
715 	switch (chan->band_width) {
716 	case RTW89_CHANNEL_WIDTH_80:
717 		rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
718 		rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
719 		break;
720 	case RTW89_CHANNEL_WIDTH_40:
721 		rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
722 		rtw89_write32(rtwdev, sub_carr, txsc20);
723 		break;
724 	case RTW89_CHANNEL_WIDTH_20:
725 		rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
726 		rtw89_write32(rtwdev, sub_carr, 0);
727 		break;
728 	default:
729 		break;
730 	}
731 
732 	if (chan->channel > 14)
733 		rtw89_write8_set(rtwdev, chk_rate,
734 				 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
735 	else
736 		rtw89_write8_clr(rtwdev, chk_rate,
737 				 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
738 }
739 
740 static const u32 rtw8852a_sco_barker_threshold[14] = {
741 	0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
742 	0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
743 };
744 
745 static const u32 rtw8852a_sco_cck_threshold[14] = {
746 	0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
747 	0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
748 };
749 
750 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
751 				 u8 primary_ch, enum rtw89_bandwidth bw)
752 {
753 	u8 ch_element;
754 
755 	if (bw == RTW89_CHANNEL_WIDTH_20) {
756 		ch_element = central_ch - 1;
757 	} else if (bw == RTW89_CHANNEL_WIDTH_40) {
758 		if (primary_ch == 1)
759 			ch_element = central_ch - 1 + 2;
760 		else
761 			ch_element = central_ch - 1 - 2;
762 	} else {
763 		rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
764 		return -EINVAL;
765 	}
766 	rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
767 			       rtw8852a_sco_barker_threshold[ch_element]);
768 	rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
769 			       rtw8852a_sco_cck_threshold[ch_element]);
770 
771 	return 0;
772 }
773 
774 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
775 				u8 path)
776 {
777 	u32 val;
778 
779 	val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
780 	if (val == INV_RF_DATA) {
781 		rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
782 		return;
783 	}
784 	val &= ~0x303ff;
785 	val |= central_ch;
786 	if (central_ch > 14)
787 		val |= (BIT(16) | BIT(8));
788 	rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
789 }
790 
791 static u8 rtw8852a_sco_mapping(u8 central_ch)
792 {
793 	if (central_ch == 1)
794 		return 109;
795 	else if (central_ch >= 2 && central_ch <= 6)
796 		return 108;
797 	else if (central_ch >= 7 && central_ch <= 10)
798 		return 107;
799 	else if (central_ch >= 11 && central_ch <= 14)
800 		return 106;
801 	else if (central_ch == 36 || central_ch == 38)
802 		return 51;
803 	else if (central_ch >= 40 && central_ch <= 58)
804 		return 50;
805 	else if (central_ch >= 60 && central_ch <= 64)
806 		return 49;
807 	else if (central_ch == 100 || central_ch == 102)
808 		return 48;
809 	else if (central_ch >= 104 && central_ch <= 126)
810 		return 47;
811 	else if (central_ch >= 128 && central_ch <= 151)
812 		return 46;
813 	else if (central_ch >= 153 && central_ch <= 177)
814 		return 45;
815 	else
816 		return 0;
817 }
818 
819 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
820 			     enum rtw89_phy_idx phy_idx)
821 {
822 	u8 sco_comp;
823 	bool is_2g = central_ch <= 14;
824 
825 	if (phy_idx == RTW89_PHY_0) {
826 		/* Path A */
827 		rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A);
828 		if (is_2g)
829 			rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
830 					      B_PATH0_TIA_ERR_G1_SEL, 1,
831 					      phy_idx);
832 		else
833 			rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
834 					      B_PATH0_TIA_ERR_G1_SEL, 0,
835 					      phy_idx);
836 
837 		/* Path B */
838 		if (!rtwdev->dbcc_en) {
839 			rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
840 			if (is_2g)
841 				rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
842 						      B_P1_MODE_SEL,
843 						      1, phy_idx);
844 			else
845 				rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
846 						      B_P1_MODE_SEL,
847 						      0, phy_idx);
848 		} else {
849 			if (is_2g)
850 				rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
851 						      B_2P4G_BAND_SEL);
852 			else
853 				rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
854 						      B_2P4G_BAND_SEL);
855 		}
856 		/* SCO compensate FC setting */
857 		sco_comp = rtw8852a_sco_mapping(central_ch);
858 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
859 				      sco_comp, phy_idx);
860 	} else {
861 		/* Path B */
862 		rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
863 		if (is_2g)
864 			rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
865 					      B_P1_MODE_SEL,
866 					      1, phy_idx);
867 		else
868 			rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
869 					      B_P1_MODE_SEL,
870 					      0, phy_idx);
871 		/* SCO compensate FC setting */
872 		sco_comp = rtw8852a_sco_mapping(central_ch);
873 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
874 				      sco_comp, phy_idx);
875 	}
876 
877 	/* Band edge */
878 	if (is_2g)
879 		rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1,
880 				      phy_idx);
881 	else
882 		rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,
883 				      phy_idx);
884 
885 	/* CCK parameters */
886 	if (central_ch == 14) {
887 		rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
888 				       0x3b13ff);
889 		rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
890 				       0x1c42de);
891 		rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
892 				       0xfdb0ad);
893 		rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
894 				       0xf60f6e);
895 		rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
896 				       0xfd8f92);
897 		rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
898 		rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
899 		rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
900 				       0xfff00a);
901 	} else {
902 		rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
903 				       0x3d23ff);
904 		rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
905 				       0x29b354);
906 		rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
907 		rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
908 				       0xfdb053);
909 		rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
910 				       0xf86f9a);
911 		rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
912 				       0xfaef92);
913 		rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
914 				       0xfe5fcc);
915 		rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
916 				       0xffdff5);
917 	}
918 }
919 
920 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
921 {
922 	u32 val = 0;
923 	u32 adc_sel[2] = {0x12d0, 0x32d0};
924 	u32 wbadc_sel[2] = {0x12ec, 0x32ec};
925 
926 	val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
927 	if (val == INV_RF_DATA) {
928 		rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
929 		return;
930 	}
931 	val &= ~(BIT(11) | BIT(10));
932 	switch (bw) {
933 	case RTW89_CHANNEL_WIDTH_5:
934 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
935 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
936 		val |= (BIT(11) | BIT(10));
937 		break;
938 	case RTW89_CHANNEL_WIDTH_10:
939 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
940 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
941 		val |= (BIT(11) | BIT(10));
942 		break;
943 	case RTW89_CHANNEL_WIDTH_20:
944 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
945 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
946 		val |= (BIT(11) | BIT(10));
947 		break;
948 	case RTW89_CHANNEL_WIDTH_40:
949 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
950 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
951 		val |= BIT(11);
952 		break;
953 	case RTW89_CHANNEL_WIDTH_80:
954 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
955 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
956 		val |= BIT(10);
957 		break;
958 	default:
959 		rtw89_warn(rtwdev, "Fail to set ADC\n");
960 	}
961 
962 	rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
963 }
964 
965 static void
966 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
967 		 enum rtw89_phy_idx phy_idx)
968 {
969 	/* Switch bandwidth */
970 	switch (bw) {
971 	case RTW89_CHANNEL_WIDTH_5:
972 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
973 				      phy_idx);
974 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1,
975 				      phy_idx);
976 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
977 				      0x0, phy_idx);
978 		break;
979 	case RTW89_CHANNEL_WIDTH_10:
980 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
981 				      phy_idx);
982 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2,
983 				      phy_idx);
984 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
985 				      0x0, phy_idx);
986 		break;
987 	case RTW89_CHANNEL_WIDTH_20:
988 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
989 				      phy_idx);
990 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
991 				      phy_idx);
992 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
993 				      0x0, phy_idx);
994 		break;
995 	case RTW89_CHANNEL_WIDTH_40:
996 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
997 				      phy_idx);
998 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
999 				      phy_idx);
1000 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1001 				      pri_ch,
1002 				      phy_idx);
1003 		if (pri_ch == RTW89_SC_20_UPPER)
1004 			rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1005 		else
1006 			rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1007 		break;
1008 	case RTW89_CHANNEL_WIDTH_80:
1009 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1010 				      phy_idx);
1011 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1012 				      phy_idx);
1013 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1014 				      pri_ch,
1015 				      phy_idx);
1016 		break;
1017 	default:
1018 		rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1019 			   pri_ch);
1020 	}
1021 
1022 	if (phy_idx == RTW89_PHY_0) {
1023 		rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A);
1024 		if (!rtwdev->dbcc_en)
1025 			rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1026 	} else {
1027 		rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1028 	}
1029 }
1030 
1031 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)
1032 {
1033 	if (central_ch == 153) {
1034 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1035 				       0x210);
1036 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1037 				       0x210);
1038 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0);
1039 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1040 				       B_P0_NBIIDX_NOTCH_EN, 0x1);
1041 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1042 				       B_P1_NBIIDX_NOTCH_EN, 0x1);
1043 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1044 				       0x1);
1045 	} else if (central_ch == 151) {
1046 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1047 				       0x210);
1048 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1049 				       0x210);
1050 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40);
1051 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1052 				       B_P0_NBIIDX_NOTCH_EN, 0x1);
1053 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1054 				       B_P1_NBIIDX_NOTCH_EN, 0x1);
1055 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1056 				       0x1);
1057 	} else if (central_ch == 155) {
1058 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1059 				       0x2d0);
1060 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1061 				       0x2d0);
1062 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740);
1063 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1064 				       B_P0_NBIIDX_NOTCH_EN, 0x1);
1065 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1066 				       B_P1_NBIIDX_NOTCH_EN, 0x1);
1067 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1068 				       0x1);
1069 	} else {
1070 		rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1071 				       B_P0_NBIIDX_NOTCH_EN, 0x0);
1072 		rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1073 				       B_P1_NBIIDX_NOTCH_EN, 0x0);
1074 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1075 				       0x0);
1076 	}
1077 }
1078 
1079 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,
1080 				  enum rtw89_phy_idx phy_idx)
1081 {
1082 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1083 			      phy_idx);
1084 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1085 			      phy_idx);
1086 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1087 			      phy_idx);
1088 }
1089 
1090 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,
1091 				 enum rtw89_phy_idx phy_idx, bool en)
1092 {
1093 	if (en)
1094 		rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1095 				      1,
1096 				      phy_idx);
1097 	else
1098 		rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1099 				      0,
1100 				      phy_idx);
1101 }
1102 
1103 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,
1104 			      enum rtw89_phy_idx phy_idx)
1105 {
1106 	rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1107 	rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1108 	rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1109 	rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1110 	rtw8852a_bb_reset_all(rtwdev, phy_idx);
1111 	rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1112 	rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1113 	rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1114 	rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1115 }
1116 
1117 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1118 					enum rtw89_phy_idx phy_idx)
1119 {
1120 	u32 addr;
1121 
1122 	for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1123 	     addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1124 		rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1125 }
1126 
1127 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)
1128 {
1129 	rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1130 	rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1131 
1132 	if (rtwdev->hal.cv <= CHIP_CCV) {
1133 		rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
1134 		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);
1135 		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F);
1136 		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);
1137 		rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
1138 		rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1139 		rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1140 		rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);
1141 	}
1142 	rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);
1143 	rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);
1144 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1145 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1);
1146 	rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK);
1147 	rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
1148 
1149 	rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1150 }
1151 
1152 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,
1153 				   enum rtw89_phy_idx phy_idx)
1154 {
1155 	rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1156 	rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1157 	rtw8852a_bb_reset_all(rtwdev, phy_idx);
1158 	rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1159 	rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1160 	udelay(1);
1161 }
1162 
1163 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,
1164 				    const struct rtw89_chan *chan,
1165 				    enum rtw89_phy_idx phy_idx)
1166 {
1167 	bool cck_en = chan->channel <= 14;
1168 	u8 pri_ch_idx = chan->pri_ch_idx;
1169 
1170 	if (cck_en)
1171 		rtw8852a_ctrl_sco_cck(rtwdev, chan->channel,
1172 				      chan->primary_channel,
1173 				      chan->band_width);
1174 
1175 	rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx);
1176 	rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1177 	if (cck_en) {
1178 		rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1179 	} else {
1180 		rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1181 		rtw8852a_bbrst_for_rfk(rtwdev, phy_idx);
1182 	}
1183 	rtw8852a_spur_elimination(rtwdev, chan->channel);
1184 	rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
1185 			       chan->primary_channel);
1186 	rtw8852a_bb_reset_all(rtwdev, phy_idx);
1187 }
1188 
1189 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,
1190 				 const struct rtw89_chan *chan,
1191 				 enum rtw89_mac_idx mac_idx,
1192 				 enum rtw89_phy_idx phy_idx)
1193 {
1194 	rtw8852a_set_channel_mac(rtwdev, chan, mac_idx);
1195 	rtw8852a_set_channel_bb(rtwdev, chan, phy_idx);
1196 }
1197 
1198 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)
1199 {
1200 	if (en)
1201 		rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1202 	else
1203 		rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1204 }
1205 
1206 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1207 				  enum rtw89_rf_path path)
1208 {
1209 	static const u32 tssi_trk[2] = {0x5818, 0x7818};
1210 	static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc};
1211 
1212 	if (en) {
1213 		rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0);
1214 		rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
1215 	} else {
1216 		rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1);
1217 		rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
1218 	}
1219 }
1220 
1221 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1222 					 u8 phy_idx)
1223 {
1224 	if (!rtwdev->dbcc_en) {
1225 		rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1226 		rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1227 	} else {
1228 		if (phy_idx == RTW89_PHY_0)
1229 			rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1230 		else
1231 			rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1232 	}
1233 }
1234 
1235 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)
1236 {
1237 	if (en)
1238 		rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1239 				       0x0);
1240 	else
1241 		rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1242 				       0xf);
1243 }
1244 
1245 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1246 				      struct rtw89_channel_help_params *p,
1247 				      const struct rtw89_chan *chan,
1248 				      enum rtw89_mac_idx mac_idx,
1249 				      enum rtw89_phy_idx phy_idx)
1250 {
1251 	if (enter) {
1252 		rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1253 				       RTW89_SCH_TX_SEL_ALL);
1254 		rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1255 		rtw8852a_dfs_en(rtwdev, false);
1256 		rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
1257 		rtw8852a_adc_en(rtwdev, false);
1258 		fsleep(40);
1259 		rtw8852a_bb_reset_en(rtwdev, phy_idx, false);
1260 	} else {
1261 		rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1262 		rtw8852a_adc_en(rtwdev, true);
1263 		rtw8852a_dfs_en(rtwdev, true);
1264 		rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
1265 		rtw8852a_bb_reset_en(rtwdev, phy_idx, true);
1266 		rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1267 	}
1268 }
1269 
1270 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)
1271 {
1272 	struct rtw89_efuse *efuse = &rtwdev->efuse;
1273 
1274 	switch (efuse->rfe_type) {
1275 	case 11:
1276 	case 12:
1277 	case 17:
1278 	case 18:
1279 	case 51:
1280 	case 53:
1281 		rtwdev->fem.epa_2g = true;
1282 		rtwdev->fem.elna_2g = true;
1283 		fallthrough;
1284 	case 9:
1285 	case 10:
1286 	case 15:
1287 	case 16:
1288 		rtwdev->fem.epa_5g = true;
1289 		rtwdev->fem.elna_5g = true;
1290 		break;
1291 	default:
1292 		break;
1293 	}
1294 }
1295 
1296 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)
1297 {
1298 	rtwdev->is_tssi_mode[RF_PATH_A] = false;
1299 	rtwdev->is_tssi_mode[RF_PATH_B] = false;
1300 
1301 	rtw8852a_rck(rtwdev);
1302 	rtw8852a_dack(rtwdev);
1303 	rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true);
1304 }
1305 
1306 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev)
1307 {
1308 	enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1309 
1310 	rtw8852a_rx_dck(rtwdev, phy_idx, true);
1311 	rtw8852a_iqk(rtwdev, phy_idx);
1312 	rtw8852a_tssi(rtwdev, phy_idx);
1313 	rtw8852a_dpk(rtwdev, phy_idx);
1314 }
1315 
1316 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev,
1317 				      enum rtw89_phy_idx phy_idx)
1318 {
1319 	rtw8852a_tssi_scan(rtwdev, phy_idx);
1320 }
1321 
1322 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1323 {
1324 	rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1325 }
1326 
1327 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
1328 {
1329 	rtw8852a_dpk_track(rtwdev);
1330 	rtw8852a_iqk_track(rtwdev);
1331 	rtw8852a_tssi_track(rtwdev);
1332 }
1333 
1334 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1335 				     enum rtw89_phy_idx phy_idx, s16 ref)
1336 {
1337 	s8 ofst_int = 0;
1338 	u8 base_cw_0db = 0x27;
1339 	u16 tssi_16dbm_cw = 0x12c;
1340 	s16 pwr_s10_3 = 0;
1341 	s16 rf_pwr_cw = 0;
1342 	u16 bb_pwr_cw = 0;
1343 	u32 pwr_cw = 0;
1344 	u32 tssi_ofst_cw = 0;
1345 
1346 	pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1347 	bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1348 	rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1349 	rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1350 	pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1351 
1352 	tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1353 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1354 		    "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1355 		    tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1356 
1357 	return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
1358 }
1359 
1360 static
1361 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1362 				     s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1363 {
1364 	s8 val_1t = 0;
1365 	s8 val_2t = 0;
1366 	u32 reg;
1367 
1368 	if (pw_ofst < -16 || pw_ofst > 15) {
1369 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n",
1370 			    pw_ofst);
1371 		return;
1372 	}
1373 	reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx);
1374 	rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1375 	val_1t = pw_ofst;
1376 	reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
1377 	rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t);
1378 	val_2t = max(val_1t - 3, -16);
1379 	reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
1380 	rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t);
1381 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n",
1382 		    val_1t, val_2t);
1383 }
1384 
1385 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
1386 				   enum rtw89_phy_idx phy_idx)
1387 {
1388 	static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800};
1389 	const u32 mask = 0x7FFFFFF;
1390 	const u8 ofst_ofdm = 0x4;
1391 	const u8 ofst_cck = 0x8;
1392 	s16 ref_ofdm = 0;
1393 	s16 ref_cck = 0;
1394 	u32 val;
1395 	u8 i;
1396 
1397 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1398 
1399 	rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1400 				     GENMASK(27, 10), 0x0);
1401 
1402 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1403 	val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1404 
1405 	for (i = 0; i < RF_PATH_NUM_8852A; i++)
1406 		rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1407 				      phy_idx);
1408 
1409 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1410 	val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1411 
1412 	for (i = 0; i < RF_PATH_NUM_8852A; i++)
1413 		rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1414 				      phy_idx);
1415 }
1416 
1417 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
1418 			       const struct rtw89_chan *chan,
1419 			       enum rtw89_phy_idx phy_idx)
1420 {
1421 	rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1422 	rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1423 	rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1424 	rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1425 }
1426 
1427 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1428 				    enum rtw89_phy_idx phy_idx)
1429 {
1430 	rtw8852a_set_txpwr_ref(rtwdev, phy_idx);
1431 }
1432 
1433 static int
1434 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1435 {
1436 	int ret;
1437 
1438 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1439 	if (ret)
1440 		return ret;
1441 
1442 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004);
1443 	if (ret)
1444 		return ret;
1445 
1446 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1447 	if (ret)
1448 		return ret;
1449 
1450 	return 0;
1451 }
1452 
1453 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1454 {
1455 	u8 i = 0;
1456 	u32 addr, val;
1457 
1458 	for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) {
1459 		addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr;
1460 		val = rtw8852a_pmac_ht20_mcs7_tbl[i].data;
1461 		rtw89_phy_write32(rtwdev, addr, val);
1462 	}
1463 }
1464 
1465 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,
1466 				  struct rtw8852a_bb_pmac_info *tx_info,
1467 				  enum rtw89_phy_idx idx)
1468 {
1469 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1470 	if (tx_info->mode == CONT_TX)
1471 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0,
1472 				      idx);
1473 	else if (tx_info->mode == PKTS_TX)
1474 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0,
1475 				      idx);
1476 }
1477 
1478 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,
1479 				   struct rtw8852a_bb_pmac_info *tx_info,
1480 				   enum rtw89_phy_idx idx)
1481 {
1482 	enum rtw8852a_pmac_mode mode = tx_info->mode;
1483 	u32 pkt_cnt = tx_info->tx_cnt;
1484 	u16 period = tx_info->period;
1485 
1486 	if (mode == CONT_TX && !tx_info->is_cck) {
1487 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1,
1488 				      idx);
1489 		rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1490 	} else if (mode == PKTS_TX) {
1491 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1,
1492 				      idx);
1493 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1494 				      B_PMAC_TX_PRD_MSK, period, idx);
1495 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1496 				      pkt_cnt, idx);
1497 		rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1498 	}
1499 	rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1500 	rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1501 }
1502 
1503 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1504 			     struct rtw8852a_bb_pmac_info *tx_info,
1505 			     enum rtw89_phy_idx idx)
1506 {
1507 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1508 
1509 	if (!tx_info->en_pmac_tx) {
1510 		rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx);
1511 		rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1512 		if (chan->band_type == RTW89_BAND_2G)
1513 			rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1514 		return;
1515 	}
1516 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1517 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1518 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1519 	rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f,
1520 			      idx);
1521 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1522 	rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1523 	rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1524 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1525 	rtw8852a_start_pmac_tx(rtwdev, tx_info, idx);
1526 }
1527 
1528 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1529 				 u16 tx_cnt, u16 period, u16 tx_time,
1530 				 enum rtw89_phy_idx idx)
1531 {
1532 	struct rtw8852a_bb_pmac_info tx_info = {0};
1533 
1534 	tx_info.en_pmac_tx = enable;
1535 	tx_info.is_cck = 0;
1536 	tx_info.mode = PKTS_TX;
1537 	tx_info.tx_cnt = tx_cnt;
1538 	tx_info.period = period;
1539 	tx_info.tx_time = tx_time;
1540 	rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx);
1541 }
1542 
1543 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1544 			   enum rtw89_phy_idx idx)
1545 {
1546 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1547 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1548 	rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1549 }
1550 
1551 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1552 {
1553 	u32 rst_mask0 = 0;
1554 	u32 rst_mask1 = 0;
1555 
1556 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1557 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1);
1558 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1559 	if (!rtwdev->dbcc_en) {
1560 		if (tx_path == RF_PATH_A) {
1561 			rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1562 					       B_TXPATH_SEL_MSK, 1);
1563 			rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1564 					       B_TXNSS_MAP_MSK, 0);
1565 		} else if (tx_path == RF_PATH_B) {
1566 			rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1567 					       B_TXPATH_SEL_MSK, 2);
1568 			rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1569 					       B_TXNSS_MAP_MSK, 0);
1570 		} else if (tx_path == RF_PATH_AB) {
1571 			rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1572 					       B_TXPATH_SEL_MSK, 3);
1573 			rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1574 					       B_TXNSS_MAP_MSK, 4);
1575 		} else {
1576 			rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1577 		}
1578 	} else {
1579 		rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK,
1580 				       1);
1581 		rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2,
1582 				      RTW89_PHY_1);
1583 		rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK,
1584 				       0);
1585 		rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4,
1586 				      RTW89_PHY_1);
1587 	}
1588 	rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1589 	rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
1590 	if (tx_path == RF_PATH_A) {
1591 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1592 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1593 	} else {
1594 		rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
1595 		rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
1596 	}
1597 }
1598 
1599 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1600 				enum rtw89_phy_idx idx, u8 mode)
1601 {
1602 	if (mode != 0)
1603 		return;
1604 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1605 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1606 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1607 	rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1608 	rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1609 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1610 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1611 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1612 }
1613 
1614 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
1615 {
1616 	rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl :
1617 						 &rtw8852a_btc_preagc_dis_defs_tbl);
1618 }
1619 
1620 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1621 {
1622 	if (rtwdev->is_tssi_mode[rf_path]) {
1623 		u32 addr = 0x1c10 + (rf_path << 13);
1624 
1625 		return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
1626 	}
1627 
1628 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1629 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1630 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1631 
1632 	fsleep(200);
1633 
1634 	return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1635 }
1636 
1637 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)
1638 {
1639 	struct rtw89_btc *btc = &rtwdev->btc;
1640 	struct rtw89_btc_module *module = &btc->mdinfo;
1641 
1642 	module->rfe_type = rtwdev->efuse.rfe_type;
1643 	module->cv = rtwdev->hal.cv;
1644 	module->bt_solo = 0;
1645 	module->switch_type = BTC_SWITCH_INTERNAL;
1646 
1647 	if (module->rfe_type > 0)
1648 		module->ant.num = (module->rfe_type % 2 ? 2 : 3);
1649 	else
1650 		module->ant.num = 2;
1651 
1652 	module->ant.diversity = 0;
1653 	module->ant.isolation = 10;
1654 
1655 	if (module->ant.num == 3) {
1656 		module->ant.type = BTC_ANT_DEDICATED;
1657 		module->bt_pos = BTC_BT_ALONE;
1658 	} else {
1659 		module->ant.type = BTC_ANT_SHARED;
1660 		module->bt_pos = BTC_BT_BTG;
1661 	}
1662 }
1663 
1664 static
1665 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1666 {
1667 	rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000);
1668 	rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group);
1669 	rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val);
1670 	rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0);
1671 }
1672 
1673 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
1674 {
1675 	if (btg) {
1676 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1);
1677 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3);
1678 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1679 	} else {
1680 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0);
1681 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0);
1682 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
1683 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
1684 	}
1685 }
1686 
1687 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)
1688 {
1689 	struct rtw89_btc *btc = &rtwdev->btc;
1690 	struct rtw89_btc_module *module = &btc->mdinfo;
1691 	const struct rtw89_chip_info *chip = rtwdev->chip;
1692 	const struct rtw89_mac_ax_coex coex_params = {
1693 		.pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1694 		.direction = RTW89_MAC_AX_COEX_INNER,
1695 	};
1696 
1697 	/* PTA init  */
1698 	rtw89_mac_coex_init(rtwdev, &coex_params);
1699 
1700 	/* set WL Tx response = Hi-Pri */
1701 	chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1702 	chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1703 
1704 	/* set rf gnt debug off */
1705 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0);
1706 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0);
1707 
1708 	/* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
1709 	if (module->ant.type == BTC_ANT_SHARED) {
1710 		rtw8852a_set_trx_mask(rtwdev,
1711 				      RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
1712 		rtw8852a_set_trx_mask(rtwdev,
1713 				      RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
1714 		/* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
1715 		rtw8852a_set_trx_mask(rtwdev,
1716 				      RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
1717 	} else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
1718 		rtw8852a_set_trx_mask(rtwdev,
1719 				      RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
1720 		rtw8852a_set_trx_mask(rtwdev,
1721 				      RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
1722 	}
1723 
1724 	/* set PTA break table */
1725 	rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1726 
1727 	 /* enable BT counter 0xda40[16,2] = 2b'11 */
1728 	rtw89_write32_set(rtwdev,
1729 			  R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
1730 	btc->cx.wl.status.map.init_ok = true;
1731 }
1732 
1733 static
1734 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1735 {
1736 	u32 bitmap = 0;
1737 	u32 reg = 0;
1738 
1739 	switch (map) {
1740 	case BTC_PRI_MASK_TX_RESP:
1741 		reg = R_BTC_BT_COEX_MSK_TABLE;
1742 		bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
1743 		break;
1744 	case BTC_PRI_MASK_BEACON:
1745 		reg = R_AX_WL_PRI_MSK;
1746 		bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
1747 		break;
1748 	default:
1749 		return;
1750 	}
1751 
1752 	if (state)
1753 		rtw89_write32_set(rtwdev, reg, bitmap);
1754 	else
1755 		rtw89_write32_clr(rtwdev, reg, bitmap);
1756 }
1757 
1758 static inline u32 __btc_ctrl_val_all_time(u32 ctrl)
1759 {
1760 	return FIELD_GET(GENMASK(15, 0), ctrl);
1761 }
1762 
1763 static inline u32 __btc_ctrl_rst_all_time(u32 cur)
1764 {
1765 	return cur & ~B_AX_FORCE_PWR_BY_RATE_EN;
1766 }
1767 
1768 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val)
1769 {
1770 	u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1771 	u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1772 
1773 	return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN;
1774 }
1775 
1776 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl)
1777 {
1778 	return FIELD_GET(GENMASK(31, 16), ctrl);
1779 }
1780 
1781 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur)
1782 {
1783 	return cur & ~B_AX_TXAGC_BT_EN;
1784 }
1785 
1786 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val)
1787 {
1788 	u32 ov = cur & ~B_AX_TXAGC_BT_MASK;
1789 	u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val);
1790 
1791 	return ov | iv | B_AX_TXAGC_BT_EN;
1792 }
1793 
1794 static void
1795 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
1796 {
1797 	const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL;
1798 	const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL;
1799 
1800 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0))
1801 #define __handle(_case)							\
1802 	do {								\
1803 		const u32 _reg = __btc_cr_ ## _case;			\
1804 		u32 _val = __btc_ctrl_val_ ## _case(txpwr_val);		\
1805 		u32 _cur, _wrt;						\
1806 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR,			\
1807 			    "btc ctrl %s: 0x%x\n", #_case, _val);	\
1808 		if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\
1809 			break;						\
1810 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR,			\
1811 			    "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur);	\
1812 		_wrt = __do_clr(_val) ?					\
1813 			__btc_ctrl_rst_ ## _case(_cur) :		\
1814 			__btc_ctrl_gen_ ## _case(_cur, _val);		\
1815 		rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\
1816 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR,			\
1817 			    "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt);	\
1818 	} while (0)
1819 
1820 	__handle(all_time);
1821 	__handle(gnt_bt);
1822 
1823 #undef __handle
1824 #undef __do_clr
1825 }
1826 
1827 static
1828 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
1829 {
1830 	return clamp_t(s8, val, -100, 0) + 100;
1831 }
1832 
1833 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = {
1834 	{255, 0, 0, 7}, /* 0 -> original */
1835 	{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
1836 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1837 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1838 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1839 	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1840 	{6, 1, 0, 7},
1841 	{13, 1, 0, 7},
1842 	{13, 1, 0, 7}
1843 };
1844 
1845 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = {
1846 	{255, 0, 0, 7}, /* 0 -> original */
1847 	{255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
1848 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1849 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1850 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1851 	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1852 	{255, 1, 0, 7},
1853 	{255, 1, 0, 7},
1854 	{255, 1, 0, 7}
1855 };
1856 
1857 static const
1858 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
1859 static const
1860 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
1861 
1862 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = {
1863 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
1864 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
1865 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
1866 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
1867 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
1868 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
1869 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
1870 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
1871 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
1872 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
1873 	RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
1874 	RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
1875 };
1876 
1877 static
1878 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
1879 {
1880 	struct rtw89_btc *btc = &rtwdev->btc;
1881 	const struct rtw89_btc_ver *ver = btc->ver;
1882 	struct rtw89_btc_cx *cx = &btc->cx;
1883 	u32 val;
1884 
1885 	if (ver->fcxbtcrpt != 1)
1886 		return;
1887 
1888 	val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH);
1889 	cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
1890 	cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
1891 
1892 	val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW);
1893 	cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
1894 	cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
1895 
1896 	/* clock-gate off before reset counter*/
1897 	rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1898 	rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1899 	rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1900 	rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1901 }
1902 
1903 static
1904 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
1905 {
1906 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
1907 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1908 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1);
1909 
1910 	/* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
1911 	if (state)
1912 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1913 			       RFREG_MASK, 0xa2d7c);
1914 	else
1915 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1916 			       RFREG_MASK, 0xa2020);
1917 
1918 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1919 }
1920 
1921 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
1922 {
1923 	/* level=0 Default:    TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
1924 	 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
1925 	 * To improve BT ACI in co-rx
1926 	 */
1927 
1928 	switch (level) {
1929 	case 0: /* default */
1930 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1931 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1932 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
1933 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1934 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1935 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1936 		break;
1937 	case 1: /* Fix LNA2=5  */
1938 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1939 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1940 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
1941 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1942 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1943 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1944 		break;
1945 	}
1946 }
1947 
1948 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
1949 {
1950 	switch (level) {
1951 	case 0: /* original */
1952 		rtw8852a_bb_ctrl_btc_preagc(rtwdev, false);
1953 		rtw8852a_set_wl_lna2(rtwdev, 0);
1954 		break;
1955 	case 1: /* for FDD free-run */
1956 		rtw8852a_bb_ctrl_btc_preagc(rtwdev, true);
1957 		rtw8852a_set_wl_lna2(rtwdev, 0);
1958 		break;
1959 	case 2: /* for BTG Co-Rx*/
1960 		rtw8852a_bb_ctrl_btc_preagc(rtwdev, false);
1961 		rtw8852a_set_wl_lna2(rtwdev, 1);
1962 		break;
1963 	}
1964 }
1965 
1966 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
1967 					 struct rtw89_rx_phy_ppdu *phy_ppdu,
1968 					 struct ieee80211_rx_status *status)
1969 {
1970 	u16 chan = phy_ppdu->chan_idx;
1971 	u8 band;
1972 
1973 	if (chan == 0)
1974 		return;
1975 
1976 	band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
1977 	status->freq = ieee80211_channel_to_frequency(chan, band);
1978 	status->band = band;
1979 }
1980 
1981 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
1982 				struct rtw89_rx_phy_ppdu *phy_ppdu,
1983 				struct ieee80211_rx_status *status)
1984 {
1985 	u8 path;
1986 	u8 *rx_power = phy_ppdu->rssi;
1987 
1988 	status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
1989 	for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
1990 		status->chains |= BIT(path);
1991 		status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
1992 	}
1993 	if (phy_ppdu->valid)
1994 		rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
1995 }
1996 
1997 #ifdef CONFIG_PM
1998 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
1999 	.flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2000 	.n_patterns = RTW89_MAX_PATTERN_NUM,
2001 	.pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2002 	.pattern_min_len = 1,
2003 };
2004 #endif
2005 
2006 static const struct rtw89_chip_ops rtw8852a_chip_ops = {
2007 	.enable_bb_rf		= rtw89_mac_enable_bb_rf,
2008 	.disable_bb_rf		= rtw89_mac_disable_bb_rf,
2009 	.bb_reset		= rtw8852a_bb_reset,
2010 	.bb_sethw		= rtw8852a_bb_sethw,
2011 	.read_rf		= rtw89_phy_read_rf,
2012 	.write_rf		= rtw89_phy_write_rf,
2013 	.set_channel		= rtw8852a_set_channel,
2014 	.set_channel_help	= rtw8852a_set_channel_help,
2015 	.read_efuse		= rtw8852a_read_efuse,
2016 	.read_phycap		= rtw8852a_read_phycap,
2017 	.fem_setup		= rtw8852a_fem_setup,
2018 	.rfk_init		= rtw8852a_rfk_init,
2019 	.rfk_channel		= rtw8852a_rfk_channel,
2020 	.rfk_band_changed	= rtw8852a_rfk_band_changed,
2021 	.rfk_scan		= rtw8852a_rfk_scan,
2022 	.rfk_track		= rtw8852a_rfk_track,
2023 	.power_trim		= rtw8852a_power_trim,
2024 	.set_txpwr		= rtw8852a_set_txpwr,
2025 	.set_txpwr_ctrl		= rtw8852a_set_txpwr_ctrl,
2026 	.init_txpwr_unit	= rtw8852a_init_txpwr_unit,
2027 	.get_thermal		= rtw8852a_get_thermal,
2028 	.ctrl_btg		= rtw8852a_ctrl_btg,
2029 	.query_ppdu		= rtw8852a_query_ppdu,
2030 	.bb_ctrl_btc_preagc	= rtw8852a_bb_ctrl_btc_preagc,
2031 	.cfg_txrx_path		= NULL,
2032 	.set_txpwr_ul_tb_offset	= rtw8852a_set_txpwr_ul_tb_offset,
2033 	.pwr_on_func		= NULL,
2034 	.pwr_off_func		= NULL,
2035 	.fill_txdesc		= rtw89_core_fill_txdesc,
2036 	.fill_txdesc_fwcmd	= rtw89_core_fill_txdesc,
2037 	.cfg_ctrl_path		= rtw89_mac_cfg_ctrl_path,
2038 	.mac_cfg_gnt		= rtw89_mac_cfg_gnt,
2039 	.stop_sch_tx		= rtw89_mac_stop_sch_tx,
2040 	.resume_sch_tx		= rtw89_mac_resume_sch_tx,
2041 	.h2c_dctl_sec_cam	= NULL,
2042 
2043 	.btc_set_rfe		= rtw8852a_btc_set_rfe,
2044 	.btc_init_cfg		= rtw8852a_btc_init_cfg,
2045 	.btc_set_wl_pri		= rtw8852a_btc_set_wl_pri,
2046 	.btc_set_wl_txpwr_ctrl	= rtw8852a_btc_set_wl_txpwr_ctrl,
2047 	.btc_get_bt_rssi	= rtw8852a_btc_get_bt_rssi,
2048 	.btc_update_bt_cnt	= rtw8852a_btc_update_bt_cnt,
2049 	.btc_wl_s1_standby	= rtw8852a_btc_wl_s1_standby,
2050 	.btc_set_wl_rx_gain	= rtw8852a_btc_set_wl_rx_gain,
2051 	.btc_set_policy		= rtw89_btc_set_policy,
2052 };
2053 
2054 const struct rtw89_chip_info rtw8852a_chip_info = {
2055 	.chip_id		= RTL8852A,
2056 	.ops			= &rtw8852a_chip_ops,
2057 	.fw_name		= "rtw89/rtw8852a_fw.bin",
2058 	.try_ce_fw		= false,
2059 	.fifo_size		= 458752,
2060 	.dle_scc_rsvd_size	= 0,
2061 	.max_amsdu_limit	= 3500,
2062 	.dis_2g_40m_ul_ofdma	= true,
2063 	.rsvd_ple_ofst		= 0x6f800,
2064 	.hfc_param_ini		= rtw8852a_hfc_param_ini_pcie,
2065 	.dle_mem		= rtw8852a_dle_mem_pcie,
2066 	.wde_qempty_acq_num	= 16,
2067 	.wde_qempty_mgq_sel	= 16,
2068 	.rf_base_addr		= {0xc000, 0xd000},
2069 	.pwr_on_seq		= pwr_on_seq_8852a,
2070 	.pwr_off_seq		= pwr_off_seq_8852a,
2071 	.bb_table		= &rtw89_8852a_phy_bb_table,
2072 	.bb_gain_table		= NULL,
2073 	.rf_table		= {&rtw89_8852a_phy_radioa_table,
2074 				   &rtw89_8852a_phy_radiob_table,},
2075 	.nctl_table		= &rtw89_8852a_phy_nctl_table,
2076 	.byr_table		= &rtw89_8852a_byr_table,
2077 	.txpwr_lmt_2g		= &rtw89_8852a_txpwr_lmt_2g,
2078 	.txpwr_lmt_5g		= &rtw89_8852a_txpwr_lmt_5g,
2079 	.txpwr_lmt_ru_2g	= &rtw89_8852a_txpwr_lmt_ru_2g,
2080 	.txpwr_lmt_ru_5g	= &rtw89_8852a_txpwr_lmt_ru_5g,
2081 	.txpwr_factor_rf	= 2,
2082 	.txpwr_factor_mac	= 1,
2083 	.dig_table		= &rtw89_8852a_phy_dig_table,
2084 	.dig_regs		= &rtw8852a_dig_regs,
2085 	.tssi_dbw_table		= NULL,
2086 	.support_chanctx_num	= 1,
2087 	.support_bands		= BIT(NL80211_BAND_2GHZ) |
2088 				  BIT(NL80211_BAND_5GHZ),
2089 	.support_bw160		= false,
2090 	.support_ul_tb_ctrl     = false,
2091 	.hw_sec_hdr		= false,
2092 	.rf_path_num		= 2,
2093 	.tx_nss			= 2,
2094 	.rx_nss			= 2,
2095 	.acam_num		= 128,
2096 	.bcam_num		= 10,
2097 	.scam_num		= 128,
2098 	.bacam_num		= 2,
2099 	.bacam_dynamic_num	= 4,
2100 	.bacam_v1		= false,
2101 	.sec_ctrl_efuse_size	= 4,
2102 	.physical_efuse_size	= 1216,
2103 	.logical_efuse_size	= 1536,
2104 	.limit_efuse_size	= 1152,
2105 	.dav_phy_efuse_size	= 0,
2106 	.dav_log_efuse_size	= 0,
2107 	.phycap_addr		= 0x580,
2108 	.phycap_size		= 128,
2109 	.para_ver		= 0x0,
2110 	.wlcx_desired		= 0x06000000,
2111 	.btcx_desired		= 0x7,
2112 	.scbd			= 0x1,
2113 	.mailbox		= 0x1,
2114 
2115 	.afh_guard_ch		= 6,
2116 	.wl_rssi_thres		= rtw89_btc_8852a_wl_rssi_thres,
2117 	.bt_rssi_thres		= rtw89_btc_8852a_bt_rssi_thres,
2118 	.rssi_tol		= 2,
2119 	.mon_reg_num		= ARRAY_SIZE(rtw89_btc_8852a_mon_reg),
2120 	.mon_reg		= rtw89_btc_8852a_mon_reg,
2121 	.rf_para_ulink_num	= ARRAY_SIZE(rtw89_btc_8852a_rf_ul),
2122 	.rf_para_ulink		= rtw89_btc_8852a_rf_ul,
2123 	.rf_para_dlink_num	= ARRAY_SIZE(rtw89_btc_8852a_rf_dl),
2124 	.rf_para_dlink		= rtw89_btc_8852a_rf_dl,
2125 	.ps_mode_supported	= BIT(RTW89_PS_MODE_RFOFF) |
2126 				  BIT(RTW89_PS_MODE_CLK_GATED) |
2127 				  BIT(RTW89_PS_MODE_PWR_GATED),
2128 	.low_power_hci_modes	= 0,
2129 	.h2c_cctl_func_id	= H2C_FUNC_MAC_CCTLINFO_UD,
2130 	.hci_func_en_addr	= R_AX_HCI_FUNC_EN,
2131 	.h2c_desc_size		= sizeof(struct rtw89_txwd_body),
2132 	.txwd_body_size		= sizeof(struct rtw89_txwd_body),
2133 	.h2c_ctrl_reg		= R_AX_H2CREG_CTRL,
2134 	.h2c_regs		= rtw8852a_h2c_regs,
2135 	.c2h_ctrl_reg		= R_AX_C2HREG_CTRL,
2136 	.c2h_regs		= rtw8852a_c2h_regs,
2137 	.page_regs		= &rtw8852a_page_regs,
2138 	.cfo_src_fd		= false,
2139 	.dcfo_comp		= &rtw8852a_dcfo_comp,
2140 	.dcfo_comp_sft		= 3,
2141 	.imr_info		= &rtw8852a_imr_info,
2142 	.rrsr_cfgs		= &rtw8852a_rrsr_cfgs,
2143 	.bss_clr_map_reg	= R_BSS_CLR_MAP,
2144 	.dma_ch_mask		= 0,
2145 #ifdef CONFIG_PM
2146 	.wowlan_stub		= &rtw_wowlan_stub_8852a,
2147 #endif
2148 };
2149 EXPORT_SYMBOL(rtw8852a_chip_info);
2150 
2151 MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin");
2152 MODULE_AUTHOR("Realtek Corporation");
2153 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver");
2154 MODULE_LICENSE("Dual BSD/GPL");
2155