1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852a.h" 11 #include "rtw8852a_rfk.h" 12 #include "rtw8852a_table.h" 13 #include "txrx.h" 14 15 #define RTW8852A_FW_FORMAT_MAX 0 16 #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw" 17 #define RTW8852A_MODULE_FIRMWARE \ 18 RTW8852A_FW_BASENAME ".bin" 19 20 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 21 {128, 1896, grp_0}, /* ACH 0 */ 22 {128, 1896, grp_0}, /* ACH 1 */ 23 {128, 1896, grp_0}, /* ACH 2 */ 24 {128, 1896, grp_0}, /* ACH 3 */ 25 {128, 1896, grp_1}, /* ACH 4 */ 26 {128, 1896, grp_1}, /* ACH 5 */ 27 {128, 1896, grp_1}, /* ACH 6 */ 28 {128, 1896, grp_1}, /* ACH 7 */ 29 {32, 1896, grp_0}, /* B0MGQ */ 30 {128, 1896, grp_0}, /* B0HIQ */ 31 {32, 1896, grp_1}, /* B1MGQ */ 32 {128, 1896, grp_1}, /* B1HIQ */ 33 {40, 0, 0} /* FWCMDQ */ 34 }; 35 36 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 37 1896, /* Group 0 */ 38 1896, /* Group 1 */ 39 3792, /* Public Max */ 40 0 /* WP threshold */ 41 }; 42 43 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 47 RTW89_HCIFC_POH}, 48 [RTW89_QTA_INVALID] = {NULL}, 49 }; 50 51 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0, 53 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 54 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 55 &rtw89_mac_size.ple_qt5}, 56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0, 57 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 58 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 59 &rtw89_mac_size.ple_qt_52a_wow}, 60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 61 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 63 &rtw89_mac_size.ple_qt13}, 64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 65 NULL}, 66 }; 67 68 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 69 {0x44AC, 0x00000000}, 70 {0x44B0, 0x00000000}, 71 {0x44B4, 0x00000000}, 72 {0x44B8, 0x00000000}, 73 {0x44BC, 0x00000000}, 74 {0x44C0, 0x00000000}, 75 {0x44C4, 0x00000000}, 76 {0x44C8, 0x00000000}, 77 {0x44CC, 0x00000000}, 78 {0x44D0, 0x00000000}, 79 {0x44D4, 0x00000000}, 80 {0x44D8, 0x00000000}, 81 {0x44DC, 0x00000000}, 82 {0x44E0, 0x00000000}, 83 {0x44E4, 0x00000000}, 84 {0x44E8, 0x00000000}, 85 {0x44EC, 0x00000000}, 86 {0x44F0, 0x00000000}, 87 {0x44F4, 0x00000000}, 88 {0x44F8, 0x00000000}, 89 {0x44FC, 0x00000000}, 90 {0x4500, 0x00000000}, 91 {0x4504, 0x00000000}, 92 {0x4508, 0x00000000}, 93 {0x450C, 0x00000000}, 94 {0x4510, 0x00000000}, 95 {0x4514, 0x00000000}, 96 {0x4518, 0x00000000}, 97 {0x451C, 0x00000000}, 98 {0x4520, 0x00000000}, 99 {0x4524, 0x00000000}, 100 {0x4528, 0x00000000}, 101 {0x452C, 0x00000000}, 102 {0x4530, 0x4E1F3E81}, 103 {0x4534, 0x00000000}, 104 {0x4538, 0x0000005A}, 105 {0x453C, 0x00000000}, 106 {0x4540, 0x00000000}, 107 {0x4544, 0x00000000}, 108 {0x4548, 0x00000000}, 109 {0x454C, 0x00000000}, 110 {0x4550, 0x00000000}, 111 {0x4554, 0x00000000}, 112 {0x4558, 0x00000000}, 113 {0x455C, 0x00000000}, 114 {0x4560, 0x4060001A}, 115 {0x4564, 0x40000000}, 116 {0x4568, 0x00000000}, 117 {0x456C, 0x00000000}, 118 {0x4570, 0x04000007}, 119 {0x4574, 0x0000DC87}, 120 {0x4578, 0x00000BAB}, 121 {0x457C, 0x03E00000}, 122 {0x4580, 0x00000048}, 123 {0x4584, 0x00000000}, 124 {0x4588, 0x000003E8}, 125 {0x458C, 0x30000000}, 126 {0x4590, 0x00000000}, 127 {0x4594, 0x10000000}, 128 {0x4598, 0x00000001}, 129 {0x459C, 0x00030000}, 130 {0x45A0, 0x01000000}, 131 {0x45A4, 0x03000200}, 132 {0x45A8, 0xC00001C0}, 133 {0x45AC, 0x78018000}, 134 {0x45B0, 0x80000000}, 135 {0x45B4, 0x01C80600}, 136 {0x45B8, 0x00000002}, 137 {0x4594, 0x10000000} 138 }; 139 140 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 141 {0x4624, GENMASK(20, 14), 0x40}, 142 {0x46f8, GENMASK(20, 14), 0x40}, 143 {0x4674, GENMASK(20, 19), 0x2}, 144 {0x4748, GENMASK(20, 19), 0x2}, 145 {0x4650, GENMASK(14, 10), 0x18}, 146 {0x4724, GENMASK(14, 10), 0x18}, 147 {0x4688, GENMASK(1, 0), 0x3}, 148 {0x475c, GENMASK(1, 0), 0x3}, 149 }; 150 151 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 152 153 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 154 {0x4624, GENMASK(20, 14), 0x1a}, 155 {0x46f8, GENMASK(20, 14), 0x1a}, 156 {0x4674, GENMASK(20, 19), 0x1}, 157 {0x4748, GENMASK(20, 19), 0x1}, 158 {0x4650, GENMASK(14, 10), 0x12}, 159 {0x4724, GENMASK(14, 10), 0x12}, 160 {0x4688, GENMASK(1, 0), 0x0}, 161 {0x475c, GENMASK(1, 0), 0x0}, 162 }; 163 164 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 165 166 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 167 {0x00C6, 168 PWR_CV_MSK_B, 169 PWR_INTF_MSK_PCIE, 170 PWR_BASE_MAC, 171 PWR_CMD_WRITE, BIT(6), BIT(6)}, 172 {0x1086, 173 PWR_CV_MSK_ALL, 174 PWR_INTF_MSK_SDIO, 175 PWR_BASE_MAC, 176 PWR_CMD_WRITE, BIT(0), 0}, 177 {0x1086, 178 PWR_CV_MSK_ALL, 179 PWR_INTF_MSK_SDIO, 180 PWR_BASE_MAC, 181 PWR_CMD_POLL, BIT(1), BIT(1)}, 182 {0x0005, 183 PWR_CV_MSK_ALL, 184 PWR_INTF_MSK_ALL, 185 PWR_BASE_MAC, 186 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 187 {0x0005, 188 PWR_CV_MSK_ALL, 189 PWR_INTF_MSK_ALL, 190 PWR_BASE_MAC, 191 PWR_CMD_WRITE, BIT(7), 0}, 192 {0x0005, 193 PWR_CV_MSK_ALL, 194 PWR_INTF_MSK_ALL, 195 PWR_BASE_MAC, 196 PWR_CMD_WRITE, BIT(2), 0}, 197 {0x0006, 198 PWR_CV_MSK_ALL, 199 PWR_INTF_MSK_ALL, 200 PWR_BASE_MAC, 201 PWR_CMD_POLL, BIT(1), BIT(1)}, 202 {0x0006, 203 PWR_CV_MSK_ALL, 204 PWR_INTF_MSK_ALL, 205 PWR_BASE_MAC, 206 PWR_CMD_WRITE, BIT(0), BIT(0)}, 207 {0x0005, 208 PWR_CV_MSK_ALL, 209 PWR_INTF_MSK_ALL, 210 PWR_BASE_MAC, 211 PWR_CMD_WRITE, BIT(0), BIT(0)}, 212 {0x0005, 213 PWR_CV_MSK_ALL, 214 PWR_INTF_MSK_ALL, 215 PWR_BASE_MAC, 216 PWR_CMD_POLL, BIT(0), 0}, 217 {0x106D, 218 PWR_CV_MSK_B | PWR_CV_MSK_C, 219 PWR_INTF_MSK_USB, 220 PWR_BASE_MAC, 221 PWR_CMD_WRITE, BIT(6), 0}, 222 {0x0088, 223 PWR_CV_MSK_ALL, 224 PWR_INTF_MSK_ALL, 225 PWR_BASE_MAC, 226 PWR_CMD_WRITE, BIT(0), BIT(0)}, 227 {0x0088, 228 PWR_CV_MSK_ALL, 229 PWR_INTF_MSK_ALL, 230 PWR_BASE_MAC, 231 PWR_CMD_WRITE, BIT(0), 0}, 232 {0x0088, 233 PWR_CV_MSK_ALL, 234 PWR_INTF_MSK_ALL, 235 PWR_BASE_MAC, 236 PWR_CMD_WRITE, BIT(0), BIT(0)}, 237 {0x0088, 238 PWR_CV_MSK_ALL, 239 PWR_INTF_MSK_ALL, 240 PWR_BASE_MAC, 241 PWR_CMD_WRITE, BIT(0), 0}, 242 {0x0088, 243 PWR_CV_MSK_ALL, 244 PWR_INTF_MSK_ALL, 245 PWR_BASE_MAC, 246 PWR_CMD_WRITE, BIT(0), BIT(0)}, 247 {0x0083, 248 PWR_CV_MSK_ALL, 249 PWR_INTF_MSK_ALL, 250 PWR_BASE_MAC, 251 PWR_CMD_WRITE, BIT(6), 0}, 252 {0x0080, 253 PWR_CV_MSK_ALL, 254 PWR_INTF_MSK_ALL, 255 PWR_BASE_MAC, 256 PWR_CMD_WRITE, BIT(5), BIT(5)}, 257 {0x0024, 258 PWR_CV_MSK_ALL, 259 PWR_INTF_MSK_ALL, 260 PWR_BASE_MAC, 261 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 262 {0x02A0, 263 PWR_CV_MSK_ALL, 264 PWR_INTF_MSK_ALL, 265 PWR_BASE_MAC, 266 PWR_CMD_WRITE, BIT(1), BIT(1)}, 267 {0x02A2, 268 PWR_CV_MSK_ALL, 269 PWR_INTF_MSK_ALL, 270 PWR_BASE_MAC, 271 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 272 {0x0071, 273 PWR_CV_MSK_ALL, 274 PWR_INTF_MSK_PCIE, 275 PWR_BASE_MAC, 276 PWR_CMD_WRITE, BIT(4), 0}, 277 {0x0010, 278 PWR_CV_MSK_A, 279 PWR_INTF_MSK_PCIE, 280 PWR_BASE_MAC, 281 PWR_CMD_WRITE, BIT(2), BIT(2)}, 282 {0x02A0, 283 PWR_CV_MSK_A, 284 PWR_INTF_MSK_ALL, 285 PWR_BASE_MAC, 286 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 287 {0xFFFF, 288 PWR_CV_MSK_ALL, 289 PWR_INTF_MSK_ALL, 290 0, 291 PWR_CMD_END, 0, 0}, 292 }; 293 294 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 295 {0x02F0, 296 PWR_CV_MSK_ALL, 297 PWR_INTF_MSK_ALL, 298 PWR_BASE_MAC, 299 PWR_CMD_WRITE, 0xFF, 0}, 300 {0x02F1, 301 PWR_CV_MSK_ALL, 302 PWR_INTF_MSK_ALL, 303 PWR_BASE_MAC, 304 PWR_CMD_WRITE, 0xFF, 0}, 305 {0x0006, 306 PWR_CV_MSK_ALL, 307 PWR_INTF_MSK_ALL, 308 PWR_BASE_MAC, 309 PWR_CMD_WRITE, BIT(0), BIT(0)}, 310 {0x0002, 311 PWR_CV_MSK_ALL, 312 PWR_INTF_MSK_ALL, 313 PWR_BASE_MAC, 314 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 315 {0x0082, 316 PWR_CV_MSK_ALL, 317 PWR_INTF_MSK_ALL, 318 PWR_BASE_MAC, 319 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 320 {0x106D, 321 PWR_CV_MSK_B | PWR_CV_MSK_C, 322 PWR_INTF_MSK_USB, 323 PWR_BASE_MAC, 324 PWR_CMD_WRITE, BIT(6), BIT(6)}, 325 {0x0005, 326 PWR_CV_MSK_ALL, 327 PWR_INTF_MSK_ALL, 328 PWR_BASE_MAC, 329 PWR_CMD_WRITE, BIT(1), BIT(1)}, 330 {0x0005, 331 PWR_CV_MSK_ALL, 332 PWR_INTF_MSK_ALL, 333 PWR_BASE_MAC, 334 PWR_CMD_POLL, BIT(1), 0}, 335 {0x0091, 336 PWR_CV_MSK_ALL, 337 PWR_INTF_MSK_PCIE, 338 PWR_BASE_MAC, 339 PWR_CMD_WRITE, BIT(0), 0}, 340 {0x0005, 341 PWR_CV_MSK_ALL, 342 PWR_INTF_MSK_PCIE, 343 PWR_BASE_MAC, 344 PWR_CMD_WRITE, BIT(2), BIT(2)}, 345 {0x0007, 346 PWR_CV_MSK_ALL, 347 PWR_INTF_MSK_USB, 348 PWR_BASE_MAC, 349 PWR_CMD_WRITE, BIT(4), 0}, 350 {0x0007, 351 PWR_CV_MSK_ALL, 352 PWR_INTF_MSK_SDIO, 353 PWR_BASE_MAC, 354 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 355 {0x0005, 356 PWR_CV_MSK_ALL, 357 PWR_INTF_MSK_SDIO, 358 PWR_BASE_MAC, 359 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 360 {0x0005, 361 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 362 PWR_CV_MSK_G, 363 PWR_INTF_MSK_USB, 364 PWR_BASE_MAC, 365 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 366 {0x1086, 367 PWR_CV_MSK_ALL, 368 PWR_INTF_MSK_SDIO, 369 PWR_BASE_MAC, 370 PWR_CMD_WRITE, BIT(0), BIT(0)}, 371 {0x1086, 372 PWR_CV_MSK_ALL, 373 PWR_INTF_MSK_SDIO, 374 PWR_BASE_MAC, 375 PWR_CMD_POLL, BIT(1), 0}, 376 {0xFFFF, 377 PWR_CV_MSK_ALL, 378 PWR_INTF_MSK_ALL, 379 0, 380 PWR_CMD_END, 0, 0}, 381 }; 382 383 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 384 rtw8852a_pwron, NULL 385 }; 386 387 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 388 rtw8852a_pwroff, NULL 389 }; 390 391 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 392 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 393 R_AX_H2CREG_DATA3 394 }; 395 396 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 397 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 398 R_AX_C2HREG_DATA3 399 }; 400 401 static const struct rtw89_page_regs rtw8852a_page_regs = { 402 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 403 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 404 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 405 .ach_page_info = R_AX_ACH0_PAGE_INFO, 406 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 407 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 408 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 409 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 410 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 411 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 412 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 413 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 414 }; 415 416 static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 417 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 418 }; 419 420 static const struct rtw89_imr_info rtw8852a_imr_info = { 421 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 422 .wsec_imr_reg = R_AX_SEC_DEBUG, 423 .wsec_imr_set = B_AX_IMR_ERROR, 424 .mpdu_tx_imr_set = 0, 425 .mpdu_rx_imr_set = 0, 426 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 427 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 428 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 429 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 430 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 431 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 432 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 433 .wde_imr_clr = B_AX_WDE_IMR_CLR, 434 .wde_imr_set = B_AX_WDE_IMR_SET, 435 .ple_imr_clr = B_AX_PLE_IMR_CLR, 436 .ple_imr_set = B_AX_PLE_IMR_SET, 437 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 438 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 439 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 440 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 441 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 442 .other_disp_imr_set = 0, 443 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 444 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 445 .bbrpt_err_imr_set = 0, 446 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 447 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR, 448 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 449 .cdma_imr_0_reg = R_AX_DLE_CTRL, 450 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 451 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 452 .cdma_imr_1_reg = 0, 453 .cdma_imr_1_clr = 0, 454 .cdma_imr_1_set = 0, 455 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 456 .phy_intf_imr_clr = 0, 457 .phy_intf_imr_set = 0, 458 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 459 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 460 .rmac_imr_set = B_AX_RMAC_IMR_SET, 461 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 462 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 463 .tmac_imr_set = B_AX_TMAC_IMR_SET, 464 }; 465 466 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = { 467 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 468 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 469 }; 470 471 static const struct rtw89_dig_regs rtw8852a_dig_regs = { 472 .seg0_pd_reg = R_SEG0R_PD, 473 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 474 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 475 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK}, 476 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK}, 477 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK}, 478 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK}, 479 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK}, 480 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK}, 481 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC, 482 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 483 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC, 484 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 485 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC, 486 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 487 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC, 488 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 489 }; 490 491 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 492 struct rtw8852a_efuse *map) 493 { 494 ether_addr_copy(efuse->addr, map->e.mac_addr); 495 efuse->rfe_type = map->rfe_type; 496 efuse->xtal_cap = map->xtal_k; 497 } 498 499 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 500 struct rtw8852a_efuse *map) 501 { 502 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 503 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 504 u8 i, j; 505 506 tssi->thermal[RF_PATH_A] = map->path_a_therm; 507 tssi->thermal[RF_PATH_B] = map->path_b_therm; 508 509 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 510 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 511 sizeof(ofst[i]->cck_tssi)); 512 513 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 514 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 515 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 516 i, j, tssi->tssi_cck[i][j]); 517 518 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 519 sizeof(ofst[i]->bw40_tssi)); 520 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 521 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 522 523 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 524 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 525 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 526 i, j, tssi->tssi_mcs[i][j]); 527 } 528 } 529 530 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 531 { 532 struct rtw89_efuse *efuse = &rtwdev->efuse; 533 struct rtw8852a_efuse *map; 534 535 map = (struct rtw8852a_efuse *)log_map; 536 537 efuse->country_code[0] = map->country_code[0]; 538 efuse->country_code[1] = map->country_code[1]; 539 rtw8852a_efuse_parsing_tssi(rtwdev, map); 540 541 switch (rtwdev->hci.type) { 542 case RTW89_HCI_TYPE_PCIE: 543 rtw8852ae_efuse_parsing(efuse, map); 544 break; 545 default: 546 return -ENOTSUPP; 547 } 548 549 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 550 551 return 0; 552 } 553 554 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 555 { 556 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 557 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 558 u32 addr = rtwdev->chip->phycap_addr; 559 bool pg = false; 560 u32 ofst; 561 u8 i, j; 562 563 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 564 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 565 /* addrs are in decreasing order */ 566 ofst = tssi_trim_addr[i] - addr - j; 567 tssi->tssi_trim[i][j] = phycap_map[ofst]; 568 569 if (phycap_map[ofst] != 0xff) 570 pg = true; 571 } 572 } 573 574 if (!pg) { 575 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 576 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 577 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 578 } 579 580 for (i = 0; i < RF_PATH_NUM_8852A; i++) 581 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 582 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 583 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 584 i, j, tssi->tssi_trim[i][j], 585 tssi_trim_addr[i] - j); 586 } 587 588 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 589 u8 *phycap_map) 590 { 591 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 592 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 593 u32 addr = rtwdev->chip->phycap_addr; 594 u8 i; 595 596 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 597 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 598 599 rtw89_debug(rtwdev, RTW89_DBG_RFK, 600 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 601 i, info->thermal_trim[i]); 602 603 if (info->thermal_trim[i] != 0xff) 604 info->pg_thermal_trim = true; 605 } 606 } 607 608 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 609 { 610 #define __thm_setting(raw) \ 611 ({ \ 612 u8 __v = (raw); \ 613 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 614 }) 615 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 616 u8 i, val; 617 618 if (!info->pg_thermal_trim) { 619 rtw89_debug(rtwdev, RTW89_DBG_RFK, 620 "[THERMAL][TRIM] no PG, do nothing\n"); 621 622 return; 623 } 624 625 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 626 val = __thm_setting(info->thermal_trim[i]); 627 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 628 629 rtw89_debug(rtwdev, RTW89_DBG_RFK, 630 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 631 i, val); 632 } 633 #undef __thm_setting 634 } 635 636 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 637 u8 *phycap_map) 638 { 639 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 640 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 641 u32 addr = rtwdev->chip->phycap_addr; 642 u8 i; 643 644 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 645 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 646 647 rtw89_debug(rtwdev, RTW89_DBG_RFK, 648 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 649 i, info->pa_bias_trim[i]); 650 651 if (info->pa_bias_trim[i] != 0xff) 652 info->pg_pa_bias_trim = true; 653 } 654 } 655 656 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 657 { 658 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 659 u8 pabias_2g, pabias_5g; 660 u8 i; 661 662 if (!info->pg_pa_bias_trim) { 663 rtw89_debug(rtwdev, RTW89_DBG_RFK, 664 "[PA_BIAS][TRIM] no PG, do nothing\n"); 665 666 return; 667 } 668 669 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 670 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 671 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 672 673 rtw89_debug(rtwdev, RTW89_DBG_RFK, 674 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 675 i, pabias_2g, pabias_5g); 676 677 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 678 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 679 } 680 } 681 682 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 683 { 684 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 685 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 686 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 687 688 return 0; 689 } 690 691 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 692 { 693 rtw8852a_thermal_trim(rtwdev); 694 rtw8852a_pa_bias_trim(rtwdev); 695 } 696 697 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 698 const struct rtw89_chan *chan, 699 u8 mac_idx) 700 { 701 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 702 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 703 mac_idx); 704 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 705 u8 txsc20 = 0, txsc40 = 0; 706 707 switch (chan->band_width) { 708 case RTW89_CHANNEL_WIDTH_80: 709 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 710 RTW89_CHANNEL_WIDTH_40); 711 fallthrough; 712 case RTW89_CHANNEL_WIDTH_40: 713 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 714 RTW89_CHANNEL_WIDTH_20); 715 break; 716 default: 717 break; 718 } 719 720 switch (chan->band_width) { 721 case RTW89_CHANNEL_WIDTH_80: 722 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 723 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 724 break; 725 case RTW89_CHANNEL_WIDTH_40: 726 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 727 rtw89_write32(rtwdev, sub_carr, txsc20); 728 break; 729 case RTW89_CHANNEL_WIDTH_20: 730 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 731 rtw89_write32(rtwdev, sub_carr, 0); 732 break; 733 default: 734 break; 735 } 736 737 if (chan->channel > 14) 738 rtw89_write8_set(rtwdev, chk_rate, 739 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 740 else 741 rtw89_write8_clr(rtwdev, chk_rate, 742 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 743 } 744 745 static const u32 rtw8852a_sco_barker_threshold[14] = { 746 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 747 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 748 }; 749 750 static const u32 rtw8852a_sco_cck_threshold[14] = { 751 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 752 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 753 }; 754 755 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 756 u8 primary_ch, enum rtw89_bandwidth bw) 757 { 758 u8 ch_element; 759 760 if (bw == RTW89_CHANNEL_WIDTH_20) { 761 ch_element = central_ch - 1; 762 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 763 if (primary_ch == 1) 764 ch_element = central_ch - 1 + 2; 765 else 766 ch_element = central_ch - 1 - 2; 767 } else { 768 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 769 return -EINVAL; 770 } 771 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 772 rtw8852a_sco_barker_threshold[ch_element]); 773 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 774 rtw8852a_sco_cck_threshold[ch_element]); 775 776 return 0; 777 } 778 779 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 780 u8 path) 781 { 782 u32 val; 783 784 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 785 if (val == INV_RF_DATA) { 786 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 787 return; 788 } 789 val &= ~0x303ff; 790 val |= central_ch; 791 if (central_ch > 14) 792 val |= (BIT(16) | BIT(8)); 793 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 794 } 795 796 static u8 rtw8852a_sco_mapping(u8 central_ch) 797 { 798 if (central_ch == 1) 799 return 109; 800 else if (central_ch >= 2 && central_ch <= 6) 801 return 108; 802 else if (central_ch >= 7 && central_ch <= 10) 803 return 107; 804 else if (central_ch >= 11 && central_ch <= 14) 805 return 106; 806 else if (central_ch == 36 || central_ch == 38) 807 return 51; 808 else if (central_ch >= 40 && central_ch <= 58) 809 return 50; 810 else if (central_ch >= 60 && central_ch <= 64) 811 return 49; 812 else if (central_ch == 100 || central_ch == 102) 813 return 48; 814 else if (central_ch >= 104 && central_ch <= 126) 815 return 47; 816 else if (central_ch >= 128 && central_ch <= 151) 817 return 46; 818 else if (central_ch >= 153 && central_ch <= 177) 819 return 45; 820 else 821 return 0; 822 } 823 824 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 825 enum rtw89_phy_idx phy_idx) 826 { 827 u8 sco_comp; 828 bool is_2g = central_ch <= 14; 829 830 if (phy_idx == RTW89_PHY_0) { 831 /* Path A */ 832 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 833 if (is_2g) 834 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 835 B_PATH0_TIA_ERR_G1_SEL, 1, 836 phy_idx); 837 else 838 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 839 B_PATH0_TIA_ERR_G1_SEL, 0, 840 phy_idx); 841 842 /* Path B */ 843 if (!rtwdev->dbcc_en) { 844 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 845 if (is_2g) 846 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 847 B_P1_MODE_SEL, 848 1, phy_idx); 849 else 850 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 851 B_P1_MODE_SEL, 852 0, phy_idx); 853 } else { 854 if (is_2g) 855 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 856 B_2P4G_BAND_SEL); 857 else 858 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 859 B_2P4G_BAND_SEL); 860 } 861 /* SCO compensate FC setting */ 862 sco_comp = rtw8852a_sco_mapping(central_ch); 863 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 864 sco_comp, phy_idx); 865 } else { 866 /* Path B */ 867 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 868 if (is_2g) 869 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 870 B_P1_MODE_SEL, 871 1, phy_idx); 872 else 873 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 874 B_P1_MODE_SEL, 875 0, phy_idx); 876 /* SCO compensate FC setting */ 877 sco_comp = rtw8852a_sco_mapping(central_ch); 878 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 879 sco_comp, phy_idx); 880 } 881 882 /* Band edge */ 883 if (is_2g) 884 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 885 phy_idx); 886 else 887 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 888 phy_idx); 889 890 /* CCK parameters */ 891 if (central_ch == 14) { 892 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 893 0x3b13ff); 894 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 895 0x1c42de); 896 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 897 0xfdb0ad); 898 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 899 0xf60f6e); 900 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 901 0xfd8f92); 902 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 903 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 904 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 905 0xfff00a); 906 } else { 907 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 908 0x3d23ff); 909 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 910 0x29b354); 911 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 912 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 913 0xfdb053); 914 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 915 0xf86f9a); 916 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 917 0xfaef92); 918 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 919 0xfe5fcc); 920 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 921 0xffdff5); 922 } 923 } 924 925 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 926 { 927 u32 val = 0; 928 u32 adc_sel[2] = {0x12d0, 0x32d0}; 929 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 930 931 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 932 if (val == INV_RF_DATA) { 933 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 934 return; 935 } 936 val &= ~(BIT(11) | BIT(10)); 937 switch (bw) { 938 case RTW89_CHANNEL_WIDTH_5: 939 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 940 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 941 val |= (BIT(11) | BIT(10)); 942 break; 943 case RTW89_CHANNEL_WIDTH_10: 944 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 945 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 946 val |= (BIT(11) | BIT(10)); 947 break; 948 case RTW89_CHANNEL_WIDTH_20: 949 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 950 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 951 val |= (BIT(11) | BIT(10)); 952 break; 953 case RTW89_CHANNEL_WIDTH_40: 954 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 955 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 956 val |= BIT(11); 957 break; 958 case RTW89_CHANNEL_WIDTH_80: 959 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 960 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 961 val |= BIT(10); 962 break; 963 default: 964 rtw89_warn(rtwdev, "Fail to set ADC\n"); 965 } 966 967 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 968 } 969 970 static void 971 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 972 enum rtw89_phy_idx phy_idx) 973 { 974 /* Switch bandwidth */ 975 switch (bw) { 976 case RTW89_CHANNEL_WIDTH_5: 977 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 978 phy_idx); 979 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 980 phy_idx); 981 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 982 0x0, phy_idx); 983 break; 984 case RTW89_CHANNEL_WIDTH_10: 985 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 986 phy_idx); 987 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 988 phy_idx); 989 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 990 0x0, phy_idx); 991 break; 992 case RTW89_CHANNEL_WIDTH_20: 993 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 994 phy_idx); 995 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 996 phy_idx); 997 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 998 0x0, phy_idx); 999 break; 1000 case RTW89_CHANNEL_WIDTH_40: 1001 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1002 phy_idx); 1003 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1004 phy_idx); 1005 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1006 pri_ch, 1007 phy_idx); 1008 if (pri_ch == RTW89_SC_20_UPPER) 1009 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1010 else 1011 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1012 break; 1013 case RTW89_CHANNEL_WIDTH_80: 1014 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1015 phy_idx); 1016 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1017 phy_idx); 1018 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1019 pri_ch, 1020 phy_idx); 1021 break; 1022 default: 1023 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1024 pri_ch); 1025 } 1026 1027 if (phy_idx == RTW89_PHY_0) { 1028 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 1029 if (!rtwdev->dbcc_en) 1030 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1031 } else { 1032 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1033 } 1034 } 1035 1036 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 1037 { 1038 if (central_ch == 153) { 1039 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1040 0x210); 1041 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1042 0x210); 1043 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0); 1044 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1045 B_P0_NBIIDX_NOTCH_EN, 0x1); 1046 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1047 B_P1_NBIIDX_NOTCH_EN, 0x1); 1048 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1049 0x1); 1050 } else if (central_ch == 151) { 1051 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1052 0x210); 1053 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1054 0x210); 1055 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40); 1056 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1057 B_P0_NBIIDX_NOTCH_EN, 0x1); 1058 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1059 B_P1_NBIIDX_NOTCH_EN, 0x1); 1060 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1061 0x1); 1062 } else if (central_ch == 155) { 1063 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1064 0x2d0); 1065 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1066 0x2d0); 1067 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740); 1068 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1069 B_P0_NBIIDX_NOTCH_EN, 0x1); 1070 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1071 B_P1_NBIIDX_NOTCH_EN, 0x1); 1072 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1073 0x1); 1074 } else { 1075 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1076 B_P0_NBIIDX_NOTCH_EN, 0x0); 1077 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1078 B_P1_NBIIDX_NOTCH_EN, 0x0); 1079 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1080 0x0); 1081 } 1082 } 1083 1084 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1085 enum rtw89_phy_idx phy_idx) 1086 { 1087 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1088 phy_idx); 1089 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1090 phy_idx); 1091 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1092 phy_idx); 1093 } 1094 1095 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1096 enum rtw89_phy_idx phy_idx, bool en) 1097 { 1098 if (en) 1099 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1100 1, 1101 phy_idx); 1102 else 1103 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1104 0, 1105 phy_idx); 1106 } 1107 1108 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1109 enum rtw89_phy_idx phy_idx) 1110 { 1111 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1112 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1113 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1114 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1115 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1116 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1117 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1118 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1119 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1120 } 1121 1122 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1123 enum rtw89_phy_idx phy_idx) 1124 { 1125 u32 addr; 1126 1127 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1128 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1129 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1130 } 1131 1132 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1133 { 1134 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1135 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1136 1137 if (rtwdev->hal.cv <= CHIP_CCV) { 1138 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1139 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1140 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F); 1141 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1142 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1143 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1144 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1145 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME); 1146 } 1147 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1148 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1149 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1150 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1151 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1152 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1153 1154 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1155 } 1156 1157 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1158 enum rtw89_phy_idx phy_idx) 1159 { 1160 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1161 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1162 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1163 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1164 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1165 udelay(1); 1166 } 1167 1168 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1169 const struct rtw89_chan *chan, 1170 enum rtw89_phy_idx phy_idx) 1171 { 1172 bool cck_en = chan->channel <= 14; 1173 u8 pri_ch_idx = chan->pri_ch_idx; 1174 1175 if (cck_en) 1176 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel, 1177 chan->primary_channel, 1178 chan->band_width); 1179 1180 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx); 1181 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1182 if (cck_en) { 1183 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1184 } else { 1185 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1186 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1187 } 1188 rtw8852a_spur_elimination(rtwdev, chan->channel); 1189 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1190 chan->primary_channel); 1191 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1192 } 1193 1194 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1195 const struct rtw89_chan *chan, 1196 enum rtw89_mac_idx mac_idx, 1197 enum rtw89_phy_idx phy_idx) 1198 { 1199 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx); 1200 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx); 1201 } 1202 1203 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1204 { 1205 if (en) 1206 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1207 else 1208 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1209 } 1210 1211 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1212 enum rtw89_rf_path path) 1213 { 1214 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1215 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1216 1217 if (en) { 1218 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1219 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1220 } else { 1221 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1222 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1223 } 1224 } 1225 1226 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1227 u8 phy_idx) 1228 { 1229 if (!rtwdev->dbcc_en) { 1230 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1231 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1232 } else { 1233 if (phy_idx == RTW89_PHY_0) 1234 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1235 else 1236 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1237 } 1238 } 1239 1240 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1241 { 1242 if (en) 1243 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1244 0x0); 1245 else 1246 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1247 0xf); 1248 } 1249 1250 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1251 struct rtw89_channel_help_params *p, 1252 const struct rtw89_chan *chan, 1253 enum rtw89_mac_idx mac_idx, 1254 enum rtw89_phy_idx phy_idx) 1255 { 1256 if (enter) { 1257 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1258 RTW89_SCH_TX_SEL_ALL); 1259 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1260 rtw8852a_dfs_en(rtwdev, false); 1261 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1262 rtw8852a_adc_en(rtwdev, false); 1263 fsleep(40); 1264 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1265 } else { 1266 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1267 rtw8852a_adc_en(rtwdev, true); 1268 rtw8852a_dfs_en(rtwdev, true); 1269 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1270 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1271 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1272 } 1273 } 1274 1275 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1276 { 1277 struct rtw89_efuse *efuse = &rtwdev->efuse; 1278 1279 switch (efuse->rfe_type) { 1280 case 11: 1281 case 12: 1282 case 17: 1283 case 18: 1284 case 51: 1285 case 53: 1286 rtwdev->fem.epa_2g = true; 1287 rtwdev->fem.elna_2g = true; 1288 fallthrough; 1289 case 9: 1290 case 10: 1291 case 15: 1292 case 16: 1293 rtwdev->fem.epa_5g = true; 1294 rtwdev->fem.elna_5g = true; 1295 break; 1296 default: 1297 break; 1298 } 1299 } 1300 1301 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1302 { 1303 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1304 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1305 1306 rtw8852a_rck(rtwdev); 1307 rtw8852a_dack(rtwdev); 1308 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); 1309 } 1310 1311 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) 1312 { 1313 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1314 1315 rtw8852a_rx_dck(rtwdev, phy_idx, true); 1316 rtw8852a_iqk(rtwdev, phy_idx); 1317 rtw8852a_tssi(rtwdev, phy_idx); 1318 rtw8852a_dpk(rtwdev, phy_idx); 1319 } 1320 1321 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev, 1322 enum rtw89_phy_idx phy_idx) 1323 { 1324 rtw8852a_tssi_scan(rtwdev, phy_idx); 1325 } 1326 1327 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1328 { 1329 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1330 } 1331 1332 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1333 { 1334 rtw8852a_dpk_track(rtwdev); 1335 rtw8852a_iqk_track(rtwdev); 1336 rtw8852a_tssi_track(rtwdev); 1337 } 1338 1339 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1340 enum rtw89_phy_idx phy_idx, s16 ref) 1341 { 1342 s8 ofst_int = 0; 1343 u8 base_cw_0db = 0x27; 1344 u16 tssi_16dbm_cw = 0x12c; 1345 s16 pwr_s10_3 = 0; 1346 s16 rf_pwr_cw = 0; 1347 u16 bb_pwr_cw = 0; 1348 u32 pwr_cw = 0; 1349 u32 tssi_ofst_cw = 0; 1350 1351 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1352 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1353 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1354 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1355 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1356 1357 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1358 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1359 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1360 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1361 1362 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1363 } 1364 1365 static 1366 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1367 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1368 { 1369 s8 val_1t = 0; 1370 s8 val_2t = 0; 1371 u32 reg; 1372 1373 if (pw_ofst < -16 || pw_ofst > 15) { 1374 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1375 pw_ofst); 1376 return; 1377 } 1378 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); 1379 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1380 val_1t = pw_ofst; 1381 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1382 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1383 val_2t = max(val_1t - 3, -16); 1384 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1385 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1386 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1387 val_1t, val_2t); 1388 } 1389 1390 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1391 enum rtw89_phy_idx phy_idx) 1392 { 1393 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1394 const u32 mask = 0x7FFFFFF; 1395 const u8 ofst_ofdm = 0x4; 1396 const u8 ofst_cck = 0x8; 1397 s16 ref_ofdm = 0; 1398 s16 ref_cck = 0; 1399 u32 val; 1400 u8 i; 1401 1402 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1403 1404 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1405 GENMASK(27, 10), 0x0); 1406 1407 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1408 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1409 1410 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1411 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1412 phy_idx); 1413 1414 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1415 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1416 1417 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1418 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1419 phy_idx); 1420 } 1421 1422 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, 1423 const struct rtw89_chan *chan, 1424 enum rtw89_phy_idx phy_idx) 1425 { 1426 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1427 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1428 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1429 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1430 } 1431 1432 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1433 enum rtw89_phy_idx phy_idx) 1434 { 1435 rtw8852a_set_txpwr_ref(rtwdev, phy_idx); 1436 } 1437 1438 static int 1439 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1440 { 1441 int ret; 1442 1443 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1444 if (ret) 1445 return ret; 1446 1447 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1448 if (ret) 1449 return ret; 1450 1451 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1452 if (ret) 1453 return ret; 1454 1455 return 0; 1456 } 1457 1458 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1459 { 1460 u8 i = 0; 1461 u32 addr, val; 1462 1463 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1464 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1465 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1466 rtw89_phy_write32(rtwdev, addr, val); 1467 } 1468 } 1469 1470 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1471 struct rtw8852a_bb_pmac_info *tx_info, 1472 enum rtw89_phy_idx idx) 1473 { 1474 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1475 if (tx_info->mode == CONT_TX) 1476 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1477 idx); 1478 else if (tx_info->mode == PKTS_TX) 1479 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1480 idx); 1481 } 1482 1483 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1484 struct rtw8852a_bb_pmac_info *tx_info, 1485 enum rtw89_phy_idx idx) 1486 { 1487 enum rtw8852a_pmac_mode mode = tx_info->mode; 1488 u32 pkt_cnt = tx_info->tx_cnt; 1489 u16 period = tx_info->period; 1490 1491 if (mode == CONT_TX && !tx_info->is_cck) { 1492 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1493 idx); 1494 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1495 } else if (mode == PKTS_TX) { 1496 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1497 idx); 1498 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1499 B_PMAC_TX_PRD_MSK, period, idx); 1500 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1501 pkt_cnt, idx); 1502 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1503 } 1504 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1505 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1506 } 1507 1508 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1509 struct rtw8852a_bb_pmac_info *tx_info, 1510 enum rtw89_phy_idx idx) 1511 { 1512 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1513 1514 if (!tx_info->en_pmac_tx) { 1515 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1516 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1517 if (chan->band_type == RTW89_BAND_2G) 1518 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1519 return; 1520 } 1521 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1522 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1523 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1524 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1525 idx); 1526 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1527 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1528 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1529 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1530 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1531 } 1532 1533 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1534 u16 tx_cnt, u16 period, u16 tx_time, 1535 enum rtw89_phy_idx idx) 1536 { 1537 struct rtw8852a_bb_pmac_info tx_info = {0}; 1538 1539 tx_info.en_pmac_tx = enable; 1540 tx_info.is_cck = 0; 1541 tx_info.mode = PKTS_TX; 1542 tx_info.tx_cnt = tx_cnt; 1543 tx_info.period = period; 1544 tx_info.tx_time = tx_time; 1545 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1546 } 1547 1548 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1549 enum rtw89_phy_idx idx) 1550 { 1551 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1552 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1553 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1554 } 1555 1556 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1557 { 1558 u32 rst_mask0 = 0; 1559 u32 rst_mask1 = 0; 1560 1561 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1562 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1563 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1564 if (!rtwdev->dbcc_en) { 1565 if (tx_path == RF_PATH_A) { 1566 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1567 B_TXPATH_SEL_MSK, 1); 1568 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1569 B_TXNSS_MAP_MSK, 0); 1570 } else if (tx_path == RF_PATH_B) { 1571 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1572 B_TXPATH_SEL_MSK, 2); 1573 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1574 B_TXNSS_MAP_MSK, 0); 1575 } else if (tx_path == RF_PATH_AB) { 1576 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1577 B_TXPATH_SEL_MSK, 3); 1578 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1579 B_TXNSS_MAP_MSK, 4); 1580 } else { 1581 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1582 } 1583 } else { 1584 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1585 1); 1586 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1587 RTW89_PHY_1); 1588 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1589 0); 1590 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1591 RTW89_PHY_1); 1592 } 1593 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1594 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1595 if (tx_path == RF_PATH_A) { 1596 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1597 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1598 } else { 1599 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1600 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1601 } 1602 } 1603 1604 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1605 enum rtw89_phy_idx idx, u8 mode) 1606 { 1607 if (mode != 0) 1608 return; 1609 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1610 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1611 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1612 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1613 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1614 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1615 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1616 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1617 } 1618 1619 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 1620 { 1621 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl : 1622 &rtw8852a_btc_preagc_dis_defs_tbl); 1623 } 1624 1625 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1626 { 1627 if (rtwdev->is_tssi_mode[rf_path]) { 1628 u32 addr = 0x1c10 + (rf_path << 13); 1629 1630 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1631 } 1632 1633 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1634 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1635 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1636 1637 fsleep(200); 1638 1639 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1640 } 1641 1642 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1643 { 1644 struct rtw89_btc *btc = &rtwdev->btc; 1645 struct rtw89_btc_module *module = &btc->mdinfo; 1646 1647 module->rfe_type = rtwdev->efuse.rfe_type; 1648 module->cv = rtwdev->hal.cv; 1649 module->bt_solo = 0; 1650 module->switch_type = BTC_SWITCH_INTERNAL; 1651 1652 if (module->rfe_type > 0) 1653 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 1654 else 1655 module->ant.num = 2; 1656 1657 module->ant.diversity = 0; 1658 module->ant.isolation = 10; 1659 1660 if (module->ant.num == 3) { 1661 module->ant.type = BTC_ANT_DEDICATED; 1662 module->bt_pos = BTC_BT_ALONE; 1663 } else { 1664 module->ant.type = BTC_ANT_SHARED; 1665 module->bt_pos = BTC_BT_BTG; 1666 } 1667 } 1668 1669 static 1670 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1671 { 1672 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1673 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1674 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1675 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1676 } 1677 1678 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 1679 { 1680 if (btg) { 1681 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1682 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1683 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1684 } else { 1685 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1686 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1687 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1688 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1689 } 1690 } 1691 1692 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1693 { 1694 struct rtw89_btc *btc = &rtwdev->btc; 1695 struct rtw89_btc_module *module = &btc->mdinfo; 1696 const struct rtw89_chip_info *chip = rtwdev->chip; 1697 const struct rtw89_mac_ax_coex coex_params = { 1698 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1699 .direction = RTW89_MAC_AX_COEX_INNER, 1700 }; 1701 1702 /* PTA init */ 1703 rtw89_mac_coex_init(rtwdev, &coex_params); 1704 1705 /* set WL Tx response = Hi-Pri */ 1706 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1707 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1708 1709 /* set rf gnt debug off */ 1710 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1711 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1712 1713 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1714 if (module->ant.type == BTC_ANT_SHARED) { 1715 rtw8852a_set_trx_mask(rtwdev, 1716 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1717 rtw8852a_set_trx_mask(rtwdev, 1718 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1719 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1720 rtw8852a_set_trx_mask(rtwdev, 1721 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1722 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1723 rtw8852a_set_trx_mask(rtwdev, 1724 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1725 rtw8852a_set_trx_mask(rtwdev, 1726 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1727 } 1728 1729 /* set PTA break table */ 1730 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1731 1732 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1733 rtw89_write32_set(rtwdev, 1734 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1735 btc->cx.wl.status.map.init_ok = true; 1736 } 1737 1738 static 1739 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1740 { 1741 u32 bitmap = 0; 1742 u32 reg = 0; 1743 1744 switch (map) { 1745 case BTC_PRI_MASK_TX_RESP: 1746 reg = R_BTC_BT_COEX_MSK_TABLE; 1747 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1748 break; 1749 case BTC_PRI_MASK_BEACON: 1750 reg = R_AX_WL_PRI_MSK; 1751 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1752 break; 1753 default: 1754 return; 1755 } 1756 1757 if (state) 1758 rtw89_write32_set(rtwdev, reg, bitmap); 1759 else 1760 rtw89_write32_clr(rtwdev, reg, bitmap); 1761 } 1762 1763 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1764 { 1765 return FIELD_GET(GENMASK(15, 0), ctrl); 1766 } 1767 1768 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1769 { 1770 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1771 } 1772 1773 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1774 { 1775 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1776 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1777 1778 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1779 } 1780 1781 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1782 { 1783 return FIELD_GET(GENMASK(31, 16), ctrl); 1784 } 1785 1786 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1787 { 1788 return cur & ~B_AX_TXAGC_BT_EN; 1789 } 1790 1791 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1792 { 1793 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1794 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1795 1796 return ov | iv | B_AX_TXAGC_BT_EN; 1797 } 1798 1799 static void 1800 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1801 { 1802 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1803 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1804 1805 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1806 #define __handle(_case) \ 1807 do { \ 1808 const u32 _reg = __btc_cr_ ## _case; \ 1809 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1810 u32 _cur, _wrt; \ 1811 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1812 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1813 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\ 1814 break; \ 1815 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1816 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1817 _wrt = __do_clr(_val) ? \ 1818 __btc_ctrl_rst_ ## _case(_cur) : \ 1819 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1820 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1821 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1822 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1823 } while (0) 1824 1825 __handle(all_time); 1826 __handle(gnt_bt); 1827 1828 #undef __handle 1829 #undef __do_clr 1830 } 1831 1832 static 1833 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1834 { 1835 /* +6 for compensate offset */ 1836 return clamp_t(s8, val + 6, -100, 0) + 100; 1837 } 1838 1839 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1840 {255, 0, 0, 7}, /* 0 -> original */ 1841 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1842 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1843 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1844 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1845 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1846 {6, 1, 0, 7}, 1847 {13, 1, 0, 7}, 1848 {13, 1, 0, 7} 1849 }; 1850 1851 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1852 {255, 0, 0, 7}, /* 0 -> original */ 1853 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1854 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1855 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1856 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1857 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1858 {255, 1, 0, 7}, 1859 {255, 1, 0, 7}, 1860 {255, 1, 0, 7} 1861 }; 1862 1863 static const 1864 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1865 static const 1866 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1867 1868 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1869 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1870 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1871 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1872 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1873 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1874 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1875 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1876 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1877 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1878 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1879 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1880 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1881 }; 1882 1883 static 1884 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1885 { 1886 struct rtw89_btc *btc = &rtwdev->btc; 1887 const struct rtw89_btc_ver *ver = btc->ver; 1888 struct rtw89_btc_cx *cx = &btc->cx; 1889 u32 val; 1890 1891 if (ver->fcxbtcrpt != 1) 1892 return; 1893 1894 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 1895 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 1896 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 1897 1898 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 1899 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 1900 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 1901 1902 /* clock-gate off before reset counter*/ 1903 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1904 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1905 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1906 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1907 } 1908 1909 static 1910 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1911 { 1912 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1913 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1914 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 1915 1916 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1917 if (state) 1918 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1919 RFREG_MASK, 0xa2d7c); 1920 else 1921 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1922 RFREG_MASK, 0xa2020); 1923 1924 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1925 } 1926 1927 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 1928 { 1929 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 1930 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 1931 * To improve BT ACI in co-rx 1932 */ 1933 1934 switch (level) { 1935 case 0: /* default */ 1936 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 1937 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 1938 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 1939 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 1940 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1941 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1942 break; 1943 case 1: /* Fix LNA2=5 */ 1944 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 1945 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 1946 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 1947 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 1948 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1949 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1950 break; 1951 } 1952 } 1953 1954 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 1955 { 1956 struct rtw89_btc *btc = &rtwdev->btc; 1957 1958 switch (level) { 1959 case 0: /* original */ 1960 default: 1961 rtw8852a_bb_ctrl_btc_preagc(rtwdev, false); 1962 btc->dm.wl_lna2 = 0; 1963 break; 1964 case 1: /* for FDD free-run */ 1965 rtw8852a_bb_ctrl_btc_preagc(rtwdev, true); 1966 btc->dm.wl_lna2 = 0; 1967 break; 1968 case 2: /* for BTG Co-Rx*/ 1969 rtw8852a_bb_ctrl_btc_preagc(rtwdev, false); 1970 btc->dm.wl_lna2 = 1; 1971 break; 1972 } 1973 1974 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 1975 } 1976 1977 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 1978 struct rtw89_rx_phy_ppdu *phy_ppdu, 1979 struct ieee80211_rx_status *status) 1980 { 1981 u16 chan = phy_ppdu->chan_idx; 1982 u8 band; 1983 1984 if (chan == 0) 1985 return; 1986 1987 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1988 status->freq = ieee80211_channel_to_frequency(chan, band); 1989 status->band = band; 1990 } 1991 1992 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 1993 struct rtw89_rx_phy_ppdu *phy_ppdu, 1994 struct ieee80211_rx_status *status) 1995 { 1996 u8 path; 1997 u8 *rx_power = phy_ppdu->rssi; 1998 1999 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2000 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2001 status->chains |= BIT(path); 2002 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2003 } 2004 if (phy_ppdu->valid) 2005 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2006 } 2007 2008 #ifdef CONFIG_PM 2009 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = { 2010 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2011 .n_patterns = RTW89_MAX_PATTERN_NUM, 2012 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2013 .pattern_min_len = 1, 2014 }; 2015 #endif 2016 2017 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 2018 .enable_bb_rf = rtw89_mac_enable_bb_rf, 2019 .disable_bb_rf = rtw89_mac_disable_bb_rf, 2020 .bb_reset = rtw8852a_bb_reset, 2021 .bb_sethw = rtw8852a_bb_sethw, 2022 .read_rf = rtw89_phy_read_rf, 2023 .write_rf = rtw89_phy_write_rf, 2024 .set_channel = rtw8852a_set_channel, 2025 .set_channel_help = rtw8852a_set_channel_help, 2026 .read_efuse = rtw8852a_read_efuse, 2027 .read_phycap = rtw8852a_read_phycap, 2028 .fem_setup = rtw8852a_fem_setup, 2029 .rfk_init = rtw8852a_rfk_init, 2030 .rfk_channel = rtw8852a_rfk_channel, 2031 .rfk_band_changed = rtw8852a_rfk_band_changed, 2032 .rfk_scan = rtw8852a_rfk_scan, 2033 .rfk_track = rtw8852a_rfk_track, 2034 .power_trim = rtw8852a_power_trim, 2035 .set_txpwr = rtw8852a_set_txpwr, 2036 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2037 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2038 .get_thermal = rtw8852a_get_thermal, 2039 .ctrl_btg = rtw8852a_ctrl_btg, 2040 .query_ppdu = rtw8852a_query_ppdu, 2041 .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc, 2042 .cfg_txrx_path = NULL, 2043 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2044 .pwr_on_func = NULL, 2045 .pwr_off_func = NULL, 2046 .fill_txdesc = rtw89_core_fill_txdesc, 2047 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2048 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2049 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2050 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2051 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2052 .h2c_dctl_sec_cam = NULL, 2053 2054 .btc_set_rfe = rtw8852a_btc_set_rfe, 2055 .btc_init_cfg = rtw8852a_btc_init_cfg, 2056 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2057 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2058 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2059 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2060 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2061 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain, 2062 .btc_set_policy = rtw89_btc_set_policy, 2063 }; 2064 2065 const struct rtw89_chip_info rtw8852a_chip_info = { 2066 .chip_id = RTL8852A, 2067 .ops = &rtw8852a_chip_ops, 2068 .fw_basename = RTW8852A_FW_BASENAME, 2069 .fw_format_max = RTW8852A_FW_FORMAT_MAX, 2070 .try_ce_fw = false, 2071 .fifo_size = 458752, 2072 .dle_scc_rsvd_size = 0, 2073 .max_amsdu_limit = 3500, 2074 .dis_2g_40m_ul_ofdma = true, 2075 .rsvd_ple_ofst = 0x6f800, 2076 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 2077 .dle_mem = rtw8852a_dle_mem_pcie, 2078 .wde_qempty_acq_num = 16, 2079 .wde_qempty_mgq_sel = 16, 2080 .rf_base_addr = {0xc000, 0xd000}, 2081 .pwr_on_seq = pwr_on_seq_8852a, 2082 .pwr_off_seq = pwr_off_seq_8852a, 2083 .bb_table = &rtw89_8852a_phy_bb_table, 2084 .bb_gain_table = NULL, 2085 .rf_table = {&rtw89_8852a_phy_radioa_table, 2086 &rtw89_8852a_phy_radiob_table,}, 2087 .nctl_table = &rtw89_8852a_phy_nctl_table, 2088 .byr_table = &rtw89_8852a_byr_table, 2089 .dflt_parms = &rtw89_8852a_dflt_parms, 2090 .rfe_parms_conf = NULL, 2091 .txpwr_factor_rf = 2, 2092 .txpwr_factor_mac = 1, 2093 .dig_table = &rtw89_8852a_phy_dig_table, 2094 .dig_regs = &rtw8852a_dig_regs, 2095 .tssi_dbw_table = NULL, 2096 .support_chanctx_num = 1, 2097 .support_bands = BIT(NL80211_BAND_2GHZ) | 2098 BIT(NL80211_BAND_5GHZ), 2099 .support_bw160 = false, 2100 .support_ul_tb_ctrl = false, 2101 .hw_sec_hdr = false, 2102 .rf_path_num = 2, 2103 .tx_nss = 2, 2104 .rx_nss = 2, 2105 .acam_num = 128, 2106 .bcam_num = 10, 2107 .scam_num = 128, 2108 .bacam_num = 2, 2109 .bacam_dynamic_num = 4, 2110 .bacam_v1 = false, 2111 .sec_ctrl_efuse_size = 4, 2112 .physical_efuse_size = 1216, 2113 .logical_efuse_size = 1536, 2114 .limit_efuse_size = 1152, 2115 .dav_phy_efuse_size = 0, 2116 .dav_log_efuse_size = 0, 2117 .phycap_addr = 0x580, 2118 .phycap_size = 128, 2119 .para_ver = 0x0, 2120 .wlcx_desired = 0x06000000, 2121 .btcx_desired = 0x7, 2122 .scbd = 0x1, 2123 .mailbox = 0x1, 2124 2125 .afh_guard_ch = 6, 2126 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2127 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2128 .rssi_tol = 2, 2129 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2130 .mon_reg = rtw89_btc_8852a_mon_reg, 2131 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2132 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2133 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2134 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2135 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2136 BIT(RTW89_PS_MODE_CLK_GATED) | 2137 BIT(RTW89_PS_MODE_PWR_GATED), 2138 .low_power_hci_modes = 0, 2139 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2140 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2141 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2142 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2143 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2144 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2145 .h2c_regs = rtw8852a_h2c_regs, 2146 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2147 .c2h_regs = rtw8852a_c2h_regs, 2148 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2149 .page_regs = &rtw8852a_page_regs, 2150 .cfo_src_fd = false, 2151 .cfo_hw_comp = false, 2152 .dcfo_comp = &rtw8852a_dcfo_comp, 2153 .dcfo_comp_sft = 10, 2154 .imr_info = &rtw8852a_imr_info, 2155 .rrsr_cfgs = &rtw8852a_rrsr_cfgs, 2156 .bss_clr_map_reg = R_BSS_CLR_MAP, 2157 .dma_ch_mask = 0, 2158 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL, 2159 #ifdef CONFIG_PM 2160 .wowlan_stub = &rtw_wowlan_stub_8852a, 2161 #endif 2162 }; 2163 EXPORT_SYMBOL(rtw8852a_chip_info); 2164 2165 MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE); 2166 MODULE_AUTHOR("Realtek Corporation"); 2167 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2168 MODULE_LICENSE("Dual BSD/GPL"); 2169